drivers/gpu/drm/nouveau/nouveau_chan.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include <nvif/push006c.h>
  25
  26 #include <nvif/class.h>
  27 #include <nvif/cl0002.h>
  28 #include <nvif/if0020.h>
  29
  30 #include "nouveau_drv.h"
  31 #include "nouveau_dma.h"
  32 #include "nouveau_bo.h"
  33 #include "nouveau_chan.h"
  34 #include "nouveau_fence.h"
  35 #include "nouveau_abi16.h"
  36 #include "nouveau_vmm.h"
  37 #include "nouveau_svm.h"
  38
  39 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
  40 int nouveau_vram_pushbuf;
  41 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  42
  43 void
  44 nouveau_channel_kill(struct nouveau_channel *chan)
  45 {
  46         atomic_set(&chan->killed, 1);
  47         if (chan->fence)
  48                 nouveau_fence_context_kill(chan->fence, -ENODEV);
  49 }
  50
  51 static int
  52 nouveau_channel_killed(struct nvif_event *event, void *repv, u32 repc)
  53 {
  54         struct nouveau_channel *chan = container_of(event, typeof(*chan), kill);
  55         struct nouveau_cli *cli = (void *)chan->user.client;
  56
  57         NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid);
  58
  59         if (unlikely(!atomic_read(&chan->killed)))
  60                 nouveau_channel_kill(chan);
  61
  62         return NVIF_EVENT_DROP;
  63 }
  64
  65 int
  66 nouveau_channel_idle(struct nouveau_channel *chan)
  67 {
  68         if (likely(chan && chan->fence && !atomic_read(&chan->killed))) {
  69                 struct nouveau_cli *cli = (void *)chan->user.client;
  70                 struct nouveau_fence *fence = NULL;
  71                 int ret;
  72
  73                 ret = nouveau_fence_new(&fence, chan);
  74                 if (!ret) {
  75                         ret = nouveau_fence_wait(fence, false, false);
  76                         nouveau_fence_unref(&fence);
  77                 }
  78
  79                 if (ret) {
  80                         NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n",
  81                                   chan->chid, nvxx_client(&cli->base)->name);
  82                         return ret;
  83                 }
  84         }
  85         return 0;
  86 }
  87
  88 void
  89 nouveau_channel_del(struct nouveau_channel **pchan)
  90 {
  91         struct nouveau_channel *chan = *pchan;
  92         if (chan) {
  93                 struct nouveau_cli *cli = (void *)chan->user.client;
  94
  95                 if (chan->fence)
  96                         nouveau_fence(chan->drm)->context_del(chan);
  97
  98                 if (cli)
  99                         nouveau_svmm_part(chan->vmm->svmm, chan->inst);
 100
 101                 nvif_object_dtor(&chan->blit);
 102                 nvif_object_dtor(&chan->nvsw);
 103                 nvif_object_dtor(&chan->gart);
 104                 nvif_object_dtor(&chan->vram);
 105                 nvif_event_dtor(&chan->kill);
 106                 nvif_object_dtor(&chan->user);
 107                 nvif_mem_dtor(&chan->mem_userd);
 108                 nvif_object_dtor(&chan->push.ctxdma);
 109                 nouveau_vma_del(&chan->push.vma);
 110                 nouveau_bo_unmap(chan->push.buffer);
 111                 if (chan->push.buffer && chan->push.buffer->bo.pin_count)
 112                         nouveau_bo_unpin(chan->push.buffer);
 113                 nouveau_bo_ref(NULL, &chan->push.buffer);
 114                 kfree(chan);
 115         }
 116         *pchan = NULL;
 117 }
 118
 119 static void
 120 nouveau_channel_kick(struct nvif_push *push)
 121 {
 122         struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push);
 123         chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn);
 124         FIRE_RING(chan);
 125         chan->chan._push.bgn = chan->chan._push.cur;
 126 }
 127
 128 static int
 129 nouveau_channel_wait(struct nvif_push *push, u32 size)
 130 {
 131         struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push);
 132         int ret;
 133         chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn);
 134         ret = RING_SPACE(chan, size);
 135         if (ret == 0) {
 136                 chan->chan._push.bgn = chan->chan._push.mem.object.map.ptr;
 137                 chan->chan._push.bgn = chan->chan._push.bgn + chan->dma.cur;
 138                 chan->chan._push.cur = chan->chan._push.bgn;
 139                 chan->chan._push.end = chan->chan._push.bgn + size;
 140         }
 141         return ret;
 142 }
 143
 144 static int
 145 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
 146                      u32 size, struct nouveau_channel **pchan)
 147 {
 148         struct nouveau_cli *cli = (void *)device->object.client;
 149         struct nv_dma_v0 args = {};
 150         struct nouveau_channel *chan;
 151         u32 target;
 152         int ret;
 153
 154         chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
 155         if (!chan)
 156                 return -ENOMEM;
 157
 158         chan->device = device;
 159         chan->drm = drm;
 160         chan->vmm = nouveau_cli_vmm(cli);
 161         atomic_set(&chan->killed, 0);
 162
 163         /* allocate memory for dma push buffer */
 164         target = NOUVEAU_GEM_DOMAIN_GART | NOUVEAU_GEM_DOMAIN_COHERENT;
 165         if (nouveau_vram_pushbuf)
 166                 target = NOUVEAU_GEM_DOMAIN_VRAM;
 167
 168         ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL,
 169                             &chan->push.buffer);
 170         if (ret == 0) {
 171                 ret = nouveau_bo_pin(chan->push.buffer, target, false);
 172                 if (ret == 0)
 173                         ret = nouveau_bo_map(chan->push.buffer);
 174         }
 175
 176         if (ret) {
 177                 nouveau_channel_del(pchan);
 178                 return ret;
 179         }
 180
 181         chan->chan._push.mem.object.parent = cli->base.object.parent;
 182         chan->chan._push.mem.object.client = &cli->base;
 183         chan->chan._push.mem.object.name = "chanPush";
 184         chan->chan._push.mem.object.map.ptr = chan->push.buffer->kmap.virtual;
 185         chan->chan._push.wait = nouveau_channel_wait;
 186         chan->chan._push.kick = nouveau_channel_kick;
 187         chan->chan.push = &chan->chan._push;
 188
 189         /* create dma object covering the *entire* memory space that the
 190          * pushbuf lives in, this is because the GEM code requires that
 191          * we be able to call out to other (indirect) push buffers
 192          */
 193         chan->push.addr = chan->push.buffer->offset;
 194
 195         if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
 196                 ret = nouveau_vma_new(chan->push.buffer, chan->vmm,
 197                                       &chan->push.vma);
 198                 if (ret) {
 199                         nouveau_channel_del(pchan);
 200                         return ret;
 201                 }
 202
 203                 chan->push.addr = chan->push.vma->addr;
 204
 205                 if (device->info.family >= NV_DEVICE_INFO_V0_FERMI)
 206                         return 0;
 207
 208                 args.target = NV_DMA_V0_TARGET_VM;
 209                 args.access = NV_DMA_V0_ACCESS_VM;
 210                 args.start = 0;
 211                 args.limit = chan->vmm->vmm.limit - 1;
 212         } else
 213         if (chan->push.buffer->bo.resource->mem_type == TTM_PL_VRAM) {
 214                 if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
 215                         /* nv04 vram pushbuf hack, retarget to its location in
 216                          * the framebuffer bar rather than direct vram access..
 217                          * nfi why this exists, it came from the -nv ddx.
 218                          */
 219                         args.target = NV_DMA_V0_TARGET_PCI;
 220                         args.access = NV_DMA_V0_ACCESS_RDWR;
 221                         args.start = nvxx_device(device)->func->
 222                                 resource_addr(nvxx_device(device), 1);
 223                         args.limit = args.start + device->info.ram_user - 1;
 224                 } else {
 225                         args.target = NV_DMA_V0_TARGET_VRAM;
 226                         args.access = NV_DMA_V0_ACCESS_RDWR;
 227                         args.start = 0;
 228                         args.limit = device->info.ram_user - 1;
 229                 }
 230         } else {
 231                 if (chan->drm->agp.bridge) {
 232                         args.target = NV_DMA_V0_TARGET_AGP;
 233                         args.access = NV_DMA_V0_ACCESS_RDWR;
 234                         args.start = chan->drm->agp.base;
 235                         args.limit = chan->drm->agp.base +
 236                                      chan->drm->agp.size - 1;
 237                 } else {
 238                         args.target = NV_DMA_V0_TARGET_VM;
 239                         args.access = NV_DMA_V0_ACCESS_RDWR;
 240                         args.start = 0;
 241                         args.limit = chan->vmm->vmm.limit - 1;
 242                 }
 243         }
 244
 245         ret = nvif_object_ctor(&device->object, "abi16PushCtxDma", 0,
 246                                NV_DMA_FROM_MEMORY, &args, sizeof(args),
 247                                &chan->push.ctxdma);
 248         if (ret) {
 249                 nouveau_channel_del(pchan);
 250                 return ret;
 251         }
 252
 253         return 0;
 254 }
 255
 256 static int
 257 nouveau_channel_ctor(struct nouveau_drm *drm, struct nvif_device *device, bool priv, u64 runm,
 258                      struct nouveau_channel **pchan)
 259 {
 260         static const struct {
 261                 s32 oclass;
 262                 int version;
 263         } hosts[] = {
 264                 {  AMPERE_CHANNEL_GPFIFO_B, 0 },
 265                 {  AMPERE_CHANNEL_GPFIFO_A, 0 },
 266                 {  TURING_CHANNEL_GPFIFO_A, 0 },
 267                 {   VOLTA_CHANNEL_GPFIFO_A, 0 },
 268                 {  PASCAL_CHANNEL_GPFIFO_A, 0 },
 269                 { MAXWELL_CHANNEL_GPFIFO_A, 0 },
 270                 {  KEPLER_CHANNEL_GPFIFO_B, 0 },
 271                 {  KEPLER_CHANNEL_GPFIFO_A, 0 },
 272                 {   FERMI_CHANNEL_GPFIFO  , 0 },
 273                 {     G82_CHANNEL_GPFIFO  , 0 },
 274                 {    NV50_CHANNEL_GPFIFO  , 0 },
 275                 {    NV40_CHANNEL_DMA     , 0 },
 276                 {    NV17_CHANNEL_DMA     , 0 },
 277                 {    NV10_CHANNEL_DMA     , 0 },
 278                 {    NV03_CHANNEL_DMA     , 0 },
 279                 {}
 280         };
 281         struct {
 282                 struct nvif_chan_v0 chan;
 283                 char name[TASK_COMM_LEN+16];
 284         } args;
 285         struct nouveau_cli *cli = (void *)device->object.client;
 286         struct nouveau_channel *chan;
 287         const u64 plength = 0x10000;
 288         const u64 ioffset = plength;
 289         const u64 ilength = 0x02000;
 290         char name[TASK_COMM_LEN];
 291         int cid, ret;
 292         u64 size;
 293
 294         cid = nvif_mclass(&device->object, hosts);
 295         if (cid < 0)
 296                 return cid;
 297
 298         if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO)
 299                 size = plength;
 300         else
 301                 size = ioffset + ilength;
 302
 303         /* allocate dma push buffer */
 304         ret = nouveau_channel_prep(drm, device, size, &chan);
 305         *pchan = chan;
 306         if (ret)
 307                 return ret;
 308
 309         /* create channel object */
 310         args.chan.version = 0;
 311         args.chan.namelen = sizeof(args.name);
 312         args.chan.runlist = __ffs64(runm);
 313         args.chan.runq = 0;
 314         args.chan.priv = priv;
 315         args.chan.devm = BIT(0);
 316         if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO) {
 317                 args.chan.vmm = 0;
 318                 args.chan.ctxdma = nvif_handle(&chan->push.ctxdma);
 319                 args.chan.offset = chan->push.addr;
 320                 args.chan.length = 0;
 321         } else {
 322                 args.chan.vmm = nvif_handle(&chan->vmm->vmm.object);
 323                 if (hosts[cid].oclass < FERMI_CHANNEL_GPFIFO)
 324                         args.chan.ctxdma = nvif_handle(&chan->push.ctxdma);
 325                 else
 326                         args.chan.ctxdma = 0;
 327                 args.chan.offset = ioffset + chan->push.addr;
 328                 args.chan.length = ilength;
 329         }
 330         args.chan.huserd = 0;
 331         args.chan.ouserd = 0;
 332
 333         /* allocate userd */
 334         if (hosts[cid].oclass >= VOLTA_CHANNEL_GPFIFO_A) {
 335                 ret = nvif_mem_ctor(&cli->mmu, "abi16ChanUSERD", NVIF_CLASS_MEM_GF100,
 336                                     NVIF_MEM_VRAM | NVIF_MEM_COHERENT | NVIF_MEM_MAPPABLE,
 337                                     0, PAGE_SIZE, NULL, 0, &chan->mem_userd);
 338                 if (ret)
 339                         return ret;
 340
 341                 args.chan.huserd = nvif_handle(&chan->mem_userd.object);
 342                 args.chan.ouserd = 0;
 343
 344                 chan->userd = &chan->mem_userd.object;
 345         } else {
 346                 chan->userd = &chan->user;
 347         }
 348
 349         get_task_comm(name, current);
 350         snprintf(args.name, sizeof(args.name), "%s[%d]", name, task_pid_nr(current));
 351
 352         ret = nvif_object_ctor(&device->object, "abi16ChanUser", 0, hosts[cid].oclass,
 353                                &args, sizeof(args), &chan->user);
 354         if (ret) {
 355                 nouveau_channel_del(pchan);
 356                 return ret;
 357         }
 358
 359         chan->runlist = args.chan.runlist;
 360         chan->chid = args.chan.chid;
 361         chan->inst = args.chan.inst;
 362         chan->token = args.chan.token;
 363         return 0;
 364 }
 365
 366 static int
 367 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
 368 {
 369         struct nvif_device *device = chan->device;
 370         struct nouveau_drm *drm = chan->drm;
 371         struct nv_dma_v0 args = {};
 372         int ret, i;
 373
 374         ret = nvif_object_map(chan->userd, NULL, 0);
 375         if (ret)
 376                 return ret;
 377
 378         if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) {
 379                 struct {
 380                         struct nvif_event_v0 base;
 381                         struct nvif_chan_event_v0 host;
 382                 } args;
 383
 384                 args.host.version = 0;
 385                 args.host.type = NVIF_CHAN_EVENT_V0_KILLED;
 386
 387                 ret = nvif_event_ctor(&chan->user, "abi16ChanKilled", chan->chid,
 388                                       nouveau_channel_killed, false,
 389                                       &args.base, sizeof(args), &chan->kill);
 390                 if (ret == 0)
 391                         ret = nvif_event_allow(&chan->kill);
 392                 if (ret) {
 393                         NV_ERROR(drm, "Failed to request channel kill "
 394                                       "notification: %d\n", ret);
 395                         return ret;
 396                 }
 397         }
 398
 399         /* allocate dma objects to cover all allowed vram, and gart */
 400         if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
 401                 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
 402                         args.target = NV_DMA_V0_TARGET_VM;
 403                         args.access = NV_DMA_V0_ACCESS_VM;
 404                         args.start = 0;
 405                         args.limit = chan->vmm->vmm.limit - 1;
 406                 } else {
 407                         args.target = NV_DMA_V0_TARGET_VRAM;
 408                         args.access = NV_DMA_V0_ACCESS_RDWR;
 409                         args.start = 0;
 410                         args.limit = device->info.ram_user - 1;
 411                 }
 412
 413                 ret = nvif_object_ctor(&chan->user, "abi16ChanVramCtxDma", vram,
 414                                        NV_DMA_IN_MEMORY, &args, sizeof(args),
 415                                        &chan->vram);
 416                 if (ret)
 417                         return ret;
 418
 419                 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
 420                         args.target = NV_DMA_V0_TARGET_VM;
 421                         args.access = NV_DMA_V0_ACCESS_VM;
 422                         args.start = 0;
 423                         args.limit = chan->vmm->vmm.limit - 1;
 424                 } else
 425                 if (chan->drm->agp.bridge) {
 426                         args.target = NV_DMA_V0_TARGET_AGP;
 427                         args.access = NV_DMA_V0_ACCESS_RDWR;
 428                         args.start = chan->drm->agp.base;
 429                         args.limit = chan->drm->agp.base +
 430                                      chan->drm->agp.size - 1;
 431                 } else {
 432                         args.target = NV_DMA_V0_TARGET_VM;
 433                         args.access = NV_DMA_V0_ACCESS_RDWR;
 434                         args.start = 0;
 435                         args.limit = chan->vmm->vmm.limit - 1;
 436                 }
 437
 438                 ret = nvif_object_ctor(&chan->user, "abi16ChanGartCtxDma", gart,
 439                                        NV_DMA_IN_MEMORY, &args, sizeof(args),
 440                                        &chan->gart);
 441                 if (ret)
 442                         return ret;
 443         }
 444
 445         /* initialise dma tracking parameters */
 446         switch (chan->user.oclass & 0x00ff) {
 447         case 0x006b:
 448         case 0x006e:
 449                 chan->user_put = 0x40;
 450                 chan->user_get = 0x44;
 451                 chan->dma.max = (0x10000 / 4) - 2;
 452                 break;
 453         default:
 454                 chan->user_put = 0x40;
 455                 chan->user_get = 0x44;
 456                 chan->user_get_hi = 0x60;
 457                 chan->dma.ib_base =  0x10000 / 4;
 458                 chan->dma.ib_max  = (0x02000 / 8) - 1;
 459                 chan->dma.ib_put  = 0;
 460                 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
 461                 chan->dma.max = chan->dma.ib_base;
 462                 break;
 463         }
 464
 465         chan->dma.put = 0;
 466         chan->dma.cur = chan->dma.put;
 467         chan->dma.free = chan->dma.max - chan->dma.cur;
 468
 469         ret = PUSH_WAIT(chan->chan.push, NOUVEAU_DMA_SKIPS);
 470         if (ret)
 471                 return ret;
 472
 473         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
 474                 PUSH_DATA(chan->chan.push, 0x00000000);
 475
 476         /* allocate software object class (used for fences on <= nv05) */
 477         if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
 478                 ret = nvif_object_ctor(&chan->user, "abi16NvswFence", 0x006e,
 479                                        NVIF_CLASS_SW_NV04,
 480                                        NULL, 0, &chan->nvsw);
 481                 if (ret)
 482                         return ret;
 483
 484                 ret = PUSH_WAIT(chan->chan.push, 2);
 485                 if (ret)
 486                         return ret;
 487
 488                 PUSH_NVSQ(chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle);
 489                 PUSH_KICK(chan->chan.push);
 490         }
 491
 492         /* initialise synchronisation */
 493         return nouveau_fence(chan->drm)->context_new(chan);
 494 }
 495
 496 int
 497 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device,
 498                     bool priv, u64 runm, u32 vram, u32 gart, struct nouveau_channel **pchan)
 499 {
 500         struct nouveau_cli *cli = (void *)device->object.client;
 501         int ret;
 502
 503         ret = nouveau_channel_ctor(drm, device, priv, runm, pchan);
 504         if (ret) {
 505                 NV_PRINTK(dbg, cli, "channel create, %d\n", ret);
 506                 return ret;
 507         }
 508
 509         ret = nouveau_channel_init(*pchan, vram, gart);
 510         if (ret) {
 511                 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
 512                 nouveau_channel_del(pchan);
 513                 return ret;
 514         }
 515
 516         ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst);
 517         if (ret)
 518                 nouveau_channel_del(pchan);
 519
 520         return ret;
 521 }
 522
 523 void
 524 nouveau_channels_fini(struct nouveau_drm *drm)
 525 {
 526         kfree(drm->runl);
 527 }
 528
 529 int
 530 nouveau_channels_init(struct nouveau_drm *drm)
 531 {
 532         struct {
 533                 struct nv_device_info_v1 m;
 534                 struct {
 535                         struct nv_device_info_v1_data channels;
 536                         struct nv_device_info_v1_data runlists;
 537                 } v;
 538         } args = {
 539                 .m.version = 1,
 540                 .m.count = sizeof(args.v) / sizeof(args.v.channels),
 541                 .v.channels.mthd = NV_DEVICE_HOST_CHANNELS,
 542                 .v.runlists.mthd = NV_DEVICE_HOST_RUNLISTS,
 543         };
 544         struct nvif_object *device = &drm->client.device.object;
 545         int ret, i;
 546
 547         ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args));
 548         if (ret ||
 549             args.v.runlists.mthd == NV_DEVICE_INFO_INVALID || !args.v.runlists.data ||
 550             args.v.channels.mthd == NV_DEVICE_INFO_INVALID)
 551                 return -ENODEV;
 552
 553         drm->chan_nr = drm->chan_total = args.v.channels.data;
 554         drm->runl_nr = fls64(args.v.runlists.data);
 555         drm->runl = kcalloc(drm->runl_nr, sizeof(*drm->runl), GFP_KERNEL);
 556         if (!drm->runl)
 557                 return -ENOMEM;
 558
 559         if (drm->chan_nr == 0) {
 560                 for (i = 0; i < drm->runl_nr; i++) {
 561                         if (!(args.v.runlists.data & BIT(i)))
 562                                 continue;
 563
 564                         args.v.channels.mthd = NV_DEVICE_HOST_RUNLIST_CHANNELS;
 565                         args.v.channels.data = i;
 566
 567                         ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args));
 568                         if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID)
 569                                 return -ENODEV;
 570
 571                         drm->runl[i].chan_nr = args.v.channels.data;
 572                         drm->runl[i].chan_id_base = drm->chan_total;
 573                         drm->runl[i].context_base = dma_fence_context_alloc(drm->runl[i].chan_nr);
 574
 575                         drm->chan_total += drm->runl[i].chan_nr;
 576                 }
 577         } else {
 578                 drm->runl[0].context_base = dma_fence_context_alloc(drm->chan_nr);
 579                 for (i = 1; i < drm->runl_nr; i++)
 580                         drm->runl[i].context_base = drm->runl[0].context_base;
 581
 582         }
 583
 584         return 0;
 585 }