2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/console.h>
26 #include <linux/delay.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/vga_switcheroo.h>
31 #include <linux/mmu_notifier.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_ioctl.h>
35 #include <drm/drm_vblank.h>
37 #include <core/gpuobj.h>
38 #include <core/option.h>
40 #include <core/tegra.h>
42 #include <nvif/driver.h>
43 #include <nvif/fifo.h>
44 #include <nvif/user.h>
46 #include <nvif/class.h>
47 #include <nvif/cl0002.h>
48 #include <nvif/cla06f.h>
50 #include "nouveau_drv.h"
51 #include "nouveau_dma.h"
52 #include "nouveau_ttm.h"
53 #include "nouveau_gem.h"
54 #include "nouveau_vga.h"
55 #include "nouveau_led.h"
56 #include "nouveau_hwmon.h"
57 #include "nouveau_acpi.h"
58 #include "nouveau_bios.h"
59 #include "nouveau_ioctl.h"
60 #include "nouveau_abi16.h"
61 #include "nouveau_fbcon.h"
62 #include "nouveau_fence.h"
63 #include "nouveau_debugfs.h"
64 #include "nouveau_usif.h"
65 #include "nouveau_connector.h"
66 #include "nouveau_platform.h"
67 #include "nouveau_svm.h"
68 #include "nouveau_dmem.h"
70 MODULE_PARM_DESC(config, "option string to pass to driver core");
71 static char *nouveau_config;
72 module_param_named(config, nouveau_config, charp, 0400);
74 MODULE_PARM_DESC(debug, "debug string to pass to driver core");
75 static char *nouveau_debug;
76 module_param_named(debug, nouveau_debug, charp, 0400);
78 MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
79 static int nouveau_noaccel = 0;
80 module_param_named(noaccel, nouveau_noaccel, int, 0400);
82 MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
83 "0 = disabled, 1 = enabled, 2 = headless)");
84 int nouveau_modeset = -1;
85 module_param_named(modeset, nouveau_modeset, int, 0400);
87 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
88 static int nouveau_atomic = 0;
89 module_param_named(atomic, nouveau_atomic, int, 0400);
91 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
92 static int nouveau_runtime_pm = -1;
93 module_param_named(runpm, nouveau_runtime_pm, int, 0400);
95 static struct drm_driver driver_stub;
96 static struct drm_driver driver_pci;
97 static struct drm_driver driver_platform;
100 nouveau_pci_name(struct pci_dev *pdev)
102 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
103 name |= pdev->bus->number << 16;
104 name |= PCI_SLOT(pdev->devfn) << 8;
105 return name | PCI_FUNC(pdev->devfn);
109 nouveau_platform_name(struct platform_device *platformdev)
111 return platformdev->id;
115 nouveau_name(struct drm_device *dev)
118 return nouveau_pci_name(dev->pdev);
120 return nouveau_platform_name(to_platform_device(dev->dev));
124 nouveau_cli_work_ready(struct dma_fence *fence)
126 if (!dma_fence_is_signaled(fence))
128 dma_fence_put(fence);
133 nouveau_cli_work(struct work_struct *w)
135 struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
136 struct nouveau_cli_work *work, *wtmp;
137 mutex_lock(&cli->lock);
138 list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
139 if (!work->fence || nouveau_cli_work_ready(work->fence)) {
140 list_del(&work->head);
144 mutex_unlock(&cli->lock);
148 nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
150 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
151 schedule_work(&work->cli->work);
155 nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
156 struct nouveau_cli_work *work)
158 work->fence = dma_fence_get(fence);
160 mutex_lock(&cli->lock);
161 list_add_tail(&work->head, &cli->worker);
162 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
163 nouveau_cli_work_fence(fence, &work->cb);
164 mutex_unlock(&cli->lock);
168 nouveau_cli_fini(struct nouveau_cli *cli)
170 /* All our channels are dead now, which means all the fences they
171 * own are signalled, and all callback functions have been called.
173 * So, after flushing the workqueue, there should be nothing left.
175 flush_work(&cli->work);
176 WARN_ON(!list_empty(&cli->worker));
178 usif_client_fini(cli);
179 nouveau_vmm_fini(&cli->svm);
180 nouveau_vmm_fini(&cli->vmm);
181 nvif_mmu_fini(&cli->mmu);
182 nvif_device_fini(&cli->device);
183 mutex_lock(&cli->drm->master.lock);
184 nvif_client_fini(&cli->base);
185 mutex_unlock(&cli->drm->master.lock);
189 nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
190 struct nouveau_cli *cli)
192 static const struct nvif_mclass
194 { NVIF_CLASS_MEM_GF100, -1 },
195 { NVIF_CLASS_MEM_NV50 , -1 },
196 { NVIF_CLASS_MEM_NV04 , -1 },
199 static const struct nvif_mclass
201 { NVIF_CLASS_MMU_GF100, -1 },
202 { NVIF_CLASS_MMU_NV50 , -1 },
203 { NVIF_CLASS_MMU_NV04 , -1 },
206 static const struct nvif_mclass
208 { NVIF_CLASS_VMM_GP100, -1 },
209 { NVIF_CLASS_VMM_GM200, -1 },
210 { NVIF_CLASS_VMM_GF100, -1 },
211 { NVIF_CLASS_VMM_NV50 , -1 },
212 { NVIF_CLASS_VMM_NV04 , -1 },
215 u64 device = nouveau_name(drm->dev);
218 snprintf(cli->name, sizeof(cli->name), "%s", sname);
220 mutex_init(&cli->mutex);
221 usif_client_init(cli);
223 INIT_WORK(&cli->work, nouveau_cli_work);
224 INIT_LIST_HEAD(&cli->worker);
225 mutex_init(&cli->lock);
227 if (cli == &drm->master) {
228 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
229 cli->name, device, &cli->base);
231 mutex_lock(&drm->master.lock);
232 ret = nvif_client_init(&drm->master.base, cli->name, device,
234 mutex_unlock(&drm->master.lock);
237 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
241 ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE,
242 &(struct nv_device_v0) {
244 }, sizeof(struct nv_device_v0),
247 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
251 ret = nvif_mclass(&cli->device.object, mmus);
253 NV_PRINTK(err, cli, "No supported MMU class\n");
257 ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu);
259 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
263 ret = nvif_mclass(&cli->mmu.object, vmms);
265 NV_PRINTK(err, cli, "No supported VMM class\n");
269 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
271 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
275 ret = nvif_mclass(&cli->mmu.object, mems);
277 NV_PRINTK(err, cli, "No supported MEM class\n");
281 cli->mem = &mems[ret];
285 nouveau_cli_fini(cli);
290 nouveau_accel_ce_fini(struct nouveau_drm *drm)
292 nouveau_channel_idle(drm->cechan);
293 nvif_object_fini(&drm->ttm.copy);
294 nouveau_channel_del(&drm->cechan);
298 nouveau_accel_ce_init(struct nouveau_drm *drm)
300 struct nvif_device *device = &drm->client.device;
303 /* Allocate channel that has access to a (preferably async) copy
304 * engine, to use for TTM buffer moves.
306 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
307 ret = nouveau_channel_new(drm, device,
308 nvif_fifo_runlist_ce(device), 0,
311 if (device->info.chipset >= 0xa3 &&
312 device->info.chipset != 0xaa &&
313 device->info.chipset != 0xac) {
314 /* Prior to Kepler, there's only a single runlist, so all
315 * engines can be accessed from any channel.
317 * We still want to use a separate channel though.
319 ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false,
324 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
328 nouveau_accel_gr_fini(struct nouveau_drm *drm)
330 nouveau_channel_idle(drm->channel);
331 nvif_object_fini(&drm->ntfy);
332 nvkm_gpuobj_del(&drm->notify);
333 nvif_object_fini(&drm->nvsw);
334 nouveau_channel_del(&drm->channel);
338 nouveau_accel_gr_init(struct nouveau_drm *drm)
340 struct nvif_device *device = &drm->client.device;
344 /* Allocate channel that has access to the graphics engine. */
345 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
346 arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR);
353 ret = nouveau_channel_new(drm, device, arg0, arg1, false,
356 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
357 nouveau_accel_gr_fini(drm);
361 /* A SW class is used on pre-NV50 HW to assist with handling the
362 * synchronisation of page flips, as well as to implement fences
363 * on TNT/TNT2 HW that lacks any kind of support in host.
365 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
366 ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW,
367 nouveau_abi16_swclass(drm), NULL, 0,
370 ret = RING_SPACE(drm->channel, 2);
372 BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
373 OUT_RING (drm->channel, drm->nvsw.handle);
378 NV_ERROR(drm, "failed to allocate sw class, %d\n", ret);
379 nouveau_accel_gr_fini(drm);
384 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
385 * even if notification is never requested, so, allocate a ctxdma on
386 * any GPU where it's possible we'll end up using M2MF for BO moves.
388 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
389 ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL,
392 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
393 nouveau_accel_gr_fini(drm);
397 ret = nvif_object_init(&drm->channel->user, NvNotify0,
399 &(struct nv_dma_v0) {
400 .target = NV_DMA_V0_TARGET_VRAM,
401 .access = NV_DMA_V0_ACCESS_RDWR,
402 .start = drm->notify->addr,
403 .limit = drm->notify->addr + 31
404 }, sizeof(struct nv_dma_v0),
407 nouveau_accel_gr_fini(drm);
414 nouveau_accel_fini(struct nouveau_drm *drm)
416 nouveau_accel_ce_fini(drm);
417 nouveau_accel_gr_fini(drm);
419 nouveau_fence(drm)->dtor(drm);
423 nouveau_accel_init(struct nouveau_drm *drm)
425 struct nvif_device *device = &drm->client.device;
426 struct nvif_sclass *sclass;
432 /* Initialise global support for channels, and synchronisation. */
433 ret = nouveau_channels_init(drm);
437 /*XXX: this is crap, but the fence/channel stuff is a little
438 * backwards in some places. this will be fixed.
440 ret = n = nvif_object_sclass_get(&device->object, &sclass);
444 for (ret = -ENOSYS, i = 0; i < n; i++) {
445 switch (sclass[i].oclass) {
446 case NV03_CHANNEL_DMA:
447 ret = nv04_fence_create(drm);
449 case NV10_CHANNEL_DMA:
450 ret = nv10_fence_create(drm);
452 case NV17_CHANNEL_DMA:
453 case NV40_CHANNEL_DMA:
454 ret = nv17_fence_create(drm);
456 case NV50_CHANNEL_GPFIFO:
457 ret = nv50_fence_create(drm);
459 case G82_CHANNEL_GPFIFO:
460 ret = nv84_fence_create(drm);
462 case FERMI_CHANNEL_GPFIFO:
463 case KEPLER_CHANNEL_GPFIFO_A:
464 case KEPLER_CHANNEL_GPFIFO_B:
465 case MAXWELL_CHANNEL_GPFIFO_A:
466 case PASCAL_CHANNEL_GPFIFO_A:
467 case VOLTA_CHANNEL_GPFIFO_A:
468 case TURING_CHANNEL_GPFIFO_A:
469 ret = nvc0_fence_create(drm);
476 nvif_object_sclass_put(&sclass);
478 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
479 nouveau_accel_fini(drm);
483 /* Volta requires access to a doorbell register for kickoff. */
484 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
485 ret = nvif_user_init(device);
490 /* Allocate channels we need to support various functions. */
491 nouveau_accel_gr_init(drm);
492 nouveau_accel_ce_init(drm);
494 /* Initialise accelerated TTM buffer moves. */
495 nouveau_bo_move_init(drm);
499 nouveau_drm_device_init(struct drm_device *dev)
501 struct nouveau_drm *drm;
504 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
506 dev->dev_private = drm;
509 ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
513 ret = nouveau_cli_init(drm, "DRM", &drm->client);
517 dev->irq_enabled = true;
519 nvxx_client(&drm->client.base)->debug =
520 nvkm_dbgopt(nouveau_debug, "DRM");
522 INIT_LIST_HEAD(&drm->clients);
523 spin_lock_init(&drm->tile.lock);
525 /* workaround an odd issue on nvc1 by disabling the device's
526 * nosnoop capability. hopefully won't cause issues until a
527 * better fix is found - assuming there is one...
529 if (drm->client.device.info.chipset == 0xc1)
530 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
532 nouveau_vga_init(drm);
534 ret = nouveau_ttm_init(drm);
538 ret = nouveau_bios_init(dev);
542 nouveau_accel_init(drm);
544 ret = nouveau_display_create(dev);
548 if (dev->mode_config.num_crtc) {
549 ret = nouveau_display_init(dev, false, false);
554 nouveau_debugfs_init(drm);
555 nouveau_hwmon_init(dev);
556 nouveau_svm_init(drm);
557 nouveau_dmem_init(drm);
558 nouveau_fbcon_init(dev);
559 nouveau_led_init(dev);
561 if (nouveau_pmops_runtime()) {
562 pm_runtime_use_autosuspend(dev->dev);
563 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
564 pm_runtime_set_active(dev->dev);
565 pm_runtime_allow(dev->dev);
566 pm_runtime_mark_last_busy(dev->dev);
567 pm_runtime_put(dev->dev);
573 nouveau_display_destroy(dev);
575 nouveau_accel_fini(drm);
576 nouveau_bios_takedown(dev);
578 nouveau_ttm_fini(drm);
580 nouveau_vga_fini(drm);
581 nouveau_cli_fini(&drm->client);
583 nouveau_cli_fini(&drm->master);
590 nouveau_drm_device_fini(struct drm_device *dev)
592 struct nouveau_drm *drm = nouveau_drm(dev);
594 if (nouveau_pmops_runtime()) {
595 pm_runtime_get_sync(dev->dev);
596 pm_runtime_forbid(dev->dev);
599 nouveau_led_fini(dev);
600 nouveau_fbcon_fini(dev);
601 nouveau_dmem_fini(drm);
602 nouveau_svm_fini(drm);
603 nouveau_hwmon_fini(dev);
604 nouveau_debugfs_fini(drm);
606 if (dev->mode_config.num_crtc)
607 nouveau_display_fini(dev, false, false);
608 nouveau_display_destroy(dev);
610 nouveau_accel_fini(drm);
611 nouveau_bios_takedown(dev);
613 nouveau_ttm_fini(drm);
614 nouveau_vga_fini(drm);
616 nouveau_cli_fini(&drm->client);
617 nouveau_cli_fini(&drm->master);
622 * On some Intel PCIe bridge controllers doing a
623 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear.
624 * Skipping the intermediate D3hot step seems to make it work again. This is
625 * probably caused by not meeting the expectation the involved AML code has
626 * when the GPU is put into D3hot state before invoking it.
628 * This leads to various manifestations of this issue:
629 * - AML code execution to power on the GPU hits an infinite loop (as the
630 * code waits on device memory to change).
631 * - kernel crashes, as all PCI reads return -1, which most code isn't able
632 * to handle well enough.
634 * In all cases dmesg will contain at least one line like this:
635 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3'
636 * followed by a lot of nouveau timeouts.
638 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
639 * documented PCI config space register 0x248 of the Intel PCIe bridge
640 * controller (0x1901) in order to change the state of the PCIe link between
641 * the PCIe port and the GPU. There are alternative code paths using other
642 * registers, which seem to work fine (executed pre Windows 8):
643 * - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
644 * - 0xb0 bit 0x10 (link disable)
645 * Changing the conditions inside the firmware by poking into the relevant
646 * addresses does resolve the issue, but it seemed to be ACPI private memory
647 * and not any device accessible memory at all, so there is no portable way of
648 * changing the conditions.
649 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
651 * The only systems where this behavior can be seen are hybrid graphics laptops
652 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether
653 * this issue only occurs in combination with listed Intel PCIe bridge
654 * controllers and the mentioned GPUs or other devices as well.
656 * documentation on the PCIe bridge controller can be found in the
657 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2"
658 * Section "12 PCI Express* Controller (x16) Registers"
661 static void quirk_broken_nv_runpm(struct pci_dev *pdev)
663 struct drm_device *dev = pci_get_drvdata(pdev);
664 struct nouveau_drm *drm = nouveau_drm(dev);
665 struct pci_dev *bridge = pci_upstream_bridge(pdev);
667 if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL)
670 switch (bridge->device) {
672 drm->old_pm_cap = pdev->pm_cap;
674 NV_INFO(drm, "Disabling PCI power management to avoid bug\n");
679 static int nouveau_drm_probe(struct pci_dev *pdev,
680 const struct pci_device_id *pent)
682 struct nvkm_device *device;
683 struct drm_device *drm_dev;
684 struct apertures_struct *aper;
688 if (vga_switcheroo_client_probe_defer(pdev))
689 return -EPROBE_DEFER;
691 /* We need to check that the chipset is supported before booting
692 * fbdev off the hardware, as there's no way to put it back.
694 ret = nvkm_device_pci_new(pdev, nouveau_config, "error",
695 true, false, 0, &device);
699 nvkm_device_del(&device);
701 /* Remove conflicting drivers (vesafb, efifb etc). */
702 aper = alloc_apertures(3);
706 aper->ranges[0].base = pci_resource_start(pdev, 1);
707 aper->ranges[0].size = pci_resource_len(pdev, 1);
710 if (pci_resource_len(pdev, 2)) {
711 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
712 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
716 if (pci_resource_len(pdev, 3)) {
717 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
718 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
723 boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
725 if (nouveau_modeset != 2)
726 drm_fb_helper_remove_conflicting_framebuffers(aper, "nouveaufb", boot);
729 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
730 true, true, ~0ULL, &device);
734 pci_set_master(pdev);
737 driver_pci.driver_features |= DRIVER_ATOMIC;
739 drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev);
740 if (IS_ERR(drm_dev)) {
741 ret = PTR_ERR(drm_dev);
745 ret = pci_enable_device(pdev);
749 drm_dev->pdev = pdev;
750 pci_set_drvdata(pdev, drm_dev);
752 ret = nouveau_drm_device_init(drm_dev);
756 ret = drm_dev_register(drm_dev, pent->driver_data);
758 goto fail_drm_dev_init;
760 quirk_broken_nv_runpm(pdev);
764 nouveau_drm_device_fini(drm_dev);
766 pci_disable_device(pdev);
768 drm_dev_put(drm_dev);
770 nvkm_device_del(&device);
775 nouveau_drm_device_remove(struct drm_device *dev)
777 struct nouveau_drm *drm = nouveau_drm(dev);
778 struct nvkm_client *client;
779 struct nvkm_device *device;
781 drm_dev_unregister(dev);
783 dev->irq_enabled = false;
784 client = nvxx_client(&drm->client.base);
785 device = nvkm_device_find(client->device);
787 nouveau_drm_device_fini(dev);
789 nvkm_device_del(&device);
793 nouveau_drm_remove(struct pci_dev *pdev)
795 struct drm_device *dev = pci_get_drvdata(pdev);
796 struct nouveau_drm *drm = nouveau_drm(dev);
798 /* revert our workaround */
800 pdev->pm_cap = drm->old_pm_cap;
801 nouveau_drm_device_remove(dev);
802 pci_disable_device(pdev);
806 nouveau_do_suspend(struct drm_device *dev, bool runtime)
808 struct nouveau_drm *drm = nouveau_drm(dev);
811 nouveau_svm_suspend(drm);
812 nouveau_dmem_suspend(drm);
813 nouveau_led_suspend(dev);
815 if (dev->mode_config.num_crtc) {
816 NV_DEBUG(drm, "suspending console...\n");
817 nouveau_fbcon_set_suspend(dev, 1);
818 NV_DEBUG(drm, "suspending display...\n");
819 ret = nouveau_display_suspend(dev, runtime);
824 NV_DEBUG(drm, "evicting buffers...\n");
825 ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
827 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
829 ret = nouveau_channel_idle(drm->cechan);
835 ret = nouveau_channel_idle(drm->channel);
840 NV_DEBUG(drm, "suspending fence...\n");
841 if (drm->fence && nouveau_fence(drm)->suspend) {
842 if (!nouveau_fence(drm)->suspend(drm)) {
848 NV_DEBUG(drm, "suspending object tree...\n");
849 ret = nvif_client_suspend(&drm->master.base);
856 if (drm->fence && nouveau_fence(drm)->resume)
857 nouveau_fence(drm)->resume(drm);
860 if (dev->mode_config.num_crtc) {
861 NV_DEBUG(drm, "resuming display...\n");
862 nouveau_display_resume(dev, runtime);
868 nouveau_do_resume(struct drm_device *dev, bool runtime)
871 struct nouveau_drm *drm = nouveau_drm(dev);
873 NV_DEBUG(drm, "resuming object tree...\n");
874 ret = nvif_client_resume(&drm->master.base);
876 NV_ERROR(drm, "Client resume failed with error: %d\n", ret);
880 NV_DEBUG(drm, "resuming fence...\n");
881 if (drm->fence && nouveau_fence(drm)->resume)
882 nouveau_fence(drm)->resume(drm);
884 nouveau_run_vbios_init(dev);
886 if (dev->mode_config.num_crtc) {
887 NV_DEBUG(drm, "resuming display...\n");
888 nouveau_display_resume(dev, runtime);
889 NV_DEBUG(drm, "resuming console...\n");
890 nouveau_fbcon_set_suspend(dev, 0);
893 nouveau_led_resume(dev);
894 nouveau_dmem_resume(drm);
895 nouveau_svm_resume(drm);
900 nouveau_pmops_suspend(struct device *dev)
902 struct pci_dev *pdev = to_pci_dev(dev);
903 struct drm_device *drm_dev = pci_get_drvdata(pdev);
906 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
907 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
910 ret = nouveau_do_suspend(drm_dev, false);
914 pci_save_state(pdev);
915 pci_disable_device(pdev);
916 pci_set_power_state(pdev, PCI_D3hot);
922 nouveau_pmops_resume(struct device *dev)
924 struct pci_dev *pdev = to_pci_dev(dev);
925 struct drm_device *drm_dev = pci_get_drvdata(pdev);
928 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
929 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
932 pci_set_power_state(pdev, PCI_D0);
933 pci_restore_state(pdev);
934 ret = pci_enable_device(pdev);
937 pci_set_master(pdev);
939 ret = nouveau_do_resume(drm_dev, false);
941 /* Monitors may have been connected / disconnected during suspend */
942 schedule_work(&nouveau_drm(drm_dev)->hpd_work);
948 nouveau_pmops_freeze(struct device *dev)
950 struct pci_dev *pdev = to_pci_dev(dev);
951 struct drm_device *drm_dev = pci_get_drvdata(pdev);
952 return nouveau_do_suspend(drm_dev, false);
956 nouveau_pmops_thaw(struct device *dev)
958 struct pci_dev *pdev = to_pci_dev(dev);
959 struct drm_device *drm_dev = pci_get_drvdata(pdev);
960 return nouveau_do_resume(drm_dev, false);
964 nouveau_pmops_runtime(void)
966 if (nouveau_runtime_pm == -1)
967 return nouveau_is_optimus() || nouveau_is_v1_dsm();
968 return nouveau_runtime_pm == 1;
972 nouveau_pmops_runtime_suspend(struct device *dev)
974 struct pci_dev *pdev = to_pci_dev(dev);
975 struct drm_device *drm_dev = pci_get_drvdata(pdev);
978 if (!nouveau_pmops_runtime()) {
979 pm_runtime_forbid(dev);
983 nouveau_switcheroo_optimus_dsm();
984 ret = nouveau_do_suspend(drm_dev, true);
985 pci_save_state(pdev);
986 pci_disable_device(pdev);
987 pci_ignore_hotplug(pdev);
988 pci_set_power_state(pdev, PCI_D3cold);
989 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
994 nouveau_pmops_runtime_resume(struct device *dev)
996 struct pci_dev *pdev = to_pci_dev(dev);
997 struct drm_device *drm_dev = pci_get_drvdata(pdev);
998 struct nouveau_drm *drm = nouveau_drm(drm_dev);
999 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
1002 if (!nouveau_pmops_runtime()) {
1003 pm_runtime_forbid(dev);
1007 pci_set_power_state(pdev, PCI_D0);
1008 pci_restore_state(pdev);
1009 ret = pci_enable_device(pdev);
1012 pci_set_master(pdev);
1014 ret = nouveau_do_resume(drm_dev, true);
1016 NV_ERROR(drm, "resume failed with: %d\n", ret);
1021 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
1022 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1024 /* Monitors may have been connected / disconnected during suspend */
1025 schedule_work(&nouveau_drm(drm_dev)->hpd_work);
1031 nouveau_pmops_runtime_idle(struct device *dev)
1033 if (!nouveau_pmops_runtime()) {
1034 pm_runtime_forbid(dev);
1038 pm_runtime_mark_last_busy(dev);
1039 pm_runtime_autosuspend(dev);
1040 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1045 nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
1047 struct nouveau_drm *drm = nouveau_drm(dev);
1048 struct nouveau_cli *cli;
1049 char name[32], tmpname[TASK_COMM_LEN];
1052 /* need to bring up power immediately if opening device */
1053 ret = pm_runtime_get_sync(dev->dev);
1054 if (ret < 0 && ret != -EACCES)
1057 get_task_comm(tmpname, current);
1058 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
1060 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) {
1065 ret = nouveau_cli_init(drm, name, cli);
1069 cli->base.super = false;
1071 fpriv->driver_priv = cli;
1073 mutex_lock(&drm->client.mutex);
1074 list_add(&cli->head, &drm->clients);
1075 mutex_unlock(&drm->client.mutex);
1079 nouveau_cli_fini(cli);
1083 pm_runtime_mark_last_busy(dev->dev);
1084 pm_runtime_put_autosuspend(dev->dev);
1089 nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
1091 struct nouveau_cli *cli = nouveau_cli(fpriv);
1092 struct nouveau_drm *drm = nouveau_drm(dev);
1094 pm_runtime_get_sync(dev->dev);
1096 mutex_lock(&cli->mutex);
1098 nouveau_abi16_fini(cli->abi16);
1099 mutex_unlock(&cli->mutex);
1101 mutex_lock(&drm->client.mutex);
1102 list_del(&cli->head);
1103 mutex_unlock(&drm->client.mutex);
1105 nouveau_cli_fini(cli);
1107 pm_runtime_mark_last_busy(dev->dev);
1108 pm_runtime_put_autosuspend(dev->dev);
1111 static const struct drm_ioctl_desc
1112 nouveau_ioctls[] = {
1113 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW),
1114 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1115 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW),
1116 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW),
1117 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW),
1118 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW),
1119 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW),
1120 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW),
1121 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW),
1122 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW),
1123 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW),
1124 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW),
1125 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW),
1126 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW),
1130 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1132 struct drm_file *filp = file->private_data;
1133 struct drm_device *dev = filp->minor->dev;
1136 ret = pm_runtime_get_sync(dev->dev);
1137 if (ret < 0 && ret != -EACCES)
1140 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1141 case DRM_NOUVEAU_NVIF:
1142 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1145 ret = drm_ioctl(file, cmd, arg);
1149 pm_runtime_mark_last_busy(dev->dev);
1150 pm_runtime_put_autosuspend(dev->dev);
1154 static const struct file_operations
1155 nouveau_driver_fops = {
1156 .owner = THIS_MODULE,
1158 .release = drm_release,
1159 .unlocked_ioctl = nouveau_drm_ioctl,
1160 .mmap = nouveau_ttm_mmap,
1163 #if defined(CONFIG_COMPAT)
1164 .compat_ioctl = nouveau_compat_ioctl,
1166 .llseek = noop_llseek,
1169 static struct drm_driver
1172 DRIVER_GEM | DRIVER_MODESET | DRIVER_RENDER
1173 #if defined(CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT)
1174 | DRIVER_KMS_LEGACY_CONTEXT
1178 .open = nouveau_drm_open,
1179 .postclose = nouveau_drm_postclose,
1180 .lastclose = nouveau_vga_lastclose,
1182 #if defined(CONFIG_DEBUG_FS)
1183 .debugfs_init = nouveau_drm_debugfs_init,
1186 .ioctls = nouveau_ioctls,
1187 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
1188 .fops = &nouveau_driver_fops,
1190 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1191 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1192 .gem_prime_pin = nouveau_gem_prime_pin,
1193 .gem_prime_unpin = nouveau_gem_prime_unpin,
1194 .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
1195 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1196 .gem_prime_vmap = nouveau_gem_prime_vmap,
1197 .gem_prime_vunmap = nouveau_gem_prime_vunmap,
1199 .gem_free_object_unlocked = nouveau_gem_object_del,
1200 .gem_open_object = nouveau_gem_object_open,
1201 .gem_close_object = nouveau_gem_object_close,
1203 .dumb_create = nouveau_display_dumb_create,
1204 .dumb_map_offset = nouveau_display_dumb_map_offset,
1206 .name = DRIVER_NAME,
1207 .desc = DRIVER_DESC,
1209 .date = GIT_REVISION,
1211 .date = DRIVER_DATE,
1213 .major = DRIVER_MAJOR,
1214 .minor = DRIVER_MINOR,
1215 .patchlevel = DRIVER_PATCHLEVEL,
1218 static struct pci_device_id
1219 nouveau_drm_pci_table[] = {
1221 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1222 .class = PCI_BASE_CLASS_DISPLAY << 16,
1223 .class_mask = 0xff << 16,
1226 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1227 .class = PCI_BASE_CLASS_DISPLAY << 16,
1228 .class_mask = 0xff << 16,
1233 static void nouveau_display_options(void)
1235 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1237 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1238 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1239 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1240 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
1241 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1242 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1243 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1244 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1245 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1246 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
1247 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
1250 static const struct dev_pm_ops nouveau_pm_ops = {
1251 .suspend = nouveau_pmops_suspend,
1252 .resume = nouveau_pmops_resume,
1253 .freeze = nouveau_pmops_freeze,
1254 .thaw = nouveau_pmops_thaw,
1255 .poweroff = nouveau_pmops_freeze,
1256 .restore = nouveau_pmops_resume,
1257 .runtime_suspend = nouveau_pmops_runtime_suspend,
1258 .runtime_resume = nouveau_pmops_runtime_resume,
1259 .runtime_idle = nouveau_pmops_runtime_idle,
1262 static struct pci_driver
1263 nouveau_drm_pci_driver = {
1265 .id_table = nouveau_drm_pci_table,
1266 .probe = nouveau_drm_probe,
1267 .remove = nouveau_drm_remove,
1268 .driver.pm = &nouveau_pm_ops,
1272 nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1273 struct platform_device *pdev,
1274 struct nvkm_device **pdevice)
1276 struct drm_device *drm;
1279 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
1280 true, true, ~0ULL, pdevice);
1284 drm = drm_dev_alloc(&driver_platform, &pdev->dev);
1290 err = nouveau_drm_device_init(drm);
1294 platform_set_drvdata(pdev, drm);
1301 nvkm_device_del(pdevice);
1303 return ERR_PTR(err);
1307 nouveau_drm_init(void)
1309 driver_pci = driver_stub;
1310 driver_platform = driver_stub;
1312 nouveau_display_options();
1314 if (nouveau_modeset == -1) {
1315 if (vgacon_text_force())
1316 nouveau_modeset = 0;
1319 if (!nouveau_modeset)
1322 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1323 platform_driver_register(&nouveau_platform_driver);
1326 nouveau_register_dsm_handler();
1327 nouveau_backlight_ctor();
1330 return pci_register_driver(&nouveau_drm_pci_driver);
1337 nouveau_drm_exit(void)
1339 if (!nouveau_modeset)
1343 pci_unregister_driver(&nouveau_drm_pci_driver);
1345 nouveau_backlight_dtor();
1346 nouveau_unregister_dsm_handler();
1348 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1349 platform_driver_unregister(&nouveau_platform_driver);
1351 if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM))
1352 mmu_notifier_synchronize();
1355 module_init(nouveau_drm_init);
1356 module_exit(nouveau_drm_exit);
1358 MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
1359 MODULE_AUTHOR(DRIVER_AUTHOR);
1360 MODULE_DESCRIPTION(DRIVER_DESC);
1361 MODULE_LICENSE("GPL and additional rights");