drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_pm.h"
  40 #include "nv50_display.h"
  41
  42 static void nouveau_stub_takedown(struct drm_device *dev) {}
  43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  44
  45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  46 {
  47         struct drm_nouveau_private *dev_priv = dev->dev_private;
  48         struct nouveau_engine *engine = &dev_priv->engine;
  49
  50         switch (dev_priv->chipset & 0xf0) {
  51         case 0x00:
  52                 engine->instmem.init            = nv04_instmem_init;
  53                 engine->instmem.takedown        = nv04_instmem_takedown;
  54                 engine->instmem.suspend         = nv04_instmem_suspend;
  55                 engine->instmem.resume          = nv04_instmem_resume;
  56                 engine->instmem.get             = nv04_instmem_get;
  57                 engine->instmem.put             = nv04_instmem_put;
  58                 engine->instmem.map             = nv04_instmem_map;
  59                 engine->instmem.unmap           = nv04_instmem_unmap;
  60                 engine->instmem.flush           = nv04_instmem_flush;
  61                 engine->mc.init                 = nv04_mc_init;
  62                 engine->mc.takedown             = nv04_mc_takedown;
  63                 engine->timer.init              = nv04_timer_init;
  64                 engine->timer.read              = nv04_timer_read;
  65                 engine->timer.takedown          = nv04_timer_takedown;
  66                 engine->fb.init                 = nv04_fb_init;
  67                 engine->fb.takedown             = nv04_fb_takedown;
  68                 engine->fifo.channels           = 16;
  69                 engine->fifo.init               = nv04_fifo_init;
  70                 engine->fifo.takedown           = nv04_fifo_fini;
  71                 engine->fifo.disable            = nv04_fifo_disable;
  72                 engine->fifo.enable             = nv04_fifo_enable;
  73                 engine->fifo.reassign           = nv04_fifo_reassign;
  74                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  75                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  76                 engine->fifo.create_context     = nv04_fifo_create_context;
  77                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  78                 engine->fifo.load_context       = nv04_fifo_load_context;
  79                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  80                 engine->display.early_init      = nv04_display_early_init;
  81                 engine->display.late_takedown   = nv04_display_late_takedown;
  82                 engine->display.create          = nv04_display_create;
  83                 engine->display.init            = nv04_display_init;
  84                 engine->display.destroy         = nv04_display_destroy;
  85                 engine->gpio.init               = nouveau_stub_init;
  86                 engine->gpio.takedown           = nouveau_stub_takedown;
  87                 engine->gpio.get                = NULL;
  88                 engine->gpio.set                = NULL;
  89                 engine->gpio.irq_enable         = NULL;
  90                 engine->pm.clock_get            = nv04_pm_clock_get;
  91                 engine->pm.clock_pre            = nv04_pm_clock_pre;
  92                 engine->pm.clock_set            = nv04_pm_clock_set;
  93                 engine->vram.init               = nouveau_mem_detect;
  94                 engine->vram.takedown           = nouveau_stub_takedown;
  95                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
  96                 break;
  97         case 0x10:
  98                 engine->instmem.init            = nv04_instmem_init;
  99                 engine->instmem.takedown        = nv04_instmem_takedown;
 100                 engine->instmem.suspend         = nv04_instmem_suspend;
 101                 engine->instmem.resume          = nv04_instmem_resume;
 102                 engine->instmem.get             = nv04_instmem_get;
 103                 engine->instmem.put             = nv04_instmem_put;
 104                 engine->instmem.map             = nv04_instmem_map;
 105                 engine->instmem.unmap           = nv04_instmem_unmap;
 106                 engine->instmem.flush           = nv04_instmem_flush;
 107                 engine->mc.init                 = nv04_mc_init;
 108                 engine->mc.takedown             = nv04_mc_takedown;
 109                 engine->timer.init              = nv04_timer_init;
 110                 engine->timer.read              = nv04_timer_read;
 111                 engine->timer.takedown          = nv04_timer_takedown;
 112                 engine->fb.init                 = nv10_fb_init;
 113                 engine->fb.takedown             = nv10_fb_takedown;
 114                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 115                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 116                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 117                 engine->fifo.channels           = 32;
 118                 engine->fifo.init               = nv10_fifo_init;
 119                 engine->fifo.takedown           = nv04_fifo_fini;
 120                 engine->fifo.disable            = nv04_fifo_disable;
 121                 engine->fifo.enable             = nv04_fifo_enable;
 122                 engine->fifo.reassign           = nv04_fifo_reassign;
 123                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 124                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 125                 engine->fifo.create_context     = nv10_fifo_create_context;
 126                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 127                 engine->fifo.load_context       = nv10_fifo_load_context;
 128                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 129                 engine->display.early_init      = nv04_display_early_init;
 130                 engine->display.late_takedown   = nv04_display_late_takedown;
 131                 engine->display.create          = nv04_display_create;
 132                 engine->display.init            = nv04_display_init;
 133                 engine->display.destroy         = nv04_display_destroy;
 134                 engine->gpio.init               = nouveau_stub_init;
 135                 engine->gpio.takedown           = nouveau_stub_takedown;
 136                 engine->gpio.get                = nv10_gpio_get;
 137                 engine->gpio.set                = nv10_gpio_set;
 138                 engine->gpio.irq_enable         = NULL;
 139                 engine->pm.clock_get            = nv04_pm_clock_get;
 140                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 141                 engine->pm.clock_set            = nv04_pm_clock_set;
 142                 engine->vram.init               = nouveau_mem_detect;
 143                 engine->vram.takedown           = nouveau_stub_takedown;
 144                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 145                 break;
 146         case 0x20:
 147                 engine->instmem.init            = nv04_instmem_init;
 148                 engine->instmem.takedown        = nv04_instmem_takedown;
 149                 engine->instmem.suspend         = nv04_instmem_suspend;
 150                 engine->instmem.resume          = nv04_instmem_resume;
 151                 engine->instmem.get             = nv04_instmem_get;
 152                 engine->instmem.put             = nv04_instmem_put;
 153                 engine->instmem.map             = nv04_instmem_map;
 154                 engine->instmem.unmap           = nv04_instmem_unmap;
 155                 engine->instmem.flush           = nv04_instmem_flush;
 156                 engine->mc.init                 = nv04_mc_init;
 157                 engine->mc.takedown             = nv04_mc_takedown;
 158                 engine->timer.init              = nv04_timer_init;
 159                 engine->timer.read              = nv04_timer_read;
 160                 engine->timer.takedown          = nv04_timer_takedown;
 161                 engine->fb.init                 = nv10_fb_init;
 162                 engine->fb.takedown             = nv10_fb_takedown;
 163                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 164                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 165                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 166                 engine->fifo.channels           = 32;
 167                 engine->fifo.init               = nv10_fifo_init;
 168                 engine->fifo.takedown           = nv04_fifo_fini;
 169                 engine->fifo.disable            = nv04_fifo_disable;
 170                 engine->fifo.enable             = nv04_fifo_enable;
 171                 engine->fifo.reassign           = nv04_fifo_reassign;
 172                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 173                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 174                 engine->fifo.create_context     = nv10_fifo_create_context;
 175                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 176                 engine->fifo.load_context       = nv10_fifo_load_context;
 177                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 178                 engine->display.early_init      = nv04_display_early_init;
 179                 engine->display.late_takedown   = nv04_display_late_takedown;
 180                 engine->display.create          = nv04_display_create;
 181                 engine->display.init            = nv04_display_init;
 182                 engine->display.destroy         = nv04_display_destroy;
 183                 engine->gpio.init               = nouveau_stub_init;
 184                 engine->gpio.takedown           = nouveau_stub_takedown;
 185                 engine->gpio.get                = nv10_gpio_get;
 186                 engine->gpio.set                = nv10_gpio_set;
 187                 engine->gpio.irq_enable         = NULL;
 188                 engine->pm.clock_get            = nv04_pm_clock_get;
 189                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 190                 engine->pm.clock_set            = nv04_pm_clock_set;
 191                 engine->vram.init               = nouveau_mem_detect;
 192                 engine->vram.takedown           = nouveau_stub_takedown;
 193                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 194                 break;
 195         case 0x30:
 196                 engine->instmem.init            = nv04_instmem_init;
 197                 engine->instmem.takedown        = nv04_instmem_takedown;
 198                 engine->instmem.suspend         = nv04_instmem_suspend;
 199                 engine->instmem.resume          = nv04_instmem_resume;
 200                 engine->instmem.get             = nv04_instmem_get;
 201                 engine->instmem.put             = nv04_instmem_put;
 202                 engine->instmem.map             = nv04_instmem_map;
 203                 engine->instmem.unmap           = nv04_instmem_unmap;
 204                 engine->instmem.flush           = nv04_instmem_flush;
 205                 engine->mc.init                 = nv04_mc_init;
 206                 engine->mc.takedown             = nv04_mc_takedown;
 207                 engine->timer.init              = nv04_timer_init;
 208                 engine->timer.read              = nv04_timer_read;
 209                 engine->timer.takedown          = nv04_timer_takedown;
 210                 engine->fb.init                 = nv30_fb_init;
 211                 engine->fb.takedown             = nv30_fb_takedown;
 212                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 213                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 214                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 215                 engine->fifo.channels           = 32;
 216                 engine->fifo.init               = nv10_fifo_init;
 217                 engine->fifo.takedown           = nv04_fifo_fini;
 218                 engine->fifo.disable            = nv04_fifo_disable;
 219                 engine->fifo.enable             = nv04_fifo_enable;
 220                 engine->fifo.reassign           = nv04_fifo_reassign;
 221                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 222                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 223                 engine->fifo.create_context     = nv10_fifo_create_context;
 224                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 225                 engine->fifo.load_context       = nv10_fifo_load_context;
 226                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 227                 engine->display.early_init      = nv04_display_early_init;
 228                 engine->display.late_takedown   = nv04_display_late_takedown;
 229                 engine->display.create          = nv04_display_create;
 230                 engine->display.init            = nv04_display_init;
 231                 engine->display.destroy         = nv04_display_destroy;
 232                 engine->gpio.init               = nouveau_stub_init;
 233                 engine->gpio.takedown           = nouveau_stub_takedown;
 234                 engine->gpio.get                = nv10_gpio_get;
 235                 engine->gpio.set                = nv10_gpio_set;
 236                 engine->gpio.irq_enable         = NULL;
 237                 engine->pm.clock_get            = nv04_pm_clock_get;
 238                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 239                 engine->pm.clock_set            = nv04_pm_clock_set;
 240                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 241                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 242                 engine->vram.init               = nouveau_mem_detect;
 243                 engine->vram.takedown           = nouveau_stub_takedown;
 244                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 245                 break;
 246         case 0x40:
 247         case 0x60:
 248                 engine->instmem.init            = nv04_instmem_init;
 249                 engine->instmem.takedown        = nv04_instmem_takedown;
 250                 engine->instmem.suspend         = nv04_instmem_suspend;
 251                 engine->instmem.resume          = nv04_instmem_resume;
 252                 engine->instmem.get             = nv04_instmem_get;
 253                 engine->instmem.put             = nv04_instmem_put;
 254                 engine->instmem.map             = nv04_instmem_map;
 255                 engine->instmem.unmap           = nv04_instmem_unmap;
 256                 engine->instmem.flush           = nv04_instmem_flush;
 257                 engine->mc.init                 = nv40_mc_init;
 258                 engine->mc.takedown             = nv40_mc_takedown;
 259                 engine->timer.init              = nv04_timer_init;
 260                 engine->timer.read              = nv04_timer_read;
 261                 engine->timer.takedown          = nv04_timer_takedown;
 262                 engine->fb.init                 = nv40_fb_init;
 263                 engine->fb.takedown             = nv40_fb_takedown;
 264                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 265                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 266                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 267                 engine->fifo.channels           = 32;
 268                 engine->fifo.init               = nv40_fifo_init;
 269                 engine->fifo.takedown           = nv04_fifo_fini;
 270                 engine->fifo.disable            = nv04_fifo_disable;
 271                 engine->fifo.enable             = nv04_fifo_enable;
 272                 engine->fifo.reassign           = nv04_fifo_reassign;
 273                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 274                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 275                 engine->fifo.create_context     = nv40_fifo_create_context;
 276                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 277                 engine->fifo.load_context       = nv40_fifo_load_context;
 278                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 279                 engine->display.early_init      = nv04_display_early_init;
 280                 engine->display.late_takedown   = nv04_display_late_takedown;
 281                 engine->display.create          = nv04_display_create;
 282                 engine->display.init            = nv04_display_init;
 283                 engine->display.destroy         = nv04_display_destroy;
 284                 engine->gpio.init               = nouveau_stub_init;
 285                 engine->gpio.takedown           = nouveau_stub_takedown;
 286                 engine->gpio.get                = nv10_gpio_get;
 287                 engine->gpio.set                = nv10_gpio_set;
 288                 engine->gpio.irq_enable         = NULL;
 289                 engine->pm.clock_get            = nv04_pm_clock_get;
 290                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 291                 engine->pm.clock_set            = nv04_pm_clock_set;
 292                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 293                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 294                 engine->pm.temp_get             = nv40_temp_get;
 295                 engine->vram.init               = nouveau_mem_detect;
 296                 engine->vram.takedown           = nouveau_stub_takedown;
 297                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 298                 break;
 299         case 0x50:
 300         case 0x80: /* gotta love NVIDIA's consistency.. */
 301         case 0x90:
 302         case 0xA0:
 303                 engine->instmem.init            = nv50_instmem_init;
 304                 engine->instmem.takedown        = nv50_instmem_takedown;
 305                 engine->instmem.suspend         = nv50_instmem_suspend;
 306                 engine->instmem.resume          = nv50_instmem_resume;
 307                 engine->instmem.get             = nv50_instmem_get;
 308                 engine->instmem.put             = nv50_instmem_put;
 309                 engine->instmem.map             = nv50_instmem_map;
 310                 engine->instmem.unmap           = nv50_instmem_unmap;
 311                 if (dev_priv->chipset == 0x50)
 312                         engine->instmem.flush   = nv50_instmem_flush;
 313                 else
 314                         engine->instmem.flush   = nv84_instmem_flush;
 315                 engine->mc.init                 = nv50_mc_init;
 316                 engine->mc.takedown             = nv50_mc_takedown;
 317                 engine->timer.init              = nv04_timer_init;
 318                 engine->timer.read              = nv04_timer_read;
 319                 engine->timer.takedown          = nv04_timer_takedown;
 320                 engine->fb.init                 = nv50_fb_init;
 321                 engine->fb.takedown             = nv50_fb_takedown;
 322                 engine->fifo.channels           = 128;
 323                 engine->fifo.init               = nv50_fifo_init;
 324                 engine->fifo.takedown           = nv50_fifo_takedown;
 325                 engine->fifo.disable            = nv04_fifo_disable;
 326                 engine->fifo.enable             = nv04_fifo_enable;
 327                 engine->fifo.reassign           = nv04_fifo_reassign;
 328                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 329                 engine->fifo.create_context     = nv50_fifo_create_context;
 330                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 331                 engine->fifo.load_context       = nv50_fifo_load_context;
 332                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 333                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 334                 engine->display.early_init      = nv50_display_early_init;
 335                 engine->display.late_takedown   = nv50_display_late_takedown;
 336                 engine->display.create          = nv50_display_create;
 337                 engine->display.init            = nv50_display_init;
 338                 engine->display.destroy         = nv50_display_destroy;
 339                 engine->gpio.init               = nv50_gpio_init;
 340                 engine->gpio.takedown           = nv50_gpio_fini;
 341                 engine->gpio.get                = nv50_gpio_get;
 342                 engine->gpio.set                = nv50_gpio_set;
 343                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 344                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 345                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 346                 switch (dev_priv->chipset) {
 347                 case 0x84:
 348                 case 0x86:
 349                 case 0x92:
 350                 case 0x94:
 351                 case 0x96:
 352                 case 0x98:
 353                 case 0xa0:
 354                 case 0xaa:
 355                 case 0xac:
 356                 case 0x50:
 357                         engine->pm.clock_get    = nv50_pm_clock_get;
 358                         engine->pm.clock_pre    = nv50_pm_clock_pre;
 359                         engine->pm.clock_set    = nv50_pm_clock_set;
 360                         break;
 361                 default:
 362                         engine->pm.clocks_get   = nva3_pm_clocks_get;
 363                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
 364                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 365                         break;
 366                 }
 367                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 368                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 369                 if (dev_priv->chipset >= 0x84)
 370                         engine->pm.temp_get     = nv84_temp_get;
 371                 else
 372                         engine->pm.temp_get     = nv40_temp_get;
 373                 engine->vram.init               = nv50_vram_init;
 374                 engine->vram.takedown           = nv50_vram_fini;
 375                 engine->vram.get                = nv50_vram_new;
 376                 engine->vram.put                = nv50_vram_del;
 377                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 378                 break;
 379         case 0xC0:
 380                 engine->instmem.init            = nvc0_instmem_init;
 381                 engine->instmem.takedown        = nvc0_instmem_takedown;
 382                 engine->instmem.suspend         = nvc0_instmem_suspend;
 383                 engine->instmem.resume          = nvc0_instmem_resume;
 384                 engine->instmem.get             = nv50_instmem_get;
 385                 engine->instmem.put             = nv50_instmem_put;
 386                 engine->instmem.map             = nv50_instmem_map;
 387                 engine->instmem.unmap           = nv50_instmem_unmap;
 388                 engine->instmem.flush           = nv84_instmem_flush;
 389                 engine->mc.init                 = nv50_mc_init;
 390                 engine->mc.takedown             = nv50_mc_takedown;
 391                 engine->timer.init              = nv04_timer_init;
 392                 engine->timer.read              = nv04_timer_read;
 393                 engine->timer.takedown          = nv04_timer_takedown;
 394                 engine->fb.init                 = nvc0_fb_init;
 395                 engine->fb.takedown             = nvc0_fb_takedown;
 396                 engine->fifo.channels           = 128;
 397                 engine->fifo.init               = nvc0_fifo_init;
 398                 engine->fifo.takedown           = nvc0_fifo_takedown;
 399                 engine->fifo.disable            = nvc0_fifo_disable;
 400                 engine->fifo.enable             = nvc0_fifo_enable;
 401                 engine->fifo.reassign           = nvc0_fifo_reassign;
 402                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 403                 engine->fifo.create_context     = nvc0_fifo_create_context;
 404                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 405                 engine->fifo.load_context       = nvc0_fifo_load_context;
 406                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 407                 engine->display.early_init      = nv50_display_early_init;
 408                 engine->display.late_takedown   = nv50_display_late_takedown;
 409                 engine->display.create          = nv50_display_create;
 410                 engine->display.init            = nv50_display_init;
 411                 engine->display.destroy         = nv50_display_destroy;
 412                 engine->gpio.init               = nv50_gpio_init;
 413                 engine->gpio.takedown           = nouveau_stub_takedown;
 414                 engine->gpio.get                = nv50_gpio_get;
 415                 engine->gpio.set                = nv50_gpio_set;
 416                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 417                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 418                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 419                 engine->vram.init               = nvc0_vram_init;
 420                 engine->vram.takedown           = nv50_vram_fini;
 421                 engine->vram.get                = nvc0_vram_new;
 422                 engine->vram.put                = nv50_vram_del;
 423                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 424                 engine->pm.temp_get             = nv84_temp_get;
 425                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 426                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 427                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 428                 break;
 429         default:
 430                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 431                 return 1;
 432         }
 433
 434         return 0;
 435 }
 436
 437 static unsigned int
 438 nouveau_vga_set_decode(void *priv, bool state)
 439 {
 440         struct drm_device *dev = priv;
 441         struct drm_nouveau_private *dev_priv = dev->dev_private;
 442
 443         if (dev_priv->chipset >= 0x40)
 444                 nv_wr32(dev, 0x88054, state);
 445         else
 446                 nv_wr32(dev, 0x1854, state);
 447
 448         if (state)
 449                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 450                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 451         else
 452                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 453 }
 454
 455 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 456                                          enum vga_switcheroo_state state)
 457 {
 458         struct drm_device *dev = pci_get_drvdata(pdev);
 459         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 460         if (state == VGA_SWITCHEROO_ON) {
 461                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 462                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 463                 nouveau_pci_resume(pdev);
 464                 drm_kms_helper_poll_enable(dev);
 465                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 466         } else {
 467                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 468                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 469                 drm_kms_helper_poll_disable(dev);
 470                 nouveau_pci_suspend(pdev, pmm);
 471                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 472         }
 473 }
 474
 475 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 476 {
 477         struct drm_device *dev = pci_get_drvdata(pdev);
 478         nouveau_fbcon_output_poll_changed(dev);
 479 }
 480
 481 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 482 {
 483         struct drm_device *dev = pci_get_drvdata(pdev);
 484         bool can_switch;
 485
 486         spin_lock(&dev->count_lock);
 487         can_switch = (dev->open_count == 0);
 488         spin_unlock(&dev->count_lock);
 489         return can_switch;
 490 }
 491
 492 int
 493 nouveau_card_init(struct drm_device *dev)
 494 {
 495         struct drm_nouveau_private *dev_priv = dev->dev_private;
 496         struct nouveau_engine *engine;
 497         int ret, e = 0;
 498
 499         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 500         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 501                                        nouveau_switcheroo_reprobe,
 502                                        nouveau_switcheroo_can_switch);
 503
 504         /* Initialise internal driver API hooks */
 505         ret = nouveau_init_engine_ptrs(dev);
 506         if (ret)
 507                 goto out;
 508         engine = &dev_priv->engine;
 509         spin_lock_init(&dev_priv->channels.lock);
 510         spin_lock_init(&dev_priv->tile.lock);
 511         spin_lock_init(&dev_priv->context_switch_lock);
 512         spin_lock_init(&dev_priv->vm_lock);
 513
 514         /* Make the CRTCs and I2C buses accessible */
 515         ret = engine->display.early_init(dev);
 516         if (ret)
 517                 goto out;
 518
 519         /* Parse BIOS tables / Run init tables if card not POSTed */
 520         ret = nouveau_bios_init(dev);
 521         if (ret)
 522                 goto out_display_early;
 523
 524         nouveau_pm_init(dev);
 525
 526         ret = engine->vram.init(dev);
 527         if (ret)
 528                 goto out_bios;
 529
 530         ret = nouveau_gpuobj_init(dev);
 531         if (ret)
 532                 goto out_vram;
 533
 534         ret = engine->instmem.init(dev);
 535         if (ret)
 536                 goto out_gpuobj;
 537
 538         ret = nouveau_mem_vram_init(dev);
 539         if (ret)
 540                 goto out_instmem;
 541
 542         ret = nouveau_mem_gart_init(dev);
 543         if (ret)
 544                 goto out_ttmvram;
 545
 546         /* PMC */
 547         ret = engine->mc.init(dev);
 548         if (ret)
 549                 goto out_gart;
 550
 551         /* PGPIO */
 552         ret = engine->gpio.init(dev);
 553         if (ret)
 554                 goto out_mc;
 555
 556         /* PTIMER */
 557         ret = engine->timer.init(dev);
 558         if (ret)
 559                 goto out_gpio;
 560
 561         /* PFB */
 562         ret = engine->fb.init(dev);
 563         if (ret)
 564                 goto out_timer;
 565
 566         if (!dev_priv->noaccel) {
 567                 switch (dev_priv->card_type) {
 568                 case NV_04:
 569                         nv04_graph_create(dev);
 570                         break;
 571                 case NV_10:
 572                         nv10_graph_create(dev);
 573                         break;
 574                 case NV_20:
 575                 case NV_30:
 576                         nv20_graph_create(dev);
 577                         break;
 578                 case NV_40:
 579                         nv40_graph_create(dev);
 580                         break;
 581                 case NV_50:
 582                         nv50_graph_create(dev);
 583                         break;
 584                 case NV_C0:
 585                         nvc0_graph_create(dev);
 586                         break;
 587                 default:
 588                         break;
 589                 }
 590
 591                 switch (dev_priv->chipset) {
 592                 case 0x84:
 593                 case 0x86:
 594                 case 0x92:
 595                 case 0x94:
 596                 case 0x96:
 597                 case 0xa0:
 598                         nv84_crypt_create(dev);
 599                         break;
 600                 }
 601
 602                 switch (dev_priv->card_type) {
 603                 case NV_50:
 604                         switch (dev_priv->chipset) {
 605                         case 0xa3:
 606                         case 0xa5:
 607                         case 0xa8:
 608                         case 0xaf:
 609                                 nva3_copy_create(dev);
 610                                 break;
 611                         }
 612                         break;
 613                 case NV_C0:
 614                         nvc0_copy_create(dev, 0);
 615                         nvc0_copy_create(dev, 1);
 616                         break;
 617                 default:
 618                         break;
 619                 }
 620
 621                 if (dev_priv->card_type == NV_40 ||
 622                     dev_priv->chipset == 0x31 ||
 623                     dev_priv->chipset == 0x34 ||
 624                     dev_priv->chipset == 0x36)
 625                         nv31_mpeg_create(dev);
 626                 else
 627                 if (dev_priv->card_type == NV_50 &&
 628                     (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
 629                         nv50_mpeg_create(dev);
 630
 631                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 632                         if (dev_priv->eng[e]) {
 633                                 ret = dev_priv->eng[e]->init(dev, e);
 634                                 if (ret)
 635                                         goto out_engine;
 636                         }
 637                 }
 638
 639                 /* PFIFO */
 640                 ret = engine->fifo.init(dev);
 641                 if (ret)
 642                         goto out_engine;
 643         }
 644
 645         ret = nouveau_irq_init(dev);
 646         if (ret)
 647                 goto out_fifo;
 648
 649         /* initialise general modesetting */
 650         drm_mode_config_init(dev);
 651         drm_mode_create_scaling_mode_property(dev);
 652         drm_mode_create_dithering_property(dev);
 653         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
 654         dev->mode_config.fb_base = pci_resource_start(dev->pdev, 1);
 655         dev->mode_config.min_width = 0;
 656         dev->mode_config.min_height = 0;
 657         if (dev_priv->card_type < NV_10) {
 658                 dev->mode_config.max_width = 2048;
 659                 dev->mode_config.max_height = 2048;
 660         } else
 661         if (dev_priv->card_type < NV_50) {
 662                 dev->mode_config.max_width = 4096;
 663                 dev->mode_config.max_height = 4096;
 664         } else {
 665                 dev->mode_config.max_width = 8192;
 666                 dev->mode_config.max_height = 8192;
 667         }
 668
 669         ret = engine->display.create(dev);
 670         if (ret)
 671                 goto out_irq;
 672
 673         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 674                 ret = nouveau_fence_init(dev);
 675                 if (ret)
 676                         goto out_disp;
 677
 678                 ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL,
 679                                             NvDmaFB, NvDmaTT);
 680                 if (ret)
 681                         goto out_fence;
 682
 683                 mutex_unlock(&dev_priv->channel->mutex);
 684         }
 685
 686         if (dev->mode_config.num_crtc) {
 687                 ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
 688                 if (ret)
 689                         goto out_chan;
 690
 691                 nouveau_fbcon_init(dev);
 692                 drm_kms_helper_poll_init(dev);
 693         }
 694
 695         return 0;
 696
 697 out_chan:
 698         nouveau_channel_put_unlocked(&dev_priv->channel);
 699 out_fence:
 700         nouveau_fence_fini(dev);
 701 out_disp:
 702         engine->display.destroy(dev);
 703 out_irq:
 704         nouveau_irq_fini(dev);
 705 out_fifo:
 706         if (!dev_priv->noaccel)
 707                 engine->fifo.takedown(dev);
 708 out_engine:
 709         if (!dev_priv->noaccel) {
 710                 for (e = e - 1; e >= 0; e--) {
 711                         if (!dev_priv->eng[e])
 712                                 continue;
 713                         dev_priv->eng[e]->fini(dev, e, false);
 714                         dev_priv->eng[e]->destroy(dev,e );
 715                 }
 716         }
 717
 718         engine->fb.takedown(dev);
 719 out_timer:
 720         engine->timer.takedown(dev);
 721 out_gpio:
 722         engine->gpio.takedown(dev);
 723 out_mc:
 724         engine->mc.takedown(dev);
 725 out_gart:
 726         nouveau_mem_gart_fini(dev);
 727 out_ttmvram:
 728         nouveau_mem_vram_fini(dev);
 729 out_instmem:
 730         engine->instmem.takedown(dev);
 731 out_gpuobj:
 732         nouveau_gpuobj_takedown(dev);
 733 out_vram:
 734         engine->vram.takedown(dev);
 735 out_bios:
 736         nouveau_pm_fini(dev);
 737         nouveau_bios_takedown(dev);
 738 out_display_early:
 739         engine->display.late_takedown(dev);
 740 out:
 741         vga_client_register(dev->pdev, NULL, NULL, NULL);
 742         return ret;
 743 }
 744
 745 static void nouveau_card_takedown(struct drm_device *dev)
 746 {
 747         struct drm_nouveau_private *dev_priv = dev->dev_private;
 748         struct nouveau_engine *engine = &dev_priv->engine;
 749         int e;
 750
 751         if (dev->mode_config.num_crtc) {
 752                 drm_kms_helper_poll_fini(dev);
 753                 nouveau_fbcon_fini(dev);
 754                 drm_vblank_cleanup(dev);
 755         }
 756
 757         if (dev_priv->channel) {
 758                 nouveau_channel_put_unlocked(&dev_priv->channel);
 759                 nouveau_fence_fini(dev);
 760         }
 761
 762         engine->display.destroy(dev);
 763         drm_mode_config_cleanup(dev);
 764
 765         if (!dev_priv->noaccel) {
 766                 engine->fifo.takedown(dev);
 767                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
 768                         if (dev_priv->eng[e]) {
 769                                 dev_priv->eng[e]->fini(dev, e, false);
 770                                 dev_priv->eng[e]->destroy(dev,e );
 771                         }
 772                 }
 773         }
 774         engine->fb.takedown(dev);
 775         engine->timer.takedown(dev);
 776         engine->gpio.takedown(dev);
 777         engine->mc.takedown(dev);
 778         engine->display.late_takedown(dev);
 779
 780         if (dev_priv->vga_ram) {
 781                 nouveau_bo_unpin(dev_priv->vga_ram);
 782                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 783         }
 784
 785         mutex_lock(&dev->struct_mutex);
 786         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 787         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 788         mutex_unlock(&dev->struct_mutex);
 789         nouveau_mem_gart_fini(dev);
 790         nouveau_mem_vram_fini(dev);
 791
 792         engine->instmem.takedown(dev);
 793         nouveau_gpuobj_takedown(dev);
 794         engine->vram.takedown(dev);
 795
 796         nouveau_irq_fini(dev);
 797
 798         nouveau_pm_fini(dev);
 799         nouveau_bios_takedown(dev);
 800
 801         vga_client_register(dev->pdev, NULL, NULL, NULL);
 802 }
 803
 804 int
 805 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
 806 {
 807         struct drm_nouveau_private *dev_priv = dev->dev_private;
 808         struct nouveau_fpriv *fpriv;
 809         int ret;
 810
 811         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 812         if (unlikely(!fpriv))
 813                 return -ENOMEM;
 814
 815         spin_lock_init(&fpriv->lock);
 816         INIT_LIST_HEAD(&fpriv->channels);
 817
 818         if (dev_priv->card_type == NV_50) {
 819                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
 820                                      &fpriv->vm);
 821                 if (ret) {
 822                         kfree(fpriv);
 823                         return ret;
 824                 }
 825         } else
 826         if (dev_priv->card_type >= NV_C0) {
 827                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
 828                                      &fpriv->vm);
 829                 if (ret) {
 830                         kfree(fpriv);
 831                         return ret;
 832                 }
 833         }
 834
 835         file_priv->driver_priv = fpriv;
 836         return 0;
 837 }
 838
 839 /* here a client dies, release the stuff that was allocated for its
 840  * file_priv */
 841 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 842 {
 843         nouveau_channel_cleanup(dev, file_priv);
 844 }
 845
 846 void
 847 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
 848 {
 849         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
 850         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
 851         kfree(fpriv);
 852 }
 853
 854 /* first module load, setup the mmio/fb mapping */
 855 /* KMS: we need mmio at load time, not when the first drm client opens. */
 856 int nouveau_firstopen(struct drm_device *dev)
 857 {
 858         return 0;
 859 }
 860
 861 /* if we have an OF card, copy vbios to RAMIN */
 862 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 863 {
 864 #if defined(__powerpc__)
 865         int size, i;
 866         const uint32_t *bios;
 867         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 868         if (!dn) {
 869                 NV_INFO(dev, "Unable to get the OF node\n");
 870                 return;
 871         }
 872
 873         bios = of_get_property(dn, "NVDA,BMP", &size);
 874         if (bios) {
 875                 for (i = 0; i < size; i += 4)
 876                         nv_wi32(dev, i, bios[i/4]);
 877                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 878         } else {
 879                 NV_INFO(dev, "Unable to get the OF bios\n");
 880         }
 881 #endif
 882 }
 883
 884 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 885 {
 886         struct pci_dev *pdev = dev->pdev;
 887         struct apertures_struct *aper = alloc_apertures(3);
 888         if (!aper)
 889                 return NULL;
 890
 891         aper->ranges[0].base = pci_resource_start(pdev, 1);
 892         aper->ranges[0].size = pci_resource_len(pdev, 1);
 893         aper->count = 1;
 894
 895         if (pci_resource_len(pdev, 2)) {
 896                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 897                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 898                 aper->count++;
 899         }
 900
 901         if (pci_resource_len(pdev, 3)) {
 902                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 903                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 904                 aper->count++;
 905         }
 906
 907         return aper;
 908 }
 909
 910 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 911 {
 912         struct drm_nouveau_private *dev_priv = dev->dev_private;
 913         bool primary = false;
 914         dev_priv->apertures = nouveau_get_apertures(dev);
 915         if (!dev_priv->apertures)
 916                 return -ENOMEM;
 917
 918 #ifdef CONFIG_X86
 919         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 920 #endif
 921
 922         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 923         return 0;
 924 }
 925
 926 int nouveau_load(struct drm_device *dev, unsigned long flags)
 927 {
 928         struct drm_nouveau_private *dev_priv;
 929         uint32_t reg0;
 930         resource_size_t mmio_start_offs;
 931         int ret;
 932
 933         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 934         if (!dev_priv) {
 935                 ret = -ENOMEM;
 936                 goto err_out;
 937         }
 938         dev->dev_private = dev_priv;
 939         dev_priv->dev = dev;
 940
 941         dev_priv->flags = flags & NOUVEAU_FLAGS;
 942
 943         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
 944                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
 945
 946         /* resource 0 is mmio regs */
 947         /* resource 1 is linear FB */
 948         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 949         /* resource 6 is bios */
 950
 951         /* map the mmio regs */
 952         mmio_start_offs = pci_resource_start(dev->pdev, 0);
 953         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
 954         if (!dev_priv->mmio) {
 955                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 956                          "Please report your setup to " DRIVER_EMAIL "\n");
 957                 ret = -EINVAL;
 958                 goto err_priv;
 959         }
 960         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 961                                         (unsigned long long)mmio_start_offs);
 962
 963 #ifdef __BIG_ENDIAN
 964         /* Put the card in BE mode if it's not */
 965         if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
 966                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
 967
 968         DRM_MEMORYBARRIER();
 969 #endif
 970
 971         /* Time to determine the card architecture */
 972         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 973         dev_priv->stepping = 0; /* XXX: add stepping for pre-NV10? */
 974
 975         /* We're dealing with >=NV10 */
 976         if ((reg0 & 0x0f000000) > 0) {
 977                 /* Bit 27-20 contain the architecture in hex */
 978                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 979                 dev_priv->stepping = (reg0 & 0xff);
 980         /* NV04 or NV05 */
 981         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 982                 if (reg0 & 0x00f00000)
 983                         dev_priv->chipset = 0x05;
 984                 else
 985                         dev_priv->chipset = 0x04;
 986         } else
 987                 dev_priv->chipset = 0xff;
 988
 989         switch (dev_priv->chipset & 0xf0) {
 990         case 0x00:
 991         case 0x10:
 992         case 0x20:
 993         case 0x30:
 994                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 995                 break;
 996         case 0x40:
 997         case 0x60:
 998                 dev_priv->card_type = NV_40;
 999                 break;
1000         case 0x50:
1001         case 0x80:
1002         case 0x90:
1003         case 0xa0:
1004                 dev_priv->card_type = NV_50;
1005                 break;
1006         case 0xc0:
1007                 dev_priv->card_type = NV_C0;
1008                 break;
1009         default:
1010                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
1011                 ret = -EINVAL;
1012                 goto err_mmio;
1013         }
1014
1015         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1016                 dev_priv->card_type, reg0);
1017
1018         /* Determine whether we'll attempt acceleration or not, some
1019          * cards are disabled by default here due to them being known
1020          * non-functional, or never been tested due to lack of hw.
1021          */
1022         dev_priv->noaccel = !!nouveau_noaccel;
1023         if (nouveau_noaccel == -1) {
1024                 switch (dev_priv->chipset) {
1025                 case 0xc1: /* known broken */
1026                 case 0xc8: /* never tested */
1027                         NV_INFO(dev, "acceleration disabled by default, pass "
1028                                      "noaccel=0 to force enable\n");
1029                         dev_priv->noaccel = true;
1030                         break;
1031                 default:
1032                         dev_priv->noaccel = false;
1033                         break;
1034                 }
1035         }
1036
1037         ret = nouveau_remove_conflicting_drivers(dev);
1038         if (ret)
1039                 goto err_mmio;
1040
1041         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1042         if (dev_priv->card_type >= NV_40) {
1043                 int ramin_bar = 2;
1044                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1045                         ramin_bar = 3;
1046
1047                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1048                 dev_priv->ramin =
1049                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1050                                 dev_priv->ramin_size);
1051                 if (!dev_priv->ramin) {
1052                         NV_ERROR(dev, "Failed to PRAMIN BAR");
1053                         ret = -ENOMEM;
1054                         goto err_mmio;
1055                 }
1056         } else {
1057                 dev_priv->ramin_size = 1 * 1024 * 1024;
1058                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
1059                                           dev_priv->ramin_size);
1060                 if (!dev_priv->ramin) {
1061                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1062                         ret = -ENOMEM;
1063                         goto err_mmio;
1064                 }
1065         }
1066
1067         nouveau_OF_copy_vbios_to_ramin(dev);
1068
1069         /* Special flags */
1070         if (dev->pci_device == 0x01a0)
1071                 dev_priv->flags |= NV_NFORCE;
1072         else if (dev->pci_device == 0x01f0)
1073                 dev_priv->flags |= NV_NFORCE2;
1074
1075         /* For kernel modesetting, init card now and bring up fbcon */
1076         ret = nouveau_card_init(dev);
1077         if (ret)
1078                 goto err_ramin;
1079
1080         return 0;
1081
1082 err_ramin:
1083         iounmap(dev_priv->ramin);
1084 err_mmio:
1085         iounmap(dev_priv->mmio);
1086 err_priv:
1087         kfree(dev_priv);
1088         dev->dev_private = NULL;
1089 err_out:
1090         return ret;
1091 }
1092
1093 void nouveau_lastclose(struct drm_device *dev)
1094 {
1095         vga_switcheroo_process_delayed_switch();
1096 }
1097
1098 int nouveau_unload(struct drm_device *dev)
1099 {
1100         struct drm_nouveau_private *dev_priv = dev->dev_private;
1101
1102         nouveau_card_takedown(dev);
1103
1104         iounmap(dev_priv->mmio);
1105         iounmap(dev_priv->ramin);
1106
1107         kfree(dev_priv);
1108         dev->dev_private = NULL;
1109         return 0;
1110 }
1111
1112 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1113                                                 struct drm_file *file_priv)
1114 {
1115         struct drm_nouveau_private *dev_priv = dev->dev_private;
1116         struct drm_nouveau_getparam *getparam = data;
1117
1118         switch (getparam->param) {
1119         case NOUVEAU_GETPARAM_CHIPSET_ID:
1120                 getparam->value = dev_priv->chipset;
1121                 break;
1122         case NOUVEAU_GETPARAM_PCI_VENDOR:
1123                 getparam->value = dev->pci_vendor;
1124                 break;
1125         case NOUVEAU_GETPARAM_PCI_DEVICE:
1126                 getparam->value = dev->pci_device;
1127                 break;
1128         case NOUVEAU_GETPARAM_BUS_TYPE:
1129                 if (drm_pci_device_is_agp(dev))
1130                         getparam->value = NV_AGP;
1131                 else if (pci_is_pcie(dev->pdev))
1132                         getparam->value = NV_PCIE;
1133                 else
1134                         getparam->value = NV_PCI;
1135                 break;
1136         case NOUVEAU_GETPARAM_FB_SIZE:
1137                 getparam->value = dev_priv->fb_available_size;
1138                 break;
1139         case NOUVEAU_GETPARAM_AGP_SIZE:
1140                 getparam->value = dev_priv->gart_info.aper_size;
1141                 break;
1142         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1143                 getparam->value = 0; /* deprecated */
1144                 break;
1145         case NOUVEAU_GETPARAM_PTIMER_TIME:
1146                 getparam->value = dev_priv->engine.timer.read(dev);
1147                 break;
1148         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1149                 getparam->value = 1;
1150                 break;
1151         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1152                 getparam->value = 1;
1153                 break;
1154         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1155                 /* NV40 and NV50 versions are quite different, but register
1156                  * address is the same. User is supposed to know the card
1157                  * family anyway... */
1158                 if (dev_priv->chipset >= 0x40) {
1159                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1160                         break;
1161                 }
1162                 /* FALLTHRU */
1163         default:
1164                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1165                 return -EINVAL;
1166         }
1167
1168         return 0;
1169 }
1170
1171 int
1172 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1173                        struct drm_file *file_priv)
1174 {
1175         struct drm_nouveau_setparam *setparam = data;
1176
1177         switch (setparam->param) {
1178         default:
1179                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1180                 return -EINVAL;
1181         }
1182
1183         return 0;
1184 }
1185
1186 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1187 bool
1188 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1189                 uint32_t reg, uint32_t mask, uint32_t val)
1190 {
1191         struct drm_nouveau_private *dev_priv = dev->dev_private;
1192         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1193         uint64_t start = ptimer->read(dev);
1194
1195         do {
1196                 if ((nv_rd32(dev, reg) & mask) == val)
1197                         return true;
1198         } while (ptimer->read(dev) - start < timeout);
1199
1200         return false;
1201 }
1202
1203 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1204 bool
1205 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1206                 uint32_t reg, uint32_t mask, uint32_t val)
1207 {
1208         struct drm_nouveau_private *dev_priv = dev->dev_private;
1209         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1210         uint64_t start = ptimer->read(dev);
1211
1212         do {
1213                 if ((nv_rd32(dev, reg) & mask) != val)
1214                         return true;
1215         } while (ptimer->read(dev) - start < timeout);
1216
1217         return false;
1218 }
1219
1220 /* Wait until cond(data) == true, up until timeout has hit */
1221 bool
1222 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1223                 bool (*cond)(void *), void *data)
1224 {
1225         struct drm_nouveau_private *dev_priv = dev->dev_private;
1226         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1227         u64 start = ptimer->read(dev);
1228
1229         do {
1230                 if (cond(data) == true)
1231                         return true;
1232         } while (ptimer->read(dev) - start < timeout);
1233
1234         return false;
1235 }
1236
1237 /* Waits for PGRAPH to go completely idle */
1238 bool nouveau_wait_for_idle(struct drm_device *dev)
1239 {
1240         struct drm_nouveau_private *dev_priv = dev->dev_private;
1241         uint32_t mask = ~0;
1242
1243         if (dev_priv->card_type == NV_40)
1244                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1245
1246         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1247                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1248                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1249                 return false;
1250         }
1251
1252         return true;
1253 }
1254