2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 nv40_identify(struct nvkm_device *device)
29 switch (device->chipset) {
31 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
32 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
33 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
34 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
35 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
36 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
37 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
38 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
39 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
40 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
41 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
44 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
45 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
46 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
47 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
48 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
49 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
50 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
51 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
52 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
53 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
54 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
57 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
59 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
60 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
61 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
62 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
63 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
64 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
65 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
66 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
67 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
70 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
72 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
73 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
74 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
75 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
76 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
77 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
78 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
79 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
80 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
83 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
84 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
85 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
86 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
87 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
88 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
89 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
90 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
91 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
92 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
93 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
96 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
97 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
98 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
99 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
101 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
102 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
103 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
104 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
105 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
106 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
109 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
110 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
111 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
112 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
113 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
114 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
115 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
116 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
117 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
118 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
119 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
122 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
123 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
124 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
125 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
126 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
127 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
128 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
129 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
130 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
131 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
132 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
135 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
136 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
137 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
138 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
139 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
140 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
141 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
142 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
143 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
144 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
145 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
148 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
149 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
150 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
151 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
152 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
153 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
154 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
155 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
156 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
157 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
158 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
161 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
162 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
163 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
164 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
165 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
166 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
167 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
168 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
169 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
170 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
171 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
174 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
175 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
176 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
177 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
178 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
179 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
180 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
181 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
182 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
183 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
184 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
187 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
188 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
189 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
190 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
191 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
192 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
193 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
194 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
195 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
196 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
197 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
200 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
201 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
202 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
203 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
204 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
205 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
206 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
207 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
208 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
209 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
210 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
213 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
214 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
215 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
216 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
217 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
218 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
219 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
220 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
221 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
222 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
223 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
226 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
227 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
228 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
229 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
230 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
231 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
232 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
233 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
234 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
235 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
236 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;