2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <core/gpuobj.h>
27 #include <subdev/fb.h>
28 #include <subdev/mmu/nv04.h>
30 #include <nvif/class.h>
33 struct nvkm_dmaobj base;
40 nv04_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_object *parent,
41 struct nvkm_gpuobj **pgpuobj)
43 struct nv04_dmaobj *dmaobj = container_of(obj, typeof(*dmaobj), base);
44 struct nvkm_gpuobj *gpuobj;
45 u64 offset = dmaobj->base.start & 0xfffff000;
46 u64 adjust = dmaobj->base.start & 0x00000fff;
47 u32 length = dmaobj->base.limit - dmaobj->base.start;
50 if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
51 switch (nv_mclass(parent->parent)) {
52 case NV03_CHANNEL_DMA:
53 case NV10_CHANNEL_DMA:
54 case NV17_CHANNEL_DMA:
55 case NV40_CHANNEL_DMA:
63 struct nv04_mmu *mmu = nv04_mmu(dmaobj);
64 struct nvkm_memory *pgt = mmu->vm->pgt[0].mem[0];
65 if (!dmaobj->base.start)
66 return nvkm_gpuobj_dup(parent, pgt, pgpuobj);
68 offset = nvkm_ro32(pgt, 8 + (offset >> 10));
73 ret = nvkm_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj);
77 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20));
78 nvkm_wo32(*pgpuobj, 0x04, length);
79 nvkm_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset);
80 nvkm_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset);
88 nv04_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
89 struct nvkm_oclass *oclass, void *data, u32 size,
90 struct nvkm_object **pobject)
92 struct nvkm_dmaeng *dmaeng = (void *)engine;
93 struct nv04_mmu *mmu = nv04_mmu(engine);
94 struct nv04_dmaobj *dmaobj;
97 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &dmaobj);
98 *pobject = nv_object(dmaobj);
99 if (ret || (ret = -ENOSYS, size))
102 if (dmaobj->base.target == NV_MEM_TARGET_VM) {
103 if (nv_object(mmu)->oclass == &nv04_mmu_oclass)
104 dmaobj->clone = true;
105 dmaobj->base.target = NV_MEM_TARGET_PCI;
106 dmaobj->base.access = NV_MEM_ACCESS_RW;
109 dmaobj->flags0 = nv_mclass(dmaobj);
110 switch (dmaobj->base.target) {
111 case NV_MEM_TARGET_VRAM:
112 dmaobj->flags0 |= 0x00003000;
114 case NV_MEM_TARGET_PCI:
115 dmaobj->flags0 |= 0x00023000;
117 case NV_MEM_TARGET_PCI_NOSNOOP:
118 dmaobj->flags0 |= 0x00033000;
124 switch (dmaobj->base.access) {
125 case NV_MEM_ACCESS_RO:
126 dmaobj->flags0 |= 0x00004000;
128 case NV_MEM_ACCESS_WO:
129 dmaobj->flags0 |= 0x00008000;
130 case NV_MEM_ACCESS_RW:
131 dmaobj->flags2 |= 0x00000002;
137 return dmaeng->bind(&dmaobj->base, nv_object(dmaobj), (void *)pobject);
140 static struct nvkm_ofuncs
141 nv04_dmaobj_ofuncs = {
142 .ctor = nv04_dmaobj_ctor,
143 .dtor = _nvkm_dmaobj_dtor,
144 .init = _nvkm_dmaobj_init,
145 .fini = _nvkm_dmaobj_fini,
148 static struct nvkm_oclass
149 nv04_dmaeng_sclass[] = {
150 { NV_DMA_FROM_MEMORY, &nv04_dmaobj_ofuncs },
151 { NV_DMA_TO_MEMORY, &nv04_dmaobj_ofuncs },
152 { NV_DMA_IN_MEMORY, &nv04_dmaobj_ofuncs },
157 nv04_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
158 .base.handle = NV_ENGINE(DMAOBJ, 0x04),
159 .base.ofuncs = &(struct nvkm_ofuncs) {
160 .ctor = _nvkm_dmaeng_ctor,
161 .dtor = _nvkm_dmaeng_dtor,
162 .init = _nvkm_dmaeng_init,
163 .fini = _nvkm_dmaeng_fini,
165 .sclass = nv04_dmaeng_sclass,
166 .bind = nv04_dmaobj_bind,