2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <core/client.h>
27 #include <core/engctx.h>
28 #include <core/ramht.h>
29 #include <subdev/instmem.h>
31 #include <nvif/class.h>
32 #include <nvif/unpack.h>
34 static struct ramfc_desc
36 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
37 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
38 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
39 { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
40 { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
41 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE },
42 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH },
43 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE },
44 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 },
45 { 32, 0, 0x20, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
46 { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
47 { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
48 { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_SEMAPHORE },
49 { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
53 /*******************************************************************************
54 * FIFO channel objects
55 ******************************************************************************/
58 nv17_fifo_chan_ctor(struct nvkm_object *parent,
59 struct nvkm_object *engine,
60 struct nvkm_oclass *oclass, void *data, u32 size,
61 struct nvkm_object **pobject)
64 struct nv03_channel_dma_v0 v0;
66 struct nv04_fifo *fifo = (void *)engine;
67 struct nv04_fifo_chan *chan;
70 nvif_ioctl(parent, "create channel dma size %d\n", size);
71 if (nvif_unpack(args->v0, 0, 0, false)) {
72 nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
73 "offset %08x\n", args->v0.version,
74 args->v0.pushbuf, args->v0.offset);
78 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
79 0x10000, args->v0.pushbuf,
80 (1ULL << NVDEV_ENGINE_DMAOBJ) |
81 (1ULL << NVDEV_ENGINE_SW) |
82 (1ULL << NVDEV_ENGINE_GR) |
83 (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */
85 *pobject = nv_object(chan);
89 args->v0.chid = chan->base.chid;
91 nv_parent(chan)->object_attach = nv04_fifo_object_attach;
92 nv_parent(chan)->object_detach = nv04_fifo_object_detach;
93 nv_parent(chan)->context_attach = nv04_fifo_context_attach;
94 chan->ramfc = chan->base.chid * 64;
96 nvkm_kmap(fifo->ramfc);
97 nvkm_wo32(fifo->ramfc, chan->ramfc + 0x00, args->v0.offset);
98 nvkm_wo32(fifo->ramfc, chan->ramfc + 0x04, args->v0.offset);
99 nvkm_wo32(fifo->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
100 nvkm_wo32(fifo->ramfc, chan->ramfc + 0x14,
101 NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
102 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
104 NV_PFIFO_CACHE1_BIG_ENDIAN |
106 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
107 nvkm_done(fifo->ramfc);
111 static struct nvkm_ofuncs
113 .ctor = nv17_fifo_chan_ctor,
114 .dtor = nv04_fifo_chan_dtor,
115 .init = nv04_fifo_chan_init,
116 .fini = nv04_fifo_chan_fini,
117 .map = _nvkm_fifo_channel_map,
118 .rd32 = _nvkm_fifo_channel_rd32,
119 .wr32 = _nvkm_fifo_channel_wr32,
120 .ntfy = _nvkm_fifo_channel_ntfy
123 static struct nvkm_oclass
124 nv17_fifo_sclass[] = {
125 { NV17_CHANNEL_DMA, &nv17_fifo_ofuncs },
129 /*******************************************************************************
130 * FIFO context - basically just the instmem reserved for the channel
131 ******************************************************************************/
133 static struct nvkm_oclass
135 .handle = NV_ENGCTX(FIFO, 0x17),
136 .ofuncs = &(struct nvkm_ofuncs) {
137 .ctor = nv04_fifo_context_ctor,
138 .dtor = _nvkm_fifo_context_dtor,
139 .init = _nvkm_fifo_context_init,
140 .fini = _nvkm_fifo_context_fini,
141 .rd32 = _nvkm_fifo_context_rd32,
142 .wr32 = _nvkm_fifo_context_wr32,
146 /*******************************************************************************
148 ******************************************************************************/
151 nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
152 struct nvkm_oclass *oclass, void *data, u32 size,
153 struct nvkm_object **pobject)
155 struct nvkm_device *device = (void *)parent;
156 struct nvkm_instmem *imem = device->imem;
157 struct nv04_fifo *fifo;
160 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo);
161 *pobject = nv_object(fifo);
165 nvkm_ramht_ref(imem->ramht, &fifo->ramht);
166 nvkm_gpuobj_ref(imem->ramro, &fifo->ramro);
167 nvkm_gpuobj_ref(imem->ramfc, &fifo->ramfc);
169 nv_subdev(fifo)->unit = 0x00000100;
170 nv_subdev(fifo)->intr = nv04_fifo_intr;
171 nv_engine(fifo)->cclass = &nv17_fifo_cclass;
172 nv_engine(fifo)->sclass = nv17_fifo_sclass;
173 fifo->base.pause = nv04_fifo_pause;
174 fifo->base.start = nv04_fifo_start;
175 fifo->ramfc_desc = nv17_ramfc;
180 nv17_fifo_init(struct nvkm_object *object)
182 struct nv04_fifo *fifo = (void *)object;
183 struct nvkm_device *device = fifo->base.engine.subdev.device;
186 ret = nvkm_fifo_init(&fifo->base);
190 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff);
191 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
193 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
194 ((fifo->ramht->bits - 9) << 16) |
195 (fifo->ramht->gpuobj.addr >> 8));
196 nvkm_wr32(device, NV03_PFIFO_RAMRO, fifo->ramro->addr >> 8);
197 nvkm_wr32(device, NV03_PFIFO_RAMFC, fifo->ramfc->addr >> 8 | 0x00010000);
199 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max);
201 nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);
202 nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);
204 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
205 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
206 nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
211 nv17_fifo_oclass = &(struct nvkm_oclass) {
212 .handle = NV_ENGINE(FIFO, 0x17),
213 .ofuncs = &(struct nvkm_ofuncs) {
214 .ctor = nv17_fifo_ctor,
215 .dtor = nv04_fifo_dtor,
216 .init = nv17_fifo_init,
217 .fini = _nvkm_fifo_fini,