2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <core/gpuobj.h>
27 #include <subdev/fb.h>
28 #include <subdev/mmu.h>
31 struct nvkm_gpuobj *mem;
32 struct nvkm_gpuobj *pgd;
39 struct gf100_bar_vm bar[2];
42 static struct nvkm_vm *
43 gf100_bar_kmap(struct nvkm_bar *obj)
45 struct gf100_bar *bar = container_of(obj, typeof(*bar), base);
46 return bar->bar[0].vm;
50 gf100_bar_umap(struct nvkm_bar *obj, u64 size, int type, struct nvkm_vma *vma)
52 struct gf100_bar *bar = container_of(obj, typeof(*bar), base);
53 return nvkm_vm_get(bar->bar[1].vm, size, type, NV_MEM_ACCESS_RW, vma);
57 gf100_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma)
65 gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm,
66 struct lock_class_key *key, int bar_nr)
68 struct nvkm_device *device = nv_device(&bar->base);
70 resource_size_t bar_len;
73 ret = nvkm_gpuobj_new(nv_object(bar), NULL, 0x1000, 0, 0,
78 ret = nvkm_gpuobj_new(nv_object(bar), NULL, 0x8000, 0, 0,
83 bar_len = nv_device_resource_len(device, bar_nr);
85 ret = nvkm_vm_new(device, 0, bar_len, 0, key, &vm);
89 atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
92 * Bootstrap page table lookup.
95 ret = nvkm_vm_boot(vm, bar_len);
100 ret = nvkm_vm_ref(vm, &bar_vm->vm, bar_vm->pgd);
101 nvkm_vm_ref(NULL, &vm, NULL);
105 nvkm_kmap(bar_vm->mem);
106 nvkm_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr));
107 nvkm_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr));
108 nvkm_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1));
109 nvkm_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1));
110 nvkm_done(bar_vm->mem);
115 gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
116 struct nvkm_oclass *oclass, void *data, u32 size,
117 struct nvkm_object **pobject)
119 static struct lock_class_key bar1_lock;
120 static struct lock_class_key bar3_lock;
121 struct nvkm_device *device = nv_device(parent);
122 struct gf100_bar *bar;
123 bool has_bar3 = nv_device_resource_len(device, 3) != 0;
126 ret = nvkm_bar_create(parent, engine, oclass, &bar);
127 *pobject = nv_object(bar);
131 device->bar = &bar->base;
132 bar->base.flush = g84_bar_flush;
133 spin_lock_init(&bar->lock);
137 ret = gf100_bar_ctor_vm(bar, &bar->bar[0], &bar3_lock, 3);
143 ret = gf100_bar_ctor_vm(bar, &bar->bar[1], &bar1_lock, 1);
148 bar->base.kmap = gf100_bar_kmap;
149 bar->base.umap = gf100_bar_umap;
150 bar->base.unmap = gf100_bar_unmap;
155 gf100_bar_dtor(struct nvkm_object *object)
157 struct gf100_bar *bar = (void *)object;
159 nvkm_vm_ref(NULL, &bar->bar[1].vm, bar->bar[1].pgd);
160 nvkm_gpuobj_ref(NULL, &bar->bar[1].pgd);
161 nvkm_gpuobj_ref(NULL, &bar->bar[1].mem);
163 if (bar->bar[0].vm) {
164 nvkm_memory_del(&bar->bar[0].vm->pgt[0].mem[0]);
165 nvkm_vm_ref(NULL, &bar->bar[0].vm, bar->bar[0].pgd);
167 nvkm_gpuobj_ref(NULL, &bar->bar[0].pgd);
168 nvkm_gpuobj_ref(NULL, &bar->bar[0].mem);
170 nvkm_bar_destroy(&bar->base);
174 gf100_bar_init(struct nvkm_object *object)
176 struct gf100_bar *bar = (void *)object;
177 struct nvkm_device *device = bar->base.subdev.device;
180 ret = nvkm_bar_init(&bar->base);
184 nvkm_mask(device, 0x000200, 0x00000100, 0x00000000);
185 nvkm_mask(device, 0x000200, 0x00000100, 0x00000100);
187 nvkm_wr32(device, 0x001704, 0x80000000 | bar->bar[1].mem->addr >> 12);
189 nvkm_wr32(device, 0x001714,
190 0xc0000000 | bar->bar[0].mem->addr >> 12);
196 .handle = NV_SUBDEV(BAR, 0xc0),
197 .ofuncs = &(struct nvkm_ofuncs) {
198 .ctor = gf100_bar_ctor,
199 .dtor = gf100_bar_dtor,
200 .init = gf100_bar_init,
201 .fini = _nvkm_bar_fini,