2 * linux/drivers/video/omap2/dss/dss.h
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
26 #include <linux/interrupt.h>
34 #ifdef DSS_SUBSYS_NAME
35 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
37 #define pr_fmt(fmt) fmt
40 #define DSSDBG(format, ...) \
41 pr_debug(format, ## __VA_ARGS__)
43 #ifdef DSS_SUBSYS_NAME
44 #define DSSERR(format, ...) \
45 pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__)
47 #define DSSERR(format, ...) \
48 pr_err("omapdss error: " format, ##__VA_ARGS__)
51 #ifdef DSS_SUBSYS_NAME
52 #define DSSINFO(format, ...) \
53 pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
55 #define DSSINFO(format, ...) \
56 pr_info("omapdss: " format, ## __VA_ARGS__)
59 #ifdef DSS_SUBSYS_NAME
60 #define DSSWARN(format, ...) \
61 pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
63 #define DSSWARN(format, ...) \
64 pr_warn("omapdss: " format, ##__VA_ARGS__)
67 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
68 number. For example 7:0 */
69 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
70 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
71 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
72 #define FLD_MOD(orig, val, start, end) \
73 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
75 enum dss_io_pad_mode {
76 DSS_IO_PAD_MODE_RESET,
78 DSS_IO_PAD_MODE_BYPASS,
81 enum dss_hdmi_venc_clk_source_select {
86 enum dss_dsi_content_type {
88 DSS_DSI_CONTENT_GENERIC,
91 enum dss_writeback_channel {
102 enum dss_clk_source {
113 DSS_CLK_SRC_HDMI_PLL,
126 #define DSS_PLL_MAX_HSDIVS 4
134 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
135 * Type-B PLLs: clkout[0] refers to m2.
137 struct dss_pll_clock_info {
138 /* rates that we get with dividers below */
140 unsigned long clkdco;
141 unsigned long clkout[DSS_PLL_MAX_HSDIVS];
147 u16 mX[DSS_PLL_MAX_HSDIVS];
152 int (*enable)(struct dss_pll *pll);
153 void (*disable)(struct dss_pll *pll);
154 int (*set_config)(struct dss_pll *pll,
155 const struct dss_pll_clock_info *cinfo);
159 enum dss_pll_type type;
166 unsigned long fint_min, fint_max;
167 unsigned long clkdco_min, clkdco_low, clkdco_max;
171 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
184 struct regulator *regulator;
188 const struct dss_pll_hw *hw;
190 const struct dss_pll_ops *ops;
192 struct dss_pll_clock_info cinfo;
195 struct dispc_clock_info {
196 /* rates that we get with dividers below */
205 struct dss_lcd_mgr_config {
206 enum dss_io_pad_mode io_pad_mode;
211 struct dispc_clock_info clock_info;
213 int video_port_width;
215 int lcden_sig_polarity;
219 struct platform_device;
222 struct platform_device *dss_get_core_pdev(void);
223 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
224 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
225 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
226 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
228 static inline bool dss_mgr_is_lcd(enum omap_channel id)
230 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
231 id == OMAP_DSS_CHANNEL_LCD3)
238 int dss_init_platform_driver(void) __init;
239 void dss_uninit_platform_driver(void);
241 int dss_runtime_get(void);
242 void dss_runtime_put(void);
244 unsigned long dss_get_dispc_clk_rate(void);
245 int dss_dpi_select_source(int port, enum omap_channel channel);
246 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
247 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
248 const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
249 void dss_dump_clocks(struct seq_file *s);
252 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
253 struct regulator *regulator);
254 void dss_video_pll_uninit(struct dss_pll *pll);
256 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
257 void dss_debug_dump_clocks(struct seq_file *s);
260 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
262 void dss_sdi_init(int datapairs);
263 int dss_sdi_enable(void);
264 void dss_sdi_disable(void);
266 void dss_select_dsi_clk_source(int dsi_module,
267 enum dss_clk_source clk_src);
268 void dss_select_lcd_clk_source(enum omap_channel channel,
269 enum dss_clk_source clk_src);
270 enum dss_clk_source dss_get_dispc_clk_source(void);
271 enum dss_clk_source dss_get_dsi_clk_source(int dsi_module);
272 enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
274 void dss_set_venc_output(enum omap_dss_venc_type type);
275 void dss_set_dac_pwrdn_bgz(bool enable);
277 int dss_set_fck_rate(unsigned long rate);
279 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
280 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
281 dss_div_calc_func func, void *data);
284 int sdi_init_platform_driver(void) __init;
285 void sdi_uninit_platform_driver(void);
287 #ifdef CONFIG_OMAP2_DSS_SDI
288 int sdi_init_port(struct platform_device *pdev, struct device_node *port);
289 void sdi_uninit_port(struct device_node *port);
291 static inline int sdi_init_port(struct platform_device *pdev,
292 struct device_node *port)
296 static inline void sdi_uninit_port(struct device_node *port)
303 #ifdef CONFIG_OMAP2_DSS_DSI
306 struct file_operations;
308 int dsi_init_platform_driver(void) __init;
309 void dsi_uninit_platform_driver(void);
311 void dsi_dump_clocks(struct seq_file *s);
313 void dsi_irq_handler(void);
318 int dpi_init_platform_driver(void) __init;
319 void dpi_uninit_platform_driver(void);
321 #ifdef CONFIG_OMAP2_DSS_DPI
322 int dpi_init_port(struct platform_device *pdev, struct device_node *port);
323 void dpi_uninit_port(struct device_node *port);
325 static inline int dpi_init_port(struct platform_device *pdev,
326 struct device_node *port)
330 static inline void dpi_uninit_port(struct device_node *port)
336 int dispc_init_platform_driver(void) __init;
337 void dispc_uninit_platform_driver(void);
338 void dispc_dump_clocks(struct seq_file *s);
340 int dispc_runtime_get(void);
341 void dispc_runtime_put(void);
343 void dispc_enable_sidle(void);
344 void dispc_disable_sidle(void);
346 void dispc_lcd_enable_signal(bool enable);
347 void dispc_pck_free_enable(bool enable);
348 void dispc_enable_fifomerge(bool enable);
349 void dispc_enable_gamma_table(bool enable);
351 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
352 unsigned long pck, void *data);
353 bool dispc_div_calc(unsigned long dispc,
354 unsigned long pck_min, unsigned long pck_max,
355 dispc_div_calc_func func, void *data);
357 bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm);
358 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
359 struct dispc_clock_info *cinfo);
362 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
363 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
364 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
367 void dispc_mgr_set_clock_div(enum omap_channel channel,
368 const struct dispc_clock_info *cinfo);
369 int dispc_mgr_get_clock_div(enum omap_channel channel,
370 struct dispc_clock_info *cinfo);
371 void dispc_set_tv_pclk(unsigned long pclk);
373 u32 dispc_wb_get_framedone_irq(void);
374 bool dispc_wb_go_busy(void);
375 void dispc_wb_go(void);
376 void dispc_wb_enable(bool enable);
377 bool dispc_wb_is_enabled(void);
378 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
379 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
380 bool mem_to_mem, const struct videomode *vm);
383 int venc_init_platform_driver(void) __init;
384 void venc_uninit_platform_driver(void);
387 int hdmi4_init_platform_driver(void) __init;
388 void hdmi4_uninit_platform_driver(void);
390 int hdmi5_init_platform_driver(void) __init;
391 void hdmi5_uninit_platform_driver(void);
394 int rfbi_init_platform_driver(void) __init;
395 void rfbi_uninit_platform_driver(void);
398 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
399 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
402 for (b = 0; b < 32; ++b) {
403 if (irqstatus & (1 << b))
410 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
411 unsigned long clkdco, void *data);
412 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
415 int dss_pll_register(struct dss_pll *pll);
416 void dss_pll_unregister(struct dss_pll *pll);
417 struct dss_pll *dss_pll_find(const char *name);
418 struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src);
419 unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
420 int dss_pll_enable(struct dss_pll *pll);
421 void dss_pll_disable(struct dss_pll *pll);
422 int dss_pll_set_config(struct dss_pll *pll,
423 const struct dss_pll_clock_info *cinfo);
425 bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
426 unsigned long out_min, unsigned long out_max,
427 dss_hsdiv_calc_func func, void *data);
428 bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
429 unsigned long pll_min, unsigned long pll_max,
430 dss_pll_calc_func func, void *data);
432 bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
433 unsigned long target_clkout, struct dss_pll_clock_info *cinfo);
435 int dss_pll_write_config_type_a(struct dss_pll *pll,
436 const struct dss_pll_clock_info *cinfo);
437 int dss_pll_write_config_type_b(struct dss_pll *pll,
438 const struct dss_pll_clock_info *cinfo);
439 int dss_pll_wait_reset_done(struct dss_pll *pll);