2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/i2c.h>
27 #include <linux/media-bus-format.h>
28 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regulator/consumer.h>
34 #include <video/display_timing.h>
35 #include <video/of_display_timing.h>
36 #include <video/videomode.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_device.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_mipi_dsi.h>
42 #include <drm/drm_panel.h>
45 * struct panel_desc - Describes a simple panel.
49 * @modes: Pointer to array of fixed modes appropriate for this panel.
51 * If only one mode then this can just be the address of the mode.
52 * NOTE: cannot be used with "timings" and also if this is specified
53 * then you cannot override the mode in the device tree.
55 const struct drm_display_mode *modes;
57 /** @num_modes: Number of elements in modes array. */
58 unsigned int num_modes;
61 * @timings: Pointer to array of display timings
63 * NOTE: cannot be used with "modes" and also these will be used to
64 * validate a device tree override if one is present.
66 const struct display_timing *timings;
68 /** @num_timings: Number of elements in timings array. */
69 unsigned int num_timings;
71 /** @bpc: Bits per color. */
74 /** @size: Structure containing the physical size of this panel. */
77 * @size.width: Width (in mm) of the active display area.
82 * @size.height: Height (in mm) of the active display area.
87 /** @delay: Structure containing various delay values for this panel. */
90 * @delay.prepare: Time for the panel to become ready.
92 * The time (in milliseconds) that it takes for the panel to
93 * become ready and start receiving video data
98 * @delay.enable: Time for the panel to display a valid frame.
100 * The time (in milliseconds) that it takes for the panel to
101 * display the first valid frame after starting to receive
107 * @delay.disable: Time for the panel to turn the display off.
109 * The time (in milliseconds) that it takes for the panel to
110 * turn the display off (no content is visible).
112 unsigned int disable;
115 * @delay.unprepare: Time to power down completely.
117 * The time (in milliseconds) that it takes for the panel
118 * to power itself down completely.
120 * This time is used to prevent a future "prepare" from
121 * starting until at least this many milliseconds has passed.
122 * If at prepare time less time has passed since unprepare
123 * finished, the driver waits for the remaining time.
125 unsigned int unprepare;
128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
138 struct panel_simple {
139 struct drm_panel base;
144 ktime_t prepared_time;
145 ktime_t unprepared_time;
147 const struct panel_desc *desc;
149 struct regulator *supply;
150 struct i2c_adapter *ddc;
152 struct gpio_desc *enable_gpio;
156 struct drm_display_mode override_mode;
158 enum drm_panel_orientation orientation;
161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
163 return container_of(panel, struct panel_simple, base);
166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
167 struct drm_connector *connector)
169 struct drm_display_mode *mode;
170 unsigned int i, num = 0;
172 for (i = 0; i < panel->desc->num_timings; i++) {
173 const struct display_timing *dt = &panel->desc->timings[i];
176 videomode_from_timing(dt, &vm);
177 mode = drm_mode_create(connector->dev);
179 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
180 dt->hactive.typ, dt->vactive.typ);
184 drm_display_mode_from_videomode(&vm, mode);
186 mode->type |= DRM_MODE_TYPE_DRIVER;
188 if (panel->desc->num_timings == 1)
189 mode->type |= DRM_MODE_TYPE_PREFERRED;
191 drm_mode_probed_add(connector, mode);
198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
199 struct drm_connector *connector)
201 struct drm_display_mode *mode;
202 unsigned int i, num = 0;
204 for (i = 0; i < panel->desc->num_modes; i++) {
205 const struct drm_display_mode *m = &panel->desc->modes[i];
207 mode = drm_mode_duplicate(connector->dev, m);
209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
210 m->hdisplay, m->vdisplay,
211 drm_mode_vrefresh(m));
215 mode->type |= DRM_MODE_TYPE_DRIVER;
217 if (panel->desc->num_modes == 1)
218 mode->type |= DRM_MODE_TYPE_PREFERRED;
220 drm_mode_set_name(mode);
222 drm_mode_probed_add(connector, mode);
229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
230 struct drm_connector *connector)
232 struct drm_display_mode *mode;
233 bool has_override = panel->override_mode.type;
234 unsigned int num = 0;
240 mode = drm_mode_duplicate(connector->dev,
241 &panel->override_mode);
243 drm_mode_probed_add(connector, mode);
246 dev_err(panel->base.dev, "failed to add override mode\n");
250 /* Only add timings if override was not there or failed to validate */
251 if (num == 0 && panel->desc->num_timings)
252 num = panel_simple_get_timings_modes(panel, connector);
255 * Only add fixed modes if timings/override added no mode.
257 * We should only ever have either the display timings specified
258 * or a fixed mode. Anything else is rather bogus.
260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
262 num = panel_simple_get_display_modes(panel, connector);
264 connector->display_info.bpc = panel->desc->bpc;
265 connector->display_info.width_mm = panel->desc->size.width;
266 connector->display_info.height_mm = panel->desc->size.height;
267 if (panel->desc->bus_format)
268 drm_display_info_set_bus_formats(&connector->display_info,
269 &panel->desc->bus_format, 1);
270 connector->display_info.bus_flags = panel->desc->bus_flags;
275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
277 ktime_t now_ktime, min_ktime;
282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
283 now_ktime = ktime_get_boottime();
285 if (ktime_before(now_ktime, min_ktime))
286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
289 static int panel_simple_disable(struct drm_panel *panel)
291 struct panel_simple *p = to_panel_simple(panel);
296 if (p->desc->delay.disable)
297 msleep(p->desc->delay.disable);
304 static int panel_simple_suspend(struct device *dev)
306 struct panel_simple *p = dev_get_drvdata(dev);
308 gpiod_set_value_cansleep(p->enable_gpio, 0);
309 regulator_disable(p->supply);
310 p->unprepared_time = ktime_get_boottime();
318 static int panel_simple_unprepare(struct drm_panel *panel)
320 struct panel_simple *p = to_panel_simple(panel);
323 /* Unpreparing when already unprepared is a no-op */
327 pm_runtime_mark_last_busy(panel->dev);
328 ret = pm_runtime_put_autosuspend(panel->dev);
336 static int panel_simple_resume(struct device *dev)
338 struct panel_simple *p = dev_get_drvdata(dev);
341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
343 err = regulator_enable(p->supply);
345 dev_err(dev, "failed to enable supply: %d\n", err);
349 gpiod_set_value_cansleep(p->enable_gpio, 1);
351 if (p->desc->delay.prepare)
352 msleep(p->desc->delay.prepare);
354 p->prepared_time = ktime_get_boottime();
359 static int panel_simple_prepare(struct drm_panel *panel)
361 struct panel_simple *p = to_panel_simple(panel);
364 /* Preparing when already prepared is a no-op */
368 ret = pm_runtime_get_sync(panel->dev);
370 pm_runtime_put_autosuspend(panel->dev);
379 static int panel_simple_enable(struct drm_panel *panel)
381 struct panel_simple *p = to_panel_simple(panel);
386 if (p->desc->delay.enable)
387 msleep(p->desc->delay.enable);
394 static int panel_simple_get_modes(struct drm_panel *panel,
395 struct drm_connector *connector)
397 struct panel_simple *p = to_panel_simple(panel);
400 /* probe EDID if a DDC bus is available */
402 pm_runtime_get_sync(panel->dev);
405 p->edid = drm_get_edid(connector, p->ddc);
408 num += drm_add_edid_modes(connector, p->edid);
410 pm_runtime_mark_last_busy(panel->dev);
411 pm_runtime_put_autosuspend(panel->dev);
414 /* add hard-coded panel modes */
415 num += panel_simple_get_non_edid_modes(p, connector);
418 * TODO: Remove once all drm drivers call
419 * drm_connector_set_orientation_from_panel()
421 drm_connector_set_panel_orientation(connector, p->orientation);
426 static int panel_simple_get_timings(struct drm_panel *panel,
427 unsigned int num_timings,
428 struct display_timing *timings)
430 struct panel_simple *p = to_panel_simple(panel);
433 if (p->desc->num_timings < num_timings)
434 num_timings = p->desc->num_timings;
437 for (i = 0; i < num_timings; i++)
438 timings[i] = p->desc->timings[i];
440 return p->desc->num_timings;
443 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
445 struct panel_simple *p = to_panel_simple(panel);
447 return p->orientation;
450 static const struct drm_panel_funcs panel_simple_funcs = {
451 .disable = panel_simple_disable,
452 .unprepare = panel_simple_unprepare,
453 .prepare = panel_simple_prepare,
454 .enable = panel_simple_enable,
455 .get_modes = panel_simple_get_modes,
456 .get_orientation = panel_simple_get_orientation,
457 .get_timings = panel_simple_get_timings,
460 static struct panel_desc panel_dpi;
462 static int panel_dpi_probe(struct device *dev,
463 struct panel_simple *panel)
465 struct display_timing *timing;
466 const struct device_node *np;
467 struct panel_desc *desc;
468 unsigned int bus_flags;
473 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
477 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
481 ret = of_get_display_timing(np, "panel-timing", timing);
483 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
488 desc->timings = timing;
489 desc->num_timings = 1;
491 of_property_read_u32(np, "width-mm", &desc->size.width);
492 of_property_read_u32(np, "height-mm", &desc->size.height);
494 /* Extract bus_flags from display_timing */
496 vm.flags = timing->flags;
497 drm_bus_flags_from_videomode(&vm, &bus_flags);
498 desc->bus_flags = bus_flags;
500 /* We do not know the connector for the DT node, so guess it */
501 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
508 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
509 (to_check->field.typ >= bounds->field.min && \
510 to_check->field.typ <= bounds->field.max)
511 static void panel_simple_parse_panel_timing_node(struct device *dev,
512 struct panel_simple *panel,
513 const struct display_timing *ot)
515 const struct panel_desc *desc = panel->desc;
519 if (WARN_ON(desc->num_modes)) {
520 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
523 if (WARN_ON(!desc->num_timings)) {
524 dev_err(dev, "Reject override mode: no timings specified\n");
528 for (i = 0; i < panel->desc->num_timings; i++) {
529 const struct display_timing *dt = &panel->desc->timings[i];
531 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
537 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
538 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
541 if (ot->flags != dt->flags)
544 videomode_from_timing(ot, &vm);
545 drm_display_mode_from_videomode(&vm, &panel->override_mode);
546 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
547 DRM_MODE_TYPE_PREFERRED;
551 if (WARN_ON(!panel->override_mode.type))
552 dev_err(dev, "Reject override mode: No display_timing found\n");
555 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
557 struct panel_simple *panel;
558 struct display_timing dt;
559 struct device_node *ddc;
564 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
568 panel->enabled = false;
569 panel->prepared_time = 0;
572 panel->supply = devm_regulator_get(dev, "power");
573 if (IS_ERR(panel->supply))
574 return PTR_ERR(panel->supply);
576 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
578 if (IS_ERR(panel->enable_gpio))
579 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
580 "failed to request GPIO\n");
582 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
584 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
588 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
590 panel->ddc = of_find_i2c_adapter_by_node(ddc);
594 return -EPROBE_DEFER;
597 if (desc == &panel_dpi) {
598 /* Handle the generic panel-dpi binding */
599 err = panel_dpi_probe(dev, panel);
604 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
605 panel_simple_parse_panel_timing_node(dev, panel, &dt);
608 connector_type = desc->connector_type;
609 /* Catch common mistakes for panels. */
610 switch (connector_type) {
612 dev_warn(dev, "Specify missing connector_type\n");
613 connector_type = DRM_MODE_CONNECTOR_DPI;
615 case DRM_MODE_CONNECTOR_LVDS:
616 WARN_ON(desc->bus_flags &
617 ~(DRM_BUS_FLAG_DE_LOW |
618 DRM_BUS_FLAG_DE_HIGH |
619 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
620 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
621 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
622 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
623 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
624 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
626 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
627 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
630 case DRM_MODE_CONNECTOR_eDP:
631 dev_warn(dev, "eDP panels moved to panel-edp\n");
634 case DRM_MODE_CONNECTOR_DSI:
635 if (desc->bpc != 6 && desc->bpc != 8)
636 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
638 case DRM_MODE_CONNECTOR_DPI:
639 bus_flags = DRM_BUS_FLAG_DE_LOW |
640 DRM_BUS_FLAG_DE_HIGH |
641 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
642 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
643 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
644 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
645 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
646 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
647 if (desc->bus_flags & ~bus_flags)
648 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
649 if (!(desc->bus_flags & bus_flags))
650 dev_warn(dev, "Specify missing bus_flags\n");
651 if (desc->bus_format == 0)
652 dev_warn(dev, "Specify missing bus_format\n");
653 if (desc->bpc != 6 && desc->bpc != 8)
654 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
657 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
658 connector_type = DRM_MODE_CONNECTOR_DPI;
662 dev_set_drvdata(dev, panel);
665 * We use runtime PM for prepare / unprepare since those power the panel
666 * on and off and those can be very slow operations. This is important
667 * to optimize powering the panel on briefly to read the EDID before
668 * fully enabling the panel.
670 pm_runtime_enable(dev);
671 pm_runtime_set_autosuspend_delay(dev, 1000);
672 pm_runtime_use_autosuspend(dev);
674 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
676 err = drm_panel_of_backlight(&panel->base);
678 dev_err_probe(dev, err, "Could not find backlight\n");
679 goto disable_pm_runtime;
682 drm_panel_add(&panel->base);
687 pm_runtime_dont_use_autosuspend(dev);
688 pm_runtime_disable(dev);
691 put_device(&panel->ddc->dev);
696 static void panel_simple_remove(struct device *dev)
698 struct panel_simple *panel = dev_get_drvdata(dev);
700 drm_panel_remove(&panel->base);
701 drm_panel_disable(&panel->base);
702 drm_panel_unprepare(&panel->base);
704 pm_runtime_dont_use_autosuspend(dev);
705 pm_runtime_disable(dev);
707 put_device(&panel->ddc->dev);
710 static void panel_simple_shutdown(struct device *dev)
712 struct panel_simple *panel = dev_get_drvdata(dev);
714 drm_panel_disable(&panel->base);
715 drm_panel_unprepare(&panel->base);
718 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
721 .hsync_start = 1280 + 40,
722 .hsync_end = 1280 + 40 + 80,
723 .htotal = 1280 + 40 + 80 + 40,
725 .vsync_start = 800 + 3,
726 .vsync_end = 800 + 3 + 10,
727 .vtotal = 800 + 3 + 10 + 10,
728 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
731 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
732 .modes = &ire_am_1280800n3tzqw_t00h_mode,
739 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
740 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
741 .connector_type = DRM_MODE_CONNECTOR_LVDS,
744 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
747 .hsync_start = 480 + 2,
748 .hsync_end = 480 + 2 + 41,
749 .htotal = 480 + 2 + 41 + 2,
751 .vsync_start = 272 + 2,
752 .vsync_end = 272 + 2 + 10,
753 .vtotal = 272 + 2 + 10 + 2,
754 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
757 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
758 .modes = &ire_am_480272h3tmqw_t01h_mode,
765 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
768 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
771 .hsync_start = 800 + 0,
772 .hsync_end = 800 + 0 + 255,
773 .htotal = 800 + 0 + 255 + 0,
775 .vsync_start = 480 + 2,
776 .vsync_end = 480 + 2 + 45,
777 .vtotal = 480 + 2 + 45 + 0,
778 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
781 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
782 .pixelclock = { 29930000, 33260000, 36590000 },
783 .hactive = { 800, 800, 800 },
784 .hfront_porch = { 1, 40, 168 },
785 .hback_porch = { 88, 88, 88 },
786 .hsync_len = { 1, 128, 128 },
787 .vactive = { 480, 480, 480 },
788 .vfront_porch = { 1, 35, 37 },
789 .vback_porch = { 8, 8, 8 },
790 .vsync_len = { 1, 2, 2 },
791 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
792 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
793 DISPLAY_FLAGS_SYNC_POSEDGE,
796 static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
797 .timings = &ire_am_800480l1tmqw_t00h_timing,
804 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
805 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
806 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
807 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
808 .connector_type = DRM_MODE_CONNECTOR_DPI,
811 static const struct panel_desc ampire_am800480r3tmqwa1h = {
812 .modes = &ire_am800480r3tmqwa1h_mode,
819 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
822 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
823 .pixelclock = { 34500000, 39600000, 50400000 },
824 .hactive = { 800, 800, 800 },
825 .hfront_porch = { 12, 112, 312 },
826 .hback_porch = { 87, 87, 48 },
827 .hsync_len = { 1, 1, 40 },
828 .vactive = { 600, 600, 600 },
829 .vfront_porch = { 1, 21, 61 },
830 .vback_porch = { 38, 38, 19 },
831 .vsync_len = { 1, 1, 20 },
832 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
833 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
834 DISPLAY_FLAGS_SYNC_POSEDGE,
837 static const struct panel_desc ampire_am800600p5tmqwtb8h = {
838 .timings = &ire_am800600p5tmqw_tb8h_timing,
845 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
846 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
847 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
848 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
849 .connector_type = DRM_MODE_CONNECTOR_DPI,
852 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
853 .pixelclock = { 26400000, 33300000, 46800000 },
854 .hactive = { 800, 800, 800 },
855 .hfront_porch = { 16, 210, 354 },
856 .hback_porch = { 45, 36, 6 },
857 .hsync_len = { 1, 10, 40 },
858 .vactive = { 480, 480, 480 },
859 .vfront_porch = { 7, 22, 147 },
860 .vback_porch = { 22, 13, 3 },
861 .vsync_len = { 1, 10, 20 },
862 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
863 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
866 static const struct panel_desc armadeus_st0700_adapt = {
867 .timings = &santek_st0700i5y_rbslw_f_timing,
874 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
875 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
878 static const struct drm_display_mode auo_b101aw03_mode = {
881 .hsync_start = 1024 + 156,
882 .hsync_end = 1024 + 156 + 8,
883 .htotal = 1024 + 156 + 8 + 156,
885 .vsync_start = 600 + 16,
886 .vsync_end = 600 + 16 + 6,
887 .vtotal = 600 + 16 + 6 + 16,
890 static const struct panel_desc auo_b101aw03 = {
891 .modes = &auo_b101aw03_mode,
898 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
899 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
900 .connector_type = DRM_MODE_CONNECTOR_LVDS,
903 static const struct drm_display_mode auo_b101xtn01_mode = {
906 .hsync_start = 1366 + 20,
907 .hsync_end = 1366 + 20 + 70,
908 .htotal = 1366 + 20 + 70,
910 .vsync_start = 768 + 14,
911 .vsync_end = 768 + 14 + 42,
912 .vtotal = 768 + 14 + 42,
913 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
916 static const struct panel_desc auo_b101xtn01 = {
917 .modes = &auo_b101xtn01_mode,
926 static const struct display_timing auo_g070vvn01_timings = {
927 .pixelclock = { 33300000, 34209000, 45000000 },
928 .hactive = { 800, 800, 800 },
929 .hfront_porch = { 20, 40, 200 },
930 .hback_porch = { 87, 40, 1 },
931 .hsync_len = { 1, 48, 87 },
932 .vactive = { 480, 480, 480 },
933 .vfront_porch = { 5, 13, 200 },
934 .vback_porch = { 31, 31, 29 },
935 .vsync_len = { 1, 1, 3 },
938 static const struct panel_desc auo_g070vvn01 = {
939 .timings = &auo_g070vvn01_timings,
954 static const struct drm_display_mode auo_g101evn010_mode = {
957 .hsync_start = 1280 + 82,
958 .hsync_end = 1280 + 82 + 2,
959 .htotal = 1280 + 82 + 2 + 84,
961 .vsync_start = 800 + 8,
962 .vsync_end = 800 + 8 + 2,
963 .vtotal = 800 + 8 + 2 + 6,
966 static const struct panel_desc auo_g101evn010 = {
967 .modes = &auo_g101evn010_mode,
974 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
975 .connector_type = DRM_MODE_CONNECTOR_LVDS,
978 static const struct drm_display_mode auo_g104sn02_mode = {
981 .hsync_start = 800 + 40,
982 .hsync_end = 800 + 40 + 216,
983 .htotal = 800 + 40 + 216 + 128,
985 .vsync_start = 600 + 10,
986 .vsync_end = 600 + 10 + 35,
987 .vtotal = 600 + 10 + 35 + 2,
990 static const struct panel_desc auo_g104sn02 = {
991 .modes = &auo_g104sn02_mode,
998 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
999 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1002 static const struct drm_display_mode auo_g121ean01_mode = {
1005 .hsync_start = 1280 + 58,
1006 .hsync_end = 1280 + 58 + 8,
1007 .htotal = 1280 + 58 + 8 + 70,
1009 .vsync_start = 800 + 6,
1010 .vsync_end = 800 + 6 + 4,
1011 .vtotal = 800 + 6 + 4 + 10,
1014 static const struct panel_desc auo_g121ean01 = {
1015 .modes = &auo_g121ean01_mode,
1022 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1023 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1026 static const struct display_timing auo_g133han01_timings = {
1027 .pixelclock = { 134000000, 141200000, 149000000 },
1028 .hactive = { 1920, 1920, 1920 },
1029 .hfront_porch = { 39, 58, 77 },
1030 .hback_porch = { 59, 88, 117 },
1031 .hsync_len = { 28, 42, 56 },
1032 .vactive = { 1080, 1080, 1080 },
1033 .vfront_porch = { 3, 8, 11 },
1034 .vback_porch = { 5, 14, 19 },
1035 .vsync_len = { 4, 14, 19 },
1038 static const struct panel_desc auo_g133han01 = {
1039 .timings = &auo_g133han01_timings,
1052 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1053 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1056 static const struct drm_display_mode auo_g156xtn01_mode = {
1059 .hsync_start = 1366 + 33,
1060 .hsync_end = 1366 + 33 + 67,
1063 .vsync_start = 768 + 4,
1064 .vsync_end = 768 + 4 + 4,
1068 static const struct panel_desc auo_g156xtn01 = {
1069 .modes = &auo_g156xtn01_mode,
1076 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1077 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1080 static const struct display_timing auo_g185han01_timings = {
1081 .pixelclock = { 120000000, 144000000, 175000000 },
1082 .hactive = { 1920, 1920, 1920 },
1083 .hfront_porch = { 36, 120, 148 },
1084 .hback_porch = { 24, 88, 108 },
1085 .hsync_len = { 20, 48, 64 },
1086 .vactive = { 1080, 1080, 1080 },
1087 .vfront_porch = { 6, 10, 40 },
1088 .vback_porch = { 2, 5, 20 },
1089 .vsync_len = { 2, 5, 20 },
1092 static const struct panel_desc auo_g185han01 = {
1093 .timings = &auo_g185han01_timings,
1106 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1107 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1110 static const struct display_timing auo_g190ean01_timings = {
1111 .pixelclock = { 90000000, 108000000, 135000000 },
1112 .hactive = { 1280, 1280, 1280 },
1113 .hfront_porch = { 126, 184, 1266 },
1114 .hback_porch = { 84, 122, 844 },
1115 .hsync_len = { 70, 102, 704 },
1116 .vactive = { 1024, 1024, 1024 },
1117 .vfront_porch = { 4, 26, 76 },
1118 .vback_porch = { 2, 8, 25 },
1119 .vsync_len = { 2, 8, 25 },
1122 static const struct panel_desc auo_g190ean01 = {
1123 .timings = &auo_g190ean01_timings,
1136 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1137 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1140 static const struct display_timing auo_p320hvn03_timings = {
1141 .pixelclock = { 106000000, 148500000, 164000000 },
1142 .hactive = { 1920, 1920, 1920 },
1143 .hfront_porch = { 25, 50, 130 },
1144 .hback_porch = { 25, 50, 130 },
1145 .hsync_len = { 20, 40, 105 },
1146 .vactive = { 1080, 1080, 1080 },
1147 .vfront_porch = { 8, 17, 150 },
1148 .vback_porch = { 8, 17, 150 },
1149 .vsync_len = { 4, 11, 100 },
1152 static const struct panel_desc auo_p320hvn03 = {
1153 .timings = &auo_p320hvn03_timings,
1165 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1166 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1169 static const struct drm_display_mode auo_t215hvn01_mode = {
1172 .hsync_start = 1920 + 88,
1173 .hsync_end = 1920 + 88 + 44,
1174 .htotal = 1920 + 88 + 44 + 148,
1176 .vsync_start = 1080 + 4,
1177 .vsync_end = 1080 + 4 + 5,
1178 .vtotal = 1080 + 4 + 5 + 36,
1181 static const struct panel_desc auo_t215hvn01 = {
1182 .modes = &auo_t215hvn01_mode,
1195 static const struct drm_display_mode avic_tm070ddh03_mode = {
1198 .hsync_start = 1024 + 160,
1199 .hsync_end = 1024 + 160 + 4,
1200 .htotal = 1024 + 160 + 4 + 156,
1202 .vsync_start = 600 + 17,
1203 .vsync_end = 600 + 17 + 1,
1204 .vtotal = 600 + 17 + 1 + 17,
1207 static const struct panel_desc avic_tm070ddh03 = {
1208 .modes = &avic_tm070ddh03_mode,
1222 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1225 .hsync_start = 800 + 40,
1226 .hsync_end = 800 + 40 + 48,
1227 .htotal = 800 + 40 + 48 + 40,
1229 .vsync_start = 480 + 13,
1230 .vsync_end = 480 + 13 + 3,
1231 .vtotal = 480 + 13 + 3 + 29,
1234 static const struct panel_desc bananapi_s070wv20_ct16 = {
1235 .modes = &bananapi_s070wv20_ct16_mode,
1244 static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1245 .pixelclock = { 69922000, 71000000, 72293000 },
1246 .hactive = { 1280, 1280, 1280 },
1247 .hfront_porch = { 48, 48, 48 },
1248 .hback_porch = { 80, 80, 80 },
1249 .hsync_len = { 32, 32, 32 },
1250 .vactive = { 800, 800, 800 },
1251 .vfront_porch = { 3, 3, 3 },
1252 .vback_porch = { 14, 14, 14 },
1253 .vsync_len = { 6, 6, 6 },
1256 static const struct panel_desc boe_ev121wxm_n10_1850 = {
1257 .timings = &boe_ev121wxm_n10_1850_timing,
1270 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1271 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1272 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1275 static const struct drm_display_mode boe_hv070wsa_mode = {
1278 .hsync_start = 1024 + 30,
1279 .hsync_end = 1024 + 30 + 30,
1280 .htotal = 1024 + 30 + 30 + 30,
1282 .vsync_start = 600 + 10,
1283 .vsync_end = 600 + 10 + 10,
1284 .vtotal = 600 + 10 + 10 + 10,
1287 static const struct panel_desc boe_hv070wsa = {
1288 .modes = &boe_hv070wsa_mode,
1295 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1296 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1297 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1300 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1303 .hsync_start = 480 + 5,
1304 .hsync_end = 480 + 5 + 5,
1305 .htotal = 480 + 5 + 5 + 40,
1307 .vsync_start = 272 + 8,
1308 .vsync_end = 272 + 8 + 8,
1309 .vtotal = 272 + 8 + 8 + 8,
1310 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1313 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1314 .modes = &cdtech_s043wq26h_ct7_mode,
1321 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1324 /* S070PWS19HP-FC21 2017/04/22 */
1325 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1328 .hsync_start = 1024 + 160,
1329 .hsync_end = 1024 + 160 + 20,
1330 .htotal = 1024 + 160 + 20 + 140,
1332 .vsync_start = 600 + 12,
1333 .vsync_end = 600 + 12 + 3,
1334 .vtotal = 600 + 12 + 3 + 20,
1335 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1338 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1339 .modes = &cdtech_s070pws19hp_fc21_mode,
1346 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1347 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1348 .connector_type = DRM_MODE_CONNECTOR_DPI,
1351 /* S070SWV29HG-DC44 2017/09/21 */
1352 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1355 .hsync_start = 800 + 210,
1356 .hsync_end = 800 + 210 + 2,
1357 .htotal = 800 + 210 + 2 + 44,
1359 .vsync_start = 480 + 22,
1360 .vsync_end = 480 + 22 + 2,
1361 .vtotal = 480 + 22 + 2 + 21,
1362 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1365 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1366 .modes = &cdtech_s070swv29hg_dc44_mode,
1373 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1374 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1375 .connector_type = DRM_MODE_CONNECTOR_DPI,
1378 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1381 .hsync_start = 800 + 40,
1382 .hsync_end = 800 + 40 + 40,
1383 .htotal = 800 + 40 + 40 + 48,
1385 .vsync_start = 480 + 29,
1386 .vsync_end = 480 + 29 + 13,
1387 .vtotal = 480 + 29 + 13 + 3,
1388 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1391 static const struct panel_desc cdtech_s070wv95_ct16 = {
1392 .modes = &cdtech_s070wv95_ct16_mode,
1401 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1402 .pixelclock = { 68900000, 71100000, 73400000 },
1403 .hactive = { 1280, 1280, 1280 },
1404 .hfront_porch = { 65, 80, 95 },
1405 .hback_porch = { 64, 79, 94 },
1406 .hsync_len = { 1, 1, 1 },
1407 .vactive = { 800, 800, 800 },
1408 .vfront_porch = { 7, 11, 14 },
1409 .vback_porch = { 7, 11, 14 },
1410 .vsync_len = { 1, 1, 1 },
1411 .flags = DISPLAY_FLAGS_DE_HIGH,
1414 static const struct panel_desc chefree_ch101olhlwh_002 = {
1415 .timings = &chefree_ch101olhlwh_002_timing,
1426 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1427 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1428 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1431 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1434 .hsync_start = 800 + 49,
1435 .hsync_end = 800 + 49 + 33,
1436 .htotal = 800 + 49 + 33 + 17,
1438 .vsync_start = 1280 + 1,
1439 .vsync_end = 1280 + 1 + 7,
1440 .vtotal = 1280 + 1 + 7 + 15,
1441 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1444 static const struct panel_desc chunghwa_claa070wp03xg = {
1445 .modes = &chunghwa_claa070wp03xg_mode,
1452 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1453 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1454 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1457 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1460 .hsync_start = 1366 + 58,
1461 .hsync_end = 1366 + 58 + 58,
1462 .htotal = 1366 + 58 + 58 + 58,
1464 .vsync_start = 768 + 4,
1465 .vsync_end = 768 + 4 + 4,
1466 .vtotal = 768 + 4 + 4 + 4,
1469 static const struct panel_desc chunghwa_claa101wa01a = {
1470 .modes = &chunghwa_claa101wa01a_mode,
1477 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1478 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1479 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1482 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1485 .hsync_start = 1366 + 48,
1486 .hsync_end = 1366 + 48 + 32,
1487 .htotal = 1366 + 48 + 32 + 20,
1489 .vsync_start = 768 + 16,
1490 .vsync_end = 768 + 16 + 8,
1491 .vtotal = 768 + 16 + 8 + 16,
1494 static const struct panel_desc chunghwa_claa101wb01 = {
1495 .modes = &chunghwa_claa101wb01_mode,
1502 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1503 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1504 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1507 static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1508 .pixelclock = { 5000000, 9000000, 12000000 },
1509 .hactive = { 480, 480, 480 },
1510 .hfront_porch = { 12, 12, 12 },
1511 .hback_porch = { 12, 12, 12 },
1512 .hsync_len = { 21, 21, 21 },
1513 .vactive = { 272, 272, 272 },
1514 .vfront_porch = { 4, 4, 4 },
1515 .vback_porch = { 4, 4, 4 },
1516 .vsync_len = { 8, 8, 8 },
1519 static const struct panel_desc dataimage_fg040346dsswbg04 = {
1520 .timings = &dataimage_fg040346dsswbg04_timing,
1527 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1528 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1529 .connector_type = DRM_MODE_CONNECTOR_DPI,
1532 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1533 .pixelclock = { 68900000, 71110000, 73400000 },
1534 .hactive = { 1280, 1280, 1280 },
1535 .vactive = { 800, 800, 800 },
1536 .hback_porch = { 100, 100, 100 },
1537 .hfront_porch = { 100, 100, 100 },
1538 .vback_porch = { 5, 5, 5 },
1539 .vfront_porch = { 5, 5, 5 },
1540 .hsync_len = { 24, 24, 24 },
1541 .vsync_len = { 3, 3, 3 },
1542 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1543 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1546 static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1547 .timings = &dataimage_fg1001l0dsswmg01_timing,
1556 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1559 .hsync_start = 800 + 40,
1560 .hsync_end = 800 + 40 + 128,
1561 .htotal = 800 + 40 + 128 + 88,
1563 .vsync_start = 480 + 10,
1564 .vsync_end = 480 + 10 + 2,
1565 .vtotal = 480 + 10 + 2 + 33,
1566 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1569 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1570 .modes = &dataimage_scf0700c48ggu18_mode,
1577 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1578 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1581 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1582 .pixelclock = { 45000000, 51200000, 57000000 },
1583 .hactive = { 1024, 1024, 1024 },
1584 .hfront_porch = { 100, 106, 113 },
1585 .hback_porch = { 100, 106, 113 },
1586 .hsync_len = { 100, 108, 114 },
1587 .vactive = { 600, 600, 600 },
1588 .vfront_porch = { 8, 11, 15 },
1589 .vback_porch = { 8, 11, 15 },
1590 .vsync_len = { 9, 13, 15 },
1591 .flags = DISPLAY_FLAGS_DE_HIGH,
1594 static const struct panel_desc dlc_dlc0700yzg_1 = {
1595 .timings = &dlc_dlc0700yzg_1_timing,
1607 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1608 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1611 static const struct display_timing dlc_dlc1010gig_timing = {
1612 .pixelclock = { 68900000, 71100000, 73400000 },
1613 .hactive = { 1280, 1280, 1280 },
1614 .hfront_porch = { 43, 53, 63 },
1615 .hback_porch = { 43, 53, 63 },
1616 .hsync_len = { 44, 54, 64 },
1617 .vactive = { 800, 800, 800 },
1618 .vfront_porch = { 5, 8, 11 },
1619 .vback_porch = { 5, 8, 11 },
1620 .vsync_len = { 5, 7, 11 },
1621 .flags = DISPLAY_FLAGS_DE_HIGH,
1624 static const struct panel_desc dlc_dlc1010gig = {
1625 .timings = &dlc_dlc1010gig_timing,
1638 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1639 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1642 static const struct drm_display_mode edt_et035012dm6_mode = {
1645 .hsync_start = 320 + 20,
1646 .hsync_end = 320 + 20 + 30,
1647 .htotal = 320 + 20 + 68,
1649 .vsync_start = 240 + 4,
1650 .vsync_end = 240 + 4 + 4,
1651 .vtotal = 240 + 4 + 4 + 14,
1652 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1655 static const struct panel_desc edt_et035012dm6 = {
1656 .modes = &edt_et035012dm6_mode,
1663 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1664 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1667 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1670 .hsync_start = 320 + 20,
1671 .hsync_end = 320 + 20 + 68,
1672 .htotal = 320 + 20 + 68,
1674 .vsync_start = 240 + 4,
1675 .vsync_end = 240 + 4 + 18,
1676 .vtotal = 240 + 4 + 18,
1677 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1680 static const struct panel_desc edt_etm0350g0dh6 = {
1681 .modes = &edt_etm0350g0dh6_mode,
1688 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1689 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1690 .connector_type = DRM_MODE_CONNECTOR_DPI,
1693 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1696 .hsync_start = 480 + 8,
1697 .hsync_end = 480 + 8 + 4,
1698 .htotal = 480 + 8 + 4 + 41,
1701 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1706 .vsync_start = 288 + 2,
1707 .vsync_end = 288 + 2 + 4,
1708 .vtotal = 288 + 2 + 4 + 10,
1711 static const struct panel_desc edt_etm043080dh6gp = {
1712 .modes = &edt_etm043080dh6gp_mode,
1719 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1720 .connector_type = DRM_MODE_CONNECTOR_DPI,
1723 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1726 .hsync_start = 480 + 2,
1727 .hsync_end = 480 + 2 + 41,
1728 .htotal = 480 + 2 + 41 + 2,
1730 .vsync_start = 272 + 2,
1731 .vsync_end = 272 + 2 + 10,
1732 .vtotal = 272 + 2 + 10 + 2,
1733 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1736 static const struct panel_desc edt_etm0430g0dh6 = {
1737 .modes = &edt_etm0430g0dh6_mode,
1744 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1745 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1746 .connector_type = DRM_MODE_CONNECTOR_DPI,
1749 static const struct drm_display_mode edt_et057090dhu_mode = {
1752 .hsync_start = 640 + 16,
1753 .hsync_end = 640 + 16 + 30,
1754 .htotal = 640 + 16 + 30 + 114,
1756 .vsync_start = 480 + 10,
1757 .vsync_end = 480 + 10 + 3,
1758 .vtotal = 480 + 10 + 3 + 32,
1759 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1762 static const struct panel_desc edt_et057090dhu = {
1763 .modes = &edt_et057090dhu_mode,
1770 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1771 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1772 .connector_type = DRM_MODE_CONNECTOR_DPI,
1775 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1778 .hsync_start = 800 + 40,
1779 .hsync_end = 800 + 40 + 128,
1780 .htotal = 800 + 40 + 128 + 88,
1782 .vsync_start = 480 + 10,
1783 .vsync_end = 480 + 10 + 2,
1784 .vtotal = 480 + 10 + 2 + 33,
1785 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1788 static const struct panel_desc edt_etm0700g0dh6 = {
1789 .modes = &edt_etm0700g0dh6_mode,
1796 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1797 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1798 .connector_type = DRM_MODE_CONNECTOR_DPI,
1801 static const struct panel_desc edt_etm0700g0bdh6 = {
1802 .modes = &edt_etm0700g0dh6_mode,
1809 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1810 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1811 .connector_type = DRM_MODE_CONNECTOR_DPI,
1814 static const struct display_timing edt_etml0700y5dha_timing = {
1815 .pixelclock = { 40800000, 51200000, 67200000 },
1816 .hactive = { 1024, 1024, 1024 },
1817 .hfront_porch = { 30, 106, 125 },
1818 .hback_porch = { 30, 106, 125 },
1819 .hsync_len = { 30, 108, 126 },
1820 .vactive = { 600, 600, 600 },
1821 .vfront_porch = { 3, 12, 67},
1822 .vback_porch = { 3, 12, 67 },
1823 .vsync_len = { 4, 11, 66 },
1824 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1825 DISPLAY_FLAGS_DE_HIGH,
1828 static const struct panel_desc edt_etml0700y5dha = {
1829 .timings = &edt_etml0700y5dha_timing,
1836 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1837 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1840 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
1844 .hsync_end = 640 + 16,
1845 .htotal = 640 + 16 + 30 + 114,
1847 .vsync_start = 480 + 10,
1848 .vsync_end = 480 + 10 + 3,
1849 .vtotal = 480 + 10 + 3 + 35,
1850 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
1853 static const struct panel_desc edt_etmv570g2dhu = {
1854 .modes = &edt_etmv570g2dhu_mode,
1861 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1862 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1863 .connector_type = DRM_MODE_CONNECTOR_DPI,
1866 static const struct display_timing eink_vb3300_kca_timing = {
1867 .pixelclock = { 40000000, 40000000, 40000000 },
1868 .hactive = { 334, 334, 334 },
1869 .hfront_porch = { 1, 1, 1 },
1870 .hback_porch = { 1, 1, 1 },
1871 .hsync_len = { 1, 1, 1 },
1872 .vactive = { 1405, 1405, 1405 },
1873 .vfront_porch = { 1, 1, 1 },
1874 .vback_porch = { 1, 1, 1 },
1875 .vsync_len = { 1, 1, 1 },
1876 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1877 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
1880 static const struct panel_desc eink_vb3300_kca = {
1881 .timings = &eink_vb3300_kca_timing,
1888 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1889 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1890 .connector_type = DRM_MODE_CONNECTOR_DPI,
1893 static const struct display_timing evervision_vgg804821_timing = {
1894 .pixelclock = { 27600000, 33300000, 50000000 },
1895 .hactive = { 800, 800, 800 },
1896 .hfront_porch = { 40, 66, 70 },
1897 .hback_porch = { 40, 67, 70 },
1898 .hsync_len = { 40, 67, 70 },
1899 .vactive = { 480, 480, 480 },
1900 .vfront_porch = { 6, 10, 10 },
1901 .vback_porch = { 7, 11, 11 },
1902 .vsync_len = { 7, 11, 11 },
1903 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1904 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1905 DISPLAY_FLAGS_SYNC_NEGEDGE,
1908 static const struct panel_desc evervision_vgg804821 = {
1909 .timings = &evervision_vgg804821_timing,
1916 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1917 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1920 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1923 .hsync_start = 800 + 168,
1924 .hsync_end = 800 + 168 + 64,
1925 .htotal = 800 + 168 + 64 + 88,
1927 .vsync_start = 480 + 37,
1928 .vsync_end = 480 + 37 + 2,
1929 .vtotal = 480 + 37 + 2 + 8,
1932 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1933 .modes = &foxlink_fl500wvr00_a0t_mode,
1940 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1943 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1947 .hsync_start = 320 + 44,
1948 .hsync_end = 320 + 44 + 16,
1949 .htotal = 320 + 44 + 16 + 20,
1951 .vsync_start = 240 + 2,
1952 .vsync_end = 240 + 2 + 6,
1953 .vtotal = 240 + 2 + 6 + 2,
1954 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1959 .hsync_start = 320 + 56,
1960 .hsync_end = 320 + 56 + 16,
1961 .htotal = 320 + 56 + 16 + 40,
1963 .vsync_start = 240 + 2,
1964 .vsync_end = 240 + 2 + 6,
1965 .vtotal = 240 + 2 + 6 + 2,
1966 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1970 static const struct panel_desc frida_frd350h54004 = {
1971 .modes = frida_frd350h54004_modes,
1972 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1978 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1979 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1980 .connector_type = DRM_MODE_CONNECTOR_DPI,
1983 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1986 .hsync_start = 800 + 20,
1987 .hsync_end = 800 + 20 + 24,
1988 .htotal = 800 + 20 + 24 + 20,
1990 .vsync_start = 1280 + 4,
1991 .vsync_end = 1280 + 4 + 8,
1992 .vtotal = 1280 + 4 + 8 + 4,
1993 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1996 static const struct panel_desc friendlyarm_hd702e = {
1997 .modes = &friendlyarm_hd702e_mode,
2005 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2008 .hsync_start = 480 + 5,
2009 .hsync_end = 480 + 5 + 1,
2010 .htotal = 480 + 5 + 1 + 40,
2012 .vsync_start = 272 + 8,
2013 .vsync_end = 272 + 8 + 1,
2014 .vtotal = 272 + 8 + 1 + 8,
2017 static const struct panel_desc giantplus_gpg482739qs5 = {
2018 .modes = &giantplus_gpg482739qs5_mode,
2025 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2028 static const struct display_timing giantplus_gpm940b0_timing = {
2029 .pixelclock = { 13500000, 27000000, 27500000 },
2030 .hactive = { 320, 320, 320 },
2031 .hfront_porch = { 14, 686, 718 },
2032 .hback_porch = { 50, 70, 255 },
2033 .hsync_len = { 1, 1, 1 },
2034 .vactive = { 240, 240, 240 },
2035 .vfront_porch = { 1, 1, 179 },
2036 .vback_porch = { 1, 21, 31 },
2037 .vsync_len = { 1, 1, 6 },
2038 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2041 static const struct panel_desc giantplus_gpm940b0 = {
2042 .timings = &giantplus_gpm940b0_timing,
2049 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2050 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2053 static const struct display_timing hannstar_hsd070pww1_timing = {
2054 .pixelclock = { 64300000, 71100000, 82000000 },
2055 .hactive = { 1280, 1280, 1280 },
2056 .hfront_porch = { 1, 1, 10 },
2057 .hback_porch = { 1, 1, 10 },
2059 * According to the data sheet, the minimum horizontal blanking interval
2060 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2061 * minimum working horizontal blanking interval to be 60 clocks.
2063 .hsync_len = { 58, 158, 661 },
2064 .vactive = { 800, 800, 800 },
2065 .vfront_porch = { 1, 1, 10 },
2066 .vback_porch = { 1, 1, 10 },
2067 .vsync_len = { 1, 21, 203 },
2068 .flags = DISPLAY_FLAGS_DE_HIGH,
2071 static const struct panel_desc hannstar_hsd070pww1 = {
2072 .timings = &hannstar_hsd070pww1_timing,
2079 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2080 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2083 static const struct display_timing hannstar_hsd100pxn1_timing = {
2084 .pixelclock = { 55000000, 65000000, 75000000 },
2085 .hactive = { 1024, 1024, 1024 },
2086 .hfront_porch = { 40, 40, 40 },
2087 .hback_porch = { 220, 220, 220 },
2088 .hsync_len = { 20, 60, 100 },
2089 .vactive = { 768, 768, 768 },
2090 .vfront_porch = { 7, 7, 7 },
2091 .vback_porch = { 21, 21, 21 },
2092 .vsync_len = { 10, 10, 10 },
2093 .flags = DISPLAY_FLAGS_DE_HIGH,
2096 static const struct panel_desc hannstar_hsd100pxn1 = {
2097 .timings = &hannstar_hsd100pxn1_timing,
2104 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2105 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2108 static const struct display_timing hannstar_hsd101pww2_timing = {
2109 .pixelclock = { 64300000, 71100000, 82000000 },
2110 .hactive = { 1280, 1280, 1280 },
2111 .hfront_porch = { 1, 1, 10 },
2112 .hback_porch = { 1, 1, 10 },
2113 .hsync_len = { 58, 158, 661 },
2114 .vactive = { 800, 800, 800 },
2115 .vfront_porch = { 1, 1, 10 },
2116 .vback_porch = { 1, 1, 10 },
2117 .vsync_len = { 1, 21, 203 },
2118 .flags = DISPLAY_FLAGS_DE_HIGH,
2121 static const struct panel_desc hannstar_hsd101pww2 = {
2122 .timings = &hannstar_hsd101pww2_timing,
2129 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2130 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2133 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2136 .hsync_start = 800 + 85,
2137 .hsync_end = 800 + 85 + 86,
2138 .htotal = 800 + 85 + 86 + 85,
2140 .vsync_start = 480 + 16,
2141 .vsync_end = 480 + 16 + 13,
2142 .vtotal = 480 + 16 + 13 + 16,
2145 static const struct panel_desc hitachi_tx23d38vm0caa = {
2146 .modes = &hitachi_tx23d38vm0caa_mode,
2159 static const struct drm_display_mode innolux_at043tn24_mode = {
2162 .hsync_start = 480 + 2,
2163 .hsync_end = 480 + 2 + 41,
2164 .htotal = 480 + 2 + 41 + 2,
2166 .vsync_start = 272 + 2,
2167 .vsync_end = 272 + 2 + 10,
2168 .vtotal = 272 + 2 + 10 + 2,
2169 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2172 static const struct panel_desc innolux_at043tn24 = {
2173 .modes = &innolux_at043tn24_mode,
2180 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2181 .connector_type = DRM_MODE_CONNECTOR_DPI,
2182 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2185 static const struct drm_display_mode innolux_at070tn92_mode = {
2188 .hsync_start = 800 + 210,
2189 .hsync_end = 800 + 210 + 20,
2190 .htotal = 800 + 210 + 20 + 46,
2192 .vsync_start = 480 + 22,
2193 .vsync_end = 480 + 22 + 10,
2194 .vtotal = 480 + 22 + 23 + 10,
2197 static const struct panel_desc innolux_at070tn92 = {
2198 .modes = &innolux_at070tn92_mode,
2204 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2207 static const struct display_timing innolux_g070ace_l01_timing = {
2208 .pixelclock = { 25200000, 35000000, 35700000 },
2209 .hactive = { 800, 800, 800 },
2210 .hfront_porch = { 30, 32, 87 },
2211 .hback_porch = { 30, 32, 87 },
2212 .hsync_len = { 1, 1, 1 },
2213 .vactive = { 480, 480, 480 },
2214 .vfront_porch = { 3, 3, 3 },
2215 .vback_porch = { 13, 13, 13 },
2216 .vsync_len = { 1, 1, 4 },
2217 .flags = DISPLAY_FLAGS_DE_HIGH,
2220 static const struct panel_desc innolux_g070ace_l01 = {
2221 .timings = &innolux_g070ace_l01_timing,
2234 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2235 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2236 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2239 static const struct display_timing innolux_g070y2_l01_timing = {
2240 .pixelclock = { 28000000, 29500000, 32000000 },
2241 .hactive = { 800, 800, 800 },
2242 .hfront_porch = { 61, 91, 141 },
2243 .hback_porch = { 60, 90, 140 },
2244 .hsync_len = { 12, 12, 12 },
2245 .vactive = { 480, 480, 480 },
2246 .vfront_porch = { 4, 9, 30 },
2247 .vback_porch = { 4, 8, 28 },
2248 .vsync_len = { 2, 2, 2 },
2249 .flags = DISPLAY_FLAGS_DE_HIGH,
2252 static const struct panel_desc innolux_g070y2_l01 = {
2253 .timings = &innolux_g070y2_l01_timing,
2266 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2267 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2268 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2271 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2274 .hsync_start = 800 + 210,
2275 .hsync_end = 800 + 210 + 20,
2276 .htotal = 800 + 210 + 20 + 46,
2278 .vsync_start = 480 + 22,
2279 .vsync_end = 480 + 22 + 10,
2280 .vtotal = 480 + 22 + 23 + 10,
2283 static const struct panel_desc innolux_g070y2_t02 = {
2284 .modes = &innolux_g070y2_t02_mode,
2291 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2292 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2293 .connector_type = DRM_MODE_CONNECTOR_DPI,
2296 static const struct display_timing innolux_g101ice_l01_timing = {
2297 .pixelclock = { 60400000, 71100000, 74700000 },
2298 .hactive = { 1280, 1280, 1280 },
2299 .hfront_porch = { 41, 80, 100 },
2300 .hback_porch = { 40, 79, 99 },
2301 .hsync_len = { 1, 1, 1 },
2302 .vactive = { 800, 800, 800 },
2303 .vfront_porch = { 5, 11, 14 },
2304 .vback_porch = { 4, 11, 14 },
2305 .vsync_len = { 1, 1, 1 },
2306 .flags = DISPLAY_FLAGS_DE_HIGH,
2309 static const struct panel_desc innolux_g101ice_l01 = {
2310 .timings = &innolux_g101ice_l01_timing,
2321 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2322 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2325 static const struct display_timing innolux_g121i1_l01_timing = {
2326 .pixelclock = { 67450000, 71000000, 74550000 },
2327 .hactive = { 1280, 1280, 1280 },
2328 .hfront_porch = { 40, 80, 160 },
2329 .hback_porch = { 39, 79, 159 },
2330 .hsync_len = { 1, 1, 1 },
2331 .vactive = { 800, 800, 800 },
2332 .vfront_porch = { 5, 11, 100 },
2333 .vback_porch = { 4, 11, 99 },
2334 .vsync_len = { 1, 1, 1 },
2337 static const struct panel_desc innolux_g121i1_l01 = {
2338 .timings = &innolux_g121i1_l01_timing,
2349 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2350 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2353 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2356 .hsync_start = 1024 + 0,
2357 .hsync_end = 1024 + 1,
2358 .htotal = 1024 + 0 + 1 + 320,
2360 .vsync_start = 768 + 38,
2361 .vsync_end = 768 + 38 + 1,
2362 .vtotal = 768 + 38 + 1 + 0,
2363 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2366 static const struct panel_desc innolux_g121x1_l03 = {
2367 .modes = &innolux_g121x1_l03_mode,
2381 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2384 .hsync_start = 1366 + 16,
2385 .hsync_end = 1366 + 16 + 34,
2386 .htotal = 1366 + 16 + 34 + 50,
2388 .vsync_start = 768 + 2,
2389 .vsync_end = 768 + 2 + 6,
2390 .vtotal = 768 + 2 + 6 + 12,
2393 static const struct panel_desc innolux_n156bge_l21 = {
2394 .modes = &innolux_n156bge_l21_mode,
2401 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2402 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2403 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2406 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2409 .hsync_start = 1024 + 128,
2410 .hsync_end = 1024 + 128 + 64,
2411 .htotal = 1024 + 128 + 64 + 128,
2413 .vsync_start = 600 + 16,
2414 .vsync_end = 600 + 16 + 4,
2415 .vtotal = 600 + 16 + 4 + 16,
2418 static const struct panel_desc innolux_zj070na_01p = {
2419 .modes = &innolux_zj070na_01p_mode,
2428 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2429 .pixelclock = { 5580000, 5850000, 6200000 },
2430 .hactive = { 320, 320, 320 },
2431 .hfront_porch = { 30, 30, 30 },
2432 .hback_porch = { 30, 30, 30 },
2433 .hsync_len = { 1, 5, 17 },
2434 .vactive = { 240, 240, 240 },
2435 .vfront_porch = { 6, 6, 6 },
2436 .vback_porch = { 5, 5, 5 },
2437 .vsync_len = { 1, 2, 11 },
2438 .flags = DISPLAY_FLAGS_DE_HIGH,
2441 static const struct panel_desc koe_tx14d24vm1bpa = {
2442 .timings = &koe_tx14d24vm1bpa_timing,
2451 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2452 .pixelclock = { 151820000, 156720000, 159780000 },
2453 .hactive = { 1920, 1920, 1920 },
2454 .hfront_porch = { 105, 130, 142 },
2455 .hback_porch = { 45, 70, 82 },
2456 .hsync_len = { 30, 30, 30 },
2457 .vactive = { 1200, 1200, 1200},
2458 .vfront_porch = { 3, 5, 10 },
2459 .vback_porch = { 2, 5, 10 },
2460 .vsync_len = { 5, 5, 5 },
2463 static const struct panel_desc koe_tx26d202vm0bwa = {
2464 .timings = &koe_tx26d202vm0bwa_timing,
2477 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2478 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2479 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2482 static const struct display_timing koe_tx31d200vm0baa_timing = {
2483 .pixelclock = { 39600000, 43200000, 48000000 },
2484 .hactive = { 1280, 1280, 1280 },
2485 .hfront_porch = { 16, 36, 56 },
2486 .hback_porch = { 16, 36, 56 },
2487 .hsync_len = { 8, 8, 8 },
2488 .vactive = { 480, 480, 480 },
2489 .vfront_porch = { 6, 21, 33 },
2490 .vback_porch = { 6, 21, 33 },
2491 .vsync_len = { 8, 8, 8 },
2492 .flags = DISPLAY_FLAGS_DE_HIGH,
2495 static const struct panel_desc koe_tx31d200vm0baa = {
2496 .timings = &koe_tx31d200vm0baa_timing,
2503 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2504 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2507 static const struct display_timing kyo_tcg121xglp_timing = {
2508 .pixelclock = { 52000000, 65000000, 71000000 },
2509 .hactive = { 1024, 1024, 1024 },
2510 .hfront_porch = { 2, 2, 2 },
2511 .hback_porch = { 2, 2, 2 },
2512 .hsync_len = { 86, 124, 244 },
2513 .vactive = { 768, 768, 768 },
2514 .vfront_porch = { 2, 2, 2 },
2515 .vback_porch = { 2, 2, 2 },
2516 .vsync_len = { 6, 34, 73 },
2517 .flags = DISPLAY_FLAGS_DE_HIGH,
2520 static const struct panel_desc kyo_tcg121xglp = {
2521 .timings = &kyo_tcg121xglp_timing,
2528 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2529 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2532 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2535 .hsync_start = 320 + 20,
2536 .hsync_end = 320 + 20 + 30,
2537 .htotal = 320 + 20 + 30 + 38,
2539 .vsync_start = 240 + 4,
2540 .vsync_end = 240 + 4 + 3,
2541 .vtotal = 240 + 4 + 3 + 15,
2544 static const struct panel_desc lemaker_bl035_rgb_002 = {
2545 .modes = &lemaker_bl035_rgb_002_mode,
2551 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2552 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2555 static const struct drm_display_mode lg_lb070wv8_mode = {
2558 .hsync_start = 800 + 88,
2559 .hsync_end = 800 + 88 + 80,
2560 .htotal = 800 + 88 + 80 + 88,
2562 .vsync_start = 480 + 10,
2563 .vsync_end = 480 + 10 + 25,
2564 .vtotal = 480 + 10 + 25 + 10,
2567 static const struct panel_desc lg_lb070wv8 = {
2568 .modes = &lg_lb070wv8_mode,
2575 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2576 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2579 static const struct display_timing logictechno_lt161010_2nh_timing = {
2580 .pixelclock = { 26400000, 33300000, 46800000 },
2581 .hactive = { 800, 800, 800 },
2582 .hfront_porch = { 16, 210, 354 },
2583 .hback_porch = { 46, 46, 46 },
2584 .hsync_len = { 1, 20, 40 },
2585 .vactive = { 480, 480, 480 },
2586 .vfront_porch = { 7, 22, 147 },
2587 .vback_porch = { 23, 23, 23 },
2588 .vsync_len = { 1, 10, 20 },
2589 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2590 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2591 DISPLAY_FLAGS_SYNC_POSEDGE,
2594 static const struct panel_desc logictechno_lt161010_2nh = {
2595 .timings = &logictechno_lt161010_2nh_timing,
2602 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2603 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2604 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2605 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2606 .connector_type = DRM_MODE_CONNECTOR_DPI,
2609 static const struct display_timing logictechno_lt170410_2whc_timing = {
2610 .pixelclock = { 68900000, 71100000, 73400000 },
2611 .hactive = { 1280, 1280, 1280 },
2612 .hfront_porch = { 23, 60, 71 },
2613 .hback_porch = { 23, 60, 71 },
2614 .hsync_len = { 15, 40, 47 },
2615 .vactive = { 800, 800, 800 },
2616 .vfront_porch = { 5, 7, 10 },
2617 .vback_porch = { 5, 7, 10 },
2618 .vsync_len = { 6, 9, 12 },
2619 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2620 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2621 DISPLAY_FLAGS_SYNC_POSEDGE,
2624 static const struct panel_desc logictechno_lt170410_2whc = {
2625 .timings = &logictechno_lt170410_2whc_timing,
2632 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2633 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2634 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2637 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2640 .hsync_start = 800 + 112,
2641 .hsync_end = 800 + 112 + 3,
2642 .htotal = 800 + 112 + 3 + 85,
2644 .vsync_start = 480 + 38,
2645 .vsync_end = 480 + 38 + 3,
2646 .vtotal = 480 + 38 + 3 + 29,
2647 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2650 static const struct panel_desc logictechno_lttd800480070_l2rt = {
2651 .modes = &logictechno_lttd800480070_l2rt_mode,
2664 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2665 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2666 .connector_type = DRM_MODE_CONNECTOR_DPI,
2669 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2672 .hsync_start = 800 + 154,
2673 .hsync_end = 800 + 154 + 3,
2674 .htotal = 800 + 154 + 3 + 43,
2676 .vsync_start = 480 + 47,
2677 .vsync_end = 480 + 47 + 3,
2678 .vtotal = 480 + 47 + 3 + 20,
2679 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2682 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2683 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
2696 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2697 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2698 .connector_type = DRM_MODE_CONNECTOR_DPI,
2701 static const struct drm_display_mode logicpd_type_28_mode = {
2704 .hsync_start = 480 + 3,
2705 .hsync_end = 480 + 3 + 42,
2706 .htotal = 480 + 3 + 42 + 2,
2709 .vsync_start = 272 + 2,
2710 .vsync_end = 272 + 2 + 11,
2711 .vtotal = 272 + 2 + 11 + 3,
2712 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2715 static const struct panel_desc logicpd_type_28 = {
2716 .modes = &logicpd_type_28_mode,
2729 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2730 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2731 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2732 .connector_type = DRM_MODE_CONNECTOR_DPI,
2735 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2738 .hsync_start = 800 + 0,
2739 .hsync_end = 800 + 1,
2740 .htotal = 800 + 0 + 1 + 160,
2742 .vsync_start = 480 + 0,
2743 .vsync_end = 480 + 48 + 1,
2744 .vtotal = 480 + 48 + 1 + 0,
2745 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2748 static const struct panel_desc mitsubishi_aa070mc01 = {
2749 .modes = &mitsubishi_aa070mc01_mode,
2762 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2763 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2764 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2767 static const struct display_timing multi_inno_mi0700s4t_6_timing = {
2768 .pixelclock = { 29000000, 33000000, 38000000 },
2769 .hactive = { 800, 800, 800 },
2770 .hfront_porch = { 180, 210, 240 },
2771 .hback_porch = { 16, 16, 16 },
2772 .hsync_len = { 30, 30, 30 },
2773 .vactive = { 480, 480, 480 },
2774 .vfront_porch = { 12, 22, 32 },
2775 .vback_porch = { 10, 10, 10 },
2776 .vsync_len = { 13, 13, 13 },
2777 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2778 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2779 DISPLAY_FLAGS_SYNC_POSEDGE,
2782 static const struct panel_desc multi_inno_mi0700s4t_6 = {
2783 .timings = &multi_inno_mi0700s4t_6_timing,
2790 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2791 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2792 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2793 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2794 .connector_type = DRM_MODE_CONNECTOR_DPI,
2797 static const struct display_timing multi_inno_mi0800ft_9_timing = {
2798 .pixelclock = { 32000000, 40000000, 50000000 },
2799 .hactive = { 800, 800, 800 },
2800 .hfront_porch = { 16, 210, 354 },
2801 .hback_porch = { 6, 26, 45 },
2802 .hsync_len = { 1, 20, 40 },
2803 .vactive = { 600, 600, 600 },
2804 .vfront_porch = { 1, 12, 77 },
2805 .vback_porch = { 3, 13, 22 },
2806 .vsync_len = { 1, 10, 20 },
2807 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2808 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2809 DISPLAY_FLAGS_SYNC_POSEDGE,
2812 static const struct panel_desc multi_inno_mi0800ft_9 = {
2813 .timings = &multi_inno_mi0800ft_9_timing,
2820 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2821 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2822 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2823 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2824 .connector_type = DRM_MODE_CONNECTOR_DPI,
2827 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
2828 .pixelclock = { 68900000, 70000000, 73400000 },
2829 .hactive = { 1280, 1280, 1280 },
2830 .hfront_porch = { 30, 60, 71 },
2831 .hback_porch = { 30, 60, 71 },
2832 .hsync_len = { 10, 10, 48 },
2833 .vactive = { 800, 800, 800 },
2834 .vfront_porch = { 5, 10, 10 },
2835 .vback_porch = { 5, 10, 10 },
2836 .vsync_len = { 5, 6, 13 },
2837 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2838 DISPLAY_FLAGS_DE_HIGH,
2841 static const struct panel_desc multi_inno_mi1010ait_1cp = {
2842 .timings = &multi_inno_mi1010ait_1cp_timing,
2853 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2854 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2855 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2858 static const struct display_timing nec_nl12880bc20_05_timing = {
2859 .pixelclock = { 67000000, 71000000, 75000000 },
2860 .hactive = { 1280, 1280, 1280 },
2861 .hfront_porch = { 2, 30, 30 },
2862 .hback_porch = { 6, 100, 100 },
2863 .hsync_len = { 2, 30, 30 },
2864 .vactive = { 800, 800, 800 },
2865 .vfront_porch = { 5, 5, 5 },
2866 .vback_porch = { 11, 11, 11 },
2867 .vsync_len = { 7, 7, 7 },
2870 static const struct panel_desc nec_nl12880bc20_05 = {
2871 .timings = &nec_nl12880bc20_05_timing,
2882 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2883 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2886 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2889 .hsync_start = 480 + 2,
2890 .hsync_end = 480 + 2 + 41,
2891 .htotal = 480 + 2 + 41 + 2,
2893 .vsync_start = 272 + 2,
2894 .vsync_end = 272 + 2 + 4,
2895 .vtotal = 272 + 2 + 4 + 2,
2896 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2899 static const struct panel_desc nec_nl4827hc19_05b = {
2900 .modes = &nec_nl4827hc19_05b_mode,
2907 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2908 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2911 static const struct drm_display_mode netron_dy_e231732_mode = {
2914 .hsync_start = 1024 + 160,
2915 .hsync_end = 1024 + 160 + 70,
2916 .htotal = 1024 + 160 + 70 + 90,
2918 .vsync_start = 600 + 127,
2919 .vsync_end = 600 + 127 + 20,
2920 .vtotal = 600 + 127 + 20 + 3,
2923 static const struct panel_desc netron_dy_e231732 = {
2924 .modes = &netron_dy_e231732_mode,
2930 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2933 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2936 .hsync_start = 480 + 2,
2937 .hsync_end = 480 + 2 + 41,
2938 .htotal = 480 + 2 + 41 + 2,
2940 .vsync_start = 272 + 2,
2941 .vsync_end = 272 + 2 + 10,
2942 .vtotal = 272 + 2 + 10 + 2,
2943 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2946 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2947 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2954 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2955 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2956 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2957 .connector_type = DRM_MODE_CONNECTOR_DPI,
2960 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2961 .pixelclock = { 130000000, 148350000, 163000000 },
2962 .hactive = { 1920, 1920, 1920 },
2963 .hfront_porch = { 80, 100, 100 },
2964 .hback_porch = { 100, 120, 120 },
2965 .hsync_len = { 50, 60, 60 },
2966 .vactive = { 1080, 1080, 1080 },
2967 .vfront_porch = { 12, 30, 30 },
2968 .vback_porch = { 4, 10, 10 },
2969 .vsync_len = { 4, 5, 5 },
2972 static const struct panel_desc nlt_nl192108ac18_02d = {
2973 .timings = &nlt_nl192108ac18_02d_timing,
2983 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2984 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2987 static const struct drm_display_mode nvd_9128_mode = {
2990 .hsync_start = 800 + 130,
2991 .hsync_end = 800 + 130 + 98,
2992 .htotal = 800 + 0 + 130 + 98,
2994 .vsync_start = 480 + 10,
2995 .vsync_end = 480 + 10 + 50,
2996 .vtotal = 480 + 0 + 10 + 50,
2999 static const struct panel_desc nvd_9128 = {
3000 .modes = &nvd_9128_mode,
3007 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3008 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3011 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3012 .pixelclock = { 30000000, 30000000, 40000000 },
3013 .hactive = { 800, 800, 800 },
3014 .hfront_porch = { 40, 40, 40 },
3015 .hback_porch = { 40, 40, 40 },
3016 .hsync_len = { 1, 48, 48 },
3017 .vactive = { 480, 480, 480 },
3018 .vfront_porch = { 13, 13, 13 },
3019 .vback_porch = { 29, 29, 29 },
3020 .vsync_len = { 3, 3, 3 },
3021 .flags = DISPLAY_FLAGS_DE_HIGH,
3024 static const struct panel_desc okaya_rs800480t_7x0gp = {
3025 .timings = &okaya_rs800480t_7x0gp_timing,
3038 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3041 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3044 .hsync_start = 480 + 5,
3045 .hsync_end = 480 + 5 + 30,
3046 .htotal = 480 + 5 + 30 + 10,
3048 .vsync_start = 272 + 8,
3049 .vsync_end = 272 + 8 + 5,
3050 .vtotal = 272 + 8 + 5 + 3,
3053 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3054 .modes = &olimex_lcd_olinuxino_43ts_mode,
3060 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3064 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3065 * pixel clocks, but this is the timing that was being used in the Adafruit
3066 * installation instructions.
3068 static const struct drm_display_mode ontat_yx700wv03_mode = {
3078 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3083 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3085 static const struct panel_desc ontat_yx700wv03 = {
3086 .modes = &ontat_yx700wv03_mode,
3093 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3096 static const struct drm_display_mode ortustech_com37h3m_mode = {
3099 .hsync_start = 480 + 40,
3100 .hsync_end = 480 + 40 + 10,
3101 .htotal = 480 + 40 + 10 + 40,
3103 .vsync_start = 640 + 4,
3104 .vsync_end = 640 + 4 + 2,
3105 .vtotal = 640 + 4 + 2 + 4,
3106 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3109 static const struct panel_desc ortustech_com37h3m = {
3110 .modes = &ortustech_com37h3m_mode,
3114 .width = 56, /* 56.16mm */
3115 .height = 75, /* 74.88mm */
3117 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3118 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3119 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3122 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3125 .hsync_start = 480 + 10,
3126 .hsync_end = 480 + 10 + 10,
3127 .htotal = 480 + 10 + 10 + 15,
3129 .vsync_start = 800 + 3,
3130 .vsync_end = 800 + 3 + 3,
3131 .vtotal = 800 + 3 + 3 + 3,
3134 static const struct panel_desc ortustech_com43h4m85ulc = {
3135 .modes = &ortustech_com43h4m85ulc_mode,
3142 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3143 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3144 .connector_type = DRM_MODE_CONNECTOR_DPI,
3147 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3150 .hsync_start = 800 + 210,
3151 .hsync_end = 800 + 210 + 30,
3152 .htotal = 800 + 210 + 30 + 16,
3154 .vsync_start = 480 + 22,
3155 .vsync_end = 480 + 22 + 13,
3156 .vtotal = 480 + 22 + 13 + 10,
3157 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3160 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3161 .modes = &osddisplays_osd070t1718_19ts_mode,
3168 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3169 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3170 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3171 .connector_type = DRM_MODE_CONNECTOR_DPI,
3174 static const struct drm_display_mode pda_91_00156_a0_mode = {
3177 .hsync_start = 800 + 1,
3178 .hsync_end = 800 + 1 + 64,
3179 .htotal = 800 + 1 + 64 + 64,
3181 .vsync_start = 480 + 1,
3182 .vsync_end = 480 + 1 + 23,
3183 .vtotal = 480 + 1 + 23 + 22,
3186 static const struct panel_desc pda_91_00156_a0 = {
3187 .modes = &pda_91_00156_a0_mode,
3193 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3196 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3199 .hsync_start = 800 + 54,
3200 .hsync_end = 800 + 54 + 2,
3201 .htotal = 800 + 54 + 2 + 44,
3203 .vsync_start = 480 + 49,
3204 .vsync_end = 480 + 49 + 2,
3205 .vtotal = 480 + 49 + 2 + 22,
3206 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3209 static const struct panel_desc powertip_ph800480t013_idf02 = {
3210 .modes = &powertip_ph800480t013_idf02_mode,
3216 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3217 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3218 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3219 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3220 .connector_type = DRM_MODE_CONNECTOR_DPI,
3223 static const struct drm_display_mode qd43003c0_40_mode = {
3226 .hsync_start = 480 + 8,
3227 .hsync_end = 480 + 8 + 4,
3228 .htotal = 480 + 8 + 4 + 39,
3230 .vsync_start = 272 + 4,
3231 .vsync_end = 272 + 4 + 10,
3232 .vtotal = 272 + 4 + 10 + 2,
3235 static const struct panel_desc qd43003c0_40 = {
3236 .modes = &qd43003c0_40_mode,
3243 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3246 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3250 .hsync_start = 480 + 77,
3251 .hsync_end = 480 + 77 + 41,
3252 .htotal = 480 + 77 + 41 + 2,
3254 .vsync_start = 272 + 16,
3255 .vsync_end = 272 + 16 + 10,
3256 .vtotal = 272 + 16 + 10 + 2,
3257 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3262 .hsync_start = 480 + 17,
3263 .hsync_end = 480 + 17 + 41,
3264 .htotal = 480 + 17 + 41 + 2,
3266 .vsync_start = 272 + 116,
3267 .vsync_end = 272 + 116 + 10,
3268 .vtotal = 272 + 116 + 10 + 2,
3269 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3273 static const struct panel_desc qishenglong_gopher2b_lcd = {
3274 .modes = qishenglong_gopher2b_lcd_modes,
3275 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3281 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3282 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3283 .connector_type = DRM_MODE_CONNECTOR_DPI,
3286 static const struct display_timing rocktech_rk043fn48h_timing = {
3287 .pixelclock = { 6000000, 9000000, 12000000 },
3288 .hactive = { 480, 480, 480 },
3289 .hback_porch = { 8, 43, 43 },
3290 .hfront_porch = { 2, 8, 8 },
3291 .hsync_len = { 1, 1, 1 },
3292 .vactive = { 272, 272, 272 },
3293 .vback_porch = { 2, 12, 12 },
3294 .vfront_porch = { 1, 4, 4 },
3295 .vsync_len = { 1, 10, 10 },
3296 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
3297 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3300 static const struct panel_desc rocktech_rk043fn48h = {
3301 .timings = &rocktech_rk043fn48h_timing,
3308 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3309 .connector_type = DRM_MODE_CONNECTOR_DPI,
3312 static const struct display_timing rocktech_rk070er9427_timing = {
3313 .pixelclock = { 26400000, 33300000, 46800000 },
3314 .hactive = { 800, 800, 800 },
3315 .hfront_porch = { 16, 210, 354 },
3316 .hback_porch = { 46, 46, 46 },
3317 .hsync_len = { 1, 1, 1 },
3318 .vactive = { 480, 480, 480 },
3319 .vfront_porch = { 7, 22, 147 },
3320 .vback_porch = { 23, 23, 23 },
3321 .vsync_len = { 1, 1, 1 },
3322 .flags = DISPLAY_FLAGS_DE_HIGH,
3325 static const struct panel_desc rocktech_rk070er9427 = {
3326 .timings = &rocktech_rk070er9427_timing,
3339 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3342 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3345 .hsync_start = 1280 + 48,
3346 .hsync_end = 1280 + 48 + 32,
3347 .htotal = 1280 + 48 + 32 + 80,
3349 .vsync_start = 800 + 2,
3350 .vsync_end = 800 + 2 + 5,
3351 .vtotal = 800 + 2 + 5 + 16,
3354 static const struct panel_desc rocktech_rk101ii01d_ct = {
3355 .modes = &rocktech_rk101ii01d_ct_mode,
3366 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3367 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3368 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3371 static const struct display_timing samsung_ltl101al01_timing = {
3372 .pixelclock = { 66663000, 66663000, 66663000 },
3373 .hactive = { 1280, 1280, 1280 },
3374 .hfront_porch = { 18, 18, 18 },
3375 .hback_porch = { 36, 36, 36 },
3376 .hsync_len = { 16, 16, 16 },
3377 .vactive = { 800, 800, 800 },
3378 .vfront_porch = { 4, 4, 4 },
3379 .vback_porch = { 16, 16, 16 },
3380 .vsync_len = { 3, 3, 3 },
3381 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3384 static const struct panel_desc samsung_ltl101al01 = {
3385 .timings = &samsung_ltl101al01_timing,
3398 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3399 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3402 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3405 .hsync_start = 1024 + 24,
3406 .hsync_end = 1024 + 24 + 136,
3407 .htotal = 1024 + 24 + 136 + 160,
3409 .vsync_start = 600 + 3,
3410 .vsync_end = 600 + 3 + 6,
3411 .vtotal = 600 + 3 + 6 + 61,
3414 static const struct panel_desc samsung_ltn101nt05 = {
3415 .modes = &samsung_ltn101nt05_mode,
3422 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3423 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3424 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3427 static const struct display_timing satoz_sat050at40h12r2_timing = {
3428 .pixelclock = {33300000, 33300000, 50000000},
3429 .hactive = {800, 800, 800},
3430 .hfront_porch = {16, 210, 354},
3431 .hback_porch = {46, 46, 46},
3432 .hsync_len = {1, 1, 40},
3433 .vactive = {480, 480, 480},
3434 .vfront_porch = {7, 22, 147},
3435 .vback_porch = {23, 23, 23},
3436 .vsync_len = {1, 1, 20},
3439 static const struct panel_desc satoz_sat050at40h12r2 = {
3440 .timings = &satoz_sat050at40h12r2_timing,
3447 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3448 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3451 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3454 .hsync_start = 800 + 64,
3455 .hsync_end = 800 + 64 + 128,
3456 .htotal = 800 + 64 + 128 + 64,
3458 .vsync_start = 480 + 8,
3459 .vsync_end = 480 + 8 + 2,
3460 .vtotal = 480 + 8 + 2 + 35,
3461 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3464 static const struct panel_desc sharp_lq070y3dg3b = {
3465 .modes = &sharp_lq070y3dg3b_mode,
3469 .width = 152, /* 152.4mm */
3470 .height = 91, /* 91.4mm */
3472 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3473 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3474 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3477 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3480 .hsync_start = 240 + 16,
3481 .hsync_end = 240 + 16 + 7,
3482 .htotal = 240 + 16 + 7 + 5,
3484 .vsync_start = 320 + 9,
3485 .vsync_end = 320 + 9 + 1,
3486 .vtotal = 320 + 9 + 1 + 7,
3489 static const struct panel_desc sharp_lq035q7db03 = {
3490 .modes = &sharp_lq035q7db03_mode,
3497 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3500 static const struct display_timing sharp_lq101k1ly04_timing = {
3501 .pixelclock = { 60000000, 65000000, 80000000 },
3502 .hactive = { 1280, 1280, 1280 },
3503 .hfront_porch = { 20, 20, 20 },
3504 .hback_porch = { 20, 20, 20 },
3505 .hsync_len = { 10, 10, 10 },
3506 .vactive = { 800, 800, 800 },
3507 .vfront_porch = { 4, 4, 4 },
3508 .vback_porch = { 4, 4, 4 },
3509 .vsync_len = { 4, 4, 4 },
3510 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3513 static const struct panel_desc sharp_lq101k1ly04 = {
3514 .timings = &sharp_lq101k1ly04_timing,
3521 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3522 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3525 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3529 .hsync_start = 240 + 58,
3530 .hsync_end = 240 + 58 + 1,
3531 .htotal = 240 + 58 + 1 + 1,
3533 .vsync_start = 160 + 24,
3534 .vsync_end = 160 + 24 + 10,
3535 .vtotal = 160 + 24 + 10 + 6,
3536 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3541 .hsync_start = 240 + 8,
3542 .hsync_end = 240 + 8 + 1,
3543 .htotal = 240 + 8 + 1 + 1,
3545 .vsync_start = 160 + 24,
3546 .vsync_end = 160 + 24 + 10,
3547 .vtotal = 160 + 24 + 10 + 6,
3548 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3552 static const struct panel_desc sharp_ls020b1dd01d = {
3553 .modes = sharp_ls020b1dd01d_modes,
3554 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3560 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3561 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3562 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3563 | DRM_BUS_FLAG_SHARP_SIGNALS,
3566 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3569 .hsync_start = 800 + 1,
3570 .hsync_end = 800 + 1 + 64,
3571 .htotal = 800 + 1 + 64 + 64,
3573 .vsync_start = 480 + 1,
3574 .vsync_end = 480 + 1 + 23,
3575 .vtotal = 480 + 1 + 23 + 22,
3578 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3579 .modes = &shelly_sca07010_bfn_lnn_mode,
3585 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3588 static const struct drm_display_mode starry_kr070pe2t_mode = {
3591 .hsync_start = 800 + 209,
3592 .hsync_end = 800 + 209 + 1,
3593 .htotal = 800 + 209 + 1 + 45,
3595 .vsync_start = 480 + 22,
3596 .vsync_end = 480 + 22 + 1,
3597 .vtotal = 480 + 22 + 1 + 22,
3600 static const struct panel_desc starry_kr070pe2t = {
3601 .modes = &starry_kr070pe2t_mode,
3608 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3609 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3610 .connector_type = DRM_MODE_CONNECTOR_DPI,
3613 static const struct display_timing startek_kd070wvfpa_mode = {
3614 .pixelclock = { 25200000, 27200000, 30500000 },
3615 .hactive = { 800, 800, 800 },
3616 .hfront_porch = { 19, 44, 115 },
3617 .hback_porch = { 5, 16, 101 },
3618 .hsync_len = { 1, 2, 100 },
3619 .vactive = { 480, 480, 480 },
3620 .vfront_porch = { 5, 43, 67 },
3621 .vback_porch = { 5, 5, 67 },
3622 .vsync_len = { 1, 2, 66 },
3623 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3624 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3625 DISPLAY_FLAGS_SYNC_POSEDGE,
3628 static const struct panel_desc startek_kd070wvfpa = {
3629 .timings = &startek_kd070wvfpa_mode,
3641 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3642 .connector_type = DRM_MODE_CONNECTOR_DPI,
3643 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3644 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3645 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3648 static const struct display_timing tsd_tst043015cmhx_timing = {
3649 .pixelclock = { 5000000, 9000000, 12000000 },
3650 .hactive = { 480, 480, 480 },
3651 .hfront_porch = { 4, 5, 65 },
3652 .hback_porch = { 36, 40, 255 },
3653 .hsync_len = { 1, 1, 1 },
3654 .vactive = { 272, 272, 272 },
3655 .vfront_porch = { 2, 8, 97 },
3656 .vback_porch = { 3, 8, 31 },
3657 .vsync_len = { 1, 1, 1 },
3659 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3660 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3663 static const struct panel_desc tsd_tst043015cmhx = {
3664 .timings = &tsd_tst043015cmhx_timing,
3671 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3672 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3675 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3678 .hsync_start = 800 + 39,
3679 .hsync_end = 800 + 39 + 47,
3680 .htotal = 800 + 39 + 47 + 39,
3682 .vsync_start = 480 + 13,
3683 .vsync_end = 480 + 13 + 2,
3684 .vtotal = 480 + 13 + 2 + 29,
3687 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3688 .modes = &tfc_s9700rtwv43tr_01b_mode,
3695 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3696 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3699 static const struct display_timing tianma_tm070jdhg30_timing = {
3700 .pixelclock = { 62600000, 68200000, 78100000 },
3701 .hactive = { 1280, 1280, 1280 },
3702 .hfront_porch = { 15, 64, 159 },
3703 .hback_porch = { 5, 5, 5 },
3704 .hsync_len = { 1, 1, 256 },
3705 .vactive = { 800, 800, 800 },
3706 .vfront_porch = { 3, 40, 99 },
3707 .vback_porch = { 2, 2, 2 },
3708 .vsync_len = { 1, 1, 128 },
3709 .flags = DISPLAY_FLAGS_DE_HIGH,
3712 static const struct panel_desc tianma_tm070jdhg30 = {
3713 .timings = &tianma_tm070jdhg30_timing,
3720 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3721 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3724 static const struct panel_desc tianma_tm070jvhg33 = {
3725 .timings = &tianma_tm070jdhg30_timing,
3732 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3733 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3736 static const struct display_timing tianma_tm070rvhg71_timing = {
3737 .pixelclock = { 27700000, 29200000, 39600000 },
3738 .hactive = { 800, 800, 800 },
3739 .hfront_porch = { 12, 40, 212 },
3740 .hback_porch = { 88, 88, 88 },
3741 .hsync_len = { 1, 1, 40 },
3742 .vactive = { 480, 480, 480 },
3743 .vfront_porch = { 1, 13, 88 },
3744 .vback_porch = { 32, 32, 32 },
3745 .vsync_len = { 1, 1, 3 },
3746 .flags = DISPLAY_FLAGS_DE_HIGH,
3749 static const struct panel_desc tianma_tm070rvhg71 = {
3750 .timings = &tianma_tm070rvhg71_timing,
3757 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3758 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3761 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3765 .hsync_start = 320 + 50,
3766 .hsync_end = 320 + 50 + 6,
3767 .htotal = 320 + 50 + 6 + 38,
3769 .vsync_start = 240 + 3,
3770 .vsync_end = 240 + 3 + 1,
3771 .vtotal = 240 + 3 + 1 + 17,
3772 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3776 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3777 .modes = ti_nspire_cx_lcd_mode,
3784 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3785 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3788 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3792 .hsync_start = 320 + 6,
3793 .hsync_end = 320 + 6 + 6,
3794 .htotal = 320 + 6 + 6 + 6,
3796 .vsync_start = 240 + 0,
3797 .vsync_end = 240 + 0 + 1,
3798 .vtotal = 240 + 0 + 1 + 0,
3799 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3803 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3804 .modes = ti_nspire_classic_lcd_mode,
3806 /* The grayscale panel has 8 bit for the color .. Y (black) */
3812 /* This is the grayscale bus format */
3813 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3814 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3817 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3820 .hsync_start = 1280 + 192,
3821 .hsync_end = 1280 + 192 + 128,
3822 .htotal = 1280 + 192 + 128 + 64,
3824 .vsync_start = 768 + 20,
3825 .vsync_end = 768 + 20 + 7,
3826 .vtotal = 768 + 20 + 7 + 3,
3829 static const struct panel_desc toshiba_lt089ac29000 = {
3830 .modes = &toshiba_lt089ac29000_mode,
3836 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3837 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3838 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3841 static const struct drm_display_mode tpk_f07a_0102_mode = {
3844 .hsync_start = 800 + 40,
3845 .hsync_end = 800 + 40 + 128,
3846 .htotal = 800 + 40 + 128 + 88,
3848 .vsync_start = 480 + 10,
3849 .vsync_end = 480 + 10 + 2,
3850 .vtotal = 480 + 10 + 2 + 33,
3853 static const struct panel_desc tpk_f07a_0102 = {
3854 .modes = &tpk_f07a_0102_mode,
3860 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3863 static const struct drm_display_mode tpk_f10a_0102_mode = {
3866 .hsync_start = 1024 + 176,
3867 .hsync_end = 1024 + 176 + 5,
3868 .htotal = 1024 + 176 + 5 + 88,
3870 .vsync_start = 600 + 20,
3871 .vsync_end = 600 + 20 + 5,
3872 .vtotal = 600 + 20 + 5 + 25,
3875 static const struct panel_desc tpk_f10a_0102 = {
3876 .modes = &tpk_f10a_0102_mode,
3884 static const struct display_timing urt_umsh_8596md_timing = {
3885 .pixelclock = { 33260000, 33260000, 33260000 },
3886 .hactive = { 800, 800, 800 },
3887 .hfront_porch = { 41, 41, 41 },
3888 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3889 .hsync_len = { 71, 128, 128 },
3890 .vactive = { 480, 480, 480 },
3891 .vfront_porch = { 10, 10, 10 },
3892 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3893 .vsync_len = { 2, 2, 2 },
3894 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3895 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3898 static const struct panel_desc urt_umsh_8596md_lvds = {
3899 .timings = &urt_umsh_8596md_timing,
3906 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3907 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3910 static const struct panel_desc urt_umsh_8596md_parallel = {
3911 .timings = &urt_umsh_8596md_timing,
3918 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3921 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
3924 .hsync_start = 1024 + 160,
3925 .hsync_end = 1024 + 160 + 100,
3926 .htotal = 1024 + 160 + 100 + 60,
3928 .vsync_start = 600 + 12,
3929 .vsync_end = 600 + 12 + 10,
3930 .vtotal = 600 + 12 + 10 + 13,
3933 static const struct panel_desc vivax_tpc9150_panel = {
3934 .modes = &vivax_tpc9150_panel_mode,
3941 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3942 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3943 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3946 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3949 .hsync_start = 800 + 210,
3950 .hsync_end = 800 + 210 + 20,
3951 .htotal = 800 + 210 + 20 + 46,
3953 .vsync_start = 480 + 22,
3954 .vsync_end = 480 + 22 + 10,
3955 .vtotal = 480 + 22 + 10 + 23,
3956 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3959 static const struct panel_desc vl050_8048nt_c01 = {
3960 .modes = &vl050_8048nt_c01_mode,
3967 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3968 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3971 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3974 .hsync_start = 320 + 20,
3975 .hsync_end = 320 + 20 + 30,
3976 .htotal = 320 + 20 + 30 + 38,
3978 .vsync_start = 240 + 4,
3979 .vsync_end = 240 + 4 + 3,
3980 .vtotal = 240 + 4 + 3 + 15,
3981 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3984 static const struct panel_desc winstar_wf35ltiacd = {
3985 .modes = &winstar_wf35ltiacd_mode,
3992 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3995 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
3998 .hsync_start = 1024 + 100,
3999 .hsync_end = 1024 + 100 + 100,
4000 .htotal = 1024 + 100 + 100 + 120,
4002 .vsync_start = 600 + 10,
4003 .vsync_end = 600 + 10 + 10,
4004 .vtotal = 600 + 10 + 10 + 15,
4005 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4008 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4009 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4016 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4017 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4018 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4021 static const struct drm_display_mode arm_rtsm_mode[] = {
4025 .hsync_start = 1024 + 24,
4026 .hsync_end = 1024 + 24 + 136,
4027 .htotal = 1024 + 24 + 136 + 160,
4029 .vsync_start = 768 + 3,
4030 .vsync_end = 768 + 3 + 6,
4031 .vtotal = 768 + 3 + 6 + 29,
4032 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4036 static const struct panel_desc arm_rtsm = {
4037 .modes = arm_rtsm_mode,
4044 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4047 static const struct of_device_id platform_of_match[] = {
4049 .compatible = "ampire,am-1280800n3tzqw-t00h",
4050 .data = &ire_am_1280800n3tzqw_t00h,
4052 .compatible = "ampire,am-480272h3tmqw-t01h",
4053 .data = &ire_am_480272h3tmqw_t01h,
4055 .compatible = "ampire,am-800480l1tmqw-t00h",
4056 .data = &ire_am_800480l1tmqw_t00h,
4058 .compatible = "ampire,am800480r3tmqwa1h",
4059 .data = &ire_am800480r3tmqwa1h,
4061 .compatible = "ampire,am800600p5tmqw-tb8h",
4062 .data = &ire_am800600p5tmqwtb8h,
4064 .compatible = "arm,rtsm-display",
4067 .compatible = "armadeus,st0700-adapt",
4068 .data = &armadeus_st0700_adapt,
4070 .compatible = "auo,b101aw03",
4071 .data = &auo_b101aw03,
4073 .compatible = "auo,b101xtn01",
4074 .data = &auo_b101xtn01,
4076 .compatible = "auo,g070vvn01",
4077 .data = &auo_g070vvn01,
4079 .compatible = "auo,g101evn010",
4080 .data = &auo_g101evn010,
4082 .compatible = "auo,g104sn02",
4083 .data = &auo_g104sn02,
4085 .compatible = "auo,g121ean01",
4086 .data = &auo_g121ean01,
4088 .compatible = "auo,g133han01",
4089 .data = &auo_g133han01,
4091 .compatible = "auo,g156xtn01",
4092 .data = &auo_g156xtn01,
4094 .compatible = "auo,g185han01",
4095 .data = &auo_g185han01,
4097 .compatible = "auo,g190ean01",
4098 .data = &auo_g190ean01,
4100 .compatible = "auo,p320hvn03",
4101 .data = &auo_p320hvn03,
4103 .compatible = "auo,t215hvn01",
4104 .data = &auo_t215hvn01,
4106 .compatible = "avic,tm070ddh03",
4107 .data = &avic_tm070ddh03,
4109 .compatible = "bananapi,s070wv20-ct16",
4110 .data = &bananapi_s070wv20_ct16,
4112 .compatible = "boe,ev121wxm-n10-1850",
4113 .data = &boe_ev121wxm_n10_1850,
4115 .compatible = "boe,hv070wsa-100",
4116 .data = &boe_hv070wsa
4118 .compatible = "cdtech,s043wq26h-ct7",
4119 .data = &cdtech_s043wq26h_ct7,
4121 .compatible = "cdtech,s070pws19hp-fc21",
4122 .data = &cdtech_s070pws19hp_fc21,
4124 .compatible = "cdtech,s070swv29hg-dc44",
4125 .data = &cdtech_s070swv29hg_dc44,
4127 .compatible = "cdtech,s070wv95-ct16",
4128 .data = &cdtech_s070wv95_ct16,
4130 .compatible = "chefree,ch101olhlwh-002",
4131 .data = &chefree_ch101olhlwh_002,
4133 .compatible = "chunghwa,claa070wp03xg",
4134 .data = &chunghwa_claa070wp03xg,
4136 .compatible = "chunghwa,claa101wa01a",
4137 .data = &chunghwa_claa101wa01a
4139 .compatible = "chunghwa,claa101wb01",
4140 .data = &chunghwa_claa101wb01
4142 .compatible = "dataimage,fg040346dsswbg04",
4143 .data = &dataimage_fg040346dsswbg04,
4145 .compatible = "dataimage,fg1001l0dsswmg01",
4146 .data = &dataimage_fg1001l0dsswmg01,
4148 .compatible = "dataimage,scf0700c48ggu18",
4149 .data = &dataimage_scf0700c48ggu18,
4151 .compatible = "dlc,dlc0700yzg-1",
4152 .data = &dlc_dlc0700yzg_1,
4154 .compatible = "dlc,dlc1010gig",
4155 .data = &dlc_dlc1010gig,
4157 .compatible = "edt,et035012dm6",
4158 .data = &edt_et035012dm6,
4160 .compatible = "edt,etm0350g0dh6",
4161 .data = &edt_etm0350g0dh6,
4163 .compatible = "edt,etm043080dh6gp",
4164 .data = &edt_etm043080dh6gp,
4166 .compatible = "edt,etm0430g0dh6",
4167 .data = &edt_etm0430g0dh6,
4169 .compatible = "edt,et057090dhu",
4170 .data = &edt_et057090dhu,
4172 .compatible = "edt,et070080dh6",
4173 .data = &edt_etm0700g0dh6,
4175 .compatible = "edt,etm0700g0dh6",
4176 .data = &edt_etm0700g0dh6,
4178 .compatible = "edt,etm0700g0bdh6",
4179 .data = &edt_etm0700g0bdh6,
4181 .compatible = "edt,etm0700g0edh6",
4182 .data = &edt_etm0700g0bdh6,
4184 .compatible = "edt,etml0700y5dha",
4185 .data = &edt_etml0700y5dha,
4187 .compatible = "edt,etmv570g2dhu",
4188 .data = &edt_etmv570g2dhu,
4190 .compatible = "eink,vb3300-kca",
4191 .data = &eink_vb3300_kca,
4193 .compatible = "evervision,vgg804821",
4194 .data = &evervision_vgg804821,
4196 .compatible = "foxlink,fl500wvr00-a0t",
4197 .data = &foxlink_fl500wvr00_a0t,
4199 .compatible = "frida,frd350h54004",
4200 .data = &frida_frd350h54004,
4202 .compatible = "friendlyarm,hd702e",
4203 .data = &friendlyarm_hd702e,
4205 .compatible = "giantplus,gpg482739qs5",
4206 .data = &giantplus_gpg482739qs5
4208 .compatible = "giantplus,gpm940b0",
4209 .data = &giantplus_gpm940b0,
4211 .compatible = "hannstar,hsd070pww1",
4212 .data = &hannstar_hsd070pww1,
4214 .compatible = "hannstar,hsd100pxn1",
4215 .data = &hannstar_hsd100pxn1,
4217 .compatible = "hannstar,hsd101pww2",
4218 .data = &hannstar_hsd101pww2,
4220 .compatible = "hit,tx23d38vm0caa",
4221 .data = &hitachi_tx23d38vm0caa
4223 .compatible = "innolux,at043tn24",
4224 .data = &innolux_at043tn24,
4226 .compatible = "innolux,at070tn92",
4227 .data = &innolux_at070tn92,
4229 .compatible = "innolux,g070ace-l01",
4230 .data = &innolux_g070ace_l01,
4232 .compatible = "innolux,g070y2-l01",
4233 .data = &innolux_g070y2_l01,
4235 .compatible = "innolux,g070y2-t02",
4236 .data = &innolux_g070y2_t02,
4238 .compatible = "innolux,g101ice-l01",
4239 .data = &innolux_g101ice_l01
4241 .compatible = "innolux,g121i1-l01",
4242 .data = &innolux_g121i1_l01
4244 .compatible = "innolux,g121x1-l03",
4245 .data = &innolux_g121x1_l03,
4247 .compatible = "innolux,n156bge-l21",
4248 .data = &innolux_n156bge_l21,
4250 .compatible = "innolux,zj070na-01p",
4251 .data = &innolux_zj070na_01p,
4253 .compatible = "koe,tx14d24vm1bpa",
4254 .data = &koe_tx14d24vm1bpa,
4256 .compatible = "koe,tx26d202vm0bwa",
4257 .data = &koe_tx26d202vm0bwa,
4259 .compatible = "koe,tx31d200vm0baa",
4260 .data = &koe_tx31d200vm0baa,
4262 .compatible = "kyo,tcg121xglp",
4263 .data = &kyo_tcg121xglp,
4265 .compatible = "lemaker,bl035-rgb-002",
4266 .data = &lemaker_bl035_rgb_002,
4268 .compatible = "lg,lb070wv8",
4269 .data = &lg_lb070wv8,
4271 .compatible = "logicpd,type28",
4272 .data = &logicpd_type_28,
4274 .compatible = "logictechno,lt161010-2nhc",
4275 .data = &logictechno_lt161010_2nh,
4277 .compatible = "logictechno,lt161010-2nhr",
4278 .data = &logictechno_lt161010_2nh,
4280 .compatible = "logictechno,lt170410-2whc",
4281 .data = &logictechno_lt170410_2whc,
4283 .compatible = "logictechno,lttd800480070-l2rt",
4284 .data = &logictechno_lttd800480070_l2rt,
4286 .compatible = "logictechno,lttd800480070-l6wh-rt",
4287 .data = &logictechno_lttd800480070_l6wh_rt,
4289 .compatible = "mitsubishi,aa070mc01-ca1",
4290 .data = &mitsubishi_aa070mc01,
4292 .compatible = "multi-inno,mi0700s4t-6",
4293 .data = &multi_inno_mi0700s4t_6,
4295 .compatible = "multi-inno,mi0800ft-9",
4296 .data = &multi_inno_mi0800ft_9,
4298 .compatible = "multi-inno,mi1010ait-1cp",
4299 .data = &multi_inno_mi1010ait_1cp,
4301 .compatible = "nec,nl12880bc20-05",
4302 .data = &nec_nl12880bc20_05,
4304 .compatible = "nec,nl4827hc19-05b",
4305 .data = &nec_nl4827hc19_05b,
4307 .compatible = "netron-dy,e231732",
4308 .data = &netron_dy_e231732,
4310 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4311 .data = &newhaven_nhd_43_480272ef_atxl,
4313 .compatible = "nlt,nl192108ac18-02d",
4314 .data = &nlt_nl192108ac18_02d,
4316 .compatible = "nvd,9128",
4319 .compatible = "okaya,rs800480t-7x0gp",
4320 .data = &okaya_rs800480t_7x0gp,
4322 .compatible = "olimex,lcd-olinuxino-43-ts",
4323 .data = &olimex_lcd_olinuxino_43ts,
4325 .compatible = "ontat,yx700wv03",
4326 .data = &ontat_yx700wv03,
4328 .compatible = "ortustech,com37h3m05dtc",
4329 .data = &ortustech_com37h3m,
4331 .compatible = "ortustech,com37h3m99dtc",
4332 .data = &ortustech_com37h3m,
4334 .compatible = "ortustech,com43h4m85ulc",
4335 .data = &ortustech_com43h4m85ulc,
4337 .compatible = "osddisplays,osd070t1718-19ts",
4338 .data = &osddisplays_osd070t1718_19ts,
4340 .compatible = "pda,91-00156-a0",
4341 .data = &pda_91_00156_a0,
4343 .compatible = "powertip,ph800480t013-idf02",
4344 .data = &powertip_ph800480t013_idf02,
4346 .compatible = "qiaodian,qd43003c0-40",
4347 .data = &qd43003c0_40,
4349 .compatible = "qishenglong,gopher2b-lcd",
4350 .data = &qishenglong_gopher2b_lcd,
4352 .compatible = "rocktech,rk043fn48h",
4353 .data = &rocktech_rk043fn48h,
4355 .compatible = "rocktech,rk070er9427",
4356 .data = &rocktech_rk070er9427,
4358 .compatible = "rocktech,rk101ii01d-ct",
4359 .data = &rocktech_rk101ii01d_ct,
4361 .compatible = "samsung,ltl101al01",
4362 .data = &samsung_ltl101al01,
4364 .compatible = "samsung,ltn101nt05",
4365 .data = &samsung_ltn101nt05,
4367 .compatible = "satoz,sat050at40h12r2",
4368 .data = &satoz_sat050at40h12r2,
4370 .compatible = "sharp,lq035q7db03",
4371 .data = &sharp_lq035q7db03,
4373 .compatible = "sharp,lq070y3dg3b",
4374 .data = &sharp_lq070y3dg3b,
4376 .compatible = "sharp,lq101k1ly04",
4377 .data = &sharp_lq101k1ly04,
4379 .compatible = "sharp,ls020b1dd01d",
4380 .data = &sharp_ls020b1dd01d,
4382 .compatible = "shelly,sca07010-bfn-lnn",
4383 .data = &shelly_sca07010_bfn_lnn,
4385 .compatible = "starry,kr070pe2t",
4386 .data = &starry_kr070pe2t,
4388 .compatible = "startek,kd070wvfpa",
4389 .data = &startek_kd070wvfpa,
4391 .compatible = "team-source-display,tst043015cmhx",
4392 .data = &tsd_tst043015cmhx,
4394 .compatible = "tfc,s9700rtwv43tr-01b",
4395 .data = &tfc_s9700rtwv43tr_01b,
4397 .compatible = "tianma,tm070jdhg30",
4398 .data = &tianma_tm070jdhg30,
4400 .compatible = "tianma,tm070jvhg33",
4401 .data = &tianma_tm070jvhg33,
4403 .compatible = "tianma,tm070rvhg71",
4404 .data = &tianma_tm070rvhg71,
4406 .compatible = "ti,nspire-cx-lcd-panel",
4407 .data = &ti_nspire_cx_lcd_panel,
4409 .compatible = "ti,nspire-classic-lcd-panel",
4410 .data = &ti_nspire_classic_lcd_panel,
4412 .compatible = "toshiba,lt089ac29000",
4413 .data = &toshiba_lt089ac29000,
4415 .compatible = "tpk,f07a-0102",
4416 .data = &tpk_f07a_0102,
4418 .compatible = "tpk,f10a-0102",
4419 .data = &tpk_f10a_0102,
4421 .compatible = "urt,umsh-8596md-t",
4422 .data = &urt_umsh_8596md_parallel,
4424 .compatible = "urt,umsh-8596md-1t",
4425 .data = &urt_umsh_8596md_parallel,
4427 .compatible = "urt,umsh-8596md-7t",
4428 .data = &urt_umsh_8596md_parallel,
4430 .compatible = "urt,umsh-8596md-11t",
4431 .data = &urt_umsh_8596md_lvds,
4433 .compatible = "urt,umsh-8596md-19t",
4434 .data = &urt_umsh_8596md_lvds,
4436 .compatible = "urt,umsh-8596md-20t",
4437 .data = &urt_umsh_8596md_parallel,
4439 .compatible = "vivax,tpc9150-panel",
4440 .data = &vivax_tpc9150_panel,
4442 .compatible = "vxt,vl050-8048nt-c01",
4443 .data = &vl050_8048nt_c01,
4445 .compatible = "winstar,wf35ltiacd",
4446 .data = &winstar_wf35ltiacd,
4448 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4449 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4451 /* Must be the last entry */
4452 .compatible = "panel-dpi",
4458 MODULE_DEVICE_TABLE(of, platform_of_match);
4460 static int panel_simple_platform_probe(struct platform_device *pdev)
4462 const struct of_device_id *id;
4464 id = of_match_node(platform_of_match, pdev->dev.of_node);
4468 return panel_simple_probe(&pdev->dev, id->data);
4471 static int panel_simple_platform_remove(struct platform_device *pdev)
4473 panel_simple_remove(&pdev->dev);
4478 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4480 panel_simple_shutdown(&pdev->dev);
4483 static const struct dev_pm_ops panel_simple_pm_ops = {
4484 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4485 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4486 pm_runtime_force_resume)
4489 static struct platform_driver panel_simple_platform_driver = {
4491 .name = "panel-simple",
4492 .of_match_table = platform_of_match,
4493 .pm = &panel_simple_pm_ops,
4495 .probe = panel_simple_platform_probe,
4496 .remove = panel_simple_platform_remove,
4497 .shutdown = panel_simple_platform_shutdown,
4500 struct panel_desc_dsi {
4501 struct panel_desc desc;
4503 unsigned long flags;
4504 enum mipi_dsi_pixel_format format;
4508 static const struct drm_display_mode auo_b080uan01_mode = {
4511 .hsync_start = 1200 + 62,
4512 .hsync_end = 1200 + 62 + 4,
4513 .htotal = 1200 + 62 + 4 + 62,
4515 .vsync_start = 1920 + 9,
4516 .vsync_end = 1920 + 9 + 2,
4517 .vtotal = 1920 + 9 + 2 + 8,
4520 static const struct panel_desc_dsi auo_b080uan01 = {
4522 .modes = &auo_b080uan01_mode,
4529 .connector_type = DRM_MODE_CONNECTOR_DSI,
4531 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4532 .format = MIPI_DSI_FMT_RGB888,
4536 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4539 .hsync_start = 1200 + 120,
4540 .hsync_end = 1200 + 120 + 20,
4541 .htotal = 1200 + 120 + 20 + 21,
4543 .vsync_start = 1920 + 21,
4544 .vsync_end = 1920 + 21 + 3,
4545 .vtotal = 1920 + 21 + 3 + 18,
4546 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4549 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4551 .modes = &boe_tv080wum_nl0_mode,
4557 .connector_type = DRM_MODE_CONNECTOR_DSI,
4559 .flags = MIPI_DSI_MODE_VIDEO |
4560 MIPI_DSI_MODE_VIDEO_BURST |
4561 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4562 .format = MIPI_DSI_FMT_RGB888,
4566 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4569 .hsync_start = 800 + 32,
4570 .hsync_end = 800 + 32 + 1,
4571 .htotal = 800 + 32 + 1 + 57,
4573 .vsync_start = 1280 + 28,
4574 .vsync_end = 1280 + 28 + 1,
4575 .vtotal = 1280 + 28 + 1 + 14,
4578 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4580 .modes = &lg_ld070wx3_sl01_mode,
4587 .connector_type = DRM_MODE_CONNECTOR_DSI,
4589 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4590 .format = MIPI_DSI_FMT_RGB888,
4594 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4597 .hsync_start = 720 + 12,
4598 .hsync_end = 720 + 12 + 4,
4599 .htotal = 720 + 12 + 4 + 112,
4601 .vsync_start = 1280 + 8,
4602 .vsync_end = 1280 + 8 + 4,
4603 .vtotal = 1280 + 8 + 4 + 12,
4606 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4608 .modes = &lg_lh500wx1_sd03_mode,
4615 .connector_type = DRM_MODE_CONNECTOR_DSI,
4617 .flags = MIPI_DSI_MODE_VIDEO,
4618 .format = MIPI_DSI_FMT_RGB888,
4622 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4625 .hsync_start = 1920 + 154,
4626 .hsync_end = 1920 + 154 + 16,
4627 .htotal = 1920 + 154 + 16 + 32,
4629 .vsync_start = 1200 + 17,
4630 .vsync_end = 1200 + 17 + 2,
4631 .vtotal = 1200 + 17 + 2 + 16,
4634 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4636 .modes = &panasonic_vvx10f004b00_mode,
4643 .connector_type = DRM_MODE_CONNECTOR_DSI,
4645 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4646 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4647 .format = MIPI_DSI_FMT_RGB888,
4651 static const struct drm_display_mode lg_acx467akm_7_mode = {
4654 .hsync_start = 1080 + 2,
4655 .hsync_end = 1080 + 2 + 2,
4656 .htotal = 1080 + 2 + 2 + 2,
4658 .vsync_start = 1920 + 2,
4659 .vsync_end = 1920 + 2 + 2,
4660 .vtotal = 1920 + 2 + 2 + 2,
4663 static const struct panel_desc_dsi lg_acx467akm_7 = {
4665 .modes = &lg_acx467akm_7_mode,
4672 .connector_type = DRM_MODE_CONNECTOR_DSI,
4675 .format = MIPI_DSI_FMT_RGB888,
4679 static const struct drm_display_mode osd101t2045_53ts_mode = {
4682 .hsync_start = 1920 + 112,
4683 .hsync_end = 1920 + 112 + 16,
4684 .htotal = 1920 + 112 + 16 + 32,
4686 .vsync_start = 1200 + 16,
4687 .vsync_end = 1200 + 16 + 2,
4688 .vtotal = 1200 + 16 + 2 + 16,
4689 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4692 static const struct panel_desc_dsi osd101t2045_53ts = {
4694 .modes = &osd101t2045_53ts_mode,
4701 .connector_type = DRM_MODE_CONNECTOR_DSI,
4703 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4704 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4705 MIPI_DSI_MODE_NO_EOT_PACKET,
4706 .format = MIPI_DSI_FMT_RGB888,
4710 static const struct of_device_id dsi_of_match[] = {
4712 .compatible = "auo,b080uan01",
4713 .data = &auo_b080uan01
4715 .compatible = "boe,tv080wum-nl0",
4716 .data = &boe_tv080wum_nl0
4718 .compatible = "lg,ld070wx3-sl01",
4719 .data = &lg_ld070wx3_sl01
4721 .compatible = "lg,lh500wx1-sd03",
4722 .data = &lg_lh500wx1_sd03
4724 .compatible = "panasonic,vvx10f004b00",
4725 .data = &panasonic_vvx10f004b00
4727 .compatible = "lg,acx467akm-7",
4728 .data = &lg_acx467akm_7
4730 .compatible = "osddisplays,osd101t2045-53ts",
4731 .data = &osd101t2045_53ts
4736 MODULE_DEVICE_TABLE(of, dsi_of_match);
4738 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4740 const struct panel_desc_dsi *desc;
4741 const struct of_device_id *id;
4744 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4750 err = panel_simple_probe(&dsi->dev, &desc->desc);
4754 dsi->mode_flags = desc->flags;
4755 dsi->format = desc->format;
4756 dsi->lanes = desc->lanes;
4758 err = mipi_dsi_attach(dsi);
4760 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
4762 drm_panel_remove(&panel->base);
4768 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4772 err = mipi_dsi_detach(dsi);
4774 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4776 panel_simple_remove(&dsi->dev);
4779 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4781 panel_simple_shutdown(&dsi->dev);
4784 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4786 .name = "panel-simple-dsi",
4787 .of_match_table = dsi_of_match,
4788 .pm = &panel_simple_pm_ops,
4790 .probe = panel_simple_dsi_probe,
4791 .remove = panel_simple_dsi_remove,
4792 .shutdown = panel_simple_dsi_shutdown,
4795 static int __init panel_simple_init(void)
4799 err = platform_driver_register(&panel_simple_platform_driver);
4803 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4804 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4806 goto err_did_platform_register;
4811 err_did_platform_register:
4812 platform_driver_unregister(&panel_simple_platform_driver);
4816 module_init(panel_simple_init);
4818 static void __exit panel_simple_exit(void)
4820 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4821 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4823 platform_driver_unregister(&panel_simple_platform_driver);
4825 module_exit(panel_simple_exit);
4827 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4828 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4829 MODULE_LICENSE("GPL and additional rights");