drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44
  45 #include "r100_reg_safe.h"
  46 #include "rn50_reg_safe.h"
  47
  48 /* Firmware Names */
  49 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  50 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  51 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  52 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  53 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  54 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  55 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  56
  57 MODULE_FIRMWARE(FIRMWARE_R100);
  58 MODULE_FIRMWARE(FIRMWARE_R200);
  59 MODULE_FIRMWARE(FIRMWARE_R300);
  60 MODULE_FIRMWARE(FIRMWARE_R420);
  61 MODULE_FIRMWARE(FIRMWARE_RS690);
  62 MODULE_FIRMWARE(FIRMWARE_RS600);
  63 MODULE_FIRMWARE(FIRMWARE_R520);
  64
  65 #include "r100_track.h"
  66
  67 /* This files gather functions specifics to:
  68  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  69  */
  70
  71 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
  72 {
  73         /* enable the pflip int */
  74         radeon_irq_kms_pflip_irq_get(rdev, crtc);
  75 }
  76
  77 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
  78 {
  79         /* disable the pflip int */
  80         radeon_irq_kms_pflip_irq_put(rdev, crtc);
  81 }
  82
  83 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  84 {
  85         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  86         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
  87
  88         /* Lock the graphics update lock */
  89         /* update the scanout addresses */
  90         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
  91
  92         /* Wait for update_pending to go high. */
  93         while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));
  94         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  95
  96         /* Unlock the lock, so double-buffering can take place inside vblank */
  97         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
  98         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
  99
 100         /* Return current update_pending status: */
 101         return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
 102 }
 103
 104 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 105 {
 106         int i;
 107         rdev->pm.dynpm_can_upclock = true;
 108         rdev->pm.dynpm_can_downclock = true;
 109
 110         switch (rdev->pm.dynpm_planned_action) {
 111         case DYNPM_ACTION_MINIMUM:
 112                 rdev->pm.requested_power_state_index = 0;
 113                 rdev->pm.dynpm_can_downclock = false;
 114                 break;
 115         case DYNPM_ACTION_DOWNCLOCK:
 116                 if (rdev->pm.current_power_state_index == 0) {
 117                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 118                         rdev->pm.dynpm_can_downclock = false;
 119                 } else {
 120                         if (rdev->pm.active_crtc_count > 1) {
 121                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 122                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 123                                                 continue;
 124                                         else if (i >= rdev->pm.current_power_state_index) {
 125                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 126                                                 break;
 127                                         } else {
 128                                                 rdev->pm.requested_power_state_index = i;
 129                                                 break;
 130                                         }
 131                                 }
 132                         } else
 133                                 rdev->pm.requested_power_state_index =
 134                                         rdev->pm.current_power_state_index - 1;
 135                 }
 136                 /* don't use the power state if crtcs are active and no display flag is set */
 137                 if ((rdev->pm.active_crtc_count > 0) &&
 138                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 139                      RADEON_PM_MODE_NO_DISPLAY)) {
 140                         rdev->pm.requested_power_state_index++;
 141                 }
 142                 break;
 143         case DYNPM_ACTION_UPCLOCK:
 144                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 145                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 146                         rdev->pm.dynpm_can_upclock = false;
 147                 } else {
 148                         if (rdev->pm.active_crtc_count > 1) {
 149                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 150                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 151                                                 continue;
 152                                         else if (i <= rdev->pm.current_power_state_index) {
 153                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 154                                                 break;
 155                                         } else {
 156                                                 rdev->pm.requested_power_state_index = i;
 157                                                 break;
 158                                         }
 159                                 }
 160                         } else
 161                                 rdev->pm.requested_power_state_index =
 162                                         rdev->pm.current_power_state_index + 1;
 163                 }
 164                 break;
 165         case DYNPM_ACTION_DEFAULT:
 166                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 167                 rdev->pm.dynpm_can_upclock = false;
 168                 break;
 169         case DYNPM_ACTION_NONE:
 170         default:
 171                 DRM_ERROR("Requested mode for not defined action\n");
 172                 return;
 173         }
 174         /* only one clock mode per power state */
 175         rdev->pm.requested_clock_mode_index = 0;
 176
 177         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 178                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 179                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 180                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 181                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 182                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 183                   pcie_lanes);
 184 }
 185
 186 void r100_pm_init_profile(struct radeon_device *rdev)
 187 {
 188         /* default */
 189         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 190         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 191         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 192         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 193         /* low sh */
 194         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 195         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 196         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 197         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 198         /* mid sh */
 199         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 200         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 201         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 202         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 203         /* high sh */
 204         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 205         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 206         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 207         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 208         /* low mh */
 209         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 210         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 211         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 212         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 213         /* mid mh */
 214         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 215         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 216         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 217         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 218         /* high mh */
 219         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 220         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 221         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 222         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 223 }
 224
 225 void r100_pm_misc(struct radeon_device *rdev)
 226 {
 227         int requested_index = rdev->pm.requested_power_state_index;
 228         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 229         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 230         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 231
 232         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 233                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 234                         tmp = RREG32(voltage->gpio.reg);
 235                         if (voltage->active_high)
 236                                 tmp |= voltage->gpio.mask;
 237                         else
 238                                 tmp &= ~(voltage->gpio.mask);
 239                         WREG32(voltage->gpio.reg, tmp);
 240                         if (voltage->delay)
 241                                 udelay(voltage->delay);
 242                 } else {
 243                         tmp = RREG32(voltage->gpio.reg);
 244                         if (voltage->active_high)
 245                                 tmp &= ~voltage->gpio.mask;
 246                         else
 247                                 tmp |= voltage->gpio.mask;
 248                         WREG32(voltage->gpio.reg, tmp);
 249                         if (voltage->delay)
 250                                 udelay(voltage->delay);
 251                 }
 252         }
 253
 254         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 255         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 256         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 257         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 258         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 259         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 260                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 261                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 262                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 263                 else
 264                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 265                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 266                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 267                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 268                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 269         } else
 270                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 271
 272         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 273                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 274                 if (voltage->delay) {
 275                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 276                         switch (voltage->delay) {
 277                         case 33:
 278                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 279                                 break;
 280                         case 66:
 281                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 282                                 break;
 283                         case 99:
 284                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 285                                 break;
 286                         case 132:
 287                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 288                                 break;
 289                         }
 290                 } else
 291                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 292         } else
 293                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 294
 295         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 296                 sclk_cntl &= ~FORCE_HDP;
 297         else
 298                 sclk_cntl |= FORCE_HDP;
 299
 300         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 301         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 302         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 303
 304         /* set pcie lanes */
 305         if ((rdev->flags & RADEON_IS_PCIE) &&
 306             !(rdev->flags & RADEON_IS_IGP) &&
 307             rdev->asic->set_pcie_lanes &&
 308             (ps->pcie_lanes !=
 309              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 310                 radeon_set_pcie_lanes(rdev,
 311                                       ps->pcie_lanes);
 312                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 313         }
 314 }
 315
 316 void r100_pm_prepare(struct radeon_device *rdev)
 317 {
 318         struct drm_device *ddev = rdev->ddev;
 319         struct drm_crtc *crtc;
 320         struct radeon_crtc *radeon_crtc;
 321         u32 tmp;
 322
 323         /* disable any active CRTCs */
 324         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 325                 radeon_crtc = to_radeon_crtc(crtc);
 326                 if (radeon_crtc->enabled) {
 327                         if (radeon_crtc->crtc_id) {
 328                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 329                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 330                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 331                         } else {
 332                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 333                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 334                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 335                         }
 336                 }
 337         }
 338 }
 339
 340 void r100_pm_finish(struct radeon_device *rdev)
 341 {
 342         struct drm_device *ddev = rdev->ddev;
 343         struct drm_crtc *crtc;
 344         struct radeon_crtc *radeon_crtc;
 345         u32 tmp;
 346
 347         /* enable any active CRTCs */
 348         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 349                 radeon_crtc = to_radeon_crtc(crtc);
 350                 if (radeon_crtc->enabled) {
 351                         if (radeon_crtc->crtc_id) {
 352                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 353                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 354                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 355                         } else {
 356                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 357                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 358                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 359                         }
 360                 }
 361         }
 362 }
 363
 364 bool r100_gui_idle(struct radeon_device *rdev)
 365 {
 366         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 367                 return false;
 368         else
 369                 return true;
 370 }
 371
 372 /* hpd for digital panel detect/disconnect */
 373 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 374 {
 375         bool connected = false;
 376
 377         switch (hpd) {
 378         case RADEON_HPD_1:
 379                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 380                         connected = true;
 381                 break;
 382         case RADEON_HPD_2:
 383                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 384                         connected = true;
 385                 break;
 386         default:
 387                 break;
 388         }
 389         return connected;
 390 }
 391
 392 void r100_hpd_set_polarity(struct radeon_device *rdev,
 393                            enum radeon_hpd_id hpd)
 394 {
 395         u32 tmp;
 396         bool connected = r100_hpd_sense(rdev, hpd);
 397
 398         switch (hpd) {
 399         case RADEON_HPD_1:
 400                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 401                 if (connected)
 402                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 403                 else
 404                         tmp |= RADEON_FP_DETECT_INT_POL;
 405                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 406                 break;
 407         case RADEON_HPD_2:
 408                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 409                 if (connected)
 410                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 411                 else
 412                         tmp |= RADEON_FP2_DETECT_INT_POL;
 413                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 414                 break;
 415         default:
 416                 break;
 417         }
 418 }
 419
 420 void r100_hpd_init(struct radeon_device *rdev)
 421 {
 422         struct drm_device *dev = rdev->ddev;
 423         struct drm_connector *connector;
 424
 425         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 426                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 427                 switch (radeon_connector->hpd.hpd) {
 428                 case RADEON_HPD_1:
 429                         rdev->irq.hpd[0] = true;
 430                         break;
 431                 case RADEON_HPD_2:
 432                         rdev->irq.hpd[1] = true;
 433                         break;
 434                 default:
 435                         break;
 436                 }
 437                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 438         }
 439         if (rdev->irq.installed)
 440                 r100_irq_set(rdev);
 441 }
 442
 443 void r100_hpd_fini(struct radeon_device *rdev)
 444 {
 445         struct drm_device *dev = rdev->ddev;
 446         struct drm_connector *connector;
 447
 448         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 449                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 450                 switch (radeon_connector->hpd.hpd) {
 451                 case RADEON_HPD_1:
 452                         rdev->irq.hpd[0] = false;
 453                         break;
 454                 case RADEON_HPD_2:
 455                         rdev->irq.hpd[1] = false;
 456                         break;
 457                 default:
 458                         break;
 459                 }
 460         }
 461 }
 462
 463 /*
 464  * PCI GART
 465  */
 466 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 467 {
 468         /* TODO: can we do somethings here ? */
 469         /* It seems hw only cache one entry so we should discard this
 470          * entry otherwise if first GPU GART read hit this entry it
 471          * could end up in wrong address. */
 472 }
 473
 474 int r100_pci_gart_init(struct radeon_device *rdev)
 475 {
 476         int r;
 477
 478         if (rdev->gart.table.ram.ptr) {
 479                 WARN(1, "R100 PCI GART already initialized\n");
 480                 return 0;
 481         }
 482         /* Initialize common gart structure */
 483         r = radeon_gart_init(rdev);
 484         if (r)
 485                 return r;
 486         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 487         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 488         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 489         return radeon_gart_table_ram_alloc(rdev);
 490 }
 491
 492 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 493 void r100_enable_bm(struct radeon_device *rdev)
 494 {
 495         uint32_t tmp;
 496         /* Enable bus mastering */
 497         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 498         WREG32(RADEON_BUS_CNTL, tmp);
 499 }
 500
 501 int r100_pci_gart_enable(struct radeon_device *rdev)
 502 {
 503         uint32_t tmp;
 504
 505         radeon_gart_restore(rdev);
 506         /* discard memory request outside of configured range */
 507         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 508         WREG32(RADEON_AIC_CNTL, tmp);
 509         /* set address range for PCI address translate */
 510         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 511         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 512         /* set PCI GART page-table base address */
 513         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 514         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 515         WREG32(RADEON_AIC_CNTL, tmp);
 516         r100_pci_gart_tlb_flush(rdev);
 517         rdev->gart.ready = true;
 518         return 0;
 519 }
 520
 521 void r100_pci_gart_disable(struct radeon_device *rdev)
 522 {
 523         uint32_t tmp;
 524
 525         /* discard memory request outside of configured range */
 526         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 527         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 528         WREG32(RADEON_AIC_LO_ADDR, 0);
 529         WREG32(RADEON_AIC_HI_ADDR, 0);
 530 }
 531
 532 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 533 {
 534         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 535                 return -EINVAL;
 536         }
 537         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 538         return 0;
 539 }
 540
 541 void r100_pci_gart_fini(struct radeon_device *rdev)
 542 {
 543         radeon_gart_fini(rdev);
 544         r100_pci_gart_disable(rdev);
 545         radeon_gart_table_ram_free(rdev);
 546 }
 547
 548 int r100_irq_set(struct radeon_device *rdev)
 549 {
 550         uint32_t tmp = 0;
 551
 552         if (!rdev->irq.installed) {
 553                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 554                 WREG32(R_000040_GEN_INT_CNTL, 0);
 555                 return -EINVAL;
 556         }
 557         if (rdev->irq.sw_int) {
 558                 tmp |= RADEON_SW_INT_ENABLE;
 559         }
 560         if (rdev->irq.gui_idle) {
 561                 tmp |= RADEON_GUI_IDLE_MASK;
 562         }
 563         if (rdev->irq.crtc_vblank_int[0] ||
 564             rdev->irq.pflip[0]) {
 565                 tmp |= RADEON_CRTC_VBLANK_MASK;
 566         }
 567         if (rdev->irq.crtc_vblank_int[1] ||
 568             rdev->irq.pflip[1]) {
 569                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 570         }
 571         if (rdev->irq.hpd[0]) {
 572                 tmp |= RADEON_FP_DETECT_MASK;
 573         }
 574         if (rdev->irq.hpd[1]) {
 575                 tmp |= RADEON_FP2_DETECT_MASK;
 576         }
 577         WREG32(RADEON_GEN_INT_CNTL, tmp);
 578         return 0;
 579 }
 580
 581 void r100_irq_disable(struct radeon_device *rdev)
 582 {
 583         u32 tmp;
 584
 585         WREG32(R_000040_GEN_INT_CNTL, 0);
 586         /* Wait and acknowledge irq */
 587         mdelay(1);
 588         tmp = RREG32(R_000044_GEN_INT_STATUS);
 589         WREG32(R_000044_GEN_INT_STATUS, tmp);
 590 }
 591
 592 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 593 {
 594         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 595         uint32_t irq_mask = RADEON_SW_INT_TEST |
 596                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 597                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 598
 599         /* the interrupt works, but the status bit is permanently asserted */
 600         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 601                 if (!rdev->irq.gui_idle_acked)
 602                         irq_mask |= RADEON_GUI_IDLE_STAT;
 603         }
 604
 605         if (irqs) {
 606                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 607         }
 608         return irqs & irq_mask;
 609 }
 610
 611 int r100_irq_process(struct radeon_device *rdev)
 612 {
 613         uint32_t status, msi_rearm;
 614         bool queue_hotplug = false;
 615
 616         /* reset gui idle ack.  the status bit is broken */
 617         rdev->irq.gui_idle_acked = false;
 618
 619         status = r100_irq_ack(rdev);
 620         if (!status) {
 621                 return IRQ_NONE;
 622         }
 623         if (rdev->shutdown) {
 624                 return IRQ_NONE;
 625         }
 626         while (status) {
 627                 /* SW interrupt */
 628                 if (status & RADEON_SW_INT_TEST) {
 629                         radeon_fence_process(rdev);
 630                 }
 631                 /* gui idle interrupt */
 632                 if (status & RADEON_GUI_IDLE_STAT) {
 633                         rdev->irq.gui_idle_acked = true;
 634                         rdev->pm.gui_idle = true;
 635                         wake_up(&rdev->irq.idle_queue);
 636                 }
 637                 /* Vertical blank interrupts */
 638                 if (status & RADEON_CRTC_VBLANK_STAT) {
 639                         if (rdev->irq.crtc_vblank_int[0]) {
 640                                 drm_handle_vblank(rdev->ddev, 0);
 641                                 rdev->pm.vblank_sync = true;
 642                                 wake_up(&rdev->irq.vblank_queue);
 643                         }
 644                         if (rdev->irq.pflip[0])
 645                                 radeon_crtc_handle_flip(rdev, 0);
 646                 }
 647                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 648                         if (rdev->irq.crtc_vblank_int[1]) {
 649                                 drm_handle_vblank(rdev->ddev, 1);
 650                                 rdev->pm.vblank_sync = true;
 651                                 wake_up(&rdev->irq.vblank_queue);
 652                         }
 653                         if (rdev->irq.pflip[1])
 654                                 radeon_crtc_handle_flip(rdev, 1);
 655                 }
 656                 if (status & RADEON_FP_DETECT_STAT) {
 657                         queue_hotplug = true;
 658                         DRM_DEBUG("HPD1\n");
 659                 }
 660                 if (status & RADEON_FP2_DETECT_STAT) {
 661                         queue_hotplug = true;
 662                         DRM_DEBUG("HPD2\n");
 663                 }
 664                 status = r100_irq_ack(rdev);
 665         }
 666         /* reset gui idle ack.  the status bit is broken */
 667         rdev->irq.gui_idle_acked = false;
 668         if (queue_hotplug)
 669                 schedule_work(&rdev->hotplug_work);
 670         if (rdev->msi_enabled) {
 671                 switch (rdev->family) {
 672                 case CHIP_RS400:
 673                 case CHIP_RS480:
 674                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 675                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 676                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 677                         break;
 678                 default:
 679                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 680                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 681                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 682                         break;
 683                 }
 684         }
 685         return IRQ_HANDLED;
 686 }
 687
 688 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 689 {
 690         if (crtc == 0)
 691                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 692         else
 693                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 694 }
 695
 696 /* Who ever call radeon_fence_emit should call ring_lock and ask
 697  * for enough space (today caller are ib schedule and buffer move) */
 698 void r100_fence_ring_emit(struct radeon_device *rdev,
 699                           struct radeon_fence *fence)
 700 {
 701         /* We have to make sure that caches are flushed before
 702          * CPU might read something from VRAM. */
 703         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 704         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 705         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 706         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 707         /* Wait until IDLE & CLEAN */
 708         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 709         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 710         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 711         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 712                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 713         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 714         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 715         /* Emit fence sequence & fire IRQ */
 716         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 717         radeon_ring_write(rdev, fence->seq);
 718         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 719         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 720 }
 721
 722 int r100_copy_blit(struct radeon_device *rdev,
 723                    uint64_t src_offset,
 724                    uint64_t dst_offset,
 725                    unsigned num_gpu_pages,
 726                    struct radeon_fence *fence)
 727 {
 728         uint32_t cur_pages;
 729         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
 730         uint32_t pitch;
 731         uint32_t stride_pixels;
 732         unsigned ndw;
 733         int num_loops;
 734         int r = 0;
 735
 736         /* radeon limited to 16k stride */
 737         stride_bytes &= 0x3fff;
 738         /* radeon pitch is /64 */
 739         pitch = stride_bytes / 64;
 740         stride_pixels = stride_bytes / 4;
 741         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
 742
 743         /* Ask for enough room for blit + flush + fence */
 744         ndw = 64 + (10 * num_loops);
 745         r = radeon_ring_lock(rdev, ndw);
 746         if (r) {
 747                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 748                 return -EINVAL;
 749         }
 750         while (num_gpu_pages > 0) {
 751                 cur_pages = num_gpu_pages;
 752                 if (cur_pages > 8191) {
 753                         cur_pages = 8191;
 754                 }
 755                 num_gpu_pages -= cur_pages;
 756
 757                 /* pages are in Y direction - height
 758                    page width in X direction - width */
 759                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 760                 radeon_ring_write(rdev,
 761                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 762                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 763                                   RADEON_GMC_SRC_CLIPPING |
 764                                   RADEON_GMC_DST_CLIPPING |
 765                                   RADEON_GMC_BRUSH_NONE |
 766                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 767                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 768                                   RADEON_ROP3_S |
 769                                   RADEON_DP_SRC_SOURCE_MEMORY |
 770                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 771                                   RADEON_GMC_WR_MSK_DIS);
 772                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 773                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 774                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 775                 radeon_ring_write(rdev, 0);
 776                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 777                 radeon_ring_write(rdev, num_gpu_pages);
 778                 radeon_ring_write(rdev, num_gpu_pages);
 779                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 780         }
 781         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 782         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 783         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 784         radeon_ring_write(rdev,
 785                           RADEON_WAIT_2D_IDLECLEAN |
 786                           RADEON_WAIT_HOST_IDLECLEAN |
 787                           RADEON_WAIT_DMA_GUI_IDLE);
 788         if (fence) {
 789                 r = radeon_fence_emit(rdev, fence);
 790         }
 791         radeon_ring_unlock_commit(rdev);
 792         return r;
 793 }
 794
 795 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 796 {
 797         unsigned i;
 798         u32 tmp;
 799
 800         for (i = 0; i < rdev->usec_timeout; i++) {
 801                 tmp = RREG32(R_000E40_RBBM_STATUS);
 802                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 803                         return 0;
 804                 }
 805                 udelay(1);
 806         }
 807         return -1;
 808 }
 809
 810 void r100_ring_start(struct radeon_device *rdev)
 811 {
 812         int r;
 813
 814         r = radeon_ring_lock(rdev, 2);
 815         if (r) {
 816                 return;
 817         }
 818         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 819         radeon_ring_write(rdev,
 820                           RADEON_ISYNC_ANY2D_IDLE3D |
 821                           RADEON_ISYNC_ANY3D_IDLE2D |
 822                           RADEON_ISYNC_WAIT_IDLEGUI |
 823                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 824         radeon_ring_unlock_commit(rdev);
 825 }
 826
 827
 828 /* Load the microcode for the CP */
 829 static int r100_cp_init_microcode(struct radeon_device *rdev)
 830 {
 831         struct platform_device *pdev;
 832         const char *fw_name = NULL;
 833         int err;
 834
 835         DRM_DEBUG_KMS("\n");
 836
 837         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 838         err = IS_ERR(pdev);
 839         if (err) {
 840                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 841                 return -EINVAL;
 842         }
 843         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 844             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 845             (rdev->family == CHIP_RS200)) {
 846                 DRM_INFO("Loading R100 Microcode\n");
 847                 fw_name = FIRMWARE_R100;
 848         } else if ((rdev->family == CHIP_R200) ||
 849                    (rdev->family == CHIP_RV250) ||
 850                    (rdev->family == CHIP_RV280) ||
 851                    (rdev->family == CHIP_RS300)) {
 852                 DRM_INFO("Loading R200 Microcode\n");
 853                 fw_name = FIRMWARE_R200;
 854         } else if ((rdev->family == CHIP_R300) ||
 855                    (rdev->family == CHIP_R350) ||
 856                    (rdev->family == CHIP_RV350) ||
 857                    (rdev->family == CHIP_RV380) ||
 858                    (rdev->family == CHIP_RS400) ||
 859                    (rdev->family == CHIP_RS480)) {
 860                 DRM_INFO("Loading R300 Microcode\n");
 861                 fw_name = FIRMWARE_R300;
 862         } else if ((rdev->family == CHIP_R420) ||
 863                    (rdev->family == CHIP_R423) ||
 864                    (rdev->family == CHIP_RV410)) {
 865                 DRM_INFO("Loading R400 Microcode\n");
 866                 fw_name = FIRMWARE_R420;
 867         } else if ((rdev->family == CHIP_RS690) ||
 868                    (rdev->family == CHIP_RS740)) {
 869                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 870                 fw_name = FIRMWARE_RS690;
 871         } else if (rdev->family == CHIP_RS600) {
 872                 DRM_INFO("Loading RS600 Microcode\n");
 873                 fw_name = FIRMWARE_RS600;
 874         } else if ((rdev->family == CHIP_RV515) ||
 875                    (rdev->family == CHIP_R520) ||
 876                    (rdev->family == CHIP_RV530) ||
 877                    (rdev->family == CHIP_R580) ||
 878                    (rdev->family == CHIP_RV560) ||
 879                    (rdev->family == CHIP_RV570)) {
 880                 DRM_INFO("Loading R500 Microcode\n");
 881                 fw_name = FIRMWARE_R520;
 882         }
 883
 884         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 885         platform_device_unregister(pdev);
 886         if (err) {
 887                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 888                        fw_name);
 889         } else if (rdev->me_fw->size % 8) {
 890                 printk(KERN_ERR
 891                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 892                        rdev->me_fw->size, fw_name);
 893                 err = -EINVAL;
 894                 release_firmware(rdev->me_fw);
 895                 rdev->me_fw = NULL;
 896         }
 897         return err;
 898 }
 899
 900 static void r100_cp_load_microcode(struct radeon_device *rdev)
 901 {
 902         const __be32 *fw_data;
 903         int i, size;
 904
 905         if (r100_gui_wait_for_idle(rdev)) {
 906                 printk(KERN_WARNING "Failed to wait GUI idle while "
 907                        "programming pipes. Bad things might happen.\n");
 908         }
 909
 910         if (rdev->me_fw) {
 911                 size = rdev->me_fw->size / 4;
 912                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 913                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 914                 for (i = 0; i < size; i += 2) {
 915                         WREG32(RADEON_CP_ME_RAM_DATAH,
 916                                be32_to_cpup(&fw_data[i]));
 917                         WREG32(RADEON_CP_ME_RAM_DATAL,
 918                                be32_to_cpup(&fw_data[i + 1]));
 919                 }
 920         }
 921 }
 922
 923 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 924 {
 925         unsigned rb_bufsz;
 926         unsigned rb_blksz;
 927         unsigned max_fetch;
 928         unsigned pre_write_timer;
 929         unsigned pre_write_limit;
 930         unsigned indirect2_start;
 931         unsigned indirect1_start;
 932         uint32_t tmp;
 933         int r;
 934
 935         if (r100_debugfs_cp_init(rdev)) {
 936                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 937         }
 938         if (!rdev->me_fw) {
 939                 r = r100_cp_init_microcode(rdev);
 940                 if (r) {
 941                         DRM_ERROR("Failed to load firmware!\n");
 942                         return r;
 943                 }
 944         }
 945
 946         /* Align ring size */
 947         rb_bufsz = drm_order(ring_size / 8);
 948         ring_size = (1 << (rb_bufsz + 1)) * 4;
 949         r100_cp_load_microcode(rdev);
 950         r = radeon_ring_init(rdev, ring_size);
 951         if (r) {
 952                 return r;
 953         }
 954         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 955          * the rptr copy in system ram */
 956         rb_blksz = 9;
 957         /* cp will read 128bytes at a time (4 dwords) */
 958         max_fetch = 1;
 959         rdev->cp.align_mask = 16 - 1;
 960         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 961         pre_write_timer = 64;
 962         /* Force CP_RB_WPTR write if written more than one time before the
 963          * delay expire
 964          */
 965         pre_write_limit = 0;
 966         /* Setup the cp cache like this (cache size is 96 dwords) :
 967          *      RING            0  to 15
 968          *      INDIRECT1       16 to 79
 969          *      INDIRECT2       80 to 95
 970          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 971          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 972          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 973          * Idea being that most of the gpu cmd will be through indirect1 buffer
 974          * so it gets the bigger cache.
 975          */
 976         indirect2_start = 80;
 977         indirect1_start = 16;
 978         /* cp setup */
 979         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 980         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 981                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 982                REG_SET(RADEON_MAX_FETCH, max_fetch));
 983 #ifdef __BIG_ENDIAN
 984         tmp |= RADEON_BUF_SWAP_32BIT;
 985 #endif
 986         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
 987
 988         /* Set ring address */
 989         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
 990         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
 991         /* Force read & write ptr to 0 */
 992         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
 993         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 994         rdev->cp.wptr = 0;
 995         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
 996
 997         /* set the wb address whether it's enabled or not */
 998         WREG32(R_00070C_CP_RB_RPTR_ADDR,
 999                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1000         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1001
1002         if (rdev->wb.enabled)
1003                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1004         else {
1005                 tmp |= RADEON_RB_NO_UPDATE;
1006                 WREG32(R_000770_SCRATCH_UMSK, 0);
1007         }
1008
1009         WREG32(RADEON_CP_RB_CNTL, tmp);
1010         udelay(10);
1011         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1012         /* Set cp mode to bus mastering & enable cp*/
1013         WREG32(RADEON_CP_CSQ_MODE,
1014                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1015                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1016         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1017         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1018         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1019         radeon_ring_start(rdev);
1020         r = radeon_ring_test(rdev);
1021         if (r) {
1022                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1023                 return r;
1024         }
1025         rdev->cp.ready = true;
1026         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1027         return 0;
1028 }
1029
1030 void r100_cp_fini(struct radeon_device *rdev)
1031 {
1032         if (r100_cp_wait_for_idle(rdev)) {
1033                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1034         }
1035         /* Disable ring */
1036         r100_cp_disable(rdev);
1037         radeon_ring_fini(rdev);
1038         DRM_INFO("radeon: cp finalized\n");
1039 }
1040
1041 void r100_cp_disable(struct radeon_device *rdev)
1042 {
1043         /* Disable ring */
1044         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1045         rdev->cp.ready = false;
1046         WREG32(RADEON_CP_CSQ_MODE, 0);
1047         WREG32(RADEON_CP_CSQ_CNTL, 0);
1048         WREG32(R_000770_SCRATCH_UMSK, 0);
1049         if (r100_gui_wait_for_idle(rdev)) {
1050                 printk(KERN_WARNING "Failed to wait GUI idle while "
1051                        "programming pipes. Bad things might happen.\n");
1052         }
1053 }
1054
1055 void r100_cp_commit(struct radeon_device *rdev)
1056 {
1057         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1058         (void)RREG32(RADEON_CP_RB_WPTR);
1059 }
1060
1061
1062 /*
1063  * CS functions
1064  */
1065 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1066                           struct radeon_cs_packet *pkt,
1067                           const unsigned *auth, unsigned n,
1068                           radeon_packet0_check_t check)
1069 {
1070         unsigned reg;
1071         unsigned i, j, m;
1072         unsigned idx;
1073         int r;
1074
1075         idx = pkt->idx + 1;
1076         reg = pkt->reg;
1077         /* Check that register fall into register range
1078          * determined by the number of entry (n) in the
1079          * safe register bitmap.
1080          */
1081         if (pkt->one_reg_wr) {
1082                 if ((reg >> 7) > n) {
1083                         return -EINVAL;
1084                 }
1085         } else {
1086                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1087                         return -EINVAL;
1088                 }
1089         }
1090         for (i = 0; i <= pkt->count; i++, idx++) {
1091                 j = (reg >> 7);
1092                 m = 1 << ((reg >> 2) & 31);
1093                 if (auth[j] & m) {
1094                         r = check(p, pkt, idx, reg);
1095                         if (r) {
1096                                 return r;
1097                         }
1098                 }
1099                 if (pkt->one_reg_wr) {
1100                         if (!(auth[j] & m)) {
1101                                 break;
1102                         }
1103                 } else {
1104                         reg += 4;
1105                 }
1106         }
1107         return 0;
1108 }
1109
1110 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1111                          struct radeon_cs_packet *pkt)
1112 {
1113         volatile uint32_t *ib;
1114         unsigned i;
1115         unsigned idx;
1116
1117         ib = p->ib->ptr;
1118         idx = pkt->idx;
1119         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1120                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1121         }
1122 }
1123
1124 /**
1125  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1126  * @parser:     parser structure holding parsing context.
1127  * @pkt:        where to store packet informations
1128  *
1129  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1130  * if packet is bigger than remaining ib size. or if packets is unknown.
1131  **/
1132 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1133                          struct radeon_cs_packet *pkt,
1134                          unsigned idx)
1135 {
1136         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1137         uint32_t header;
1138
1139         if (idx >= ib_chunk->length_dw) {
1140                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1141                           idx, ib_chunk->length_dw);
1142                 return -EINVAL;
1143         }
1144         header = radeon_get_ib_value(p, idx);
1145         pkt->idx = idx;
1146         pkt->type = CP_PACKET_GET_TYPE(header);
1147         pkt->count = CP_PACKET_GET_COUNT(header);
1148         switch (pkt->type) {
1149         case PACKET_TYPE0:
1150                 pkt->reg = CP_PACKET0_GET_REG(header);
1151                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1152                 break;
1153         case PACKET_TYPE3:
1154                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1155                 break;
1156         case PACKET_TYPE2:
1157                 pkt->count = -1;
1158                 break;
1159         default:
1160                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1161                 return -EINVAL;
1162         }
1163         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1164                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1165                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1166                 return -EINVAL;
1167         }
1168         return 0;
1169 }
1170
1171 /**
1172  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1173  * @parser:             parser structure holding parsing context.
1174  *
1175  * Userspace sends a special sequence for VLINE waits.
1176  * PACKET0 - VLINE_START_END + value
1177  * PACKET0 - WAIT_UNTIL +_value
1178  * RELOC (P3) - crtc_id in reloc.
1179  *
1180  * This function parses this and relocates the VLINE START END
1181  * and WAIT UNTIL packets to the correct crtc.
1182  * It also detects a switched off crtc and nulls out the
1183  * wait in that case.
1184  */
1185 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1186 {
1187         struct drm_mode_object *obj;
1188         struct drm_crtc *crtc;
1189         struct radeon_crtc *radeon_crtc;
1190         struct radeon_cs_packet p3reloc, waitreloc;
1191         int crtc_id;
1192         int r;
1193         uint32_t header, h_idx, reg;
1194         volatile uint32_t *ib;
1195
1196         ib = p->ib->ptr;
1197
1198         /* parse the wait until */
1199         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1200         if (r)
1201                 return r;
1202
1203         /* check its a wait until and only 1 count */
1204         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1205             waitreloc.count != 0) {
1206                 DRM_ERROR("vline wait had illegal wait until segment\n");
1207                 return -EINVAL;
1208         }
1209
1210         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1211                 DRM_ERROR("vline wait had illegal wait until\n");
1212                 return -EINVAL;
1213         }
1214
1215         /* jump over the NOP */
1216         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1217         if (r)
1218                 return r;
1219
1220         h_idx = p->idx - 2;
1221         p->idx += waitreloc.count + 2;
1222         p->idx += p3reloc.count + 2;
1223
1224         header = radeon_get_ib_value(p, h_idx);
1225         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1226         reg = CP_PACKET0_GET_REG(header);
1227         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1228         if (!obj) {
1229                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1230                 return -EINVAL;
1231         }
1232         crtc = obj_to_crtc(obj);
1233         radeon_crtc = to_radeon_crtc(crtc);
1234         crtc_id = radeon_crtc->crtc_id;
1235
1236         if (!crtc->enabled) {
1237                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1238                 ib[h_idx + 2] = PACKET2(0);
1239                 ib[h_idx + 3] = PACKET2(0);
1240         } else if (crtc_id == 1) {
1241                 switch (reg) {
1242                 case AVIVO_D1MODE_VLINE_START_END:
1243                         header &= ~R300_CP_PACKET0_REG_MASK;
1244                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1245                         break;
1246                 case RADEON_CRTC_GUI_TRIG_VLINE:
1247                         header &= ~R300_CP_PACKET0_REG_MASK;
1248                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1249                         break;
1250                 default:
1251                         DRM_ERROR("unknown crtc reloc\n");
1252                         return -EINVAL;
1253                 }
1254                 ib[h_idx] = header;
1255                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1256         }
1257
1258         return 0;
1259 }
1260
1261 /**
1262  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1263  * @parser:             parser structure holding parsing context.
1264  * @data:               pointer to relocation data
1265  * @offset_start:       starting offset
1266  * @offset_mask:        offset mask (to align start offset on)
1267  * @reloc:              reloc informations
1268  *
1269  * Check next packet is relocation packet3, do bo validation and compute
1270  * GPU offset using the provided start.
1271  **/
1272 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1273                               struct radeon_cs_reloc **cs_reloc)
1274 {
1275         struct radeon_cs_chunk *relocs_chunk;
1276         struct radeon_cs_packet p3reloc;
1277         unsigned idx;
1278         int r;
1279
1280         if (p->chunk_relocs_idx == -1) {
1281                 DRM_ERROR("No relocation chunk !\n");
1282                 return -EINVAL;
1283         }
1284         *cs_reloc = NULL;
1285         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1286         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1287         if (r) {
1288                 return r;
1289         }
1290         p->idx += p3reloc.count + 2;
1291         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1292                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1293                           p3reloc.idx);
1294                 r100_cs_dump_packet(p, &p3reloc);
1295                 return -EINVAL;
1296         }
1297         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1298         if (idx >= relocs_chunk->length_dw) {
1299                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1300                           idx, relocs_chunk->length_dw);
1301                 r100_cs_dump_packet(p, &p3reloc);
1302                 return -EINVAL;
1303         }
1304         /* FIXME: we assume reloc size is 4 dwords */
1305         *cs_reloc = p->relocs_ptr[(idx / 4)];
1306         return 0;
1307 }
1308
1309 static int r100_get_vtx_size(uint32_t vtx_fmt)
1310 {
1311         int vtx_size;
1312         vtx_size = 2;
1313         /* ordered according to bits in spec */
1314         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1315                 vtx_size++;
1316         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1317                 vtx_size += 3;
1318         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1319                 vtx_size++;
1320         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1321                 vtx_size++;
1322         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1323                 vtx_size += 3;
1324         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1325                 vtx_size++;
1326         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1327                 vtx_size++;
1328         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1329                 vtx_size += 2;
1330         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1331                 vtx_size += 2;
1332         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1333                 vtx_size++;
1334         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1335                 vtx_size += 2;
1336         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1337                 vtx_size++;
1338         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1339                 vtx_size += 2;
1340         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1341                 vtx_size++;
1342         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1343                 vtx_size++;
1344         /* blend weight */
1345         if (vtx_fmt & (0x7 << 15))
1346                 vtx_size += (vtx_fmt >> 15) & 0x7;
1347         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1348                 vtx_size += 3;
1349         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1350                 vtx_size += 2;
1351         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1352                 vtx_size++;
1353         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1354                 vtx_size++;
1355         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1356                 vtx_size++;
1357         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1358                 vtx_size++;
1359         return vtx_size;
1360 }
1361
1362 static int r100_packet0_check(struct radeon_cs_parser *p,
1363                               struct radeon_cs_packet *pkt,
1364                               unsigned idx, unsigned reg)
1365 {
1366         struct radeon_cs_reloc *reloc;
1367         struct r100_cs_track *track;
1368         volatile uint32_t *ib;
1369         uint32_t tmp;
1370         int r;
1371         int i, face;
1372         u32 tile_flags = 0;
1373         u32 idx_value;
1374
1375         ib = p->ib->ptr;
1376         track = (struct r100_cs_track *)p->track;
1377
1378         idx_value = radeon_get_ib_value(p, idx);
1379
1380         switch (reg) {
1381         case RADEON_CRTC_GUI_TRIG_VLINE:
1382                 r = r100_cs_packet_parse_vline(p);
1383                 if (r) {
1384                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1385                                   idx, reg);
1386                         r100_cs_dump_packet(p, pkt);
1387                         return r;
1388                 }
1389                 break;
1390                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1391                  * range access */
1392         case RADEON_DST_PITCH_OFFSET:
1393         case RADEON_SRC_PITCH_OFFSET:
1394                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1395                 if (r)
1396                         return r;
1397                 break;
1398         case RADEON_RB3D_DEPTHOFFSET:
1399                 r = r100_cs_packet_next_reloc(p, &reloc);
1400                 if (r) {
1401                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1402                                   idx, reg);
1403                         r100_cs_dump_packet(p, pkt);
1404                         return r;
1405                 }
1406                 track->zb.robj = reloc->robj;
1407                 track->zb.offset = idx_value;
1408                 track->zb_dirty = true;
1409                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1410                 break;
1411         case RADEON_RB3D_COLOROFFSET:
1412                 r = r100_cs_packet_next_reloc(p, &reloc);
1413                 if (r) {
1414                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1415                                   idx, reg);
1416                         r100_cs_dump_packet(p, pkt);
1417                         return r;
1418                 }
1419                 track->cb[0].robj = reloc->robj;
1420                 track->cb[0].offset = idx_value;
1421                 track->cb_dirty = true;
1422                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1423                 break;
1424         case RADEON_PP_TXOFFSET_0:
1425         case RADEON_PP_TXOFFSET_1:
1426         case RADEON_PP_TXOFFSET_2:
1427                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1428                 r = r100_cs_packet_next_reloc(p, &reloc);
1429                 if (r) {
1430                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1431                                   idx, reg);
1432                         r100_cs_dump_packet(p, pkt);
1433                         return r;
1434                 }
1435                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1436                 track->textures[i].robj = reloc->robj;
1437                 track->tex_dirty = true;
1438                 break;
1439         case RADEON_PP_CUBIC_OFFSET_T0_0:
1440         case RADEON_PP_CUBIC_OFFSET_T0_1:
1441         case RADEON_PP_CUBIC_OFFSET_T0_2:
1442         case RADEON_PP_CUBIC_OFFSET_T0_3:
1443         case RADEON_PP_CUBIC_OFFSET_T0_4:
1444                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1445                 r = r100_cs_packet_next_reloc(p, &reloc);
1446                 if (r) {
1447                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1448                                   idx, reg);
1449                         r100_cs_dump_packet(p, pkt);
1450                         return r;
1451                 }
1452                 track->textures[0].cube_info[i].offset = idx_value;
1453                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1454                 track->textures[0].cube_info[i].robj = reloc->robj;
1455                 track->tex_dirty = true;
1456                 break;
1457         case RADEON_PP_CUBIC_OFFSET_T1_0:
1458         case RADEON_PP_CUBIC_OFFSET_T1_1:
1459         case RADEON_PP_CUBIC_OFFSET_T1_2:
1460         case RADEON_PP_CUBIC_OFFSET_T1_3:
1461         case RADEON_PP_CUBIC_OFFSET_T1_4:
1462                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1463                 r = r100_cs_packet_next_reloc(p, &reloc);
1464                 if (r) {
1465                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1466                                   idx, reg);
1467                         r100_cs_dump_packet(p, pkt);
1468                         return r;
1469                 }
1470                 track->textures[1].cube_info[i].offset = idx_value;
1471                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1472                 track->textures[1].cube_info[i].robj = reloc->robj;
1473                 track->tex_dirty = true;
1474                 break;
1475         case RADEON_PP_CUBIC_OFFSET_T2_0:
1476         case RADEON_PP_CUBIC_OFFSET_T2_1:
1477         case RADEON_PP_CUBIC_OFFSET_T2_2:
1478         case RADEON_PP_CUBIC_OFFSET_T2_3:
1479         case RADEON_PP_CUBIC_OFFSET_T2_4:
1480                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1481                 r = r100_cs_packet_next_reloc(p, &reloc);
1482                 if (r) {
1483                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1484                                   idx, reg);
1485                         r100_cs_dump_packet(p, pkt);
1486                         return r;
1487                 }
1488                 track->textures[2].cube_info[i].offset = idx_value;
1489                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1490                 track->textures[2].cube_info[i].robj = reloc->robj;
1491                 track->tex_dirty = true;
1492                 break;
1493         case RADEON_RE_WIDTH_HEIGHT:
1494                 track->maxy = ((idx_value >> 16) & 0x7FF);
1495                 track->cb_dirty = true;
1496                 track->zb_dirty = true;
1497                 break;
1498         case RADEON_RB3D_COLORPITCH:
1499                 r = r100_cs_packet_next_reloc(p, &reloc);
1500                 if (r) {
1501                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1502                                   idx, reg);
1503                         r100_cs_dump_packet(p, pkt);
1504                         return r;
1505                 }
1506
1507                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1508                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1509                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1510                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1511
1512                 tmp = idx_value & ~(0x7 << 16);
1513                 tmp |= tile_flags;
1514                 ib[idx] = tmp;
1515
1516                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1517                 track->cb_dirty = true;
1518                 break;
1519         case RADEON_RB3D_DEPTHPITCH:
1520                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1521                 track->zb_dirty = true;
1522                 break;
1523         case RADEON_RB3D_CNTL:
1524                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1525                 case 7:
1526                 case 8:
1527                 case 9:
1528                 case 11:
1529                 case 12:
1530                         track->cb[0].cpp = 1;
1531                         break;
1532                 case 3:
1533                 case 4:
1534                 case 15:
1535                         track->cb[0].cpp = 2;
1536                         break;
1537                 case 6:
1538                         track->cb[0].cpp = 4;
1539                         break;
1540                 default:
1541                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1542                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1543                         return -EINVAL;
1544                 }
1545                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1546                 track->cb_dirty = true;
1547                 track->zb_dirty = true;
1548                 break;
1549         case RADEON_RB3D_ZSTENCILCNTL:
1550                 switch (idx_value & 0xf) {
1551                 case 0:
1552                         track->zb.cpp = 2;
1553                         break;
1554                 case 2:
1555                 case 3:
1556                 case 4:
1557                 case 5:
1558                 case 9:
1559                 case 11:
1560                         track->zb.cpp = 4;
1561                         break;
1562                 default:
1563                         break;
1564                 }
1565                 track->zb_dirty = true;
1566                 break;
1567         case RADEON_RB3D_ZPASS_ADDR:
1568                 r = r100_cs_packet_next_reloc(p, &reloc);
1569                 if (r) {
1570                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1571                                   idx, reg);
1572                         r100_cs_dump_packet(p, pkt);
1573                         return r;
1574                 }
1575                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1576                 break;
1577         case RADEON_PP_CNTL:
1578                 {
1579                         uint32_t temp = idx_value >> 4;
1580                         for (i = 0; i < track->num_texture; i++)
1581                                 track->textures[i].enabled = !!(temp & (1 << i));
1582                         track->tex_dirty = true;
1583                 }
1584                 break;
1585         case RADEON_SE_VF_CNTL:
1586                 track->vap_vf_cntl = idx_value;
1587                 break;
1588         case RADEON_SE_VTX_FMT:
1589                 track->vtx_size = r100_get_vtx_size(idx_value);
1590                 break;
1591         case RADEON_PP_TEX_SIZE_0:
1592         case RADEON_PP_TEX_SIZE_1:
1593         case RADEON_PP_TEX_SIZE_2:
1594                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1595                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1596                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1597                 track->tex_dirty = true;
1598                 break;
1599         case RADEON_PP_TEX_PITCH_0:
1600         case RADEON_PP_TEX_PITCH_1:
1601         case RADEON_PP_TEX_PITCH_2:
1602                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1603                 track->textures[i].pitch = idx_value + 32;
1604                 track->tex_dirty = true;
1605                 break;
1606         case RADEON_PP_TXFILTER_0:
1607         case RADEON_PP_TXFILTER_1:
1608         case RADEON_PP_TXFILTER_2:
1609                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1610                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1611                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1612                 tmp = (idx_value >> 23) & 0x7;
1613                 if (tmp == 2 || tmp == 6)
1614                         track->textures[i].roundup_w = false;
1615                 tmp = (idx_value >> 27) & 0x7;
1616                 if (tmp == 2 || tmp == 6)
1617                         track->textures[i].roundup_h = false;
1618                 track->tex_dirty = true;
1619                 break;
1620         case RADEON_PP_TXFORMAT_0:
1621         case RADEON_PP_TXFORMAT_1:
1622         case RADEON_PP_TXFORMAT_2:
1623                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1624                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1625                         track->textures[i].use_pitch = 1;
1626                 } else {
1627                         track->textures[i].use_pitch = 0;
1628                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1629                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1630                 }
1631                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1632                         track->textures[i].tex_coord_type = 2;
1633                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1634                 case RADEON_TXFORMAT_I8:
1635                 case RADEON_TXFORMAT_RGB332:
1636                 case RADEON_TXFORMAT_Y8:
1637                         track->textures[i].cpp = 1;
1638                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1639                         break;
1640                 case RADEON_TXFORMAT_AI88:
1641                 case RADEON_TXFORMAT_ARGB1555:
1642                 case RADEON_TXFORMAT_RGB565:
1643                 case RADEON_TXFORMAT_ARGB4444:
1644                 case RADEON_TXFORMAT_VYUY422:
1645                 case RADEON_TXFORMAT_YVYU422:
1646                 case RADEON_TXFORMAT_SHADOW16:
1647                 case RADEON_TXFORMAT_LDUDV655:
1648                 case RADEON_TXFORMAT_DUDV88:
1649                         track->textures[i].cpp = 2;
1650                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1651                         break;
1652                 case RADEON_TXFORMAT_ARGB8888:
1653                 case RADEON_TXFORMAT_RGBA8888:
1654                 case RADEON_TXFORMAT_SHADOW32:
1655                 case RADEON_TXFORMAT_LDUDUV8888:
1656                         track->textures[i].cpp = 4;
1657                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1658                         break;
1659                 case RADEON_TXFORMAT_DXT1:
1660                         track->textures[i].cpp = 1;
1661                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1662                         break;
1663                 case RADEON_TXFORMAT_DXT23:
1664                 case RADEON_TXFORMAT_DXT45:
1665                         track->textures[i].cpp = 1;
1666                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1667                         break;
1668                 }
1669                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1670                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1671                 track->tex_dirty = true;
1672                 break;
1673         case RADEON_PP_CUBIC_FACES_0:
1674         case RADEON_PP_CUBIC_FACES_1:
1675         case RADEON_PP_CUBIC_FACES_2:
1676                 tmp = idx_value;
1677                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1678                 for (face = 0; face < 4; face++) {
1679                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1680                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1681                 }
1682                 track->tex_dirty = true;
1683                 break;
1684         default:
1685                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1686                        reg, idx);
1687                 return -EINVAL;
1688         }
1689         return 0;
1690 }
1691
1692 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1693                                          struct radeon_cs_packet *pkt,
1694                                          struct radeon_bo *robj)
1695 {
1696         unsigned idx;
1697         u32 value;
1698         idx = pkt->idx + 1;
1699         value = radeon_get_ib_value(p, idx + 2);
1700         if ((value + 1) > radeon_bo_size(robj)) {
1701                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1702                           "(need %u have %lu) !\n",
1703                           value + 1,
1704                           radeon_bo_size(robj));
1705                 return -EINVAL;
1706         }
1707         return 0;
1708 }
1709
1710 static int r100_packet3_check(struct radeon_cs_parser *p,
1711                               struct radeon_cs_packet *pkt)
1712 {
1713         struct radeon_cs_reloc *reloc;
1714         struct r100_cs_track *track;
1715         unsigned idx;
1716         volatile uint32_t *ib;
1717         int r;
1718
1719         ib = p->ib->ptr;
1720         idx = pkt->idx + 1;
1721         track = (struct r100_cs_track *)p->track;
1722         switch (pkt->opcode) {
1723         case PACKET3_3D_LOAD_VBPNTR:
1724                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1725                 if (r)
1726                         return r;
1727                 break;
1728         case PACKET3_INDX_BUFFER:
1729                 r = r100_cs_packet_next_reloc(p, &reloc);
1730                 if (r) {
1731                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1732                         r100_cs_dump_packet(p, pkt);
1733                         return r;
1734                 }
1735                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1736                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1737                 if (r) {
1738                         return r;
1739                 }
1740                 break;
1741         case 0x23:
1742                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1743                 r = r100_cs_packet_next_reloc(p, &reloc);
1744                 if (r) {
1745                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1746                         r100_cs_dump_packet(p, pkt);
1747                         return r;
1748                 }
1749                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1750                 track->num_arrays = 1;
1751                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1752
1753                 track->arrays[0].robj = reloc->robj;
1754                 track->arrays[0].esize = track->vtx_size;
1755
1756                 track->max_indx = radeon_get_ib_value(p, idx+1);
1757
1758                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1759                 track->immd_dwords = pkt->count - 1;
1760                 r = r100_cs_track_check(p->rdev, track);
1761                 if (r)
1762                         return r;
1763                 break;
1764         case PACKET3_3D_DRAW_IMMD:
1765                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1766                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1767                         return -EINVAL;
1768                 }
1769                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1770                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1771                 track->immd_dwords = pkt->count - 1;
1772                 r = r100_cs_track_check(p->rdev, track);
1773                 if (r)
1774                         return r;
1775                 break;
1776                 /* triggers drawing using in-packet vertex data */
1777         case PACKET3_3D_DRAW_IMMD_2:
1778                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1779                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1780                         return -EINVAL;
1781                 }
1782                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1783                 track->immd_dwords = pkt->count;
1784                 r = r100_cs_track_check(p->rdev, track);
1785                 if (r)
1786                         return r;
1787                 break;
1788                 /* triggers drawing using in-packet vertex data */
1789         case PACKET3_3D_DRAW_VBUF_2:
1790                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1791                 r = r100_cs_track_check(p->rdev, track);
1792                 if (r)
1793                         return r;
1794                 break;
1795                 /* triggers drawing of vertex buffers setup elsewhere */
1796         case PACKET3_3D_DRAW_INDX_2:
1797                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1798                 r = r100_cs_track_check(p->rdev, track);
1799                 if (r)
1800                         return r;
1801                 break;
1802                 /* triggers drawing using indices to vertex buffer */
1803         case PACKET3_3D_DRAW_VBUF:
1804                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1805                 r = r100_cs_track_check(p->rdev, track);
1806                 if (r)
1807                         return r;
1808                 break;
1809                 /* triggers drawing of vertex buffers setup elsewhere */
1810         case PACKET3_3D_DRAW_INDX:
1811                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1812                 r = r100_cs_track_check(p->rdev, track);
1813                 if (r)
1814                         return r;
1815                 break;
1816                 /* triggers drawing using indices to vertex buffer */
1817         case PACKET3_3D_CLEAR_HIZ:
1818         case PACKET3_3D_CLEAR_ZMASK:
1819                 if (p->rdev->hyperz_filp != p->filp)
1820                         return -EINVAL;
1821                 break;
1822         case PACKET3_NOP:
1823                 break;
1824         default:
1825                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1826                 return -EINVAL;
1827         }
1828         return 0;
1829 }
1830
1831 int r100_cs_parse(struct radeon_cs_parser *p)
1832 {
1833         struct radeon_cs_packet pkt;
1834         struct r100_cs_track *track;
1835         int r;
1836
1837         track = kzalloc(sizeof(*track), GFP_KERNEL);
1838         r100_cs_track_clear(p->rdev, track);
1839         p->track = track;
1840         do {
1841                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1842                 if (r) {
1843                         return r;
1844                 }
1845                 p->idx += pkt.count + 2;
1846                 switch (pkt.type) {
1847                         case PACKET_TYPE0:
1848                                 if (p->rdev->family >= CHIP_R200)
1849                                         r = r100_cs_parse_packet0(p, &pkt,
1850                                                                   p->rdev->config.r100.reg_safe_bm,
1851                                                                   p->rdev->config.r100.reg_safe_bm_size,
1852                                                                   &r200_packet0_check);
1853                                 else
1854                                         r = r100_cs_parse_packet0(p, &pkt,
1855                                                                   p->rdev->config.r100.reg_safe_bm,
1856                                                                   p->rdev->config.r100.reg_safe_bm_size,
1857                                                                   &r100_packet0_check);
1858                                 break;
1859                         case PACKET_TYPE2:
1860                                 break;
1861                         case PACKET_TYPE3:
1862                                 r = r100_packet3_check(p, &pkt);
1863                                 break;
1864                         default:
1865                                 DRM_ERROR("Unknown packet type %d !\n",
1866                                           pkt.type);
1867                                 return -EINVAL;
1868                 }
1869                 if (r) {
1870                         return r;
1871                 }
1872         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1873         return 0;
1874 }
1875
1876
1877 /*
1878  * Global GPU functions
1879  */
1880 void r100_errata(struct radeon_device *rdev)
1881 {
1882         rdev->pll_errata = 0;
1883
1884         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1885                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1886         }
1887
1888         if (rdev->family == CHIP_RV100 ||
1889             rdev->family == CHIP_RS100 ||
1890             rdev->family == CHIP_RS200) {
1891                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1892         }
1893 }
1894
1895 /* Wait for vertical sync on primary CRTC */
1896 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1897 {
1898         uint32_t crtc_gen_cntl, tmp;
1899         int i;
1900
1901         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1902         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1903             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1904                 return;
1905         }
1906         /* Clear the CRTC_VBLANK_SAVE bit */
1907         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1908         for (i = 0; i < rdev->usec_timeout; i++) {
1909                 tmp = RREG32(RADEON_CRTC_STATUS);
1910                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1911                         return;
1912                 }
1913                 DRM_UDELAY(1);
1914         }
1915 }
1916
1917 /* Wait for vertical sync on secondary CRTC */
1918 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1919 {
1920         uint32_t crtc2_gen_cntl, tmp;
1921         int i;
1922
1923         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1924         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1925             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1926                 return;
1927
1928         /* Clear the CRTC_VBLANK_SAVE bit */
1929         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1930         for (i = 0; i < rdev->usec_timeout; i++) {
1931                 tmp = RREG32(RADEON_CRTC2_STATUS);
1932                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1933                         return;
1934                 }
1935                 DRM_UDELAY(1);
1936         }
1937 }
1938
1939 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1940 {
1941         unsigned i;
1942         uint32_t tmp;
1943
1944         for (i = 0; i < rdev->usec_timeout; i++) {
1945                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1946                 if (tmp >= n) {
1947                         return 0;
1948                 }
1949                 DRM_UDELAY(1);
1950         }
1951         return -1;
1952 }
1953
1954 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1955 {
1956         unsigned i;
1957         uint32_t tmp;
1958
1959         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1960                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1961                        " Bad things might happen.\n");
1962         }
1963         for (i = 0; i < rdev->usec_timeout; i++) {
1964                 tmp = RREG32(RADEON_RBBM_STATUS);
1965                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1966                         return 0;
1967                 }
1968                 DRM_UDELAY(1);
1969         }
1970         return -1;
1971 }
1972
1973 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1974 {
1975         unsigned i;
1976         uint32_t tmp;
1977
1978         for (i = 0; i < rdev->usec_timeout; i++) {
1979                 /* read MC_STATUS */
1980                 tmp = RREG32(RADEON_MC_STATUS);
1981                 if (tmp & RADEON_MC_IDLE) {
1982                         return 0;
1983                 }
1984                 DRM_UDELAY(1);
1985         }
1986         return -1;
1987 }
1988
1989 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1990 {
1991         lockup->last_cp_rptr = cp->rptr;
1992         lockup->last_jiffies = jiffies;
1993 }
1994
1995 /**
1996  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1997  * @rdev:       radeon device structure
1998  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
1999  * @cp:         radeon_cp structure holding CP information
2000  *
2001  * We don't need to initialize the lockup tracking information as we will either
2002  * have CP rptr to a different value of jiffies wrap around which will force
2003  * initialization of the lockup tracking informations.
2004  *
2005  * A possible false positivie is if we get call after while and last_cp_rptr ==
2006  * the current CP rptr, even if it's unlikely it might happen. To avoid this
2007  * if the elapsed time since last call is bigger than 2 second than we return
2008  * false and update the tracking information. Due to this the caller must call
2009  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2010  * the fencing code should be cautious about that.
2011  *
2012  * Caller should write to the ring to force CP to do something so we don't get
2013  * false positive when CP is just gived nothing to do.
2014  *
2015  **/
2016 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2017 {
2018         unsigned long cjiffies, elapsed;
2019
2020         cjiffies = jiffies;
2021         if (!time_after(cjiffies, lockup->last_jiffies)) {
2022                 /* likely a wrap around */
2023                 lockup->last_cp_rptr = cp->rptr;
2024                 lockup->last_jiffies = jiffies;
2025                 return false;
2026         }
2027         if (cp->rptr != lockup->last_cp_rptr) {
2028                 /* CP is still working no lockup */
2029                 lockup->last_cp_rptr = cp->rptr;
2030                 lockup->last_jiffies = jiffies;
2031                 return false;
2032         }
2033         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2034         if (elapsed >= 10000) {
2035                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2036                 return true;
2037         }
2038         /* give a chance to the GPU ... */
2039         return false;
2040 }
2041
2042 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2043 {
2044         u32 rbbm_status;
2045         int r;
2046
2047         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2048         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2049                 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2050                 return false;
2051         }
2052         /* force CP activities */
2053         r = radeon_ring_lock(rdev, 2);
2054         if (!r) {
2055                 /* PACKET2 NOP */
2056                 radeon_ring_write(rdev, 0x80000000);
2057                 radeon_ring_write(rdev, 0x80000000);
2058                 radeon_ring_unlock_commit(rdev);
2059         }
2060         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2061         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2062 }
2063
2064 void r100_bm_disable(struct radeon_device *rdev)
2065 {
2066         u32 tmp;
2067
2068         /* disable bus mastering */
2069         tmp = RREG32(R_000030_BUS_CNTL);
2070         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2071         mdelay(1);
2072         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2073         mdelay(1);
2074         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2075         tmp = RREG32(RADEON_BUS_CNTL);
2076         mdelay(1);
2077         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2078         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2079         mdelay(1);
2080 }
2081
2082 int r100_asic_reset(struct radeon_device *rdev)
2083 {
2084         struct r100_mc_save save;
2085         u32 status, tmp;
2086         int ret = 0;
2087
2088         status = RREG32(R_000E40_RBBM_STATUS);
2089         if (!G_000E40_GUI_ACTIVE(status)) {
2090                 return 0;
2091         }
2092         r100_mc_stop(rdev, &save);
2093         status = RREG32(R_000E40_RBBM_STATUS);
2094         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2095         /* stop CP */
2096         WREG32(RADEON_CP_CSQ_CNTL, 0);
2097         tmp = RREG32(RADEON_CP_RB_CNTL);
2098         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2099         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2100         WREG32(RADEON_CP_RB_WPTR, 0);
2101         WREG32(RADEON_CP_RB_CNTL, tmp);
2102         /* save PCI state */
2103         pci_save_state(rdev->pdev);
2104         /* disable bus mastering */
2105         r100_bm_disable(rdev);
2106         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2107                                         S_0000F0_SOFT_RESET_RE(1) |
2108                                         S_0000F0_SOFT_RESET_PP(1) |
2109                                         S_0000F0_SOFT_RESET_RB(1));
2110         RREG32(R_0000F0_RBBM_SOFT_RESET);
2111         mdelay(500);
2112         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2113         mdelay(1);
2114         status = RREG32(R_000E40_RBBM_STATUS);
2115         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2116         /* reset CP */
2117         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2118         RREG32(R_0000F0_RBBM_SOFT_RESET);
2119         mdelay(500);
2120         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2121         mdelay(1);
2122         status = RREG32(R_000E40_RBBM_STATUS);
2123         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2124         /* restore PCI & busmastering */
2125         pci_restore_state(rdev->pdev);
2126         r100_enable_bm(rdev);
2127         /* Check if GPU is idle */
2128         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2129                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2130                 dev_err(rdev->dev, "failed to reset GPU\n");
2131                 rdev->gpu_lockup = true;
2132                 ret = -1;
2133         } else
2134                 dev_info(rdev->dev, "GPU reset succeed\n");
2135         r100_mc_resume(rdev, &save);
2136         return ret;
2137 }
2138
2139 void r100_set_common_regs(struct radeon_device *rdev)
2140 {
2141         struct drm_device *dev = rdev->ddev;
2142         bool force_dac2 = false;
2143         u32 tmp;
2144
2145         /* set these so they don't interfere with anything */
2146         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2147         WREG32(RADEON_SUBPIC_CNTL, 0);
2148         WREG32(RADEON_VIPH_CONTROL, 0);
2149         WREG32(RADEON_I2C_CNTL_1, 0);
2150         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2151         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2152         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2153
2154         /* always set up dac2 on rn50 and some rv100 as lots
2155          * of servers seem to wire it up to a VGA port but
2156          * don't report it in the bios connector
2157          * table.
2158          */
2159         switch (dev->pdev->device) {
2160                 /* RN50 */
2161         case 0x515e:
2162         case 0x5969:
2163                 force_dac2 = true;
2164                 break;
2165                 /* RV100*/
2166         case 0x5159:
2167         case 0x515a:
2168                 /* DELL triple head servers */
2169                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2170                     ((dev->pdev->subsystem_device == 0x016c) ||
2171                      (dev->pdev->subsystem_device == 0x016d) ||
2172                      (dev->pdev->subsystem_device == 0x016e) ||
2173                      (dev->pdev->subsystem_device == 0x016f) ||
2174                      (dev->pdev->subsystem_device == 0x0170) ||
2175                      (dev->pdev->subsystem_device == 0x017d) ||
2176                      (dev->pdev->subsystem_device == 0x017e) ||
2177                      (dev->pdev->subsystem_device == 0x0183) ||
2178                      (dev->pdev->subsystem_device == 0x018a) ||
2179                      (dev->pdev->subsystem_device == 0x019a)))
2180                         force_dac2 = true;
2181                 break;
2182         }
2183
2184         if (force_dac2) {
2185                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2186                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2187                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2188
2189                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2190                    enable it, even it's detected.
2191                 */
2192
2193                 /* force it to crtc0 */
2194                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2195                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2196                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2197
2198                 /* set up the TV DAC */
2199                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2200                                  RADEON_TV_DAC_STD_MASK |
2201                                  RADEON_TV_DAC_RDACPD |
2202                                  RADEON_TV_DAC_GDACPD |
2203                                  RADEON_TV_DAC_BDACPD |
2204                                  RADEON_TV_DAC_BGADJ_MASK |
2205                                  RADEON_TV_DAC_DACADJ_MASK);
2206                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2207                                 RADEON_TV_DAC_NHOLD |
2208                                 RADEON_TV_DAC_STD_PS2 |
2209                                 (0x58 << 16));
2210
2211                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2212                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2213                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2214         }
2215
2216         /* switch PM block to ACPI mode */
2217         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2218         tmp &= ~RADEON_PM_MODE_SEL;
2219         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2220
2221 }
2222
2223 /*
2224  * VRAM info
2225  */
2226 static void r100_vram_get_type(struct radeon_device *rdev)
2227 {
2228         uint32_t tmp;
2229
2230         rdev->mc.vram_is_ddr = false;
2231         if (rdev->flags & RADEON_IS_IGP)
2232                 rdev->mc.vram_is_ddr = true;
2233         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2234                 rdev->mc.vram_is_ddr = true;
2235         if ((rdev->family == CHIP_RV100) ||
2236             (rdev->family == CHIP_RS100) ||
2237             (rdev->family == CHIP_RS200)) {
2238                 tmp = RREG32(RADEON_MEM_CNTL);
2239                 if (tmp & RV100_HALF_MODE) {
2240                         rdev->mc.vram_width = 32;
2241                 } else {
2242                         rdev->mc.vram_width = 64;
2243                 }
2244                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2245                         rdev->mc.vram_width /= 4;
2246                         rdev->mc.vram_is_ddr = true;
2247                 }
2248         } else if (rdev->family <= CHIP_RV280) {
2249                 tmp = RREG32(RADEON_MEM_CNTL);
2250                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2251                         rdev->mc.vram_width = 128;
2252                 } else {
2253                         rdev->mc.vram_width = 64;
2254                 }
2255         } else {
2256                 /* newer IGPs */
2257                 rdev->mc.vram_width = 128;
2258         }
2259 }
2260
2261 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2262 {
2263         u32 aper_size;
2264         u8 byte;
2265
2266         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2267
2268         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2269          * that is has the 2nd generation multifunction PCI interface
2270          */
2271         if (rdev->family == CHIP_RV280 ||
2272             rdev->family >= CHIP_RV350) {
2273                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2274                        ~RADEON_HDP_APER_CNTL);
2275                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2276                 return aper_size * 2;
2277         }
2278
2279         /* Older cards have all sorts of funny issues to deal with. First
2280          * check if it's a multifunction card by reading the PCI config
2281          * header type... Limit those to one aperture size
2282          */
2283         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2284         if (byte & 0x80) {
2285                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2286                 DRM_INFO("Limiting VRAM to one aperture\n");
2287                 return aper_size;
2288         }
2289
2290         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2291          * have set it up. We don't write this as it's broken on some ASICs but
2292          * we expect the BIOS to have done the right thing (might be too optimistic...)
2293          */
2294         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2295                 return aper_size * 2;
2296         return aper_size;
2297 }
2298
2299 void r100_vram_init_sizes(struct radeon_device *rdev)
2300 {
2301         u64 config_aper_size;
2302
2303         /* work out accessible VRAM */
2304         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2305         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2306         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2307         /* FIXME we don't use the second aperture yet when we could use it */
2308         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2309                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2310         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2311         if (rdev->flags & RADEON_IS_IGP) {
2312                 uint32_t tom;
2313                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2314                 tom = RREG32(RADEON_NB_TOM);
2315                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2316                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2317                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2318         } else {
2319                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2320                 /* Some production boards of m6 will report 0
2321                  * if it's 8 MB
2322                  */
2323                 if (rdev->mc.real_vram_size == 0) {
2324                         rdev->mc.real_vram_size = 8192 * 1024;
2325                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2326                 }
2327                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2328                  * Novell bug 204882 + along with lots of ubuntu ones
2329                  */
2330                 if (rdev->mc.aper_size > config_aper_size)
2331                         config_aper_size = rdev->mc.aper_size;
2332
2333                 if (config_aper_size > rdev->mc.real_vram_size)
2334                         rdev->mc.mc_vram_size = config_aper_size;
2335                 else
2336                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2337         }
2338 }
2339
2340 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2341 {
2342         uint32_t temp;
2343
2344         temp = RREG32(RADEON_CONFIG_CNTL);
2345         if (state == false) {
2346                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2347                 temp |= RADEON_CFG_VGA_IO_DIS;
2348         } else {
2349                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2350         }
2351         WREG32(RADEON_CONFIG_CNTL, temp);
2352 }
2353
2354 void r100_mc_init(struct radeon_device *rdev)
2355 {
2356         u64 base;
2357
2358         r100_vram_get_type(rdev);
2359         r100_vram_init_sizes(rdev);
2360         base = rdev->mc.aper_base;
2361         if (rdev->flags & RADEON_IS_IGP)
2362                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2363         radeon_vram_location(rdev, &rdev->mc, base);
2364         rdev->mc.gtt_base_align = 0;
2365         if (!(rdev->flags & RADEON_IS_AGP))
2366                 radeon_gtt_location(rdev, &rdev->mc);
2367         radeon_update_bandwidth_info(rdev);
2368 }
2369
2370
2371 /*
2372  * Indirect registers accessor
2373  */
2374 void r100_pll_errata_after_index(struct radeon_device *rdev)
2375 {
2376         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2377                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2378                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2379         }
2380 }
2381
2382 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2383 {
2384         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2385          * or the chip could hang on a subsequent access
2386          */
2387         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2388                 udelay(5000);
2389         }
2390
2391         /* This function is required to workaround a hardware bug in some (all?)
2392          * revisions of the R300.  This workaround should be called after every
2393          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2394          * may not be correct.
2395          */
2396         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2397                 uint32_t save, tmp;
2398
2399                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2400                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2401                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2402                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2403                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2404         }
2405 }
2406
2407 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2408 {
2409         uint32_t data;
2410
2411         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2412         r100_pll_errata_after_index(rdev);
2413         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2414         r100_pll_errata_after_data(rdev);
2415         return data;
2416 }
2417
2418 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2419 {
2420         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2421         r100_pll_errata_after_index(rdev);
2422         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2423         r100_pll_errata_after_data(rdev);
2424 }
2425
2426 void r100_set_safe_registers(struct radeon_device *rdev)
2427 {
2428         if (ASIC_IS_RN50(rdev)) {
2429                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2430                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2431         } else if (rdev->family < CHIP_R200) {
2432                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2433                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2434         } else {
2435                 r200_set_safe_registers(rdev);
2436         }
2437 }
2438
2439 /*
2440  * Debugfs info
2441  */
2442 #if defined(CONFIG_DEBUG_FS)
2443 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2444 {
2445         struct drm_info_node *node = (struct drm_info_node *) m->private;
2446         struct drm_device *dev = node->minor->dev;
2447         struct radeon_device *rdev = dev->dev_private;
2448         uint32_t reg, value;
2449         unsigned i;
2450
2451         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2452         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2453         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2454         for (i = 0; i < 64; i++) {
2455                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2456                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2457                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2458                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2459                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2460         }
2461         return 0;
2462 }
2463
2464 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2465 {
2466         struct drm_info_node *node = (struct drm_info_node *) m->private;
2467         struct drm_device *dev = node->minor->dev;
2468         struct radeon_device *rdev = dev->dev_private;
2469         uint32_t rdp, wdp;
2470         unsigned count, i, j;
2471
2472         radeon_ring_free_size(rdev);
2473         rdp = RREG32(RADEON_CP_RB_RPTR);
2474         wdp = RREG32(RADEON_CP_RB_WPTR);
2475         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2476         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2477         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2478         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2479         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2480         seq_printf(m, "%u dwords in ring\n", count);
2481         for (j = 0; j <= count; j++) {
2482                 i = (rdp + j) & rdev->cp.ptr_mask;
2483                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2484         }
2485         return 0;
2486 }
2487
2488
2489 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2490 {
2491         struct drm_info_node *node = (struct drm_info_node *) m->private;
2492         struct drm_device *dev = node->minor->dev;
2493         struct radeon_device *rdev = dev->dev_private;
2494         uint32_t csq_stat, csq2_stat, tmp;
2495         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2496         unsigned i;
2497
2498         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2499         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2500         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2501         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2502         r_rptr = (csq_stat >> 0) & 0x3ff;
2503         r_wptr = (csq_stat >> 10) & 0x3ff;
2504         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2505         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2506         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2507         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2508         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2509         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2510         seq_printf(m, "Ring rptr %u\n", r_rptr);
2511         seq_printf(m, "Ring wptr %u\n", r_wptr);
2512         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2513         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2514         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2515         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2516         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2517          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2518         seq_printf(m, "Ring fifo:\n");
2519         for (i = 0; i < 256; i++) {
2520                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2521                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2522                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2523         }
2524         seq_printf(m, "Indirect1 fifo:\n");
2525         for (i = 256; i <= 512; i++) {
2526                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2527                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2528                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2529         }
2530         seq_printf(m, "Indirect2 fifo:\n");
2531         for (i = 640; i < ib1_wptr; i++) {
2532                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2533                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2534                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2535         }
2536         return 0;
2537 }
2538
2539 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2540 {
2541         struct drm_info_node *node = (struct drm_info_node *) m->private;
2542         struct drm_device *dev = node->minor->dev;
2543         struct radeon_device *rdev = dev->dev_private;
2544         uint32_t tmp;
2545
2546         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2547         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2548         tmp = RREG32(RADEON_MC_FB_LOCATION);
2549         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2550         tmp = RREG32(RADEON_BUS_CNTL);
2551         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2552         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2553         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2554         tmp = RREG32(RADEON_AGP_BASE);
2555         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2556         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2557         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2558         tmp = RREG32(0x01D0);
2559         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2560         tmp = RREG32(RADEON_AIC_LO_ADDR);
2561         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2562         tmp = RREG32(RADEON_AIC_HI_ADDR);
2563         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2564         tmp = RREG32(0x01E4);
2565         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2566         return 0;
2567 }
2568
2569 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2570         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2571 };
2572
2573 static struct drm_info_list r100_debugfs_cp_list[] = {
2574         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2575         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2576 };
2577
2578 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2579         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2580 };
2581 #endif
2582
2583 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2584 {
2585 #if defined(CONFIG_DEBUG_FS)
2586         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2587 #else
2588         return 0;
2589 #endif
2590 }
2591
2592 int r100_debugfs_cp_init(struct radeon_device *rdev)
2593 {
2594 #if defined(CONFIG_DEBUG_FS)
2595         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2596 #else
2597         return 0;
2598 #endif
2599 }
2600
2601 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2602 {
2603 #if defined(CONFIG_DEBUG_FS)
2604         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2605 #else
2606         return 0;
2607 #endif
2608 }
2609
2610 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2611                          uint32_t tiling_flags, uint32_t pitch,
2612                          uint32_t offset, uint32_t obj_size)
2613 {
2614         int surf_index = reg * 16;
2615         int flags = 0;
2616
2617         if (rdev->family <= CHIP_RS200) {
2618                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2619                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2620                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2621                 if (tiling_flags & RADEON_TILING_MACRO)
2622                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2623         } else if (rdev->family <= CHIP_RV280) {
2624                 if (tiling_flags & (RADEON_TILING_MACRO))
2625                         flags |= R200_SURF_TILE_COLOR_MACRO;
2626                 if (tiling_flags & RADEON_TILING_MICRO)
2627                         flags |= R200_SURF_TILE_COLOR_MICRO;
2628         } else {
2629                 if (tiling_flags & RADEON_TILING_MACRO)
2630                         flags |= R300_SURF_TILE_MACRO;
2631                 if (tiling_flags & RADEON_TILING_MICRO)
2632                         flags |= R300_SURF_TILE_MICRO;
2633         }
2634
2635         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2636                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2637         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2638                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2639
2640         /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2641         if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2642                 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2643                         if (ASIC_IS_RN50(rdev))
2644                                 pitch /= 16;
2645         }
2646
2647         /* r100/r200 divide by 16 */
2648         if (rdev->family < CHIP_R300)
2649                 flags |= pitch / 16;
2650         else
2651                 flags |= pitch / 8;
2652
2653
2654         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2655         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2656         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2657         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2658         return 0;
2659 }
2660
2661 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2662 {
2663         int surf_index = reg * 16;
2664         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2665 }
2666
2667 void r100_bandwidth_update(struct radeon_device *rdev)
2668 {
2669         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2670         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2671         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2672         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2673         fixed20_12 memtcas_ff[8] = {
2674                 dfixed_init(1),
2675                 dfixed_init(2),
2676                 dfixed_init(3),
2677                 dfixed_init(0),
2678                 dfixed_init_half(1),
2679                 dfixed_init_half(2),
2680                 dfixed_init(0),
2681         };
2682         fixed20_12 memtcas_rs480_ff[8] = {
2683                 dfixed_init(0),
2684                 dfixed_init(1),
2685                 dfixed_init(2),
2686                 dfixed_init(3),
2687                 dfixed_init(0),
2688                 dfixed_init_half(1),
2689                 dfixed_init_half(2),
2690                 dfixed_init_half(3),
2691         };
2692         fixed20_12 memtcas2_ff[8] = {
2693                 dfixed_init(0),
2694                 dfixed_init(1),
2695                 dfixed_init(2),
2696                 dfixed_init(3),
2697                 dfixed_init(4),
2698                 dfixed_init(5),
2699                 dfixed_init(6),
2700                 dfixed_init(7),
2701         };
2702         fixed20_12 memtrbs[8] = {
2703                 dfixed_init(1),
2704                 dfixed_init_half(1),
2705                 dfixed_init(2),
2706                 dfixed_init_half(2),
2707                 dfixed_init(3),
2708                 dfixed_init_half(3),
2709                 dfixed_init(4),
2710                 dfixed_init_half(4)
2711         };
2712         fixed20_12 memtrbs_r4xx[8] = {
2713                 dfixed_init(4),
2714                 dfixed_init(5),
2715                 dfixed_init(6),
2716                 dfixed_init(7),
2717                 dfixed_init(8),
2718                 dfixed_init(9),
2719                 dfixed_init(10),
2720                 dfixed_init(11)
2721         };
2722         fixed20_12 min_mem_eff;
2723         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2724         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2725         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2726                 disp_drain_rate2, read_return_rate;
2727         fixed20_12 time_disp1_drop_priority;
2728         int c;
2729         int cur_size = 16;       /* in octawords */
2730         int critical_point = 0, critical_point2;
2731 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2732         int stop_req, max_stop_req;
2733         struct drm_display_mode *mode1 = NULL;
2734         struct drm_display_mode *mode2 = NULL;
2735         uint32_t pixel_bytes1 = 0;
2736         uint32_t pixel_bytes2 = 0;
2737
2738         radeon_update_display_priority(rdev);
2739
2740         if (rdev->mode_info.crtcs[0]->base.enabled) {
2741                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2742                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2743         }
2744         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2745                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2746                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2747                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2748                 }
2749         }
2750
2751         min_mem_eff.full = dfixed_const_8(0);
2752         /* get modes */
2753         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2754                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2755                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2756                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2757                 /* check crtc enables */
2758                 if (mode2)
2759                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2760                 if (mode1)
2761                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2762                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2763         }
2764
2765         /*
2766          * determine is there is enough bw for current mode
2767          */
2768         sclk_ff = rdev->pm.sclk;
2769         mclk_ff = rdev->pm.mclk;
2770
2771         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2772         temp_ff.full = dfixed_const(temp);
2773         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2774
2775         pix_clk.full = 0;
2776         pix_clk2.full = 0;
2777         peak_disp_bw.full = 0;
2778         if (mode1) {
2779                 temp_ff.full = dfixed_const(1000);
2780                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2781                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2782                 temp_ff.full = dfixed_const(pixel_bytes1);
2783                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2784         }
2785         if (mode2) {
2786                 temp_ff.full = dfixed_const(1000);
2787                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2788                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2789                 temp_ff.full = dfixed_const(pixel_bytes2);
2790                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2791         }
2792
2793         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2794         if (peak_disp_bw.full >= mem_bw.full) {
2795                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2796                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2797         }
2798
2799         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2800         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2801         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2802                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2803                 mem_trp  = ((temp & 0x3)) + 1;
2804                 mem_tras = ((temp & 0x70) >> 4) + 1;
2805         } else if (rdev->family == CHIP_R300 ||
2806                    rdev->family == CHIP_R350) { /* r300, r350 */
2807                 mem_trcd = (temp & 0x7) + 1;
2808                 mem_trp = ((temp >> 8) & 0x7) + 1;
2809                 mem_tras = ((temp >> 11) & 0xf) + 4;
2810         } else if (rdev->family == CHIP_RV350 ||
2811                    rdev->family <= CHIP_RV380) {
2812                 /* rv3x0 */
2813                 mem_trcd = (temp & 0x7) + 3;
2814                 mem_trp = ((temp >> 8) & 0x7) + 3;
2815                 mem_tras = ((temp >> 11) & 0xf) + 6;
2816         } else if (rdev->family == CHIP_R420 ||
2817                    rdev->family == CHIP_R423 ||
2818                    rdev->family == CHIP_RV410) {
2819                 /* r4xx */
2820                 mem_trcd = (temp & 0xf) + 3;
2821                 if (mem_trcd > 15)
2822                         mem_trcd = 15;
2823                 mem_trp = ((temp >> 8) & 0xf) + 3;
2824                 if (mem_trp > 15)
2825                         mem_trp = 15;
2826                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2827                 if (mem_tras > 31)
2828                         mem_tras = 31;
2829         } else { /* RV200, R200 */
2830                 mem_trcd = (temp & 0x7) + 1;
2831                 mem_trp = ((temp >> 8) & 0x7) + 1;
2832                 mem_tras = ((temp >> 12) & 0xf) + 4;
2833         }
2834         /* convert to FF */
2835         trcd_ff.full = dfixed_const(mem_trcd);
2836         trp_ff.full = dfixed_const(mem_trp);
2837         tras_ff.full = dfixed_const(mem_tras);
2838
2839         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2840         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2841         data = (temp & (7 << 20)) >> 20;
2842         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2843                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2844                         tcas_ff = memtcas_rs480_ff[data];
2845                 else
2846                         tcas_ff = memtcas_ff[data];
2847         } else
2848                 tcas_ff = memtcas2_ff[data];
2849
2850         if (rdev->family == CHIP_RS400 ||
2851             rdev->family == CHIP_RS480) {
2852                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2853                 data = (temp >> 23) & 0x7;
2854                 if (data < 5)
2855                         tcas_ff.full += dfixed_const(data);
2856         }
2857
2858         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2859                 /* on the R300, Tcas is included in Trbs.
2860                  */
2861                 temp = RREG32(RADEON_MEM_CNTL);
2862                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2863                 if (data == 1) {
2864                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2865                                 temp = RREG32(R300_MC_IND_INDEX);
2866                                 temp &= ~R300_MC_IND_ADDR_MASK;
2867                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2868                                 WREG32(R300_MC_IND_INDEX, temp);
2869                                 temp = RREG32(R300_MC_IND_DATA);
2870                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2871                         } else {
2872                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2873                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2874                         }
2875                 } else {
2876                         temp = RREG32(R300_MC_READ_CNTL_AB);
2877                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2878                 }
2879                 if (rdev->family == CHIP_RV410 ||
2880                     rdev->family == CHIP_R420 ||
2881                     rdev->family == CHIP_R423)
2882                         trbs_ff = memtrbs_r4xx[data];
2883                 else
2884                         trbs_ff = memtrbs[data];
2885                 tcas_ff.full += trbs_ff.full;
2886         }
2887
2888         sclk_eff_ff.full = sclk_ff.full;
2889
2890         if (rdev->flags & RADEON_IS_AGP) {
2891                 fixed20_12 agpmode_ff;
2892                 agpmode_ff.full = dfixed_const(radeon_agpmode);
2893                 temp_ff.full = dfixed_const_666(16);
2894                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2895         }
2896         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2897
2898         if (ASIC_IS_R300(rdev)) {
2899                 sclk_delay_ff.full = dfixed_const(250);
2900         } else {
2901                 if ((rdev->family == CHIP_RV100) ||
2902                     rdev->flags & RADEON_IS_IGP) {
2903                         if (rdev->mc.vram_is_ddr)
2904                                 sclk_delay_ff.full = dfixed_const(41);
2905                         else
2906                                 sclk_delay_ff.full = dfixed_const(33);
2907                 } else {
2908                         if (rdev->mc.vram_width == 128)
2909                                 sclk_delay_ff.full = dfixed_const(57);
2910                         else
2911                                 sclk_delay_ff.full = dfixed_const(41);
2912                 }
2913         }
2914
2915         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
2916
2917         if (rdev->mc.vram_is_ddr) {
2918                 if (rdev->mc.vram_width == 32) {
2919                         k1.full = dfixed_const(40);
2920                         c  = 3;
2921                 } else {
2922                         k1.full = dfixed_const(20);
2923                         c  = 1;
2924                 }
2925         } else {
2926                 k1.full = dfixed_const(40);
2927                 c  = 3;
2928         }
2929
2930         temp_ff.full = dfixed_const(2);
2931         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2932         temp_ff.full = dfixed_const(c);
2933         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2934         temp_ff.full = dfixed_const(4);
2935         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2936         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
2937         mc_latency_mclk.full += k1.full;
2938
2939         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2940         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
2941
2942         /*
2943           HW cursor time assuming worst case of full size colour cursor.
2944         */
2945         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2946         temp_ff.full += trcd_ff.full;
2947         if (temp_ff.full < tras_ff.full)
2948                 temp_ff.full = tras_ff.full;
2949         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
2950
2951         temp_ff.full = dfixed_const(cur_size);
2952         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
2953         /*
2954           Find the total latency for the display data.
2955         */
2956         disp_latency_overhead.full = dfixed_const(8);
2957         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
2958         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2959         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2960
2961         if (mc_latency_mclk.full > mc_latency_sclk.full)
2962                 disp_latency.full = mc_latency_mclk.full;
2963         else
2964                 disp_latency.full = mc_latency_sclk.full;
2965
2966         /* setup Max GRPH_STOP_REQ default value */
2967         if (ASIC_IS_RV100(rdev))
2968                 max_stop_req = 0x5c;
2969         else
2970                 max_stop_req = 0x7c;
2971
2972         if (mode1) {
2973                 /*  CRTC1
2974                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2975                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2976                 */
2977                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2978
2979                 if (stop_req > max_stop_req)
2980                         stop_req = max_stop_req;
2981
2982                 /*
2983                   Find the drain rate of the display buffer.
2984                 */
2985                 temp_ff.full = dfixed_const((16/pixel_bytes1));
2986                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
2987
2988                 /*
2989                   Find the critical point of the display buffer.
2990                 */
2991                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
2992                 crit_point_ff.full += dfixed_const_half(0);
2993
2994                 critical_point = dfixed_trunc(crit_point_ff);
2995
2996                 if (rdev->disp_priority == 2) {
2997                         critical_point = 0;
2998                 }
2999
3000                 /*
3001                   The critical point should never be above max_stop_req-4.  Setting
3002                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3003                 */
3004                 if (max_stop_req - critical_point < 4)
3005                         critical_point = 0;
3006
3007                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3008                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3009                         critical_point = 0x10;
3010                 }
3011
3012                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3013                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3014                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3015                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3016                 if ((rdev->family == CHIP_R350) &&
3017                     (stop_req > 0x15)) {
3018                         stop_req -= 0x10;
3019                 }
3020                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3021                 temp |= RADEON_GRPH_BUFFER_SIZE;
3022                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3023                           RADEON_GRPH_CRITICAL_AT_SOF |
3024                           RADEON_GRPH_STOP_CNTL);
3025                 /*
3026                   Write the result into the register.
3027                 */
3028                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3029                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3030
3031 #if 0
3032                 if ((rdev->family == CHIP_RS400) ||
3033                     (rdev->family == CHIP_RS480)) {
3034                         /* attempt to program RS400 disp regs correctly ??? */
3035                         temp = RREG32(RS400_DISP1_REG_CNTL);
3036                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3037                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3038                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3039                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3040                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3041                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3042                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3043                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3044                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3045                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3046                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3047                 }
3048 #endif
3049
3050                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3051                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3052                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3053         }
3054
3055         if (mode2) {
3056                 u32 grph2_cntl;
3057                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3058
3059                 if (stop_req > max_stop_req)
3060                         stop_req = max_stop_req;
3061
3062                 /*
3063                   Find the drain rate of the display buffer.
3064                 */
3065                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3066                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3067
3068                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3069                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3070                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3071                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3072                 if ((rdev->family == CHIP_R350) &&
3073                     (stop_req > 0x15)) {
3074                         stop_req -= 0x10;
3075                 }
3076                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3077                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3078                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3079                           RADEON_GRPH_CRITICAL_AT_SOF |
3080                           RADEON_GRPH_STOP_CNTL);
3081
3082                 if ((rdev->family == CHIP_RS100) ||
3083                     (rdev->family == CHIP_RS200))
3084                         critical_point2 = 0;
3085                 else {
3086                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3087                         temp_ff.full = dfixed_const(temp);
3088                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3089                         if (sclk_ff.full < temp_ff.full)
3090                                 temp_ff.full = sclk_ff.full;
3091
3092                         read_return_rate.full = temp_ff.full;
3093
3094                         if (mode1) {
3095                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3096                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3097                         } else {
3098                                 time_disp1_drop_priority.full = 0;
3099                         }
3100                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3101                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3102                         crit_point_ff.full += dfixed_const_half(0);
3103
3104                         critical_point2 = dfixed_trunc(crit_point_ff);
3105
3106                         if (rdev->disp_priority == 2) {
3107                                 critical_point2 = 0;
3108                         }
3109
3110                         if (max_stop_req - critical_point2 < 4)
3111                                 critical_point2 = 0;
3112
3113                 }
3114
3115                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3116                         /* some R300 cards have problem with this set to 0 */
3117                         critical_point2 = 0x10;
3118                 }
3119
3120                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3121                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3122
3123                 if ((rdev->family == CHIP_RS400) ||
3124                     (rdev->family == CHIP_RS480)) {
3125 #if 0
3126                         /* attempt to program RS400 disp2 regs correctly ??? */
3127                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3128                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3129                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3130                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3131                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3132                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3133                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3134                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3135                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3136                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3137                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3138                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3139 #endif
3140                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3141                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3142                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3143                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3144                 }
3145
3146                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3147                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3148         }
3149 }
3150
3151 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3152 {
3153         DRM_ERROR("pitch                      %d\n", t->pitch);
3154         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3155         DRM_ERROR("width                      %d\n", t->width);
3156         DRM_ERROR("width_11                   %d\n", t->width_11);
3157         DRM_ERROR("height                     %d\n", t->height);
3158         DRM_ERROR("height_11                  %d\n", t->height_11);
3159         DRM_ERROR("num levels                 %d\n", t->num_levels);
3160         DRM_ERROR("depth                      %d\n", t->txdepth);
3161         DRM_ERROR("bpp                        %d\n", t->cpp);
3162         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3163         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3164         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3165         DRM_ERROR("compress format            %d\n", t->compress_format);
3166 }
3167
3168 static int r100_track_compress_size(int compress_format, int w, int h)
3169 {
3170         int block_width, block_height, block_bytes;
3171         int wblocks, hblocks;
3172         int min_wblocks;
3173         int sz;
3174
3175         block_width = 4;
3176         block_height = 4;
3177
3178         switch (compress_format) {
3179         case R100_TRACK_COMP_DXT1:
3180                 block_bytes = 8;
3181                 min_wblocks = 4;
3182                 break;
3183         default:
3184         case R100_TRACK_COMP_DXT35:
3185                 block_bytes = 16;
3186                 min_wblocks = 2;
3187                 break;
3188         }
3189
3190         hblocks = (h + block_height - 1) / block_height;
3191         wblocks = (w + block_width - 1) / block_width;
3192         if (wblocks < min_wblocks)
3193                 wblocks = min_wblocks;
3194         sz = wblocks * hblocks * block_bytes;
3195         return sz;
3196 }
3197
3198 static int r100_cs_track_cube(struct radeon_device *rdev,
3199                               struct r100_cs_track *track, unsigned idx)
3200 {
3201         unsigned face, w, h;
3202         struct radeon_bo *cube_robj;
3203         unsigned long size;
3204         unsigned compress_format = track->textures[idx].compress_format;
3205
3206         for (face = 0; face < 5; face++) {
3207                 cube_robj = track->textures[idx].cube_info[face].robj;
3208                 w = track->textures[idx].cube_info[face].width;
3209                 h = track->textures[idx].cube_info[face].height;
3210
3211                 if (compress_format) {
3212                         size = r100_track_compress_size(compress_format, w, h);
3213                 } else
3214                         size = w * h;
3215                 size *= track->textures[idx].cpp;
3216
3217                 size += track->textures[idx].cube_info[face].offset;
3218
3219                 if (size > radeon_bo_size(cube_robj)) {
3220                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3221                                   size, radeon_bo_size(cube_robj));
3222                         r100_cs_track_texture_print(&track->textures[idx]);
3223                         return -1;
3224                 }
3225         }
3226         return 0;
3227 }
3228
3229 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3230                                        struct r100_cs_track *track)
3231 {
3232         struct radeon_bo *robj;
3233         unsigned long size;
3234         unsigned u, i, w, h, d;
3235         int ret;
3236
3237         for (u = 0; u < track->num_texture; u++) {
3238                 if (!track->textures[u].enabled)
3239                         continue;
3240                 if (track->textures[u].lookup_disable)
3241                         continue;
3242                 robj = track->textures[u].robj;
3243                 if (robj == NULL) {
3244                         DRM_ERROR("No texture bound to unit %u\n", u);
3245                         return -EINVAL;
3246                 }
3247                 size = 0;
3248                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3249                         if (track->textures[u].use_pitch) {
3250                                 if (rdev->family < CHIP_R300)
3251                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3252                                 else
3253                                         w = track->textures[u].pitch / (1 << i);
3254                         } else {
3255                                 w = track->textures[u].width;
3256                                 if (rdev->family >= CHIP_RV515)
3257                                         w |= track->textures[u].width_11;
3258                                 w = w / (1 << i);
3259                                 if (track->textures[u].roundup_w)
3260                                         w = roundup_pow_of_two(w);
3261                         }
3262                         h = track->textures[u].height;
3263                         if (rdev->family >= CHIP_RV515)
3264                                 h |= track->textures[u].height_11;
3265                         h = h / (1 << i);
3266                         if (track->textures[u].roundup_h)
3267                                 h = roundup_pow_of_two(h);
3268                         if (track->textures[u].tex_coord_type == 1) {
3269                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3270                                 if (!d)
3271                                         d = 1;
3272                         } else {
3273                                 d = 1;
3274                         }
3275                         if (track->textures[u].compress_format) {
3276
3277                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3278                                 /* compressed textures are block based */
3279                         } else
3280                                 size += w * h * d;
3281                 }
3282                 size *= track->textures[u].cpp;
3283
3284                 switch (track->textures[u].tex_coord_type) {
3285                 case 0:
3286                 case 1:
3287                         break;
3288                 case 2:
3289                         if (track->separate_cube) {
3290                                 ret = r100_cs_track_cube(rdev, track, u);
3291                                 if (ret)
3292                                         return ret;
3293                         } else
3294                                 size *= 6;
3295                         break;
3296                 default:
3297                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3298                                   "%u\n", track->textures[u].tex_coord_type, u);
3299                         return -EINVAL;
3300                 }
3301                 if (size > radeon_bo_size(robj)) {
3302                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3303                                   "%lu\n", u, size, radeon_bo_size(robj));
3304                         r100_cs_track_texture_print(&track->textures[u]);
3305                         return -EINVAL;
3306                 }
3307         }
3308         return 0;
3309 }
3310
3311 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3312 {
3313         unsigned i;
3314         unsigned long size;
3315         unsigned prim_walk;
3316         unsigned nverts;
3317         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3318
3319         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3320             !track->blend_read_enable)
3321                 num_cb = 0;
3322
3323         for (i = 0; i < num_cb; i++) {
3324                 if (track->cb[i].robj == NULL) {
3325                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3326                         return -EINVAL;
3327                 }
3328                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3329                 size += track->cb[i].offset;
3330                 if (size > radeon_bo_size(track->cb[i].robj)) {
3331                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3332                                   "(need %lu have %lu) !\n", i, size,
3333                                   radeon_bo_size(track->cb[i].robj));
3334                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3335                                   i, track->cb[i].pitch, track->cb[i].cpp,
3336                                   track->cb[i].offset, track->maxy);
3337                         return -EINVAL;
3338                 }
3339         }
3340         track->cb_dirty = false;
3341
3342         if (track->zb_dirty && track->z_enabled) {
3343                 if (track->zb.robj == NULL) {
3344                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3345                         return -EINVAL;
3346                 }
3347                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3348                 size += track->zb.offset;
3349                 if (size > radeon_bo_size(track->zb.robj)) {
3350                         DRM_ERROR("[drm] Buffer too small for z buffer "
3351                                   "(need %lu have %lu) !\n", size,
3352                                   radeon_bo_size(track->zb.robj));
3353                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3354                                   track->zb.pitch, track->zb.cpp,
3355                                   track->zb.offset, track->maxy);
3356                         return -EINVAL;
3357                 }
3358         }
3359         track->zb_dirty = false;
3360
3361         if (track->aa_dirty && track->aaresolve) {
3362                 if (track->aa.robj == NULL) {
3363                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3364                         return -EINVAL;
3365                 }
3366                 /* I believe the format comes from colorbuffer0. */
3367                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3368                 size += track->aa.offset;
3369                 if (size > radeon_bo_size(track->aa.robj)) {
3370                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3371                                   "(need %lu have %lu) !\n", i, size,
3372                                   radeon_bo_size(track->aa.robj));
3373                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3374                                   i, track->aa.pitch, track->cb[0].cpp,
3375                                   track->aa.offset, track->maxy);
3376                         return -EINVAL;
3377                 }
3378         }
3379         track->aa_dirty = false;
3380
3381         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3382         if (track->vap_vf_cntl & (1 << 14)) {
3383                 nverts = track->vap_alt_nverts;
3384         } else {
3385                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3386         }
3387         switch (prim_walk) {
3388         case 1:
3389                 for (i = 0; i < track->num_arrays; i++) {
3390                         size = track->arrays[i].esize * track->max_indx * 4;
3391                         if (track->arrays[i].robj == NULL) {
3392                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3393                                           "bound\n", prim_walk, i);
3394                                 return -EINVAL;
3395                         }
3396                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3397                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3398                                         "need %lu dwords have %lu dwords\n",
3399                                         prim_walk, i, size >> 2,
3400                                         radeon_bo_size(track->arrays[i].robj)
3401                                         >> 2);
3402                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3403                                 return -EINVAL;
3404                         }
3405                 }
3406                 break;
3407         case 2:
3408                 for (i = 0; i < track->num_arrays; i++) {
3409                         size = track->arrays[i].esize * (nverts - 1) * 4;
3410                         if (track->arrays[i].robj == NULL) {
3411                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3412                                           "bound\n", prim_walk, i);
3413                                 return -EINVAL;
3414                         }
3415                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3416                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3417                                         "need %lu dwords have %lu dwords\n",
3418                                         prim_walk, i, size >> 2,
3419                                         radeon_bo_size(track->arrays[i].robj)
3420                                         >> 2);
3421                                 return -EINVAL;
3422                         }
3423                 }
3424                 break;
3425         case 3:
3426                 size = track->vtx_size * nverts;
3427                 if (size != track->immd_dwords) {
3428                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3429                                   track->immd_dwords, size);
3430                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3431                                   nverts, track->vtx_size);
3432                         return -EINVAL;
3433                 }
3434                 break;
3435         default:
3436                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3437                           prim_walk);
3438                 return -EINVAL;
3439         }
3440
3441         if (track->tex_dirty) {
3442                 track->tex_dirty = false;
3443                 return r100_cs_track_texture_check(rdev, track);
3444         }
3445         return 0;
3446 }
3447
3448 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3449 {
3450         unsigned i, face;
3451
3452         track->cb_dirty = true;
3453         track->zb_dirty = true;
3454         track->tex_dirty = true;
3455         track->aa_dirty = true;
3456
3457         if (rdev->family < CHIP_R300) {
3458                 track->num_cb = 1;
3459                 if (rdev->family <= CHIP_RS200)
3460                         track->num_texture = 3;
3461                 else
3462                         track->num_texture = 6;
3463                 track->maxy = 2048;
3464                 track->separate_cube = 1;
3465         } else {
3466                 track->num_cb = 4;
3467                 track->num_texture = 16;
3468                 track->maxy = 4096;
3469                 track->separate_cube = 0;
3470                 track->aaresolve = false;
3471                 track->aa.robj = NULL;
3472         }
3473
3474         for (i = 0; i < track->num_cb; i++) {
3475                 track->cb[i].robj = NULL;
3476                 track->cb[i].pitch = 8192;
3477                 track->cb[i].cpp = 16;
3478                 track->cb[i].offset = 0;
3479         }
3480         track->z_enabled = true;
3481         track->zb.robj = NULL;
3482         track->zb.pitch = 8192;
3483         track->zb.cpp = 4;
3484         track->zb.offset = 0;
3485         track->vtx_size = 0x7F;
3486         track->immd_dwords = 0xFFFFFFFFUL;
3487         track->num_arrays = 11;
3488         track->max_indx = 0x00FFFFFFUL;
3489         for (i = 0; i < track->num_arrays; i++) {
3490                 track->arrays[i].robj = NULL;
3491                 track->arrays[i].esize = 0x7F;
3492         }
3493         for (i = 0; i < track->num_texture; i++) {
3494                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3495                 track->textures[i].pitch = 16536;
3496                 track->textures[i].width = 16536;
3497                 track->textures[i].height = 16536;
3498                 track->textures[i].width_11 = 1 << 11;
3499                 track->textures[i].height_11 = 1 << 11;
3500                 track->textures[i].num_levels = 12;
3501                 if (rdev->family <= CHIP_RS200) {
3502                         track->textures[i].tex_coord_type = 0;
3503                         track->textures[i].txdepth = 0;
3504                 } else {
3505                         track->textures[i].txdepth = 16;
3506                         track->textures[i].tex_coord_type = 1;
3507                 }
3508                 track->textures[i].cpp = 64;
3509                 track->textures[i].robj = NULL;
3510                 /* CS IB emission code makes sure texture unit are disabled */
3511                 track->textures[i].enabled = false;
3512                 track->textures[i].lookup_disable = false;
3513                 track->textures[i].roundup_w = true;
3514                 track->textures[i].roundup_h = true;
3515                 if (track->separate_cube)
3516                         for (face = 0; face < 5; face++) {
3517                                 track->textures[i].cube_info[face].robj = NULL;
3518                                 track->textures[i].cube_info[face].width = 16536;
3519                                 track->textures[i].cube_info[face].height = 16536;
3520                                 track->textures[i].cube_info[face].offset = 0;
3521                         }
3522         }
3523 }
3524
3525 int r100_ring_test(struct radeon_device *rdev)
3526 {
3527         uint32_t scratch;
3528         uint32_t tmp = 0;
3529         unsigned i;
3530         int r;
3531
3532         r = radeon_scratch_get(rdev, &scratch);
3533         if (r) {
3534                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3535                 return r;
3536         }
3537         WREG32(scratch, 0xCAFEDEAD);
3538         r = radeon_ring_lock(rdev, 2);
3539         if (r) {
3540                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3541                 radeon_scratch_free(rdev, scratch);
3542                 return r;
3543         }
3544         radeon_ring_write(rdev, PACKET0(scratch, 0));
3545         radeon_ring_write(rdev, 0xDEADBEEF);
3546         radeon_ring_unlock_commit(rdev);
3547         for (i = 0; i < rdev->usec_timeout; i++) {
3548                 tmp = RREG32(scratch);
3549                 if (tmp == 0xDEADBEEF) {
3550                         break;
3551                 }
3552                 DRM_UDELAY(1);
3553         }
3554         if (i < rdev->usec_timeout) {
3555                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3556         } else {
3557                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3558                           scratch, tmp);
3559                 r = -EINVAL;
3560         }
3561         radeon_scratch_free(rdev, scratch);
3562         return r;
3563 }
3564
3565 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3566 {
3567         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3568         radeon_ring_write(rdev, ib->gpu_addr);
3569         radeon_ring_write(rdev, ib->length_dw);
3570 }
3571
3572 int r100_ib_test(struct radeon_device *rdev)
3573 {
3574         struct radeon_ib *ib;
3575         uint32_t scratch;
3576         uint32_t tmp = 0;
3577         unsigned i;
3578         int r;
3579
3580         r = radeon_scratch_get(rdev, &scratch);
3581         if (r) {
3582                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3583                 return r;
3584         }
3585         WREG32(scratch, 0xCAFEDEAD);
3586         r = radeon_ib_get(rdev, &ib);
3587         if (r) {
3588                 return r;
3589         }
3590         ib->ptr[0] = PACKET0(scratch, 0);
3591         ib->ptr[1] = 0xDEADBEEF;
3592         ib->ptr[2] = PACKET2(0);
3593         ib->ptr[3] = PACKET2(0);
3594         ib->ptr[4] = PACKET2(0);
3595         ib->ptr[5] = PACKET2(0);
3596         ib->ptr[6] = PACKET2(0);
3597         ib->ptr[7] = PACKET2(0);
3598         ib->length_dw = 8;
3599         r = radeon_ib_schedule(rdev, ib);
3600         if (r) {
3601                 radeon_scratch_free(rdev, scratch);
3602                 radeon_ib_free(rdev, &ib);
3603                 return r;
3604         }
3605         r = radeon_fence_wait(ib->fence, false);
3606         if (r) {
3607                 return r;
3608         }
3609         for (i = 0; i < rdev->usec_timeout; i++) {
3610                 tmp = RREG32(scratch);
3611                 if (tmp == 0xDEADBEEF) {
3612                         break;
3613                 }
3614                 DRM_UDELAY(1);
3615         }
3616         if (i < rdev->usec_timeout) {
3617                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3618         } else {
3619                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3620                           scratch, tmp);
3621                 r = -EINVAL;
3622         }
3623         radeon_scratch_free(rdev, scratch);
3624         radeon_ib_free(rdev, &ib);
3625         return r;
3626 }
3627
3628 void r100_ib_fini(struct radeon_device *rdev)
3629 {
3630         radeon_ib_pool_fini(rdev);
3631 }
3632
3633 int r100_ib_init(struct radeon_device *rdev)
3634 {
3635         int r;
3636
3637         r = radeon_ib_pool_init(rdev);
3638         if (r) {
3639                 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
3640                 r100_ib_fini(rdev);
3641                 return r;
3642         }
3643         r = r100_ib_test(rdev);
3644         if (r) {
3645                 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3646                 r100_ib_fini(rdev);
3647                 return r;
3648         }
3649         return 0;
3650 }
3651
3652 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3653 {
3654         /* Shutdown CP we shouldn't need to do that but better be safe than
3655          * sorry
3656          */
3657         rdev->cp.ready = false;
3658         WREG32(R_000740_CP_CSQ_CNTL, 0);
3659
3660         /* Save few CRTC registers */
3661         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3662         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3663         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3664         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3665         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3666                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3667                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3668         }
3669
3670         /* Disable VGA aperture access */
3671         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3672         /* Disable cursor, overlay, crtc */
3673         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3674         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3675                                         S_000054_CRTC_DISPLAY_DIS(1));
3676         WREG32(R_000050_CRTC_GEN_CNTL,
3677                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3678                         S_000050_CRTC_DISP_REQ_EN_B(1));
3679         WREG32(R_000420_OV0_SCALE_CNTL,
3680                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3681         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3682         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3683                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3684                                                 S_000360_CUR2_LOCK(1));
3685                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3686                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3687                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3688                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3689                 WREG32(R_000360_CUR2_OFFSET,
3690                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3691         }
3692 }
3693
3694 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3695 {
3696         /* Update base address for crtc */
3697         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3698         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3699                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3700         }
3701         /* Restore CRTC registers */
3702         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3703         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3704         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3705         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3706                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3707         }
3708 }
3709
3710 void r100_vga_render_disable(struct radeon_device *rdev)
3711 {
3712         u32 tmp;
3713
3714         tmp = RREG8(R_0003C2_GENMO_WT);
3715         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3716 }
3717
3718 static void r100_debugfs(struct radeon_device *rdev)
3719 {
3720         int r;
3721
3722         r = r100_debugfs_mc_info_init(rdev);
3723         if (r)
3724                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3725 }
3726
3727 static void r100_mc_program(struct radeon_device *rdev)
3728 {
3729         struct r100_mc_save save;
3730
3731         /* Stops all mc clients */
3732         r100_mc_stop(rdev, &save);
3733         if (rdev->flags & RADEON_IS_AGP) {
3734                 WREG32(R_00014C_MC_AGP_LOCATION,
3735                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3736                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3737                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3738                 if (rdev->family > CHIP_RV200)
3739                         WREG32(R_00015C_AGP_BASE_2,
3740                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3741         } else {
3742                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3743                 WREG32(R_000170_AGP_BASE, 0);
3744                 if (rdev->family > CHIP_RV200)
3745                         WREG32(R_00015C_AGP_BASE_2, 0);
3746         }
3747         /* Wait for mc idle */
3748         if (r100_mc_wait_for_idle(rdev))
3749                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3750         /* Program MC, should be a 32bits limited address space */
3751         WREG32(R_000148_MC_FB_LOCATION,
3752                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3753                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3754         r100_mc_resume(rdev, &save);
3755 }
3756
3757 void r100_clock_startup(struct radeon_device *rdev)
3758 {
3759         u32 tmp;
3760
3761         if (radeon_dynclks != -1 && radeon_dynclks)
3762                 radeon_legacy_set_clock_gating(rdev, 1);
3763         /* We need to force on some of the block */
3764         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3765         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3766         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3767                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3768         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3769 }
3770
3771 static int r100_startup(struct radeon_device *rdev)
3772 {
3773         int r;
3774
3775         /* set common regs */
3776         r100_set_common_regs(rdev);
3777         /* program mc */
3778         r100_mc_program(rdev);
3779         /* Resume clock */
3780         r100_clock_startup(rdev);
3781         /* Initialize GART (initialize after TTM so we can allocate
3782          * memory through TTM but finalize after TTM) */
3783         r100_enable_bm(rdev);
3784         if (rdev->flags & RADEON_IS_PCI) {
3785                 r = r100_pci_gart_enable(rdev);
3786                 if (r)
3787                         return r;
3788         }
3789
3790         /* allocate wb buffer */
3791         r = radeon_wb_init(rdev);
3792         if (r)
3793                 return r;
3794
3795         /* Enable IRQ */
3796         r100_irq_set(rdev);
3797         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3798         /* 1M ring buffer */
3799         r = r100_cp_init(rdev, 1024 * 1024);
3800         if (r) {
3801                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3802                 return r;
3803         }
3804         r = r100_ib_init(rdev);
3805         if (r) {
3806                 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
3807                 return r;
3808         }
3809         return 0;
3810 }
3811
3812 int r100_resume(struct radeon_device *rdev)
3813 {
3814         /* Make sur GART are not working */
3815         if (rdev->flags & RADEON_IS_PCI)
3816                 r100_pci_gart_disable(rdev);
3817         /* Resume clock before doing reset */
3818         r100_clock_startup(rdev);
3819         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3820         if (radeon_asic_reset(rdev)) {
3821                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3822                         RREG32(R_000E40_RBBM_STATUS),
3823                         RREG32(R_0007C0_CP_STAT));
3824         }
3825         /* post */
3826         radeon_combios_asic_init(rdev->ddev);
3827         /* Resume clock after posting */
3828         r100_clock_startup(rdev);
3829         /* Initialize surface registers */
3830         radeon_surface_init(rdev);
3831         return r100_startup(rdev);
3832 }
3833
3834 int r100_suspend(struct radeon_device *rdev)
3835 {
3836         r100_cp_disable(rdev);
3837         radeon_wb_disable(rdev);
3838         r100_irq_disable(rdev);
3839         if (rdev->flags & RADEON_IS_PCI)
3840                 r100_pci_gart_disable(rdev);
3841         return 0;
3842 }
3843
3844 void r100_fini(struct radeon_device *rdev)
3845 {
3846         r100_cp_fini(rdev);
3847         radeon_wb_fini(rdev);
3848         r100_ib_fini(rdev);
3849         radeon_gem_fini(rdev);
3850         if (rdev->flags & RADEON_IS_PCI)
3851                 r100_pci_gart_fini(rdev);
3852         radeon_agp_fini(rdev);
3853         radeon_irq_kms_fini(rdev);
3854         radeon_fence_driver_fini(rdev);
3855         radeon_bo_fini(rdev);
3856         radeon_atombios_fini(rdev);
3857         kfree(rdev->bios);
3858         rdev->bios = NULL;
3859 }
3860
3861 /*
3862  * Due to how kexec works, it can leave the hw fully initialised when it
3863  * boots the new kernel. However doing our init sequence with the CP and
3864  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3865  * do some quick sanity checks and restore sane values to avoid this
3866  * problem.
3867  */
3868 void r100_restore_sanity(struct radeon_device *rdev)
3869 {
3870         u32 tmp;
3871
3872         tmp = RREG32(RADEON_CP_CSQ_CNTL);
3873         if (tmp) {
3874                 WREG32(RADEON_CP_CSQ_CNTL, 0);
3875         }
3876         tmp = RREG32(RADEON_CP_RB_CNTL);
3877         if (tmp) {
3878                 WREG32(RADEON_CP_RB_CNTL, 0);
3879         }
3880         tmp = RREG32(RADEON_SCRATCH_UMSK);
3881         if (tmp) {
3882                 WREG32(RADEON_SCRATCH_UMSK, 0);
3883         }
3884 }
3885
3886 int r100_init(struct radeon_device *rdev)
3887 {
3888         int r;
3889
3890         /* Register debugfs file specific to this group of asics */
3891         r100_debugfs(rdev);
3892         /* Disable VGA */
3893         r100_vga_render_disable(rdev);
3894         /* Initialize scratch registers */
3895         radeon_scratch_init(rdev);
3896         /* Initialize surface registers */
3897         radeon_surface_init(rdev);
3898         /* sanity check some register to avoid hangs like after kexec */
3899         r100_restore_sanity(rdev);
3900         /* TODO: disable VGA need to use VGA request */
3901         /* BIOS*/
3902         if (!radeon_get_bios(rdev)) {
3903                 if (ASIC_IS_AVIVO(rdev))
3904                         return -EINVAL;
3905         }
3906         if (rdev->is_atom_bios) {
3907                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3908                 return -EINVAL;
3909         } else {
3910                 r = radeon_combios_init(rdev);
3911                 if (r)
3912                         return r;
3913         }
3914         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3915         if (radeon_asic_reset(rdev)) {
3916                 dev_warn(rdev->dev,
3917                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3918                         RREG32(R_000E40_RBBM_STATUS),
3919                         RREG32(R_0007C0_CP_STAT));
3920         }
3921         /* check if cards are posted or not */
3922         if (radeon_boot_test_post_card(rdev) == false)
3923                 return -EINVAL;
3924         /* Set asic errata */
3925         r100_errata(rdev);
3926         /* Initialize clocks */
3927         radeon_get_clock_info(rdev->ddev);
3928         /* initialize AGP */
3929         if (rdev->flags & RADEON_IS_AGP) {
3930                 r = radeon_agp_init(rdev);
3931                 if (r) {
3932                         radeon_agp_disable(rdev);
3933                 }
3934         }
3935         /* initialize VRAM */
3936         r100_mc_init(rdev);
3937         /* Fence driver */
3938         r = radeon_fence_driver_init(rdev);
3939         if (r)
3940                 return r;
3941         r = radeon_irq_kms_init(rdev);
3942         if (r)
3943                 return r;
3944         /* Memory manager */
3945         r = radeon_bo_init(rdev);
3946         if (r)
3947                 return r;
3948         if (rdev->flags & RADEON_IS_PCI) {
3949                 r = r100_pci_gart_init(rdev);
3950                 if (r)
3951                         return r;
3952         }
3953         r100_set_safe_registers(rdev);
3954         rdev->accel_working = true;
3955         r = r100_startup(rdev);
3956         if (r) {
3957                 /* Somethings want wront with the accel init stop accel */
3958                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3959                 r100_cp_fini(rdev);
3960                 radeon_wb_fini(rdev);
3961                 r100_ib_fini(rdev);
3962                 radeon_irq_kms_fini(rdev);
3963                 if (rdev->flags & RADEON_IS_PCI)
3964                         r100_pci_gart_fini(rdev);
3965                 rdev->accel_working = false;
3966         }
3967         return 0;
3968 }