2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
102 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
103 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
104 /* RADEON_IB_POOL_SIZE must be a power of 2 */
105 #define RADEON_IB_POOL_SIZE 16
106 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
107 #define RADEONFB_CONN_LIMIT 4
108 #define RADEON_BIOS_NUM_SCRATCH 8
111 * Errata workarounds.
113 enum radeon_pll_errata {
114 CHIP_ERRATA_R300_CG = 0x00000001,
115 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
116 CHIP_ERRATA_PLL_DELAY = 0x00000004
120 struct radeon_device;
126 #define ATRM_BIOS_PAGE 4096
128 #if defined(CONFIG_VGA_SWITCHEROO)
129 bool radeon_atrm_supported(struct pci_dev *pdev);
130 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
132 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
137 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
141 bool radeon_get_bios(struct radeon_device *rdev);
147 struct radeon_dummy_page {
151 int radeon_dummy_page_init(struct radeon_device *rdev);
152 void radeon_dummy_page_fini(struct radeon_device *rdev);
158 struct radeon_clock {
159 struct radeon_pll p1pll;
160 struct radeon_pll p2pll;
161 struct radeon_pll dcpll;
162 struct radeon_pll spll;
163 struct radeon_pll mpll;
165 uint32_t default_mclk;
166 uint32_t default_sclk;
167 uint32_t default_dispclk;
169 uint32_t max_pixel_clock;
175 int radeon_pm_init(struct radeon_device *rdev);
176 void radeon_pm_fini(struct radeon_device *rdev);
177 void radeon_pm_compute_clocks(struct radeon_device *rdev);
178 void radeon_pm_suspend(struct radeon_device *rdev);
179 void radeon_pm_resume(struct radeon_device *rdev);
180 void radeon_combios_get_power_modes(struct radeon_device *rdev);
181 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
182 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
183 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
184 void rs690_pm_info(struct radeon_device *rdev);
185 extern int rv6xx_get_temp(struct radeon_device *rdev);
186 extern int rv770_get_temp(struct radeon_device *rdev);
187 extern int evergreen_get_temp(struct radeon_device *rdev);
188 extern int sumo_get_temp(struct radeon_device *rdev);
193 struct radeon_fence_driver {
194 uint32_t scratch_reg;
197 unsigned long last_jiffies;
198 unsigned long last_timeout;
199 wait_queue_head_t queue;
201 struct list_head created;
202 struct list_head emited;
203 struct list_head signaled;
207 struct radeon_fence {
208 struct radeon_device *rdev;
210 struct list_head list;
211 /* protected by radeon_fence.lock */
217 int radeon_fence_driver_init(struct radeon_device *rdev);
218 void radeon_fence_driver_fini(struct radeon_device *rdev);
219 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
220 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
221 void radeon_fence_process(struct radeon_device *rdev);
222 bool radeon_fence_signaled(struct radeon_fence *fence);
223 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
224 int radeon_fence_wait_next(struct radeon_device *rdev);
225 int radeon_fence_wait_last(struct radeon_device *rdev);
226 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
227 void radeon_fence_unref(struct radeon_fence **fence);
232 struct radeon_surface_reg {
233 struct radeon_bo *bo;
236 #define RADEON_GEM_MAX_SURFACES 8
242 struct ttm_bo_global_ref bo_global_ref;
243 struct drm_global_reference mem_global_ref;
244 struct ttm_bo_device bdev;
245 bool mem_global_referenced;
250 /* Protected by gem.mutex */
251 struct list_head list;
252 /* Protected by tbo.reserved */
254 struct ttm_placement placement;
255 struct ttm_buffer_object tbo;
256 struct ttm_bo_kmap_obj kmap;
262 /* Constant after initialization */
263 struct radeon_device *rdev;
264 struct drm_gem_object gem_base;
266 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
268 struct radeon_bo_list {
269 struct ttm_validate_buffer tv;
270 struct radeon_bo *bo;
282 struct list_head objects;
285 int radeon_gem_init(struct radeon_device *rdev);
286 void radeon_gem_fini(struct radeon_device *rdev);
287 int radeon_gem_object_create(struct radeon_device *rdev, int size,
288 int alignment, int initial_domain,
289 bool discardable, bool kernel,
290 struct drm_gem_object **obj);
291 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
293 void radeon_gem_object_unpin(struct drm_gem_object *obj);
295 int radeon_mode_dumb_create(struct drm_file *file_priv,
296 struct drm_device *dev,
297 struct drm_mode_create_dumb *args);
298 int radeon_mode_dumb_mmap(struct drm_file *filp,
299 struct drm_device *dev,
300 uint32_t handle, uint64_t *offset_p);
301 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
302 struct drm_device *dev,
306 * GART structures, functions & helpers
310 struct radeon_gart_table_ram {
311 volatile uint32_t *ptr;
314 struct radeon_gart_table_vram {
315 struct radeon_bo *robj;
316 volatile uint32_t *ptr;
319 union radeon_gart_table {
320 struct radeon_gart_table_ram ram;
321 struct radeon_gart_table_vram vram;
324 #define RADEON_GPU_PAGE_SIZE 4096
325 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
326 #define RADEON_GPU_PAGE_SHIFT 12
329 dma_addr_t table_addr;
330 unsigned num_gpu_pages;
331 unsigned num_cpu_pages;
333 union radeon_gart_table table;
335 dma_addr_t *pages_addr;
340 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
341 void radeon_gart_table_ram_free(struct radeon_device *rdev);
342 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
343 void radeon_gart_table_vram_free(struct radeon_device *rdev);
344 int radeon_gart_init(struct radeon_device *rdev);
345 void radeon_gart_fini(struct radeon_device *rdev);
346 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
348 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
349 int pages, struct page **pagelist,
350 dma_addr_t *dma_addr);
354 * GPU MC structures, functions & helpers
357 resource_size_t aper_size;
358 resource_size_t aper_base;
359 resource_size_t agp_base;
360 /* for some chips with <= 32MB we need to lie
361 * about vram size near mc fb location */
363 u64 visible_vram_size;
373 bool igp_sideport_enabled;
377 bool radeon_combios_sideport_present(struct radeon_device *rdev);
378 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
381 * GPU scratch registers structures, functions & helpers
383 struct radeon_scratch {
390 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
391 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
398 struct radeon_unpin_work {
399 struct work_struct work;
400 struct radeon_device *rdev;
402 struct radeon_fence *fence;
403 struct drm_pending_vblank_event *event;
404 struct radeon_bo *old_rbo;
408 struct r500_irq_stat_regs {
412 struct r600_irq_stat_regs {
420 struct evergreen_irq_stat_regs {
435 union radeon_irq_stat_regs {
436 struct r500_irq_stat_regs r500;
437 struct r600_irq_stat_regs r600;
438 struct evergreen_irq_stat_regs evergreen;
444 /* FIXME: use a define max crtc rather than hardcode it */
445 bool crtc_vblank_int[6];
447 wait_queue_head_t vblank_queue;
448 /* FIXME: use defines for max hpd/dacs */
452 wait_queue_head_t idle_queue;
453 /* FIXME: use defines for max HDMI blocks */
457 union radeon_irq_stat_regs stat_regs;
458 spinlock_t pflip_lock[6];
459 int pflip_refcount[6];
462 int radeon_irq_kms_init(struct radeon_device *rdev);
463 void radeon_irq_kms_fini(struct radeon_device *rdev);
464 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
465 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
466 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
467 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
473 struct list_head list;
476 struct radeon_fence *fence;
484 * mutex protects scheduled_ibs, ready, alloc_bm
486 struct radeon_ib_pool {
488 struct radeon_bo *robj;
489 struct list_head bogus_ib;
490 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
496 struct radeon_bo *ring_obj;
497 volatile uint32_t *ring;
502 unsigned ring_free_dw;
515 struct radeon_bo *ring_obj;
516 volatile uint32_t *ring;
529 struct radeon_bo *shader_obj;
531 u32 vs_offset, ps_offset;
534 u32 vb_used, vb_total;
535 struct radeon_ib *vb_ib;
538 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
539 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
540 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
541 int radeon_ib_pool_init(struct radeon_device *rdev);
542 void radeon_ib_pool_fini(struct radeon_device *rdev);
543 int radeon_ib_test(struct radeon_device *rdev);
544 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
545 /* Ring access between begin & end cannot sleep */
546 void radeon_ring_free_size(struct radeon_device *rdev);
547 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
548 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
549 void radeon_ring_commit(struct radeon_device *rdev);
550 void radeon_ring_unlock_commit(struct radeon_device *rdev);
551 void radeon_ring_unlock_undo(struct radeon_device *rdev);
552 int radeon_ring_test(struct radeon_device *rdev);
553 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
554 void radeon_ring_fini(struct radeon_device *rdev);
560 struct radeon_cs_reloc {
561 struct drm_gem_object *gobj;
562 struct radeon_bo *robj;
563 struct radeon_bo_list lobj;
568 struct radeon_cs_chunk {
574 void __user *user_ptr;
575 int last_copied_page;
579 struct radeon_cs_parser {
581 struct radeon_device *rdev;
582 struct drm_file *filp;
585 struct radeon_cs_chunk *chunks;
586 uint64_t *chunks_array;
591 struct radeon_cs_reloc *relocs;
592 struct radeon_cs_reloc **relocs_ptr;
593 struct list_head validated;
594 /* indices of various chunks */
596 int chunk_relocs_idx;
597 struct radeon_ib *ib;
603 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
604 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
607 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
609 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
610 u32 pg_idx, pg_offset;
614 pg_idx = (idx * 4) / PAGE_SIZE;
615 pg_offset = (idx * 4) % PAGE_SIZE;
617 if (ibc->kpage_idx[0] == pg_idx)
618 return ibc->kpage[0][pg_offset/4];
619 if (ibc->kpage_idx[1] == pg_idx)
620 return ibc->kpage[1][pg_offset/4];
622 new_page = radeon_cs_update_pages(p, pg_idx);
624 p->parser_error = new_page;
628 idx_value = ibc->kpage[new_page][pg_offset/4];
632 struct radeon_cs_packet {
641 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
642 struct radeon_cs_packet *pkt,
643 unsigned idx, unsigned reg);
644 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
645 struct radeon_cs_packet *pkt);
651 int radeon_agp_init(struct radeon_device *rdev);
652 void radeon_agp_resume(struct radeon_device *rdev);
653 void radeon_agp_suspend(struct radeon_device *rdev);
654 void radeon_agp_fini(struct radeon_device *rdev);
661 struct radeon_bo *wb_obj;
662 volatile uint32_t *wb;
668 #define RADEON_WB_SCRATCH_OFFSET 0
669 #define RADEON_WB_CP_RPTR_OFFSET 1024
670 #define RADEON_WB_CP1_RPTR_OFFSET 1280
671 #define RADEON_WB_CP2_RPTR_OFFSET 1536
672 #define R600_WB_IH_WPTR_OFFSET 2048
673 #define R600_WB_EVENT_OFFSET 3072
676 * struct radeon_pm - power management datas
677 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
678 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
679 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
680 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
681 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
682 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
683 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
684 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
685 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
686 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
687 * @needed_bandwidth: current bandwidth needs
689 * It keeps track of various data needed to take powermanagement decision.
690 * Bandwidth need is used to determine minimun clock of the GPU and memory.
691 * Equation between gpu/memory clock and available bandwidth is hw dependent
692 * (type of memory, bus size, efficiency, ...)
695 enum radeon_pm_method {
700 enum radeon_dynpm_state {
701 DYNPM_STATE_DISABLED,
705 DYNPM_STATE_SUSPENDED,
707 enum radeon_dynpm_action {
709 DYNPM_ACTION_MINIMUM,
710 DYNPM_ACTION_DOWNCLOCK,
711 DYNPM_ACTION_UPCLOCK,
715 enum radeon_voltage_type {
722 enum radeon_pm_state_type {
723 POWER_STATE_TYPE_DEFAULT,
724 POWER_STATE_TYPE_POWERSAVE,
725 POWER_STATE_TYPE_BATTERY,
726 POWER_STATE_TYPE_BALANCED,
727 POWER_STATE_TYPE_PERFORMANCE,
730 enum radeon_pm_profile_type {
738 #define PM_PROFILE_DEFAULT_IDX 0
739 #define PM_PROFILE_LOW_SH_IDX 1
740 #define PM_PROFILE_MID_SH_IDX 2
741 #define PM_PROFILE_HIGH_SH_IDX 3
742 #define PM_PROFILE_LOW_MH_IDX 4
743 #define PM_PROFILE_MID_MH_IDX 5
744 #define PM_PROFILE_HIGH_MH_IDX 6
745 #define PM_PROFILE_MAX 7
747 struct radeon_pm_profile {
754 enum radeon_int_thermal_type {
758 THERMAL_TYPE_EVERGREEN,
763 struct radeon_voltage {
764 enum radeon_voltage_type type;
766 struct radeon_gpio_rec gpio;
767 u32 delay; /* delay in usec from voltage drop to sclk change */
768 bool active_high; /* voltage drop is active when bit is high */
770 u8 vddc_id; /* index into vddc voltage table */
771 u8 vddci_id; /* index into vddci voltage table */
775 /* evergreen+ vddci */
779 /* clock mode flags */
780 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
782 struct radeon_pm_clock_info {
788 struct radeon_voltage voltage;
789 /* standardized clock flags */
794 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
796 struct radeon_power_state {
797 enum radeon_pm_state_type type;
798 /* XXX: use a define for num clock modes */
799 struct radeon_pm_clock_info clock_info[8];
800 /* number of valid clock modes in this power state */
802 struct radeon_pm_clock_info *default_clock_mode;
803 /* standardized state flags */
805 u32 misc; /* vbios specific flags */
806 u32 misc2; /* vbios specific flags */
807 int pcie_lanes; /* pcie lanes */
811 * Some modes are overclocked by very low value, accept them
813 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
818 int active_crtc_count;
822 fixed20_12 max_bandwidth;
823 fixed20_12 igp_sideport_mclk;
824 fixed20_12 igp_system_mclk;
825 fixed20_12 igp_ht_link_clk;
826 fixed20_12 igp_ht_link_width;
827 fixed20_12 k8_bandwidth;
828 fixed20_12 sideport_bandwidth;
829 fixed20_12 ht_bandwidth;
830 fixed20_12 core_bandwidth;
833 fixed20_12 needed_bandwidth;
834 struct radeon_power_state *power_state;
835 /* number of valid power states */
836 int num_power_states;
837 int current_power_state_index;
838 int current_clock_mode_index;
839 int requested_power_state_index;
840 int requested_clock_mode_index;
841 int default_power_state_index;
850 struct radeon_i2c_chan *i2c_bus;
851 /* selected pm method */
852 enum radeon_pm_method pm_method;
853 /* dynpm power management */
854 struct delayed_work dynpm_idle_work;
855 enum radeon_dynpm_state dynpm_state;
856 enum radeon_dynpm_action dynpm_planned_action;
857 unsigned long dynpm_action_timeout;
858 bool dynpm_can_upclock;
859 bool dynpm_can_downclock;
860 /* profile-based power management */
861 enum radeon_pm_profile_type profile;
863 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
864 /* internal thermal controller on rv6xx+ */
865 enum radeon_int_thermal_type int_thermal_type;
866 struct device *int_hwmon_dev;
873 void radeon_benchmark(struct radeon_device *rdev);
879 void radeon_test_moves(struct radeon_device *rdev);
885 int radeon_debugfs_add_files(struct radeon_device *rdev,
886 struct drm_info_list *files,
888 int radeon_debugfs_fence_init(struct radeon_device *rdev);
892 * ASIC specific functions.
895 int (*init)(struct radeon_device *rdev);
896 void (*fini)(struct radeon_device *rdev);
897 int (*resume)(struct radeon_device *rdev);
898 int (*suspend)(struct radeon_device *rdev);
899 void (*vga_set_state)(struct radeon_device *rdev, bool state);
900 bool (*gpu_is_lockup)(struct radeon_device *rdev);
901 int (*asic_reset)(struct radeon_device *rdev);
902 void (*gart_tlb_flush)(struct radeon_device *rdev);
903 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
904 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
905 void (*cp_fini)(struct radeon_device *rdev);
906 void (*cp_disable)(struct radeon_device *rdev);
907 void (*cp_commit)(struct radeon_device *rdev);
908 void (*ring_start)(struct radeon_device *rdev);
909 int (*ring_test)(struct radeon_device *rdev);
910 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
911 int (*irq_set)(struct radeon_device *rdev);
912 int (*irq_process)(struct radeon_device *rdev);
913 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
914 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
915 int (*cs_parse)(struct radeon_cs_parser *p);
916 int (*copy_blit)(struct radeon_device *rdev,
919 unsigned num_gpu_pages,
920 struct radeon_fence *fence);
921 int (*copy_dma)(struct radeon_device *rdev,
924 unsigned num_gpu_pages,
925 struct radeon_fence *fence);
926 int (*copy)(struct radeon_device *rdev,
929 unsigned num_gpu_pages,
930 struct radeon_fence *fence);
931 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
932 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
933 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
934 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
935 int (*get_pcie_lanes)(struct radeon_device *rdev);
936 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
937 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
938 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
939 uint32_t tiling_flags, uint32_t pitch,
940 uint32_t offset, uint32_t obj_size);
941 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
942 void (*bandwidth_update)(struct radeon_device *rdev);
943 void (*hpd_init)(struct radeon_device *rdev);
944 void (*hpd_fini)(struct radeon_device *rdev);
945 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
946 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
947 /* ioctl hw specific callback. Some hw might want to perform special
948 * operation on specific ioctl. For instance on wait idle some hw
949 * might want to perform and HDP flush through MMIO as it seems that
950 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
953 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
954 bool (*gui_idle)(struct radeon_device *rdev);
955 /* power management */
956 void (*pm_misc)(struct radeon_device *rdev);
957 void (*pm_prepare)(struct radeon_device *rdev);
958 void (*pm_finish)(struct radeon_device *rdev);
959 void (*pm_init_profile)(struct radeon_device *rdev);
960 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
962 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
963 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
964 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
970 struct r100_gpu_lockup {
971 unsigned long last_jiffies;
976 const unsigned *reg_safe_bm;
977 unsigned reg_safe_bm_size;
979 struct r100_gpu_lockup lockup;
983 const unsigned *reg_safe_bm;
984 unsigned reg_safe_bm_size;
987 struct r100_gpu_lockup lockup;
992 unsigned max_tile_pipes;
994 unsigned max_backends;
996 unsigned max_threads;
997 unsigned max_stack_entries;
998 unsigned max_hw_contexts;
999 unsigned max_gs_threads;
1000 unsigned sx_max_export_size;
1001 unsigned sx_max_export_pos_size;
1002 unsigned sx_max_export_smx_size;
1003 unsigned sq_num_cf_insts;
1004 unsigned tiling_nbanks;
1005 unsigned tiling_npipes;
1006 unsigned tiling_group_size;
1007 unsigned tile_config;
1008 struct r100_gpu_lockup lockup;
1013 unsigned max_tile_pipes;
1015 unsigned max_backends;
1017 unsigned max_threads;
1018 unsigned max_stack_entries;
1019 unsigned max_hw_contexts;
1020 unsigned max_gs_threads;
1021 unsigned sx_max_export_size;
1022 unsigned sx_max_export_pos_size;
1023 unsigned sx_max_export_smx_size;
1024 unsigned sq_num_cf_insts;
1025 unsigned sx_num_of_sets;
1026 unsigned sc_prim_fifo_size;
1027 unsigned sc_hiz_tile_fifo_size;
1028 unsigned sc_earlyz_tile_fifo_fize;
1029 unsigned tiling_nbanks;
1030 unsigned tiling_npipes;
1031 unsigned tiling_group_size;
1032 unsigned tile_config;
1033 struct r100_gpu_lockup lockup;
1036 struct evergreen_asic {
1039 unsigned max_tile_pipes;
1041 unsigned max_backends;
1043 unsigned max_threads;
1044 unsigned max_stack_entries;
1045 unsigned max_hw_contexts;
1046 unsigned max_gs_threads;
1047 unsigned sx_max_export_size;
1048 unsigned sx_max_export_pos_size;
1049 unsigned sx_max_export_smx_size;
1050 unsigned sq_num_cf_insts;
1051 unsigned sx_num_of_sets;
1052 unsigned sc_prim_fifo_size;
1053 unsigned sc_hiz_tile_fifo_size;
1054 unsigned sc_earlyz_tile_fifo_size;
1055 unsigned tiling_nbanks;
1056 unsigned tiling_npipes;
1057 unsigned tiling_group_size;
1058 unsigned tile_config;
1059 struct r100_gpu_lockup lockup;
1062 struct cayman_asic {
1063 unsigned max_shader_engines;
1064 unsigned max_pipes_per_simd;
1065 unsigned max_tile_pipes;
1066 unsigned max_simds_per_se;
1067 unsigned max_backends_per_se;
1068 unsigned max_texture_channel_caches;
1070 unsigned max_threads;
1071 unsigned max_gs_threads;
1072 unsigned max_stack_entries;
1073 unsigned sx_num_of_sets;
1074 unsigned sx_max_export_size;
1075 unsigned sx_max_export_pos_size;
1076 unsigned sx_max_export_smx_size;
1077 unsigned max_hw_contexts;
1078 unsigned sq_num_cf_insts;
1079 unsigned sc_prim_fifo_size;
1080 unsigned sc_hiz_tile_fifo_size;
1081 unsigned sc_earlyz_tile_fifo_size;
1083 unsigned num_shader_engines;
1084 unsigned num_shader_pipes_per_simd;
1085 unsigned num_tile_pipes;
1086 unsigned num_simds_per_se;
1087 unsigned num_backends_per_se;
1088 unsigned backend_disable_mask_per_asic;
1089 unsigned backend_map;
1090 unsigned num_texture_channel_caches;
1091 unsigned mem_max_burst_length_bytes;
1092 unsigned mem_row_size_in_kb;
1093 unsigned shader_engine_tile_size;
1095 unsigned multi_gpu_tile_size;
1097 unsigned tile_config;
1098 struct r100_gpu_lockup lockup;
1101 union radeon_asic_config {
1102 struct r300_asic r300;
1103 struct r100_asic r100;
1104 struct r600_asic r600;
1105 struct rv770_asic rv770;
1106 struct evergreen_asic evergreen;
1107 struct cayman_asic cayman;
1111 * asic initizalization from radeon_asic.c
1113 void radeon_agp_disable(struct radeon_device *rdev);
1114 int radeon_asic_init(struct radeon_device *rdev);
1120 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1121 struct drm_file *filp);
1122 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1123 struct drm_file *filp);
1124 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1125 struct drm_file *file_priv);
1126 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1127 struct drm_file *file_priv);
1128 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1129 struct drm_file *file_priv);
1130 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1131 struct drm_file *file_priv);
1132 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1133 struct drm_file *filp);
1134 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1135 struct drm_file *filp);
1136 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1137 struct drm_file *filp);
1138 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1139 struct drm_file *filp);
1140 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1141 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1142 struct drm_file *filp);
1143 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1144 struct drm_file *filp);
1146 /* VRAM scratch page for HDP bug */
1147 struct r700_vram_scratch {
1148 struct radeon_bo *robj;
1149 volatile uint32_t *ptr;
1153 * Core structure, functions and helpers.
1155 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1156 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1158 struct radeon_device {
1160 struct drm_device *ddev;
1161 struct pci_dev *pdev;
1163 union radeon_asic_config config;
1164 enum radeon_family family;
1165 unsigned long flags;
1167 enum radeon_pll_errata pll_errata;
1174 uint16_t bios_header_start;
1175 struct radeon_bo *stollen_vga_memory;
1177 resource_size_t rmmio_base;
1178 resource_size_t rmmio_size;
1180 radeon_rreg_t mc_rreg;
1181 radeon_wreg_t mc_wreg;
1182 radeon_rreg_t pll_rreg;
1183 radeon_wreg_t pll_wreg;
1184 uint32_t pcie_reg_mask;
1185 radeon_rreg_t pciep_rreg;
1186 radeon_wreg_t pciep_wreg;
1188 void __iomem *rio_mem;
1189 resource_size_t rio_mem_size;
1190 struct radeon_clock clock;
1191 struct radeon_mc mc;
1192 struct radeon_gart gart;
1193 struct radeon_mode_info mode_info;
1194 struct radeon_scratch scratch;
1195 struct radeon_mman mman;
1196 struct radeon_fence_driver fence_drv;
1197 struct radeon_cp cp;
1198 /* cayman compute rings */
1199 struct radeon_cp cp1;
1200 struct radeon_cp cp2;
1201 struct radeon_ib_pool ib_pool;
1202 struct radeon_irq irq;
1203 struct radeon_asic *asic;
1204 struct radeon_gem gem;
1205 struct radeon_pm pm;
1206 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1207 struct mutex cs_mutex;
1208 struct radeon_wb wb;
1209 struct radeon_dummy_page dummy_page;
1215 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1216 const struct firmware *me_fw; /* all family ME firmware */
1217 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1218 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1219 const struct firmware *mc_fw; /* NI MC firmware */
1220 struct r600_blit r600_blit;
1221 struct r700_vram_scratch vram_scratch;
1222 int msi_enabled; /* msi enabled */
1223 struct r600_ih ih; /* r6/700 interrupt ring */
1224 struct work_struct hotplug_work;
1225 int num_crtc; /* number of crtcs */
1226 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1227 struct mutex vram_mutex;
1231 struct timer_list audio_timer;
1234 int audio_bits_per_sample;
1235 uint8_t audio_status_bits;
1236 uint8_t audio_category_code;
1238 struct notifier_block acpi_nb;
1239 /* only one userspace can use Hyperz features or CMASK at a time */
1240 struct drm_file *hyperz_filp;
1241 struct drm_file *cmask_filp;
1243 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1246 int radeon_device_init(struct radeon_device *rdev,
1247 struct drm_device *ddev,
1248 struct pci_dev *pdev,
1250 void radeon_device_fini(struct radeon_device *rdev);
1251 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1253 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1255 if (reg < rdev->rmmio_size)
1256 return readl(((void __iomem *)rdev->rmmio) + reg);
1258 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1259 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1263 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1265 if (reg < rdev->rmmio_size)
1266 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1268 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1269 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1273 static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1275 if (reg < rdev->rio_mem_size)
1276 return ioread32(rdev->rio_mem + reg);
1278 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1279 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1283 static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1285 if (reg < rdev->rio_mem_size)
1286 iowrite32(v, rdev->rio_mem + reg);
1288 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1289 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1296 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1299 * Registers read & write functions.
1301 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1302 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1303 #define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg))
1304 #define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg))
1305 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1306 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1307 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1308 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1309 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1310 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1311 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1312 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1313 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1314 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1315 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1316 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1317 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1318 #define WREG32_P(reg, val, mask) \
1320 uint32_t tmp_ = RREG32(reg); \
1322 tmp_ |= ((val) & ~(mask)); \
1323 WREG32(reg, tmp_); \
1325 #define WREG32_PLL_P(reg, val, mask) \
1327 uint32_t tmp_ = RREG32_PLL(reg); \
1329 tmp_ |= ((val) & ~(mask)); \
1330 WREG32_PLL(reg, tmp_); \
1332 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1333 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1334 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1337 * Indirect registers accessor
1339 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1343 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1344 r = RREG32(RADEON_PCIE_DATA);
1348 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1350 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1351 WREG32(RADEON_PCIE_DATA, (v));
1354 void r100_pll_errata_after_index(struct radeon_device *rdev);
1360 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1361 (rdev->pdev->device == 0x5969))
1362 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1363 (rdev->family == CHIP_RV200) || \
1364 (rdev->family == CHIP_RS100) || \
1365 (rdev->family == CHIP_RS200) || \
1366 (rdev->family == CHIP_RV250) || \
1367 (rdev->family == CHIP_RV280) || \
1368 (rdev->family == CHIP_RS300))
1369 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1370 (rdev->family == CHIP_RV350) || \
1371 (rdev->family == CHIP_R350) || \
1372 (rdev->family == CHIP_RV380) || \
1373 (rdev->family == CHIP_R420) || \
1374 (rdev->family == CHIP_R423) || \
1375 (rdev->family == CHIP_RV410) || \
1376 (rdev->family == CHIP_RS400) || \
1377 (rdev->family == CHIP_RS480))
1378 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1379 (rdev->ddev->pdev->device == 0x9443) || \
1380 (rdev->ddev->pdev->device == 0x944B) || \
1381 (rdev->ddev->pdev->device == 0x9506) || \
1382 (rdev->ddev->pdev->device == 0x9509) || \
1383 (rdev->ddev->pdev->device == 0x950F) || \
1384 (rdev->ddev->pdev->device == 0x689C) || \
1385 (rdev->ddev->pdev->device == 0x689D))
1386 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1387 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1388 (rdev->family == CHIP_RS690) || \
1389 (rdev->family == CHIP_RS740) || \
1390 (rdev->family >= CHIP_R600))
1391 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1392 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1393 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1394 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1395 (rdev->flags & RADEON_IS_IGP))
1396 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1401 #define RBIOS8(i) (rdev->bios[i])
1402 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1403 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1405 int radeon_combios_init(struct radeon_device *rdev);
1406 void radeon_combios_fini(struct radeon_device *rdev);
1407 int radeon_atombios_init(struct radeon_device *rdev);
1408 void radeon_atombios_fini(struct radeon_device *rdev);
1414 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1417 if (rdev->cp.count_dw <= 0) {
1418 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1421 rdev->cp.ring[rdev->cp.wptr++] = v;
1422 rdev->cp.wptr &= rdev->cp.ptr_mask;
1423 rdev->cp.count_dw--;
1424 rdev->cp.ring_free_dw--;
1431 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1432 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1433 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1434 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1435 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1436 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1437 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1438 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1439 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1440 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1441 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1442 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1443 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1444 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1445 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1446 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1447 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1448 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1449 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1450 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1451 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1452 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1453 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1454 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1455 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1456 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1457 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1458 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1459 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1460 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1461 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1462 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1463 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1464 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1465 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1466 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1467 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1468 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1469 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1470 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1471 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1472 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1473 #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1474 #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1476 /* Common functions */
1478 extern int radeon_gpu_reset(struct radeon_device *rdev);
1479 extern void radeon_agp_disable(struct radeon_device *rdev);
1480 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1481 extern void radeon_gart_restore(struct radeon_device *rdev);
1482 extern int radeon_modeset_init(struct radeon_device *rdev);
1483 extern void radeon_modeset_fini(struct radeon_device *rdev);
1484 extern bool radeon_card_posted(struct radeon_device *rdev);
1485 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1486 extern void radeon_update_display_priority(struct radeon_device *rdev);
1487 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1488 extern void radeon_scratch_init(struct radeon_device *rdev);
1489 extern void radeon_wb_fini(struct radeon_device *rdev);
1490 extern int radeon_wb_init(struct radeon_device *rdev);
1491 extern void radeon_wb_disable(struct radeon_device *rdev);
1492 extern void radeon_surface_init(struct radeon_device *rdev);
1493 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1494 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1495 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1496 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1497 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1498 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1499 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1500 extern int radeon_resume_kms(struct drm_device *dev);
1501 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1502 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1505 * r600 functions used by radeon_encoder.c
1507 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1508 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1509 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1511 extern int ni_init_microcode(struct radeon_device *rdev);
1512 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1515 #if defined(CONFIG_ACPI)
1516 extern int radeon_acpi_init(struct radeon_device *rdev);
1518 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1521 #include "radeon_object.h"