2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/console.h>
30 #include <linux/efi.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/vga_switcheroo.h>
34 #include <linux/vgaarb.h>
36 #include <drm/drm_cache.h>
37 #include <drm/drm_crtc_helper.h>
38 #include <drm/drm_debugfs.h>
39 #include <drm/drm_device.h>
40 #include <drm/drm_file.h>
41 #include <drm/drm_pci.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/radeon_drm.h>
45 #include "radeon_reg.h"
49 static const char radeon_family_name[][16] = {
115 #if defined(CONFIG_VGA_SWITCHEROO)
116 bool radeon_has_atpx_dgpu_power_cntl(void);
117 bool radeon_is_atpx_hybrid(void);
119 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
120 static inline bool radeon_is_atpx_hybrid(void) { return false; }
123 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
125 struct radeon_px_quirk {
133 static struct radeon_px_quirk radeon_px_quirk_list[] = {
134 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
135 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
137 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
138 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
139 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
141 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
142 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
143 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
145 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
146 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
147 * https://bugs.freedesktop.org/show_bug.cgi?id=101491
149 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
150 /* Asus K73TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
151 * https://bugzilla.kernel.org/show_bug.cgi?id=51381#c52
153 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2123, RADEON_PX_QUIRK_DISABLE_PX },
157 bool radeon_is_px(struct drm_device *dev)
159 struct radeon_device *rdev = dev->dev_private;
161 if (rdev->flags & RADEON_IS_PX)
166 static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
168 struct radeon_px_quirk *p = radeon_px_quirk_list;
170 /* Apply PX quirks */
171 while (p && p->chip_device != 0) {
172 if (rdev->pdev->vendor == p->chip_vendor &&
173 rdev->pdev->device == p->chip_device &&
174 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
175 rdev->pdev->subsystem_device == p->subsys_device) {
176 rdev->px_quirk_flags = p->px_quirk_flags;
182 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
183 rdev->flags &= ~RADEON_IS_PX;
185 /* disable PX is the system doesn't support dGPU power control or hybrid gfx */
186 if (!radeon_is_atpx_hybrid() &&
187 !radeon_has_atpx_dgpu_power_cntl())
188 rdev->flags &= ~RADEON_IS_PX;
192 * radeon_program_register_sequence - program an array of registers.
194 * @rdev: radeon_device pointer
195 * @registers: pointer to the register array
196 * @array_size: size of the register array
198 * Programs an array or registers with and and or masks.
199 * This is a helper for setting golden registers.
201 void radeon_program_register_sequence(struct radeon_device *rdev,
202 const u32 *registers,
203 const u32 array_size)
205 u32 tmp, reg, and_mask, or_mask;
211 for (i = 0; i < array_size; i +=3) {
212 reg = registers[i + 0];
213 and_mask = registers[i + 1];
214 or_mask = registers[i + 2];
216 if (and_mask == 0xffffffff) {
227 void radeon_pci_config_reset(struct radeon_device *rdev)
229 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
233 * radeon_surface_init - Clear GPU surface registers.
235 * @rdev: radeon_device pointer
237 * Clear GPU surface registers (r1xx-r5xx).
239 void radeon_surface_init(struct radeon_device *rdev)
241 /* FIXME: check this out */
242 if (rdev->family < CHIP_R600) {
245 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
246 if (rdev->surface_regs[i].bo)
247 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
249 radeon_clear_surface_reg(rdev, i);
251 /* enable surfaces */
252 WREG32(RADEON_SURFACE_CNTL, 0);
257 * GPU scratch registers helpers function.
260 * radeon_scratch_init - Init scratch register driver information.
262 * @rdev: radeon_device pointer
264 * Init CP scratch register driver information (r1xx-r5xx)
266 void radeon_scratch_init(struct radeon_device *rdev)
270 /* FIXME: check this out */
271 if (rdev->family < CHIP_R300) {
272 rdev->scratch.num_reg = 5;
274 rdev->scratch.num_reg = 7;
276 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
277 for (i = 0; i < rdev->scratch.num_reg; i++) {
278 rdev->scratch.free[i] = true;
279 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
284 * radeon_scratch_get - Allocate a scratch register
286 * @rdev: radeon_device pointer
287 * @reg: scratch register mmio offset
289 * Allocate a CP scratch register for use by the driver (all asics).
290 * Returns 0 on success or -EINVAL on failure.
292 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
296 for (i = 0; i < rdev->scratch.num_reg; i++) {
297 if (rdev->scratch.free[i]) {
298 rdev->scratch.free[i] = false;
299 *reg = rdev->scratch.reg[i];
307 * radeon_scratch_free - Free a scratch register
309 * @rdev: radeon_device pointer
310 * @reg: scratch register mmio offset
312 * Free a CP scratch register allocated for use by the driver (all asics)
314 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
318 for (i = 0; i < rdev->scratch.num_reg; i++) {
319 if (rdev->scratch.reg[i] == reg) {
320 rdev->scratch.free[i] = true;
327 * GPU doorbell aperture helpers function.
330 * radeon_doorbell_init - Init doorbell driver information.
332 * @rdev: radeon_device pointer
334 * Init doorbell driver information (CIK)
335 * Returns 0 on success, error on failure.
337 static int radeon_doorbell_init(struct radeon_device *rdev)
339 /* doorbell bar mapping */
340 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
341 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
343 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
344 if (rdev->doorbell.num_doorbells == 0)
347 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
348 if (rdev->doorbell.ptr == NULL) {
351 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
352 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
354 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
360 * radeon_doorbell_fini - Tear down doorbell driver information.
362 * @rdev: radeon_device pointer
364 * Tear down doorbell driver information (CIK)
366 static void radeon_doorbell_fini(struct radeon_device *rdev)
368 iounmap(rdev->doorbell.ptr);
369 rdev->doorbell.ptr = NULL;
373 * radeon_doorbell_get - Allocate a doorbell entry
375 * @rdev: radeon_device pointer
376 * @doorbell: doorbell index
378 * Allocate a doorbell for use by the driver (all asics).
379 * Returns 0 on success or -EINVAL on failure.
381 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
383 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
384 if (offset < rdev->doorbell.num_doorbells) {
385 __set_bit(offset, rdev->doorbell.used);
394 * radeon_doorbell_free - Free a doorbell entry
396 * @rdev: radeon_device pointer
397 * @doorbell: doorbell index
399 * Free a doorbell allocated for use by the driver (all asics)
401 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
403 if (doorbell < rdev->doorbell.num_doorbells)
404 __clear_bit(doorbell, rdev->doorbell.used);
409 * Writeback is the the method by which the the GPU updates special pages
410 * in memory with the status of certain GPU events (fences, ring pointers,
415 * radeon_wb_disable - Disable Writeback
417 * @rdev: radeon_device pointer
419 * Disables Writeback (all asics). Used for suspend.
421 void radeon_wb_disable(struct radeon_device *rdev)
423 rdev->wb.enabled = false;
427 * radeon_wb_fini - Disable Writeback and free memory
429 * @rdev: radeon_device pointer
431 * Disables Writeback and frees the Writeback memory (all asics).
432 * Used at driver shutdown.
434 void radeon_wb_fini(struct radeon_device *rdev)
436 radeon_wb_disable(rdev);
437 if (rdev->wb.wb_obj) {
438 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
439 radeon_bo_kunmap(rdev->wb.wb_obj);
440 radeon_bo_unpin(rdev->wb.wb_obj);
441 radeon_bo_unreserve(rdev->wb.wb_obj);
443 radeon_bo_unref(&rdev->wb.wb_obj);
445 rdev->wb.wb_obj = NULL;
450 * radeon_wb_init- Init Writeback driver info and allocate memory
452 * @rdev: radeon_device pointer
454 * Disables Writeback and frees the Writeback memory (all asics).
455 * Used at driver startup.
456 * Returns 0 on success or an -error on failure.
458 int radeon_wb_init(struct radeon_device *rdev)
462 if (rdev->wb.wb_obj == NULL) {
463 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
464 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
467 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
470 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
471 if (unlikely(r != 0)) {
472 radeon_wb_fini(rdev);
475 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
478 radeon_bo_unreserve(rdev->wb.wb_obj);
479 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
480 radeon_wb_fini(rdev);
483 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
484 radeon_bo_unreserve(rdev->wb.wb_obj);
486 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
487 radeon_wb_fini(rdev);
492 /* clear wb memory */
493 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
494 /* disable event_write fences */
495 rdev->wb.use_event = false;
496 /* disabled via module param */
497 if (radeon_no_wb == 1) {
498 rdev->wb.enabled = false;
500 if (rdev->flags & RADEON_IS_AGP) {
501 /* often unreliable on AGP */
502 rdev->wb.enabled = false;
503 } else if (rdev->family < CHIP_R300) {
504 /* often unreliable on pre-r300 */
505 rdev->wb.enabled = false;
507 rdev->wb.enabled = true;
508 /* event_write fences are only available on r600+ */
509 if (rdev->family >= CHIP_R600) {
510 rdev->wb.use_event = true;
514 /* always use writeback/events on NI, APUs */
515 if (rdev->family >= CHIP_PALM) {
516 rdev->wb.enabled = true;
517 rdev->wb.use_event = true;
520 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
526 * radeon_vram_location - try to find VRAM location
527 * @rdev: radeon device structure holding all necessary informations
528 * @mc: memory controller structure holding memory informations
529 * @base: base address at which to put VRAM
531 * Function will place try to place VRAM at base address provided
532 * as parameter (which is so far either PCI aperture address or
533 * for IGP TOM base address).
535 * If there is not enough space to fit the unvisible VRAM in the 32bits
536 * address space then we limit the VRAM size to the aperture.
538 * If we are using AGP and if the AGP aperture doesn't allow us to have
539 * room for all the VRAM than we restrict the VRAM to the PCI aperture
540 * size and print a warning.
542 * This function will never fails, worst case are limiting VRAM.
544 * Note: GTT start, end, size should be initialized before calling this
545 * function on AGP platform.
547 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
548 * this shouldn't be a problem as we are using the PCI aperture as a reference.
549 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
552 * Note: we use mc_vram_size as on some board we need to program the mc to
553 * cover the whole aperture even if VRAM size is inferior to aperture size
554 * Novell bug 204882 + along with lots of ubuntu ones
556 * Note: when limiting vram it's safe to overwritte real_vram_size because
557 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
558 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
561 * Note: IGP TOM addr should be the same as the aperture addr, we don't
562 * explicitly check for that thought.
564 * FIXME: when reducing VRAM size align new size on power of 2.
566 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
568 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
570 mc->vram_start = base;
571 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
572 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
573 mc->real_vram_size = mc->aper_size;
574 mc->mc_vram_size = mc->aper_size;
576 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
577 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
578 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
579 mc->real_vram_size = mc->aper_size;
580 mc->mc_vram_size = mc->aper_size;
582 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
583 if (limit && limit < mc->real_vram_size)
584 mc->real_vram_size = limit;
585 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
586 mc->mc_vram_size >> 20, mc->vram_start,
587 mc->vram_end, mc->real_vram_size >> 20);
591 * radeon_gtt_location - try to find GTT location
592 * @rdev: radeon device structure holding all necessary informations
593 * @mc: memory controller structure holding memory informations
595 * Function will place try to place GTT before or after VRAM.
597 * If GTT size is bigger than space left then we ajust GTT size.
598 * Thus function will never fails.
600 * FIXME: when reducing GTT size align new size on power of 2.
602 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
604 u64 size_af, size_bf;
606 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
607 size_bf = mc->vram_start & ~mc->gtt_base_align;
608 if (size_bf > size_af) {
609 if (mc->gtt_size > size_bf) {
610 dev_warn(rdev->dev, "limiting GTT\n");
611 mc->gtt_size = size_bf;
613 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
615 if (mc->gtt_size > size_af) {
616 dev_warn(rdev->dev, "limiting GTT\n");
617 mc->gtt_size = size_af;
619 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
621 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
622 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
623 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
627 * GPU helpers function.
631 * radeon_device_is_virtual - check if we are running is a virtual environment
633 * Check if the asic has been passed through to a VM (all asics).
634 * Used at driver startup.
635 * Returns true if virtual or false if not.
637 bool radeon_device_is_virtual(void)
640 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
647 * radeon_card_posted - check if the hw has already been initialized
649 * @rdev: radeon_device pointer
651 * Check if the asic has been initialized (all asics).
652 * Used at driver startup.
653 * Returns true if initialized or false if not.
655 bool radeon_card_posted(struct radeon_device *rdev)
659 /* for pass through, always force asic_init for CI */
660 if (rdev->family >= CHIP_BONAIRE &&
661 radeon_device_is_virtual())
664 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
665 if (efi_enabled(EFI_BOOT) &&
666 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
667 (rdev->family < CHIP_R600))
670 if (ASIC_IS_NODCE(rdev))
673 /* first check CRTCs */
674 if (ASIC_IS_DCE4(rdev)) {
675 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
676 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
677 if (rdev->num_crtc >= 4) {
678 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
679 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
681 if (rdev->num_crtc >= 6) {
682 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
683 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
685 if (reg & EVERGREEN_CRTC_MASTER_EN)
687 } else if (ASIC_IS_AVIVO(rdev)) {
688 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
689 RREG32(AVIVO_D2CRTC_CONTROL);
690 if (reg & AVIVO_CRTC_EN) {
694 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
695 RREG32(RADEON_CRTC2_GEN_CNTL);
696 if (reg & RADEON_CRTC_EN) {
702 /* then check MEM_SIZE, in case the crtcs are off */
703 if (rdev->family >= CHIP_R600)
704 reg = RREG32(R600_CONFIG_MEMSIZE);
706 reg = RREG32(RADEON_CONFIG_MEMSIZE);
716 * radeon_update_bandwidth_info - update display bandwidth params
718 * @rdev: radeon_device pointer
720 * Used when sclk/mclk are switched or display modes are set.
721 * params are used to calculate display watermarks (all asics)
723 void radeon_update_bandwidth_info(struct radeon_device *rdev)
726 u32 sclk = rdev->pm.current_sclk;
727 u32 mclk = rdev->pm.current_mclk;
729 /* sclk/mclk in Mhz */
730 a.full = dfixed_const(100);
731 rdev->pm.sclk.full = dfixed_const(sclk);
732 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
733 rdev->pm.mclk.full = dfixed_const(mclk);
734 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
736 if (rdev->flags & RADEON_IS_IGP) {
737 a.full = dfixed_const(16);
738 /* core_bandwidth = sclk(Mhz) * 16 */
739 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
744 * radeon_boot_test_post_card - check and possibly initialize the hw
746 * @rdev: radeon_device pointer
748 * Check if the asic is initialized and if not, attempt to initialize
750 * Returns true if initialized or false if not.
752 bool radeon_boot_test_post_card(struct radeon_device *rdev)
754 if (radeon_card_posted(rdev))
758 DRM_INFO("GPU not posted. posting now...\n");
759 if (rdev->is_atom_bios)
760 atom_asic_init(rdev->mode_info.atom_context);
762 radeon_combios_asic_init(rdev->ddev);
765 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
771 * radeon_dummy_page_init - init dummy page used by the driver
773 * @rdev: radeon_device pointer
775 * Allocate the dummy page used by the driver (all asics).
776 * This dummy page is used by the driver as a filler for gart entries
777 * when pages are taken out of the GART
778 * Returns 0 on sucess, -ENOMEM on failure.
780 int radeon_dummy_page_init(struct radeon_device *rdev)
782 if (rdev->dummy_page.page)
784 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
785 if (rdev->dummy_page.page == NULL)
787 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
788 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
789 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
790 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
791 __free_page(rdev->dummy_page.page);
792 rdev->dummy_page.page = NULL;
795 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr,
796 RADEON_GART_PAGE_DUMMY);
801 * radeon_dummy_page_fini - free dummy page used by the driver
803 * @rdev: radeon_device pointer
805 * Frees the dummy page used by the driver (all asics).
807 void radeon_dummy_page_fini(struct radeon_device *rdev)
809 if (rdev->dummy_page.page == NULL)
811 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
812 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
813 __free_page(rdev->dummy_page.page);
814 rdev->dummy_page.page = NULL;
818 /* ATOM accessor methods */
820 * ATOM is an interpreted byte code stored in tables in the vbios. The
821 * driver registers callbacks to access registers and the interpreter
822 * in the driver parses the tables and executes then to program specific
823 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
824 * atombios.h, and atom.c
828 * cail_pll_read - read PLL register
830 * @info: atom card_info pointer
831 * @reg: PLL register offset
833 * Provides a PLL register accessor for the atom interpreter (r4xx+).
834 * Returns the value of the PLL register.
836 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
838 struct radeon_device *rdev = info->dev->dev_private;
841 r = rdev->pll_rreg(rdev, reg);
846 * cail_pll_write - write PLL register
848 * @info: atom card_info pointer
849 * @reg: PLL register offset
850 * @val: value to write to the pll register
852 * Provides a PLL register accessor for the atom interpreter (r4xx+).
854 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
856 struct radeon_device *rdev = info->dev->dev_private;
858 rdev->pll_wreg(rdev, reg, val);
862 * cail_mc_read - read MC (Memory Controller) register
864 * @info: atom card_info pointer
865 * @reg: MC register offset
867 * Provides an MC register accessor for the atom interpreter (r4xx+).
868 * Returns the value of the MC register.
870 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
872 struct radeon_device *rdev = info->dev->dev_private;
875 r = rdev->mc_rreg(rdev, reg);
880 * cail_mc_write - write MC (Memory Controller) register
882 * @info: atom card_info pointer
883 * @reg: MC register offset
884 * @val: value to write to the pll register
886 * Provides a MC register accessor for the atom interpreter (r4xx+).
888 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
890 struct radeon_device *rdev = info->dev->dev_private;
892 rdev->mc_wreg(rdev, reg, val);
896 * cail_reg_write - write MMIO register
898 * @info: atom card_info pointer
899 * @reg: MMIO register offset
900 * @val: value to write to the pll register
902 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
904 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
906 struct radeon_device *rdev = info->dev->dev_private;
912 * cail_reg_read - read MMIO register
914 * @info: atom card_info pointer
915 * @reg: MMIO register offset
917 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
918 * Returns the value of the MMIO register.
920 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
922 struct radeon_device *rdev = info->dev->dev_private;
930 * cail_ioreg_write - write IO register
932 * @info: atom card_info pointer
933 * @reg: IO register offset
934 * @val: value to write to the pll register
936 * Provides a IO register accessor for the atom interpreter (r4xx+).
938 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
940 struct radeon_device *rdev = info->dev->dev_private;
942 WREG32_IO(reg*4, val);
946 * cail_ioreg_read - read IO register
948 * @info: atom card_info pointer
949 * @reg: IO register offset
951 * Provides an IO register accessor for the atom interpreter (r4xx+).
952 * Returns the value of the IO register.
954 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
956 struct radeon_device *rdev = info->dev->dev_private;
959 r = RREG32_IO(reg*4);
964 * radeon_atombios_init - init the driver info and callbacks for atombios
966 * @rdev: radeon_device pointer
968 * Initializes the driver info and register access callbacks for the
969 * ATOM interpreter (r4xx+).
970 * Returns 0 on sucess, -ENOMEM on failure.
971 * Called at driver startup.
973 int radeon_atombios_init(struct radeon_device *rdev)
975 struct card_info *atom_card_info =
976 kzalloc(sizeof(struct card_info), GFP_KERNEL);
981 rdev->mode_info.atom_card_info = atom_card_info;
982 atom_card_info->dev = rdev->ddev;
983 atom_card_info->reg_read = cail_reg_read;
984 atom_card_info->reg_write = cail_reg_write;
985 /* needed for iio ops */
987 atom_card_info->ioreg_read = cail_ioreg_read;
988 atom_card_info->ioreg_write = cail_ioreg_write;
990 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
991 atom_card_info->ioreg_read = cail_reg_read;
992 atom_card_info->ioreg_write = cail_reg_write;
994 atom_card_info->mc_read = cail_mc_read;
995 atom_card_info->mc_write = cail_mc_write;
996 atom_card_info->pll_read = cail_pll_read;
997 atom_card_info->pll_write = cail_pll_write;
999 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
1000 if (!rdev->mode_info.atom_context) {
1001 radeon_atombios_fini(rdev);
1005 mutex_init(&rdev->mode_info.atom_context->mutex);
1006 mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
1007 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1008 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1013 * radeon_atombios_fini - free the driver info and callbacks for atombios
1015 * @rdev: radeon_device pointer
1017 * Frees the driver info and register access callbacks for the ATOM
1018 * interpreter (r4xx+).
1019 * Called at driver shutdown.
1021 void radeon_atombios_fini(struct radeon_device *rdev)
1023 if (rdev->mode_info.atom_context) {
1024 kfree(rdev->mode_info.atom_context->scratch);
1026 kfree(rdev->mode_info.atom_context);
1027 rdev->mode_info.atom_context = NULL;
1028 kfree(rdev->mode_info.atom_card_info);
1029 rdev->mode_info.atom_card_info = NULL;
1034 * COMBIOS is the bios format prior to ATOM. It provides
1035 * command tables similar to ATOM, but doesn't have a unified
1036 * parser. See radeon_combios.c
1040 * radeon_combios_init - init the driver info for combios
1042 * @rdev: radeon_device pointer
1044 * Initializes the driver info for combios (r1xx-r3xx).
1045 * Returns 0 on sucess.
1046 * Called at driver startup.
1048 int radeon_combios_init(struct radeon_device *rdev)
1050 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1055 * radeon_combios_fini - free the driver info for combios
1057 * @rdev: radeon_device pointer
1059 * Frees the driver info for combios (r1xx-r3xx).
1060 * Called at driver shutdown.
1062 void radeon_combios_fini(struct radeon_device *rdev)
1066 /* if we get transitioned to only one device, take VGA back */
1068 * radeon_vga_set_decode - enable/disable vga decode
1070 * @cookie: radeon_device pointer
1071 * @state: enable/disable vga decode
1073 * Enable/disable vga decode (all asics).
1074 * Returns VGA resource flags.
1076 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
1078 struct radeon_device *rdev = cookie;
1079 radeon_vga_set_state(rdev, state);
1081 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1082 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1084 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1088 * radeon_check_pot_argument - check that argument is a power of two
1090 * @arg: value to check
1092 * Validates that a certain argument is a power of two (all asics).
1093 * Returns true if argument is valid.
1095 static bool radeon_check_pot_argument(int arg)
1097 return (arg & (arg - 1)) == 0;
1101 * Determine a sensible default GART size according to ASIC family.
1103 * @family ASIC family name
1105 static int radeon_gart_size_auto(enum radeon_family family)
1107 /* default to a larger gart size on newer asics */
1108 if (family >= CHIP_TAHITI)
1110 else if (family >= CHIP_RV770)
1117 * radeon_check_arguments - validate module params
1119 * @rdev: radeon_device pointer
1121 * Validates certain module parameters and updates
1122 * the associated values used by the driver (all asics).
1124 static void radeon_check_arguments(struct radeon_device *rdev)
1126 /* vramlimit must be a power of two */
1127 if (!radeon_check_pot_argument(radeon_vram_limit)) {
1128 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1130 radeon_vram_limit = 0;
1133 if (radeon_gart_size == -1) {
1134 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1136 /* gtt size must be power of two and greater or equal to 32M */
1137 if (radeon_gart_size < 32) {
1138 dev_warn(rdev->dev, "gart size (%d) too small\n",
1140 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1141 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
1142 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1144 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1146 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1148 /* AGP mode can only be -1, 1, 2, 4, 8 */
1149 switch (radeon_agpmode) {
1158 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1159 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1164 if (!radeon_check_pot_argument(radeon_vm_size)) {
1165 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1170 if (radeon_vm_size < 1) {
1171 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n",
1177 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1179 if (radeon_vm_size > 1024) {
1180 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1185 /* defines number of bits in page table versus page directory,
1186 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1187 * page table and the remaining bits are in the page directory */
1188 if (radeon_vm_block_size == -1) {
1190 /* Total bits covered by PD + PTs */
1191 unsigned bits = ilog2(radeon_vm_size) + 18;
1193 /* Make sure the PD is 4K in size up to 8GB address space.
1194 Above that split equal between PD and PTs */
1195 if (radeon_vm_size <= 8)
1196 radeon_vm_block_size = bits - 9;
1198 radeon_vm_block_size = (bits + 3) / 2;
1200 } else if (radeon_vm_block_size < 9) {
1201 dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1202 radeon_vm_block_size);
1203 radeon_vm_block_size = 9;
1206 if (radeon_vm_block_size > 24 ||
1207 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
1208 dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1209 radeon_vm_block_size);
1210 radeon_vm_block_size = 9;
1215 * radeon_switcheroo_set_state - set switcheroo state
1217 * @pdev: pci dev pointer
1218 * @state: vga_switcheroo state
1220 * Callback for the switcheroo driver. Suspends or resumes the
1221 * the asics before or after it is powered up using ACPI methods.
1223 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1225 struct drm_device *dev = pci_get_drvdata(pdev);
1227 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1230 if (state == VGA_SWITCHEROO_ON) {
1231 pr_info("radeon: switched on\n");
1232 /* don't suspend or resume card normally */
1233 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1235 radeon_resume_kms(dev, true, true);
1237 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1238 drm_kms_helper_poll_enable(dev);
1240 pr_info("radeon: switched off\n");
1241 drm_kms_helper_poll_disable(dev);
1242 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1243 radeon_suspend_kms(dev, true, true, false);
1244 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1249 * radeon_switcheroo_can_switch - see if switcheroo state can change
1251 * @pdev: pci dev pointer
1253 * Callback for the switcheroo driver. Check of the switcheroo
1254 * state can be changed.
1255 * Returns true if the state can be changed, false if not.
1257 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1259 struct drm_device *dev = pci_get_drvdata(pdev);
1262 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1263 * locking inversion with the driver load path. And the access here is
1264 * completely racy anyway. So don't bother with locking for now.
1266 return dev->open_count == 0;
1269 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1270 .set_gpu_state = radeon_switcheroo_set_state,
1272 .can_switch = radeon_switcheroo_can_switch,
1276 * radeon_device_init - initialize the driver
1278 * @rdev: radeon_device pointer
1279 * @pdev: drm dev pointer
1280 * @pdev: pci dev pointer
1281 * @flags: driver flags
1283 * Initializes the driver info and hw (all asics).
1284 * Returns 0 for success or an error on failure.
1285 * Called at driver startup.
1287 int radeon_device_init(struct radeon_device *rdev,
1288 struct drm_device *ddev,
1289 struct pci_dev *pdev,
1294 bool runtime = false;
1296 rdev->shutdown = false;
1297 rdev->dev = &pdev->dev;
1300 rdev->flags = flags;
1301 rdev->family = flags & RADEON_FAMILY_MASK;
1302 rdev->is_atom_bios = false;
1303 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1304 rdev->mc.gtt_size = 512 * 1024 * 1024;
1305 rdev->accel_working = false;
1306 /* set up ring ids */
1307 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1308 rdev->ring[i].idx = i;
1310 rdev->fence_context = dma_fence_context_alloc(RADEON_NUM_RINGS);
1312 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1313 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1314 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1316 /* mutex initialization are all done here so we
1317 * can recall function without having locking issues */
1318 mutex_init(&rdev->ring_lock);
1319 mutex_init(&rdev->dc_hw_i2c_mutex);
1320 atomic_set(&rdev->ih.lock, 0);
1321 mutex_init(&rdev->gem.mutex);
1322 mutex_init(&rdev->pm.mutex);
1323 mutex_init(&rdev->gpu_clock_mutex);
1324 mutex_init(&rdev->srbm_mutex);
1325 init_rwsem(&rdev->pm.mclk_lock);
1326 init_rwsem(&rdev->exclusive_lock);
1327 init_waitqueue_head(&rdev->irq.vblank_queue);
1328 r = radeon_gem_init(rdev);
1332 radeon_check_arguments(rdev);
1333 /* Adjust VM size here.
1334 * Max GPUVM size for cayman+ is 40 bits.
1336 rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1338 /* Set asic functions */
1339 r = radeon_asic_init(rdev);
1343 /* all of the newer IGP chips have an internal gart
1344 * However some rs4xx report as AGP, so remove that here.
1346 if ((rdev->family >= CHIP_RS400) &&
1347 (rdev->flags & RADEON_IS_IGP)) {
1348 rdev->flags &= ~RADEON_IS_AGP;
1351 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1352 radeon_agp_disable(rdev);
1355 /* Set the internal MC address mask
1356 * This is the max address of the GPU's
1357 * internal address space.
1359 if (rdev->family >= CHIP_CAYMAN)
1360 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1361 else if (rdev->family >= CHIP_CEDAR)
1362 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1364 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1367 * PCIE - can handle 40-bits.
1368 * IGP - can handle 40-bits
1369 * AGP - generally dma32 is safest
1370 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1373 if (rdev->flags & RADEON_IS_AGP)
1375 if ((rdev->flags & RADEON_IS_PCI) &&
1376 (rdev->family <= CHIP_RS740))
1379 if (rdev->family == CHIP_CEDAR)
1383 r = dma_set_mask_and_coherent(&rdev->pdev->dev, DMA_BIT_MASK(dma_bits));
1385 pr_warn("radeon: No suitable DMA available\n");
1388 rdev->need_swiotlb = drm_need_swiotlb(dma_bits);
1390 /* Registers mapping */
1391 /* TODO: block userspace mapping of io register */
1392 spin_lock_init(&rdev->mmio_idx_lock);
1393 spin_lock_init(&rdev->smc_idx_lock);
1394 spin_lock_init(&rdev->pll_idx_lock);
1395 spin_lock_init(&rdev->mc_idx_lock);
1396 spin_lock_init(&rdev->pcie_idx_lock);
1397 spin_lock_init(&rdev->pciep_idx_lock);
1398 spin_lock_init(&rdev->pif_idx_lock);
1399 spin_lock_init(&rdev->cg_idx_lock);
1400 spin_lock_init(&rdev->uvd_idx_lock);
1401 spin_lock_init(&rdev->rcu_idx_lock);
1402 spin_lock_init(&rdev->didt_idx_lock);
1403 spin_lock_init(&rdev->end_idx_lock);
1404 if (rdev->family >= CHIP_BONAIRE) {
1405 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1406 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1408 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1409 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1411 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1412 if (rdev->rmmio == NULL)
1415 /* doorbell bar mapping */
1416 if (rdev->family >= CHIP_BONAIRE)
1417 radeon_doorbell_init(rdev);
1419 /* io port mapping */
1420 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1421 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1422 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1423 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1427 if (rdev->rio_mem == NULL)
1428 DRM_ERROR("Unable to find PCI I/O BAR\n");
1430 if (rdev->flags & RADEON_IS_PX)
1431 radeon_device_handle_px_quirks(rdev);
1433 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1434 /* this will fail for cards that aren't VGA class devices, just
1436 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1438 if (rdev->flags & RADEON_IS_PX)
1440 if (!pci_is_thunderbolt_attached(rdev->pdev))
1441 vga_switcheroo_register_client(rdev->pdev,
1442 &radeon_switcheroo_ops, runtime);
1444 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1446 r = radeon_init(rdev);
1450 r = radeon_gem_debugfs_init(rdev);
1452 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1455 r = radeon_mst_debugfs_init(rdev);
1457 DRM_ERROR("registering mst debugfs failed (%d).\n", r);
1460 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1461 /* Acceleration not working on AGP card try again
1462 * with fallback to PCI or PCIE GART
1464 radeon_asic_reset(rdev);
1466 radeon_agp_disable(rdev);
1467 r = radeon_init(rdev);
1472 r = radeon_ib_ring_tests(rdev);
1474 DRM_ERROR("ib ring test failed (%d).\n", r);
1477 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted
1478 * after the CP ring have chew one packet at least. Hence here we stop
1479 * and restart DPM after the radeon_ib_ring_tests().
1481 if (rdev->pm.dpm_enabled &&
1482 (rdev->pm.pm_method == PM_METHOD_DPM) &&
1483 (rdev->family == CHIP_TURKS) &&
1484 (rdev->flags & RADEON_IS_MOBILITY)) {
1485 mutex_lock(&rdev->pm.mutex);
1486 radeon_dpm_disable(rdev);
1487 radeon_dpm_enable(rdev);
1488 mutex_unlock(&rdev->pm.mutex);
1491 if ((radeon_testing & 1)) {
1492 if (rdev->accel_working)
1493 radeon_test_moves(rdev);
1495 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1497 if ((radeon_testing & 2)) {
1498 if (rdev->accel_working)
1499 radeon_test_syncing(rdev);
1501 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1503 if (radeon_benchmarking) {
1504 if (rdev->accel_working)
1505 radeon_benchmark(rdev, radeon_benchmarking);
1507 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1512 /* balance pm_runtime_get_sync() in radeon_driver_unload_kms() */
1513 if (radeon_is_px(ddev))
1514 pm_runtime_put_noidle(ddev->dev);
1516 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1521 * radeon_device_fini - tear down the driver
1523 * @rdev: radeon_device pointer
1525 * Tear down the driver info (all asics).
1526 * Called at driver shutdown.
1528 void radeon_device_fini(struct radeon_device *rdev)
1530 DRM_INFO("radeon: finishing device.\n");
1531 rdev->shutdown = true;
1532 /* evict vram memory */
1533 radeon_bo_evict_vram(rdev);
1535 if (!pci_is_thunderbolt_attached(rdev->pdev))
1536 vga_switcheroo_unregister_client(rdev->pdev);
1537 if (rdev->flags & RADEON_IS_PX)
1538 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1539 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1541 pci_iounmap(rdev->pdev, rdev->rio_mem);
1542 rdev->rio_mem = NULL;
1543 iounmap(rdev->rmmio);
1545 if (rdev->family >= CHIP_BONAIRE)
1546 radeon_doorbell_fini(rdev);
1554 * radeon_suspend_kms - initiate device suspend
1556 * @pdev: drm dev pointer
1557 * @state: suspend state
1559 * Puts the hw in the suspend state (all asics).
1560 * Returns 0 for success or an error on failure.
1561 * Called at driver suspend.
1563 int radeon_suspend_kms(struct drm_device *dev, bool suspend,
1564 bool fbcon, bool freeze)
1566 struct radeon_device *rdev;
1567 struct drm_crtc *crtc;
1568 struct drm_connector *connector;
1571 if (dev == NULL || dev->dev_private == NULL) {
1575 rdev = dev->dev_private;
1577 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1580 drm_kms_helper_poll_disable(dev);
1582 drm_modeset_lock_all(dev);
1583 /* turn off display hw */
1584 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1585 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1587 drm_modeset_unlock_all(dev);
1589 /* unpin the front buffers and cursors */
1590 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1591 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1592 struct drm_framebuffer *fb = crtc->primary->fb;
1593 struct radeon_bo *robj;
1595 if (radeon_crtc->cursor_bo) {
1596 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1597 r = radeon_bo_reserve(robj, false);
1599 radeon_bo_unpin(robj);
1600 radeon_bo_unreserve(robj);
1604 if (fb == NULL || fb->obj[0] == NULL) {
1607 robj = gem_to_radeon_bo(fb->obj[0]);
1608 /* don't unpin kernel fb objects */
1609 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1610 r = radeon_bo_reserve(robj, false);
1612 radeon_bo_unpin(robj);
1613 radeon_bo_unreserve(robj);
1617 /* evict vram memory */
1618 radeon_bo_evict_vram(rdev);
1620 /* wait for gpu to finish processing current batch */
1621 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1622 r = radeon_fence_wait_empty(rdev, i);
1624 /* delay GPU reset to resume */
1625 radeon_fence_driver_force_completion(rdev, i);
1629 radeon_save_bios_scratch_regs(rdev);
1631 radeon_suspend(rdev);
1632 radeon_hpd_fini(rdev);
1633 /* evict remaining vram memory
1634 * This second call to evict vram is to evict the gart page table
1637 radeon_bo_evict_vram(rdev);
1639 radeon_agp_suspend(rdev);
1641 pci_save_state(dev->pdev);
1642 if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {
1643 rdev->asic->asic_reset(rdev, true);
1644 pci_restore_state(dev->pdev);
1645 } else if (suspend) {
1646 /* Shut down the device */
1647 pci_disable_device(dev->pdev);
1648 pci_set_power_state(dev->pdev, PCI_D3hot);
1653 radeon_fbdev_set_suspend(rdev, 1);
1660 * radeon_resume_kms - initiate device resume
1662 * @pdev: drm dev pointer
1664 * Bring the hw back to operating state (all asics).
1665 * Returns 0 for success or an error on failure.
1666 * Called at driver resume.
1668 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1670 struct drm_connector *connector;
1671 struct radeon_device *rdev = dev->dev_private;
1672 struct drm_crtc *crtc;
1675 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1682 pci_set_power_state(dev->pdev, PCI_D0);
1683 pci_restore_state(dev->pdev);
1684 if (pci_enable_device(dev->pdev)) {
1690 /* resume AGP if in use */
1691 radeon_agp_resume(rdev);
1692 radeon_resume(rdev);
1694 r = radeon_ib_ring_tests(rdev);
1696 DRM_ERROR("ib ring test failed (%d).\n", r);
1698 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1699 /* do dpm late init */
1700 r = radeon_pm_late_init(rdev);
1702 rdev->pm.dpm_enabled = false;
1703 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1706 /* resume old pm late */
1707 radeon_pm_resume(rdev);
1710 radeon_restore_bios_scratch_regs(rdev);
1713 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1714 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1716 if (radeon_crtc->cursor_bo) {
1717 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1718 r = radeon_bo_reserve(robj, false);
1720 /* Only 27 bit offset for legacy cursor */
1721 r = radeon_bo_pin_restricted(robj,
1722 RADEON_GEM_DOMAIN_VRAM,
1723 ASIC_IS_AVIVO(rdev) ?
1725 &radeon_crtc->cursor_addr);
1727 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1728 radeon_bo_unreserve(robj);
1733 /* init dig PHYs, disp eng pll */
1734 if (rdev->is_atom_bios) {
1735 radeon_atom_encoder_init(rdev);
1736 radeon_atom_disp_eng_pll_init(rdev);
1737 /* turn on the BL */
1738 if (rdev->mode_info.bl_encoder) {
1739 u8 bl_level = radeon_get_backlight_level(rdev,
1740 rdev->mode_info.bl_encoder);
1741 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1745 /* reset hpd state */
1746 radeon_hpd_init(rdev);
1747 /* blat the mode back in */
1749 drm_helper_resume_force_mode(dev);
1750 /* turn on display hw */
1751 drm_modeset_lock_all(dev);
1752 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1753 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1755 drm_modeset_unlock_all(dev);
1758 drm_kms_helper_poll_enable(dev);
1760 /* set the power state here in case we are a PX system or headless */
1761 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1762 radeon_pm_compute_clocks(rdev);
1765 radeon_fbdev_set_suspend(rdev, 0);
1773 * radeon_gpu_reset - reset the asic
1775 * @rdev: radeon device pointer
1777 * Attempt the reset the GPU if it has hung (all asics).
1778 * Returns 0 for success or an error on failure.
1780 int radeon_gpu_reset(struct radeon_device *rdev)
1782 unsigned ring_sizes[RADEON_NUM_RINGS];
1783 uint32_t *ring_data[RADEON_NUM_RINGS];
1790 down_write(&rdev->exclusive_lock);
1792 if (!rdev->needs_reset) {
1793 up_write(&rdev->exclusive_lock);
1797 atomic_inc(&rdev->gpu_reset_counter);
1799 radeon_save_bios_scratch_regs(rdev);
1801 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1802 radeon_suspend(rdev);
1803 radeon_hpd_fini(rdev);
1805 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1806 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1808 if (ring_sizes[i]) {
1810 dev_info(rdev->dev, "Saved %d dwords of commands "
1811 "on ring %d.\n", ring_sizes[i], i);
1815 r = radeon_asic_reset(rdev);
1817 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1818 radeon_resume(rdev);
1821 radeon_restore_bios_scratch_regs(rdev);
1823 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1824 if (!r && ring_data[i]) {
1825 radeon_ring_restore(rdev, &rdev->ring[i],
1826 ring_sizes[i], ring_data[i]);
1828 radeon_fence_driver_force_completion(rdev, i);
1829 kfree(ring_data[i]);
1833 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1834 /* do dpm late init */
1835 r = radeon_pm_late_init(rdev);
1837 rdev->pm.dpm_enabled = false;
1838 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1841 /* resume old pm late */
1842 radeon_pm_resume(rdev);
1845 /* init dig PHYs, disp eng pll */
1846 if (rdev->is_atom_bios) {
1847 radeon_atom_encoder_init(rdev);
1848 radeon_atom_disp_eng_pll_init(rdev);
1849 /* turn on the BL */
1850 if (rdev->mode_info.bl_encoder) {
1851 u8 bl_level = radeon_get_backlight_level(rdev,
1852 rdev->mode_info.bl_encoder);
1853 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1857 /* reset hpd state */
1858 radeon_hpd_init(rdev);
1860 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1862 rdev->in_reset = true;
1863 rdev->needs_reset = false;
1865 downgrade_write(&rdev->exclusive_lock);
1867 drm_helper_resume_force_mode(rdev->ddev);
1869 /* set the power state here in case we are a PX system or headless */
1870 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1871 radeon_pm_compute_clocks(rdev);
1874 r = radeon_ib_ring_tests(rdev);
1878 /* bad news, how to tell it to userspace ? */
1879 dev_info(rdev->dev, "GPU reset failed\n");
1882 rdev->needs_reset = r == -EAGAIN;
1883 rdev->in_reset = false;
1885 up_read(&rdev->exclusive_lock);
1893 int radeon_debugfs_add_files(struct radeon_device *rdev,
1894 struct drm_info_list *files,
1899 for (i = 0; i < rdev->debugfs_count; i++) {
1900 if (rdev->debugfs[i].files == files) {
1901 /* Already registered */
1906 i = rdev->debugfs_count + 1;
1907 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1908 DRM_ERROR("Reached maximum number of debugfs components.\n");
1909 DRM_ERROR("Report so we increase "
1910 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1913 rdev->debugfs[rdev->debugfs_count].files = files;
1914 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1915 rdev->debugfs_count = i;
1916 #if defined(CONFIG_DEBUG_FS)
1917 drm_debugfs_create_files(files, nfiles,
1918 rdev->ddev->primary->debugfs_root,
1919 rdev->ddev->primary);