2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/radeon_drm.h>
31 #include <asm/div64.h>
33 #include <linux/pm_runtime.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_edid.h>
37 #include <linux/gcd.h>
39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
58 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
62 for (i = 0; i < 256; i++) {
63 WREG32(AVIVO_DC_LUT_30_COLOR,
64 (radeon_crtc->lut_r[i] << 20) |
65 (radeon_crtc->lut_g[i] << 10) |
66 (radeon_crtc->lut_b[i] << 0));
69 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
70 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
73 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
75 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
76 struct drm_device *dev = crtc->dev;
77 struct radeon_device *rdev = dev->dev_private;
80 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
81 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
91 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
92 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
94 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
95 for (i = 0; i < 256; i++) {
96 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
97 (radeon_crtc->lut_r[i] << 20) |
98 (radeon_crtc->lut_g[i] << 10) |
99 (radeon_crtc->lut_b[i] << 0));
103 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
105 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
106 struct drm_device *dev = crtc->dev;
107 struct radeon_device *rdev = dev->dev_private;
110 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
112 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
113 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
114 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
115 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
116 NI_GRPH_PRESCALE_BYPASS);
117 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
118 NI_OVL_PRESCALE_BYPASS);
119 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
120 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
121 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
123 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
133 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
134 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
136 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
137 for (i = 0; i < 256; i++) {
138 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
139 (radeon_crtc->lut_r[i] << 20) |
140 (radeon_crtc->lut_g[i] << 10) |
141 (radeon_crtc->lut_b[i] << 0));
144 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
145 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
148 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
149 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
150 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
151 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
152 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
153 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
154 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
155 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
156 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
157 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
158 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
159 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
160 if (ASIC_IS_DCE8(rdev)) {
161 /* XXX this only needs to be programmed once per crtc at startup,
162 * not sure where the best place for it is
164 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
165 CIK_CURSOR_ALPHA_BLND_ENA);
169 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
177 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
178 if (radeon_crtc->crtc_id == 0)
179 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
181 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
182 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
184 WREG8(RADEON_PALETTE_INDEX, 0);
185 for (i = 0; i < 256; i++) {
186 WREG32(RADEON_PALETTE_30_DATA,
187 (radeon_crtc->lut_r[i] << 20) |
188 (radeon_crtc->lut_g[i] << 10) |
189 (radeon_crtc->lut_b[i] << 0));
193 void radeon_crtc_load_lut(struct drm_crtc *crtc)
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
201 if (ASIC_IS_DCE5(rdev))
202 dce5_crtc_load_lut(crtc);
203 else if (ASIC_IS_DCE4(rdev))
204 dce4_crtc_load_lut(crtc);
205 else if (ASIC_IS_AVIVO(rdev))
206 avivo_crtc_load_lut(crtc);
208 legacy_crtc_load_lut(crtc);
211 /** Sets the color ramps on behalf of fbcon */
212 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
215 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
217 radeon_crtc->lut_r[regno] = red >> 6;
218 radeon_crtc->lut_g[regno] = green >> 6;
219 radeon_crtc->lut_b[regno] = blue >> 6;
222 /** Gets the color ramps on behalf of fbcon */
223 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
224 u16 *blue, int regno)
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
228 *red = radeon_crtc->lut_r[regno] << 6;
229 *green = radeon_crtc->lut_g[regno] << 6;
230 *blue = radeon_crtc->lut_b[regno] << 6;
233 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
234 u16 *blue, uint32_t start, uint32_t size)
236 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
237 int end = (start + size > 256) ? 256 : start + size, i;
239 /* userspace palettes are always correct as is */
240 for (i = start; i < end; i++) {
241 radeon_crtc->lut_r[i] = red[i] >> 6;
242 radeon_crtc->lut_g[i] = green[i] >> 6;
243 radeon_crtc->lut_b[i] = blue[i] >> 6;
245 radeon_crtc_load_lut(crtc);
248 static void radeon_crtc_destroy(struct drm_crtc *crtc)
250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
252 drm_crtc_cleanup(crtc);
253 destroy_workqueue(radeon_crtc->flip_queue);
258 * radeon_unpin_work_func - unpin old buffer object
260 * @__work - kernel work item
262 * Unpin the old frame buffer object outside of the interrupt handler
264 static void radeon_unpin_work_func(struct work_struct *__work)
266 struct radeon_flip_work *work =
267 container_of(__work, struct radeon_flip_work, unpin_work);
270 /* unpin of the old buffer */
271 r = radeon_bo_reserve(work->old_rbo, false);
272 if (likely(r == 0)) {
273 r = radeon_bo_unpin(work->old_rbo);
274 if (unlikely(r != 0)) {
275 DRM_ERROR("failed to unpin buffer after flip\n");
277 radeon_bo_unreserve(work->old_rbo);
279 DRM_ERROR("failed to reserve buffer after flip\n");
281 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
285 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
287 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
288 struct radeon_flip_work *work;
293 /* can happen during initialization */
294 if (radeon_crtc == NULL)
297 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
298 work = radeon_crtc->flip_work;
300 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
304 update_pending = radeon_page_flip_pending(rdev, crtc_id);
306 /* Has the pageflip already completed in crtc, or is it certain
307 * to complete in this vblank?
309 if (update_pending &&
310 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
311 &vpos, &hpos, NULL, NULL)) &&
312 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
313 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
314 /* crtc didn't flip in this target vblank interval,
315 * but flip is pending in crtc. Based on the current
316 * scanout position we know that the current frame is
317 * (nearly) complete and the flip will (likely)
318 * complete before the start of the next frame.
322 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
324 radeon_crtc_handle_flip(rdev, crtc_id);
328 * radeon_crtc_handle_flip - page flip completed
330 * @rdev: radeon device pointer
331 * @crtc_id: crtc number this event is for
333 * Called when we are sure that a page flip for this crtc is completed.
335 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
337 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
338 struct radeon_flip_work *work;
341 /* this can happen at init */
342 if (radeon_crtc == NULL)
345 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
346 work = radeon_crtc->flip_work;
348 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
352 /* Pageflip completed. Clean up. */
353 radeon_crtc->flip_work = NULL;
355 /* wakeup userspace */
357 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
359 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
361 radeon_fence_unref(&work->fence);
362 radeon_irq_kms_pflip_irq_get(rdev, work->crtc_id);
363 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
367 * radeon_flip_work_func - page flip framebuffer
369 * @work - kernel work item
371 * Wait for the buffer object to become idle and do the actual page flip
373 static void radeon_flip_work_func(struct work_struct *__work)
375 struct radeon_flip_work *work =
376 container_of(__work, struct radeon_flip_work, flip_work);
377 struct radeon_device *rdev = work->rdev;
378 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
380 struct drm_crtc *crtc = &radeon_crtc->base;
381 struct drm_framebuffer *fb = work->fb;
383 uint32_t tiling_flags, pitch_pixels;
389 down_read(&rdev->exclusive_lock);
390 while (work->fence) {
391 r = radeon_fence_wait(work->fence, false);
393 up_read(&rdev->exclusive_lock);
394 r = radeon_gpu_reset(rdev);
395 down_read(&rdev->exclusive_lock);
399 DRM_ERROR("failed to wait on page flip fence (%d)!\n",
403 radeon_fence_unref(&work->fence);
406 /* pin the new buffer */
407 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
408 work->old_rbo, work->new_rbo);
410 r = radeon_bo_reserve(work->new_rbo, false);
411 if (unlikely(r != 0)) {
412 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
415 /* Only 27 bit offset for legacy CRTC */
416 r = radeon_bo_pin_restricted(work->new_rbo, RADEON_GEM_DOMAIN_VRAM,
417 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
418 if (unlikely(r != 0)) {
419 radeon_bo_unreserve(work->new_rbo);
421 DRM_ERROR("failed to pin new rbo buffer before flip\n");
424 radeon_bo_get_tiling_flags(work->new_rbo, &tiling_flags, NULL);
425 radeon_bo_unreserve(work->new_rbo);
427 if (!ASIC_IS_AVIVO(rdev)) {
428 /* crtc offset is from display base addr not FB location */
429 base -= radeon_crtc->legacy_display_base_addr;
430 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
432 if (tiling_flags & RADEON_TILING_MACRO) {
433 if (ASIC_IS_R300(rdev)) {
436 int byteshift = fb->bits_per_pixel >> 4;
437 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
438 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
441 int offset = crtc->y * pitch_pixels + crtc->x;
442 switch (fb->bits_per_pixel) {
463 /* We borrow the event spin lock for protecting flip_work */
464 spin_lock_irqsave(&crtc->dev->event_lock, flags);
466 /* set the proper interrupt */
467 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
469 /* do the flip (mmio) */
470 radeon_page_flip(rdev, radeon_crtc->crtc_id, base);
472 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
473 up_read(&rdev->exclusive_lock);
478 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
479 radeon_fence_unref(&work->fence);
481 up_read(&rdev->exclusive_lock);
484 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
485 struct drm_framebuffer *fb,
486 struct drm_pending_vblank_event *event,
487 uint32_t page_flip_flags)
489 struct drm_device *dev = crtc->dev;
490 struct radeon_device *rdev = dev->dev_private;
491 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
492 struct radeon_framebuffer *old_radeon_fb;
493 struct radeon_framebuffer *new_radeon_fb;
494 struct drm_gem_object *obj;
495 struct radeon_flip_work *work;
498 work = kzalloc(sizeof *work, GFP_KERNEL);
502 INIT_WORK(&work->flip_work, radeon_flip_work_func);
503 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
506 work->crtc_id = radeon_crtc->crtc_id;
510 /* schedule unpin of the old buffer */
511 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
512 obj = old_radeon_fb->obj;
514 /* take a reference to the old object */
515 drm_gem_object_reference(obj);
516 work->old_rbo = gem_to_radeon_bo(obj);
518 new_radeon_fb = to_radeon_framebuffer(fb);
519 obj = new_radeon_fb->obj;
520 work->new_rbo = gem_to_radeon_bo(obj);
522 spin_lock(&work->new_rbo->tbo.bdev->fence_lock);
523 if (work->new_rbo->tbo.sync_obj)
524 work->fence = radeon_fence_ref(work->new_rbo->tbo.sync_obj);
525 spin_unlock(&work->new_rbo->tbo.bdev->fence_lock);
527 /* We borrow the event spin lock for protecting flip_work */
528 spin_lock_irqsave(&crtc->dev->event_lock, flags);
530 if (radeon_crtc->flip_work) {
531 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
532 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
533 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
534 radeon_fence_unref(&work->fence);
538 radeon_crtc->flip_work = work;
541 crtc->primary->fb = fb;
543 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
545 queue_work(radeon_crtc->flip_queue, &work->flip_work);
551 radeon_crtc_set_config(struct drm_mode_set *set)
553 struct drm_device *dev;
554 struct radeon_device *rdev;
555 struct drm_crtc *crtc;
559 if (!set || !set->crtc)
562 dev = set->crtc->dev;
564 ret = pm_runtime_get_sync(dev->dev);
568 ret = drm_crtc_helper_set_config(set);
570 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
574 pm_runtime_mark_last_busy(dev->dev);
576 rdev = dev->dev_private;
577 /* if we have active crtcs and we don't have a power ref,
578 take the current one */
579 if (active && !rdev->have_disp_power_ref) {
580 rdev->have_disp_power_ref = true;
583 /* if we have no active crtcs, then drop the power ref
585 if (!active && rdev->have_disp_power_ref) {
586 pm_runtime_put_autosuspend(dev->dev);
587 rdev->have_disp_power_ref = false;
590 /* drop the power reference we got coming in here */
591 pm_runtime_put_autosuspend(dev->dev);
594 static const struct drm_crtc_funcs radeon_crtc_funcs = {
595 .cursor_set = radeon_crtc_cursor_set,
596 .cursor_move = radeon_crtc_cursor_move,
597 .gamma_set = radeon_crtc_gamma_set,
598 .set_config = radeon_crtc_set_config,
599 .destroy = radeon_crtc_destroy,
600 .page_flip = radeon_crtc_page_flip,
603 static void radeon_crtc_init(struct drm_device *dev, int index)
605 struct radeon_device *rdev = dev->dev_private;
606 struct radeon_crtc *radeon_crtc;
609 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
610 if (radeon_crtc == NULL)
613 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
615 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
616 radeon_crtc->crtc_id = index;
617 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc");
618 rdev->mode_info.crtcs[index] = radeon_crtc;
620 if (rdev->family >= CHIP_BONAIRE) {
621 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
622 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
624 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
625 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
627 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
628 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
631 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
632 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
633 radeon_crtc->mode_set.num_connectors = 0;
636 for (i = 0; i < 256; i++) {
637 radeon_crtc->lut_r[i] = i << 2;
638 radeon_crtc->lut_g[i] = i << 2;
639 radeon_crtc->lut_b[i] = i << 2;
642 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
643 radeon_atombios_init_crtc(dev, radeon_crtc);
645 radeon_legacy_init_crtc(dev, radeon_crtc);
648 static const char *encoder_names[38] = {
668 "INTERNAL_KLDSCP_TMDS1",
669 "INTERNAL_KLDSCP_DVO1",
670 "INTERNAL_KLDSCP_DAC1",
671 "INTERNAL_KLDSCP_DAC2",
680 "INTERNAL_KLDSCP_LVTMA",
689 static const char *hpd_names[6] = {
698 static void radeon_print_display_setup(struct drm_device *dev)
700 struct drm_connector *connector;
701 struct radeon_connector *radeon_connector;
702 struct drm_encoder *encoder;
703 struct radeon_encoder *radeon_encoder;
707 DRM_INFO("Radeon Display Connectors\n");
708 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
709 radeon_connector = to_radeon_connector(connector);
710 DRM_INFO("Connector %d:\n", i);
711 DRM_INFO(" %s\n", connector->name);
712 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
713 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
714 if (radeon_connector->ddc_bus) {
715 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
716 radeon_connector->ddc_bus->rec.mask_clk_reg,
717 radeon_connector->ddc_bus->rec.mask_data_reg,
718 radeon_connector->ddc_bus->rec.a_clk_reg,
719 radeon_connector->ddc_bus->rec.a_data_reg,
720 radeon_connector->ddc_bus->rec.en_clk_reg,
721 radeon_connector->ddc_bus->rec.en_data_reg,
722 radeon_connector->ddc_bus->rec.y_clk_reg,
723 radeon_connector->ddc_bus->rec.y_data_reg);
724 if (radeon_connector->router.ddc_valid)
725 DRM_INFO(" DDC Router 0x%x/0x%x\n",
726 radeon_connector->router.ddc_mux_control_pin,
727 radeon_connector->router.ddc_mux_state);
728 if (radeon_connector->router.cd_valid)
729 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
730 radeon_connector->router.cd_mux_control_pin,
731 radeon_connector->router.cd_mux_state);
733 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
734 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
735 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
736 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
737 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
738 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
739 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
741 DRM_INFO(" Encoders:\n");
742 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
743 radeon_encoder = to_radeon_encoder(encoder);
744 devices = radeon_encoder->devices & radeon_connector->devices;
746 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
747 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
748 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
749 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
750 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
751 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
752 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
753 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
754 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
755 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
756 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
757 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
758 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
759 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
760 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
761 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
762 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
763 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
764 if (devices & ATOM_DEVICE_TV1_SUPPORT)
765 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
766 if (devices & ATOM_DEVICE_CV_SUPPORT)
767 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
774 static bool radeon_setup_enc_conn(struct drm_device *dev)
776 struct radeon_device *rdev = dev->dev_private;
780 if (rdev->is_atom_bios) {
781 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
783 ret = radeon_get_atom_connector_info_from_object_table(dev);
785 ret = radeon_get_legacy_connector_info_from_bios(dev);
787 ret = radeon_get_legacy_connector_info_from_table(dev);
790 if (!ASIC_IS_AVIVO(rdev))
791 ret = radeon_get_legacy_connector_info_from_table(dev);
794 radeon_setup_encoder_clones(dev);
795 radeon_print_display_setup(dev);
801 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
803 struct drm_device *dev = radeon_connector->base.dev;
804 struct radeon_device *rdev = dev->dev_private;
807 /* on hw with routers, select right port */
808 if (radeon_connector->router.ddc_valid)
809 radeon_router_select_ddc_port(radeon_connector);
811 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
812 ENCODER_OBJECT_ID_NONE) {
813 if (radeon_connector->ddc_bus->has_aux)
814 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
815 &radeon_connector->ddc_bus->aux.ddc);
816 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
817 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
818 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
820 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
821 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
822 radeon_connector->ddc_bus->has_aux)
823 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
824 &radeon_connector->ddc_bus->aux.ddc);
825 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
826 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
827 &radeon_connector->ddc_bus->adapter);
829 if (radeon_connector->ddc_bus && !radeon_connector->edid)
830 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
831 &radeon_connector->ddc_bus->adapter);
834 if (!radeon_connector->edid) {
835 if (rdev->is_atom_bios) {
836 /* some laptops provide a hardcoded edid in rom for LCDs */
837 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
838 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
839 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
841 /* some servers provide a hardcoded edid in rom for KVMs */
842 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
844 if (radeon_connector->edid) {
845 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
846 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
847 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
850 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
857 * avivo_reduce_ratio - fractional number reduction
861 * @nom_min: minimum value for nominator
862 * @den_min: minimum value for denominator
864 * Find the greatest common divisor and apply it on both nominator and
865 * denominator, but make nominator and denominator are at least as large
866 * as their minimum values.
868 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
869 unsigned nom_min, unsigned den_min)
873 /* reduce the numbers to a simpler ratio */
874 tmp = gcd(*nom, *den);
878 /* make sure nominator is large enough */
879 if (*nom < nom_min) {
880 tmp = DIV_ROUND_UP(nom_min, *nom);
885 /* make sure the denominator is large enough */
886 if (*den < den_min) {
887 tmp = DIV_ROUND_UP(den_min, *den);
894 * avivo_get_fb_ref_div - feedback and ref divider calculation
898 * @post_div: post divider
899 * @fb_div_max: feedback divider maximum
900 * @ref_div_max: reference divider maximum
901 * @fb_div: resulting feedback divider
902 * @ref_div: resulting reference divider
904 * Calculate feedback and reference divider for a given post divider. Makes
905 * sure we stay within the limits.
907 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
908 unsigned fb_div_max, unsigned ref_div_max,
909 unsigned *fb_div, unsigned *ref_div)
911 /* limit reference * post divider to a maximum */
912 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
914 /* get matching reference and feedback divider */
915 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
916 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
918 /* limit fb divider to its maximum */
919 if (*fb_div > fb_div_max) {
920 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
921 *fb_div = fb_div_max;
926 * radeon_compute_pll_avivo - compute PLL paramaters
928 * @pll: information about the PLL
929 * @dot_clock_p: resulting pixel clock
930 * fb_div_p: resulting feedback divider
931 * frac_fb_div_p: fractional part of the feedback divider
932 * ref_div_p: resulting reference divider
933 * post_div_p: resulting reference divider
935 * Try to calculate the PLL parameters to generate the given frequency:
936 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
938 void radeon_compute_pll_avivo(struct radeon_pll *pll,
946 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
949 unsigned fb_div_min, fb_div_max, fb_div;
950 unsigned post_div_min, post_div_max, post_div;
951 unsigned ref_div_min, ref_div_max, ref_div;
952 unsigned post_div_best, diff_best;
955 /* determine allowed feedback divider range */
956 fb_div_min = pll->min_feedback_div;
957 fb_div_max = pll->max_feedback_div;
959 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
964 /* determine allowed ref divider range */
965 if (pll->flags & RADEON_PLL_USE_REF_DIV)
966 ref_div_min = pll->reference_div;
968 ref_div_min = pll->min_ref_div;
970 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
971 pll->flags & RADEON_PLL_USE_REF_DIV)
972 ref_div_max = pll->reference_div;
974 ref_div_max = pll->max_ref_div;
976 /* determine allowed post divider range */
977 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
978 post_div_min = pll->post_div;
979 post_div_max = pll->post_div;
981 unsigned vco_min, vco_max;
983 if (pll->flags & RADEON_PLL_IS_LCD) {
984 vco_min = pll->lcd_pll_out_min;
985 vco_max = pll->lcd_pll_out_max;
987 vco_min = pll->pll_out_min;
988 vco_max = pll->pll_out_max;
991 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
996 post_div_min = vco_min / target_clock;
997 if ((target_clock * post_div_min) < vco_min)
999 if (post_div_min < pll->min_post_div)
1000 post_div_min = pll->min_post_div;
1002 post_div_max = vco_max / target_clock;
1003 if ((target_clock * post_div_max) > vco_max)
1005 if (post_div_max > pll->max_post_div)
1006 post_div_max = pll->max_post_div;
1009 /* represent the searched ratio as fractional number */
1011 den = pll->reference_freq;
1013 /* reduce the numbers to a simpler ratio */
1014 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1016 /* now search for a post divider */
1017 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1018 post_div_best = post_div_min;
1020 post_div_best = post_div_max;
1023 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1025 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1026 ref_div_max, &fb_div, &ref_div);
1027 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1028 (ref_div * post_div));
1030 if (diff < diff_best || (diff == diff_best &&
1031 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1033 post_div_best = post_div;
1037 post_div = post_div_best;
1039 /* get the feedback and reference divider for the optimal value */
1040 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1043 /* reduce the numbers to a simpler ratio once more */
1044 /* this also makes sure that the reference divider is large enough */
1045 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1047 /* avoid high jitter with small fractional dividers */
1048 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1049 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1050 if (fb_div < fb_div_min) {
1051 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1057 /* and finally save the result */
1058 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1059 *fb_div_p = fb_div / 10;
1060 *frac_fb_div_p = fb_div % 10;
1066 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1067 (pll->reference_freq * *frac_fb_div_p)) /
1068 (ref_div * post_div * 10);
1069 *ref_div_p = ref_div;
1070 *post_div_p = post_div;
1072 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1073 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1078 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1088 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1090 uint32_t *dot_clock_p,
1092 uint32_t *frac_fb_div_p,
1093 uint32_t *ref_div_p,
1094 uint32_t *post_div_p)
1096 uint32_t min_ref_div = pll->min_ref_div;
1097 uint32_t max_ref_div = pll->max_ref_div;
1098 uint32_t min_post_div = pll->min_post_div;
1099 uint32_t max_post_div = pll->max_post_div;
1100 uint32_t min_fractional_feed_div = 0;
1101 uint32_t max_fractional_feed_div = 0;
1102 uint32_t best_vco = pll->best_vco;
1103 uint32_t best_post_div = 1;
1104 uint32_t best_ref_div = 1;
1105 uint32_t best_feedback_div = 1;
1106 uint32_t best_frac_feedback_div = 0;
1107 uint32_t best_freq = -1;
1108 uint32_t best_error = 0xffffffff;
1109 uint32_t best_vco_diff = 1;
1111 u32 pll_out_min, pll_out_max;
1113 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1116 if (pll->flags & RADEON_PLL_IS_LCD) {
1117 pll_out_min = pll->lcd_pll_out_min;
1118 pll_out_max = pll->lcd_pll_out_max;
1120 pll_out_min = pll->pll_out_min;
1121 pll_out_max = pll->pll_out_max;
1124 if (pll_out_min > 64800)
1125 pll_out_min = 64800;
1127 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1128 min_ref_div = max_ref_div = pll->reference_div;
1130 while (min_ref_div < max_ref_div-1) {
1131 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1132 uint32_t pll_in = pll->reference_freq / mid;
1133 if (pll_in < pll->pll_in_min)
1135 else if (pll_in > pll->pll_in_max)
1142 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1143 min_post_div = max_post_div = pll->post_div;
1145 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1146 min_fractional_feed_div = pll->min_frac_feedback_div;
1147 max_fractional_feed_div = pll->max_frac_feedback_div;
1150 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1153 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1156 /* legacy radeons only have a few post_divs */
1157 if (pll->flags & RADEON_PLL_LEGACY) {
1158 if ((post_div == 5) ||
1169 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1170 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1171 uint32_t pll_in = pll->reference_freq / ref_div;
1172 uint32_t min_feed_div = pll->min_feedback_div;
1173 uint32_t max_feed_div = pll->max_feedback_div + 1;
1175 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1178 while (min_feed_div < max_feed_div) {
1180 uint32_t min_frac_feed_div = min_fractional_feed_div;
1181 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1182 uint32_t frac_feedback_div;
1185 feedback_div = (min_feed_div + max_feed_div) / 2;
1187 tmp = (uint64_t)pll->reference_freq * feedback_div;
1188 vco = radeon_div(tmp, ref_div);
1190 if (vco < pll_out_min) {
1191 min_feed_div = feedback_div + 1;
1193 } else if (vco > pll_out_max) {
1194 max_feed_div = feedback_div;
1198 while (min_frac_feed_div < max_frac_feed_div) {
1199 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1200 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1201 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1202 current_freq = radeon_div(tmp, ref_div * post_div);
1204 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1205 if (freq < current_freq)
1208 error = freq - current_freq;
1210 error = abs(current_freq - freq);
1211 vco_diff = abs(vco - best_vco);
1213 if ((best_vco == 0 && error < best_error) ||
1215 ((best_error > 100 && error < best_error - 100) ||
1216 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1217 best_post_div = post_div;
1218 best_ref_div = ref_div;
1219 best_feedback_div = feedback_div;
1220 best_frac_feedback_div = frac_feedback_div;
1221 best_freq = current_freq;
1223 best_vco_diff = vco_diff;
1224 } else if (current_freq == freq) {
1225 if (best_freq == -1) {
1226 best_post_div = post_div;
1227 best_ref_div = ref_div;
1228 best_feedback_div = feedback_div;
1229 best_frac_feedback_div = frac_feedback_div;
1230 best_freq = current_freq;
1232 best_vco_diff = vco_diff;
1233 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1234 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1235 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1236 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1237 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1238 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1239 best_post_div = post_div;
1240 best_ref_div = ref_div;
1241 best_feedback_div = feedback_div;
1242 best_frac_feedback_div = frac_feedback_div;
1243 best_freq = current_freq;
1245 best_vco_diff = vco_diff;
1248 if (current_freq < freq)
1249 min_frac_feed_div = frac_feedback_div + 1;
1251 max_frac_feed_div = frac_feedback_div;
1253 if (current_freq < freq)
1254 min_feed_div = feedback_div + 1;
1256 max_feed_div = feedback_div;
1261 *dot_clock_p = best_freq / 10000;
1262 *fb_div_p = best_feedback_div;
1263 *frac_fb_div_p = best_frac_feedback_div;
1264 *ref_div_p = best_ref_div;
1265 *post_div_p = best_post_div;
1266 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1268 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1269 best_ref_div, best_post_div);
1273 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1275 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1277 if (radeon_fb->obj) {
1278 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1280 drm_framebuffer_cleanup(fb);
1284 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1285 struct drm_file *file_priv,
1286 unsigned int *handle)
1288 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1290 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1293 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1294 .destroy = radeon_user_framebuffer_destroy,
1295 .create_handle = radeon_user_framebuffer_create_handle,
1299 radeon_framebuffer_init(struct drm_device *dev,
1300 struct radeon_framebuffer *rfb,
1301 struct drm_mode_fb_cmd2 *mode_cmd,
1302 struct drm_gem_object *obj)
1306 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1307 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1315 static struct drm_framebuffer *
1316 radeon_user_framebuffer_create(struct drm_device *dev,
1317 struct drm_file *file_priv,
1318 struct drm_mode_fb_cmd2 *mode_cmd)
1320 struct drm_gem_object *obj;
1321 struct radeon_framebuffer *radeon_fb;
1324 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1326 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1327 "can't create framebuffer\n", mode_cmd->handles[0]);
1328 return ERR_PTR(-ENOENT);
1331 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1332 if (radeon_fb == NULL) {
1333 drm_gem_object_unreference_unlocked(obj);
1334 return ERR_PTR(-ENOMEM);
1337 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1340 drm_gem_object_unreference_unlocked(obj);
1341 return ERR_PTR(ret);
1344 return &radeon_fb->base;
1347 static void radeon_output_poll_changed(struct drm_device *dev)
1349 struct radeon_device *rdev = dev->dev_private;
1350 radeon_fb_output_poll_changed(rdev);
1353 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1354 .fb_create = radeon_user_framebuffer_create,
1355 .output_poll_changed = radeon_output_poll_changed
1358 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1363 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1364 { { TV_STD_NTSC, "ntsc" },
1365 { TV_STD_PAL, "pal" },
1366 { TV_STD_PAL_M, "pal-m" },
1367 { TV_STD_PAL_60, "pal-60" },
1368 { TV_STD_NTSC_J, "ntsc-j" },
1369 { TV_STD_SCART_PAL, "scart-pal" },
1370 { TV_STD_PAL_CN, "pal-cn" },
1371 { TV_STD_SECAM, "secam" },
1374 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1375 { { UNDERSCAN_OFF, "off" },
1376 { UNDERSCAN_ON, "on" },
1377 { UNDERSCAN_AUTO, "auto" },
1380 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1381 { { RADEON_AUDIO_DISABLE, "off" },
1382 { RADEON_AUDIO_ENABLE, "on" },
1383 { RADEON_AUDIO_AUTO, "auto" },
1386 /* XXX support different dither options? spatial, temporal, both, etc. */
1387 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1388 { { RADEON_FMT_DITHER_DISABLE, "off" },
1389 { RADEON_FMT_DITHER_ENABLE, "on" },
1392 static int radeon_modeset_create_props(struct radeon_device *rdev)
1396 if (rdev->is_atom_bios) {
1397 rdev->mode_info.coherent_mode_property =
1398 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1399 if (!rdev->mode_info.coherent_mode_property)
1403 if (!ASIC_IS_AVIVO(rdev)) {
1404 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1405 rdev->mode_info.tmds_pll_property =
1406 drm_property_create_enum(rdev->ddev, 0,
1408 radeon_tmds_pll_enum_list, sz);
1411 rdev->mode_info.load_detect_property =
1412 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1413 if (!rdev->mode_info.load_detect_property)
1416 drm_mode_create_scaling_mode_property(rdev->ddev);
1418 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1419 rdev->mode_info.tv_std_property =
1420 drm_property_create_enum(rdev->ddev, 0,
1422 radeon_tv_std_enum_list, sz);
1424 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1425 rdev->mode_info.underscan_property =
1426 drm_property_create_enum(rdev->ddev, 0,
1428 radeon_underscan_enum_list, sz);
1430 rdev->mode_info.underscan_hborder_property =
1431 drm_property_create_range(rdev->ddev, 0,
1432 "underscan hborder", 0, 128);
1433 if (!rdev->mode_info.underscan_hborder_property)
1436 rdev->mode_info.underscan_vborder_property =
1437 drm_property_create_range(rdev->ddev, 0,
1438 "underscan vborder", 0, 128);
1439 if (!rdev->mode_info.underscan_vborder_property)
1442 sz = ARRAY_SIZE(radeon_audio_enum_list);
1443 rdev->mode_info.audio_property =
1444 drm_property_create_enum(rdev->ddev, 0,
1446 radeon_audio_enum_list, sz);
1448 sz = ARRAY_SIZE(radeon_dither_enum_list);
1449 rdev->mode_info.dither_property =
1450 drm_property_create_enum(rdev->ddev, 0,
1452 radeon_dither_enum_list, sz);
1457 void radeon_update_display_priority(struct radeon_device *rdev)
1459 /* adjustment options for the display watermarks */
1460 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1461 /* set display priority to high for r3xx, rv515 chips
1462 * this avoids flickering due to underflow to the
1463 * display controllers during heavy acceleration.
1464 * Don't force high on rs4xx igp chips as it seems to
1465 * affect the sound card. See kernel bug 15982.
1467 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1468 !(rdev->flags & RADEON_IS_IGP))
1469 rdev->disp_priority = 2;
1471 rdev->disp_priority = 0;
1473 rdev->disp_priority = radeon_disp_priority;
1478 * Allocate hdmi structs and determine register offsets
1480 static void radeon_afmt_init(struct radeon_device *rdev)
1484 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1485 rdev->mode_info.afmt[i] = NULL;
1487 if (ASIC_IS_NODCE(rdev)) {
1489 } else if (ASIC_IS_DCE4(rdev)) {
1490 static uint32_t eg_offsets[] = {
1491 EVERGREEN_CRTC0_REGISTER_OFFSET,
1492 EVERGREEN_CRTC1_REGISTER_OFFSET,
1493 EVERGREEN_CRTC2_REGISTER_OFFSET,
1494 EVERGREEN_CRTC3_REGISTER_OFFSET,
1495 EVERGREEN_CRTC4_REGISTER_OFFSET,
1496 EVERGREEN_CRTC5_REGISTER_OFFSET,
1501 /* DCE8 has 7 audio blocks tied to DIG encoders */
1502 /* DCE6 has 6 audio blocks tied to DIG encoders */
1503 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1504 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1505 if (ASIC_IS_DCE8(rdev))
1507 else if (ASIC_IS_DCE6(rdev))
1509 else if (ASIC_IS_DCE5(rdev))
1511 else if (ASIC_IS_DCE41(rdev))
1516 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1517 for (i = 0; i < num_afmt; i++) {
1518 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1519 if (rdev->mode_info.afmt[i]) {
1520 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1521 rdev->mode_info.afmt[i]->id = i;
1524 } else if (ASIC_IS_DCE3(rdev)) {
1525 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1526 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1527 if (rdev->mode_info.afmt[0]) {
1528 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1529 rdev->mode_info.afmt[0]->id = 0;
1531 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1532 if (rdev->mode_info.afmt[1]) {
1533 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1534 rdev->mode_info.afmt[1]->id = 1;
1536 } else if (ASIC_IS_DCE2(rdev)) {
1537 /* DCE2 has at least 1 routable audio block */
1538 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1539 if (rdev->mode_info.afmt[0]) {
1540 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1541 rdev->mode_info.afmt[0]->id = 0;
1543 /* r6xx has 2 routable audio blocks */
1544 if (rdev->family >= CHIP_R600) {
1545 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1546 if (rdev->mode_info.afmt[1]) {
1547 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1548 rdev->mode_info.afmt[1]->id = 1;
1554 static void radeon_afmt_fini(struct radeon_device *rdev)
1558 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1559 kfree(rdev->mode_info.afmt[i]);
1560 rdev->mode_info.afmt[i] = NULL;
1564 int radeon_modeset_init(struct radeon_device *rdev)
1569 drm_mode_config_init(rdev->ddev);
1570 rdev->mode_info.mode_config_initialized = true;
1572 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1574 if (ASIC_IS_DCE5(rdev)) {
1575 rdev->ddev->mode_config.max_width = 16384;
1576 rdev->ddev->mode_config.max_height = 16384;
1577 } else if (ASIC_IS_AVIVO(rdev)) {
1578 rdev->ddev->mode_config.max_width = 8192;
1579 rdev->ddev->mode_config.max_height = 8192;
1581 rdev->ddev->mode_config.max_width = 4096;
1582 rdev->ddev->mode_config.max_height = 4096;
1585 rdev->ddev->mode_config.preferred_depth = 24;
1586 rdev->ddev->mode_config.prefer_shadow = 1;
1588 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1590 ret = radeon_modeset_create_props(rdev);
1595 /* init i2c buses */
1596 radeon_i2c_init(rdev);
1598 /* check combios for a valid hardcoded EDID - Sun servers */
1599 if (!rdev->is_atom_bios) {
1600 /* check for hardcoded EDID in BIOS */
1601 radeon_combios_check_hardcoded_edid(rdev);
1604 /* allocate crtcs */
1605 for (i = 0; i < rdev->num_crtc; i++) {
1606 radeon_crtc_init(rdev->ddev, i);
1609 /* okay we should have all the bios connectors */
1610 ret = radeon_setup_enc_conn(rdev->ddev);
1615 /* init dig PHYs, disp eng pll */
1616 if (rdev->is_atom_bios) {
1617 radeon_atom_encoder_init(rdev);
1618 radeon_atom_disp_eng_pll_init(rdev);
1621 /* initialize hpd */
1622 radeon_hpd_init(rdev);
1625 radeon_afmt_init(rdev);
1627 radeon_fbdev_init(rdev);
1628 drm_kms_helper_poll_init(rdev->ddev);
1630 if (rdev->pm.dpm_enabled) {
1631 /* do dpm late init */
1632 ret = radeon_pm_late_init(rdev);
1634 rdev->pm.dpm_enabled = false;
1635 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1637 /* set the dpm state for PX since there won't be
1638 * a modeset to call this.
1640 radeon_pm_compute_clocks(rdev);
1646 void radeon_modeset_fini(struct radeon_device *rdev)
1648 radeon_fbdev_fini(rdev);
1649 kfree(rdev->mode_info.bios_hardcoded_edid);
1651 if (rdev->mode_info.mode_config_initialized) {
1652 radeon_afmt_fini(rdev);
1653 drm_kms_helper_poll_fini(rdev->ddev);
1654 radeon_hpd_fini(rdev);
1655 drm_mode_config_cleanup(rdev->ddev);
1656 rdev->mode_info.mode_config_initialized = false;
1658 /* free i2c buses */
1659 radeon_i2c_fini(rdev);
1662 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1664 /* try and guess if this is a tv or a monitor */
1665 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1666 (mode->vdisplay == 576) || /* 576p */
1667 (mode->vdisplay == 720) || /* 720p */
1668 (mode->vdisplay == 1080)) /* 1080p */
1674 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1675 const struct drm_display_mode *mode,
1676 struct drm_display_mode *adjusted_mode)
1678 struct drm_device *dev = crtc->dev;
1679 struct radeon_device *rdev = dev->dev_private;
1680 struct drm_encoder *encoder;
1681 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1682 struct radeon_encoder *radeon_encoder;
1683 struct drm_connector *connector;
1684 struct radeon_connector *radeon_connector;
1686 u32 src_v = 1, dst_v = 1;
1687 u32 src_h = 1, dst_h = 1;
1689 radeon_crtc->h_border = 0;
1690 radeon_crtc->v_border = 0;
1692 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1693 if (encoder->crtc != crtc)
1695 radeon_encoder = to_radeon_encoder(encoder);
1696 connector = radeon_get_connector_for_encoder(encoder);
1697 radeon_connector = to_radeon_connector(connector);
1701 if (radeon_encoder->rmx_type == RMX_OFF)
1702 radeon_crtc->rmx_type = RMX_OFF;
1703 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1704 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1705 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1707 radeon_crtc->rmx_type = RMX_OFF;
1708 /* copy native mode */
1709 memcpy(&radeon_crtc->native_mode,
1710 &radeon_encoder->native_mode,
1711 sizeof(struct drm_display_mode));
1712 src_v = crtc->mode.vdisplay;
1713 dst_v = radeon_crtc->native_mode.vdisplay;
1714 src_h = crtc->mode.hdisplay;
1715 dst_h = radeon_crtc->native_mode.hdisplay;
1717 /* fix up for overscan on hdmi */
1718 if (ASIC_IS_AVIVO(rdev) &&
1719 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1720 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1721 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1722 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1723 is_hdtv_mode(mode)))) {
1724 if (radeon_encoder->underscan_hborder != 0)
1725 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1727 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1728 if (radeon_encoder->underscan_vborder != 0)
1729 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1731 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1732 radeon_crtc->rmx_type = RMX_FULL;
1733 src_v = crtc->mode.vdisplay;
1734 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1735 src_h = crtc->mode.hdisplay;
1736 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1740 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1741 /* WARNING: Right now this can't happen but
1742 * in the future we need to check that scaling
1743 * are consistent across different encoder
1744 * (ie all encoder can work with the same
1747 DRM_ERROR("Scaling not consistent across encoder.\n");
1752 if (radeon_crtc->rmx_type != RMX_OFF) {
1754 a.full = dfixed_const(src_v);
1755 b.full = dfixed_const(dst_v);
1756 radeon_crtc->vsc.full = dfixed_div(a, b);
1757 a.full = dfixed_const(src_h);
1758 b.full = dfixed_const(dst_h);
1759 radeon_crtc->hsc.full = dfixed_div(a, b);
1761 radeon_crtc->vsc.full = dfixed_const(1);
1762 radeon_crtc->hsc.full = dfixed_const(1);
1768 * Retrieve current video scanout position of crtc on a given gpu, and
1769 * an optional accurate timestamp of when query happened.
1771 * \param dev Device to query.
1772 * \param crtc Crtc to query.
1773 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1774 * \param *vpos Location where vertical scanout position should be stored.
1775 * \param *hpos Location where horizontal scanout position should go.
1776 * \param *stime Target location for timestamp taken immediately before
1777 * scanout position query. Can be NULL to skip timestamp.
1778 * \param *etime Target location for timestamp taken immediately after
1779 * scanout position query. Can be NULL to skip timestamp.
1781 * Returns vpos as a positive number while in active scanout area.
1782 * Returns vpos as a negative number inside vblank, counting the number
1783 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1784 * until start of active scanout / end of vblank."
1786 * \return Flags, or'ed together as follows:
1788 * DRM_SCANOUTPOS_VALID = Query successful.
1789 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1790 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1791 * this flag means that returned position may be offset by a constant but
1792 * unknown small number of scanlines wrt. real scanout position.
1795 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1796 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1798 u32 stat_crtc = 0, vbl = 0, position = 0;
1799 int vbl_start, vbl_end, vtotal, ret = 0;
1802 struct radeon_device *rdev = dev->dev_private;
1804 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1806 /* Get optional system timestamp before query. */
1808 *stime = ktime_get();
1810 if (ASIC_IS_DCE4(rdev)) {
1812 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1813 EVERGREEN_CRTC0_REGISTER_OFFSET);
1814 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1815 EVERGREEN_CRTC0_REGISTER_OFFSET);
1816 ret |= DRM_SCANOUTPOS_VALID;
1819 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1820 EVERGREEN_CRTC1_REGISTER_OFFSET);
1821 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1822 EVERGREEN_CRTC1_REGISTER_OFFSET);
1823 ret |= DRM_SCANOUTPOS_VALID;
1826 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1827 EVERGREEN_CRTC2_REGISTER_OFFSET);
1828 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1829 EVERGREEN_CRTC2_REGISTER_OFFSET);
1830 ret |= DRM_SCANOUTPOS_VALID;
1833 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1834 EVERGREEN_CRTC3_REGISTER_OFFSET);
1835 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1836 EVERGREEN_CRTC3_REGISTER_OFFSET);
1837 ret |= DRM_SCANOUTPOS_VALID;
1840 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1841 EVERGREEN_CRTC4_REGISTER_OFFSET);
1842 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1843 EVERGREEN_CRTC4_REGISTER_OFFSET);
1844 ret |= DRM_SCANOUTPOS_VALID;
1847 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1848 EVERGREEN_CRTC5_REGISTER_OFFSET);
1849 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1850 EVERGREEN_CRTC5_REGISTER_OFFSET);
1851 ret |= DRM_SCANOUTPOS_VALID;
1853 } else if (ASIC_IS_AVIVO(rdev)) {
1855 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1856 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1857 ret |= DRM_SCANOUTPOS_VALID;
1860 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1861 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1862 ret |= DRM_SCANOUTPOS_VALID;
1865 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1867 /* Assume vbl_end == 0, get vbl_start from
1870 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1871 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1872 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1873 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1874 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1875 if (!(stat_crtc & 1))
1878 ret |= DRM_SCANOUTPOS_VALID;
1881 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1882 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1883 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1884 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1885 if (!(stat_crtc & 1))
1888 ret |= DRM_SCANOUTPOS_VALID;
1892 /* Get optional system timestamp after query. */
1894 *etime = ktime_get();
1896 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1898 /* Decode into vertical and horizontal scanout position. */
1899 *vpos = position & 0x1fff;
1900 *hpos = (position >> 16) & 0x1fff;
1902 /* Valid vblank area boundaries from gpu retrieved? */
1905 ret |= DRM_SCANOUTPOS_ACCURATE;
1906 vbl_start = vbl & 0x1fff;
1907 vbl_end = (vbl >> 16) & 0x1fff;
1910 /* No: Fake something reasonable which gives at least ok results. */
1911 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1915 /* Test scanout position against vblank region. */
1916 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1919 /* Check if inside vblank area and apply corrective offsets:
1920 * vpos will then be >=0 in video scanout area, but negative
1921 * within vblank area, counting down the number of lines until
1925 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1926 if (in_vbl && (*vpos >= vbl_start)) {
1927 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1928 *vpos = *vpos - vtotal;
1931 /* Correct for shifted end of vbl at vbl_end. */
1932 *vpos = *vpos - vbl_end;
1936 ret |= DRM_SCANOUTPOS_INVBL;
1938 /* Is vpos outside nominal vblank area, but less than
1939 * 1/100 of a frame height away from start of vblank?
1940 * If so, assume this isn't a massively delayed vblank
1941 * interrupt, but a vblank interrupt that fired a few
1942 * microseconds before true start of vblank. Compensate
1943 * by adding a full frame duration to the final timestamp.
1944 * Happens, e.g., on ATI R500, R600.
1946 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1948 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1949 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1950 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1952 if (vbl_start - *vpos < vtotal / 100) {
1955 /* Signal this correction as "applied". */