2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <linux/pci.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/gcd.h>
31 #include <asm/div64.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_device.h>
35 #include <drm/drm_drv.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_fourcc.h>
39 #include <drm/drm_gem_framebuffer_helper.h>
40 #include <drm/drm_plane_helper.h>
41 #include <drm/drm_probe_helper.h>
42 #include <drm/drm_vblank.h>
43 #include <drm/radeon_drm.h>
48 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc);
49 int radeon_enable_vblank_kms(struct drm_crtc *crtc);
50 void radeon_disable_vblank_kms(struct drm_crtc *crtc);
52 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
54 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
55 struct drm_device *dev = crtc->dev;
56 struct radeon_device *rdev = dev->dev_private;
60 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
61 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
63 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
64 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
65 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
67 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
68 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
69 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
71 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
72 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
73 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
75 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
76 r = crtc->gamma_store;
77 g = r + crtc->gamma_size;
78 b = g + crtc->gamma_size;
79 for (i = 0; i < 256; i++) {
80 WREG32(AVIVO_DC_LUT_30_COLOR,
81 ((*r++ & 0xffc0) << 14) |
82 ((*g++ & 0xffc0) << 4) |
86 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
87 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
90 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
92 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
93 struct drm_device *dev = crtc->dev;
94 struct radeon_device *rdev = dev->dev_private;
98 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
99 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
101 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
102 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
103 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
105 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
106 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
107 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
109 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
110 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
112 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
113 r = crtc->gamma_store;
114 g = r + crtc->gamma_size;
115 b = g + crtc->gamma_size;
116 for (i = 0; i < 256; i++) {
117 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
118 ((*r++ & 0xffc0) << 14) |
119 ((*g++ & 0xffc0) << 4) |
124 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
126 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
127 struct drm_device *dev = crtc->dev;
128 struct radeon_device *rdev = dev->dev_private;
132 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
136 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
137 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
138 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
139 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
140 NI_GRPH_PRESCALE_BYPASS);
141 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
142 NI_OVL_PRESCALE_BYPASS);
143 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
144 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
145 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
147 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
149 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
150 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
151 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
153 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
154 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
155 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
157 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
158 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
160 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
161 r = crtc->gamma_store;
162 g = r + crtc->gamma_size;
163 b = g + crtc->gamma_size;
164 for (i = 0; i < 256; i++) {
165 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
166 ((*r++ & 0xffc0) << 14) |
167 ((*g++ & 0xffc0) << 4) |
171 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
172 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
173 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
174 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
175 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
176 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
177 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
178 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
179 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
180 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
181 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
182 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
183 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
184 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
185 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
186 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
187 if (ASIC_IS_DCE8(rdev)) {
188 /* XXX this only needs to be programmed once per crtc at startup,
189 * not sure where the best place for it is
191 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
192 CIK_CURSOR_ALPHA_BLND_ENA);
196 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
199 struct drm_device *dev = crtc->dev;
200 struct radeon_device *rdev = dev->dev_private;
205 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
206 if (radeon_crtc->crtc_id == 0)
207 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
209 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
210 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
212 WREG8(RADEON_PALETTE_INDEX, 0);
213 r = crtc->gamma_store;
214 g = r + crtc->gamma_size;
215 b = g + crtc->gamma_size;
216 for (i = 0; i < 256; i++) {
217 WREG32(RADEON_PALETTE_30_DATA,
218 ((*r++ & 0xffc0) << 14) |
219 ((*g++ & 0xffc0) << 4) |
224 void radeon_crtc_load_lut(struct drm_crtc *crtc)
226 struct drm_device *dev = crtc->dev;
227 struct radeon_device *rdev = dev->dev_private;
232 if (ASIC_IS_DCE5(rdev))
233 dce5_crtc_load_lut(crtc);
234 else if (ASIC_IS_DCE4(rdev))
235 dce4_crtc_load_lut(crtc);
236 else if (ASIC_IS_AVIVO(rdev))
237 avivo_crtc_load_lut(crtc);
239 legacy_crtc_load_lut(crtc);
242 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
243 u16 *blue, uint32_t size,
244 struct drm_modeset_acquire_ctx *ctx)
246 radeon_crtc_load_lut(crtc);
251 static void radeon_crtc_destroy(struct drm_crtc *crtc)
253 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
255 drm_crtc_cleanup(crtc);
256 destroy_workqueue(radeon_crtc->flip_queue);
261 * radeon_unpin_work_func - unpin old buffer object
263 * @__work - kernel work item
265 * Unpin the old frame buffer object outside of the interrupt handler
267 static void radeon_unpin_work_func(struct work_struct *__work)
269 struct radeon_flip_work *work =
270 container_of(__work, struct radeon_flip_work, unpin_work);
273 /* unpin of the old buffer */
274 r = radeon_bo_reserve(work->old_rbo, false);
275 if (likely(r == 0)) {
276 radeon_bo_unpin(work->old_rbo);
277 radeon_bo_unreserve(work->old_rbo);
279 DRM_ERROR("failed to reserve buffer after flip\n");
281 drm_gem_object_put(&work->old_rbo->tbo.base);
285 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
287 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
292 /* can happen during initialization */
293 if (radeon_crtc == NULL)
296 /* Skip the pageflip completion check below (based on polling) on
297 * asics which reliably support hw pageflip completion irqs. pflip
298 * irqs are a reliable and race-free method of handling pageflip
299 * completion detection. A use_pflipirq module parameter < 2 allows
300 * to override this in case of asics with faulty pflip irqs.
301 * A module parameter of 0 would only use this polling based path,
302 * a parameter of 1 would use pflip irq only as a backup to this
303 * path, as in Linux 3.16.
305 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
308 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
309 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
310 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
311 "RADEON_FLIP_SUBMITTED(%d)\n",
312 radeon_crtc->flip_status,
313 RADEON_FLIP_SUBMITTED);
314 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
318 update_pending = radeon_page_flip_pending(rdev, crtc_id);
320 /* Has the pageflip already completed in crtc, or is it certain
321 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
322 * distance to start of "fudged earlier" vblank in vpos, distance to
323 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
324 * the last few scanlines before start of real vblank, where the vblank
325 * irq can fire, so we have sampled update_pending a bit too early and
326 * know the flip will complete at leading edge of the upcoming real
327 * vblank. On pre-AVIVO hardware, flips also complete inside the real
328 * vblank, not only at leading edge, so if update_pending for hpos >= 0
329 * == inside real vblank, the flip will complete almost immediately.
330 * Note that this method of completion handling is still not 100% race
331 * free, as we could execute before the radeon_flip_work_func managed
332 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
333 * but the flip still gets programmed into hw and completed during
334 * vblank, leading to a delayed emission of the flip completion event.
335 * This applies at least to pre-AVIVO hardware, where flips are always
336 * completing inside vblank, not only at leading edge of vblank.
338 if (update_pending &&
339 (DRM_SCANOUTPOS_VALID &
340 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
341 GET_DISTANCE_TO_VBLANKSTART,
342 &vpos, &hpos, NULL, NULL,
343 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
344 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
345 /* crtc didn't flip in this target vblank interval,
346 * but flip is pending in crtc. Based on the current
347 * scanout position we know that the current frame is
348 * (nearly) complete and the flip will (likely)
349 * complete before the start of the next frame.
353 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
355 radeon_crtc_handle_flip(rdev, crtc_id);
359 * radeon_crtc_handle_flip - page flip completed
361 * @rdev: radeon device pointer
362 * @crtc_id: crtc number this event is for
364 * Called when we are sure that a page flip for this crtc is completed.
366 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
368 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
369 struct radeon_flip_work *work;
372 /* this can happen at init */
373 if (radeon_crtc == NULL)
376 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
377 work = radeon_crtc->flip_work;
378 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
379 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
380 "RADEON_FLIP_SUBMITTED(%d)\n",
381 radeon_crtc->flip_status,
382 RADEON_FLIP_SUBMITTED);
383 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
387 /* Pageflip completed. Clean up. */
388 radeon_crtc->flip_status = RADEON_FLIP_NONE;
389 radeon_crtc->flip_work = NULL;
391 /* wakeup userspace */
393 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
395 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
397 drm_crtc_vblank_put(&radeon_crtc->base);
398 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
399 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
403 * radeon_flip_work_func - page flip framebuffer
405 * @work - kernel work item
407 * Wait for the buffer object to become idle and do the actual page flip
409 static void radeon_flip_work_func(struct work_struct *__work)
411 struct radeon_flip_work *work =
412 container_of(__work, struct radeon_flip_work, flip_work);
413 struct radeon_device *rdev = work->rdev;
414 struct drm_device *dev = rdev->ddev;
415 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
417 struct drm_crtc *crtc = &radeon_crtc->base;
422 down_read(&rdev->exclusive_lock);
424 struct radeon_fence *fence;
426 fence = to_radeon_fence(work->fence);
427 if (fence && fence->rdev == rdev) {
428 r = radeon_fence_wait(fence, false);
430 up_read(&rdev->exclusive_lock);
432 r = radeon_gpu_reset(rdev);
433 } while (r == -EAGAIN);
434 down_read(&rdev->exclusive_lock);
437 r = dma_fence_wait(work->fence, false);
440 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
442 /* We continue with the page flip even if we failed to wait on
443 * the fence, otherwise the DRM core and userspace will be
444 * confused about which BO the CRTC is scanning out
447 dma_fence_put(work->fence);
451 /* Wait until we're out of the vertical blank period before the one
452 * targeted by the flip. Always wait on pre DCE4 to avoid races with
453 * flip completion handling from vblank irq, as these old asics don't
454 * have reliable pageflip completion interrupts.
456 while (radeon_crtc->enabled &&
457 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
458 &vpos, &hpos, NULL, NULL,
460 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
461 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
462 (!ASIC_IS_AVIVO(rdev) ||
463 ((int) (work->target_vblank -
464 crtc->funcs->get_vblank_counter(crtc)) > 0)))
465 usleep_range(1000, 2000);
467 /* We borrow the event spin lock for protecting flip_status */
468 spin_lock_irqsave(&crtc->dev->event_lock, flags);
470 /* set the proper interrupt */
471 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
473 /* do the flip (mmio) */
474 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
476 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
477 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
478 up_read(&rdev->exclusive_lock);
481 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
482 struct drm_framebuffer *fb,
483 struct drm_pending_vblank_event *event,
484 uint32_t page_flip_flags,
486 struct drm_modeset_acquire_ctx *ctx)
488 struct drm_device *dev = crtc->dev;
489 struct radeon_device *rdev = dev->dev_private;
490 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
491 struct drm_gem_object *obj;
492 struct radeon_flip_work *work;
493 struct radeon_bo *new_rbo;
494 uint32_t tiling_flags, pitch_pixels;
499 work = kzalloc(sizeof *work, GFP_KERNEL);
503 INIT_WORK(&work->flip_work, radeon_flip_work_func);
504 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
507 work->crtc_id = radeon_crtc->crtc_id;
509 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
511 /* schedule unpin of the old buffer */
512 obj = crtc->primary->fb->obj[0];
514 /* take a reference to the old object */
515 drm_gem_object_get(obj);
516 work->old_rbo = gem_to_radeon_bo(obj);
519 new_rbo = gem_to_radeon_bo(obj);
521 /* pin the new buffer */
522 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
523 work->old_rbo, new_rbo);
525 r = radeon_bo_reserve(new_rbo, false);
526 if (unlikely(r != 0)) {
527 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
530 /* Only 27 bit offset for legacy CRTC */
531 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
532 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
533 if (unlikely(r != 0)) {
534 radeon_bo_unreserve(new_rbo);
536 DRM_ERROR("failed to pin new rbo buffer before flip\n");
539 work->fence = dma_fence_get(dma_resv_get_excl(new_rbo->tbo.base.resv));
540 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
541 radeon_bo_unreserve(new_rbo);
543 if (!ASIC_IS_AVIVO(rdev)) {
544 /* crtc offset is from display base addr not FB location */
545 base -= radeon_crtc->legacy_display_base_addr;
546 pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
548 if (tiling_flags & RADEON_TILING_MACRO) {
549 if (ASIC_IS_R300(rdev)) {
552 int byteshift = fb->format->cpp[0] * 8 >> 4;
553 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
554 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
557 int offset = crtc->y * pitch_pixels + crtc->x;
558 switch (fb->format->cpp[0] * 8) {
579 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
580 crtc->funcs->get_vblank_counter(crtc);
582 /* We borrow the event spin lock for protecting flip_work */
583 spin_lock_irqsave(&crtc->dev->event_lock, flags);
585 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
586 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
587 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
591 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
592 radeon_crtc->flip_work = work;
595 crtc->primary->fb = fb;
597 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
599 queue_work(radeon_crtc->flip_queue, &work->flip_work);
603 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
604 DRM_ERROR("failed to reserve new rbo in error path\n");
607 radeon_bo_unpin(new_rbo);
608 radeon_bo_unreserve(new_rbo);
611 drm_gem_object_put(&work->old_rbo->tbo.base);
612 dma_fence_put(work->fence);
618 radeon_crtc_set_config(struct drm_mode_set *set,
619 struct drm_modeset_acquire_ctx *ctx)
621 struct drm_device *dev;
622 struct radeon_device *rdev;
623 struct drm_crtc *crtc;
627 if (!set || !set->crtc)
630 dev = set->crtc->dev;
632 ret = pm_runtime_get_sync(dev->dev);
634 pm_runtime_put_autosuspend(dev->dev);
638 ret = drm_crtc_helper_set_config(set, ctx);
640 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
644 pm_runtime_mark_last_busy(dev->dev);
646 rdev = dev->dev_private;
647 /* if we have active crtcs and we don't have a power ref,
648 take the current one */
649 if (active && !rdev->have_disp_power_ref) {
650 rdev->have_disp_power_ref = true;
653 /* if we have no active crtcs, then drop the power ref
655 if (!active && rdev->have_disp_power_ref) {
656 pm_runtime_put_autosuspend(dev->dev);
657 rdev->have_disp_power_ref = false;
660 /* drop the power reference we got coming in here */
661 pm_runtime_put_autosuspend(dev->dev);
665 static const struct drm_crtc_funcs radeon_crtc_funcs = {
666 .cursor_set2 = radeon_crtc_cursor_set2,
667 .cursor_move = radeon_crtc_cursor_move,
668 .gamma_set = radeon_crtc_gamma_set,
669 .set_config = radeon_crtc_set_config,
670 .destroy = radeon_crtc_destroy,
671 .page_flip_target = radeon_crtc_page_flip_target,
672 .get_vblank_counter = radeon_get_vblank_counter_kms,
673 .enable_vblank = radeon_enable_vblank_kms,
674 .disable_vblank = radeon_disable_vblank_kms,
675 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
678 static void radeon_crtc_init(struct drm_device *dev, int index)
680 struct radeon_device *rdev = dev->dev_private;
681 struct radeon_crtc *radeon_crtc;
683 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
684 if (radeon_crtc == NULL)
687 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
689 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
690 radeon_crtc->crtc_id = index;
691 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
692 rdev->mode_info.crtcs[index] = radeon_crtc;
694 if (rdev->family >= CHIP_BONAIRE) {
695 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
696 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
698 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
699 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
701 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
702 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
705 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
706 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
707 radeon_crtc->mode_set.num_connectors = 0;
710 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
711 radeon_atombios_init_crtc(dev, radeon_crtc);
713 radeon_legacy_init_crtc(dev, radeon_crtc);
716 static const char *encoder_names[38] = {
736 "INTERNAL_KLDSCP_TMDS1",
737 "INTERNAL_KLDSCP_DVO1",
738 "INTERNAL_KLDSCP_DAC1",
739 "INTERNAL_KLDSCP_DAC2",
748 "INTERNAL_KLDSCP_LVTMA",
757 static const char *hpd_names[6] = {
766 static void radeon_print_display_setup(struct drm_device *dev)
768 struct drm_connector *connector;
769 struct radeon_connector *radeon_connector;
770 struct drm_encoder *encoder;
771 struct radeon_encoder *radeon_encoder;
775 DRM_INFO("Radeon Display Connectors\n");
776 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
777 radeon_connector = to_radeon_connector(connector);
778 DRM_INFO("Connector %d:\n", i);
779 DRM_INFO(" %s\n", connector->name);
780 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
781 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
782 if (radeon_connector->ddc_bus) {
783 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
784 radeon_connector->ddc_bus->rec.mask_clk_reg,
785 radeon_connector->ddc_bus->rec.mask_data_reg,
786 radeon_connector->ddc_bus->rec.a_clk_reg,
787 radeon_connector->ddc_bus->rec.a_data_reg,
788 radeon_connector->ddc_bus->rec.en_clk_reg,
789 radeon_connector->ddc_bus->rec.en_data_reg,
790 radeon_connector->ddc_bus->rec.y_clk_reg,
791 radeon_connector->ddc_bus->rec.y_data_reg);
792 if (radeon_connector->router.ddc_valid)
793 DRM_INFO(" DDC Router 0x%x/0x%x\n",
794 radeon_connector->router.ddc_mux_control_pin,
795 radeon_connector->router.ddc_mux_state);
796 if (radeon_connector->router.cd_valid)
797 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
798 radeon_connector->router.cd_mux_control_pin,
799 radeon_connector->router.cd_mux_state);
801 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
802 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
803 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
804 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
805 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
806 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
807 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
809 DRM_INFO(" Encoders:\n");
810 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
811 radeon_encoder = to_radeon_encoder(encoder);
812 devices = radeon_encoder->devices & radeon_connector->devices;
814 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
815 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
816 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
817 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
818 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
819 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
820 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
821 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
822 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
823 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
824 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
825 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
826 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
827 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
828 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
829 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
830 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
831 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
832 if (devices & ATOM_DEVICE_TV1_SUPPORT)
833 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
834 if (devices & ATOM_DEVICE_CV_SUPPORT)
835 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
842 static bool radeon_setup_enc_conn(struct drm_device *dev)
844 struct radeon_device *rdev = dev->dev_private;
848 if (rdev->is_atom_bios) {
849 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
851 ret = radeon_get_atom_connector_info_from_object_table(dev);
853 ret = radeon_get_legacy_connector_info_from_bios(dev);
855 ret = radeon_get_legacy_connector_info_from_table(dev);
858 if (!ASIC_IS_AVIVO(rdev))
859 ret = radeon_get_legacy_connector_info_from_table(dev);
862 radeon_setup_encoder_clones(dev);
863 radeon_print_display_setup(dev);
872 * avivo_reduce_ratio - fractional number reduction
876 * @nom_min: minimum value for nominator
877 * @den_min: minimum value for denominator
879 * Find the greatest common divisor and apply it on both nominator and
880 * denominator, but make nominator and denominator are at least as large
881 * as their minimum values.
883 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
884 unsigned nom_min, unsigned den_min)
888 /* reduce the numbers to a simpler ratio */
889 tmp = gcd(*nom, *den);
893 /* make sure nominator is large enough */
894 if (*nom < nom_min) {
895 tmp = DIV_ROUND_UP(nom_min, *nom);
900 /* make sure the denominator is large enough */
901 if (*den < den_min) {
902 tmp = DIV_ROUND_UP(den_min, *den);
909 * avivo_get_fb_ref_div - feedback and ref divider calculation
913 * @post_div: post divider
914 * @fb_div_max: feedback divider maximum
915 * @ref_div_max: reference divider maximum
916 * @fb_div: resulting feedback divider
917 * @ref_div: resulting reference divider
919 * Calculate feedback and reference divider for a given post divider. Makes
920 * sure we stay within the limits.
922 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
923 unsigned fb_div_max, unsigned ref_div_max,
924 unsigned *fb_div, unsigned *ref_div)
926 /* limit reference * post divider to a maximum */
927 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
929 /* get matching reference and feedback divider */
930 *ref_div = min(max(den/post_div, 1u), ref_div_max);
931 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
933 /* limit fb divider to its maximum */
934 if (*fb_div > fb_div_max) {
935 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
936 *fb_div = fb_div_max;
941 * radeon_compute_pll_avivo - compute PLL paramaters
943 * @pll: information about the PLL
944 * @dot_clock_p: resulting pixel clock
945 * fb_div_p: resulting feedback divider
946 * frac_fb_div_p: fractional part of the feedback divider
947 * ref_div_p: resulting reference divider
948 * post_div_p: resulting reference divider
950 * Try to calculate the PLL parameters to generate the given frequency:
951 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
953 void radeon_compute_pll_avivo(struct radeon_pll *pll,
961 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
964 unsigned fb_div_min, fb_div_max, fb_div;
965 unsigned post_div_min, post_div_max, post_div;
966 unsigned ref_div_min, ref_div_max, ref_div;
967 unsigned post_div_best, diff_best;
970 /* determine allowed feedback divider range */
971 fb_div_min = pll->min_feedback_div;
972 fb_div_max = pll->max_feedback_div;
974 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
979 /* determine allowed ref divider range */
980 if (pll->flags & RADEON_PLL_USE_REF_DIV)
981 ref_div_min = pll->reference_div;
983 ref_div_min = pll->min_ref_div;
985 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
986 pll->flags & RADEON_PLL_USE_REF_DIV)
987 ref_div_max = pll->reference_div;
988 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
989 /* fix for problems on RS880 */
990 ref_div_max = min(pll->max_ref_div, 7u);
992 ref_div_max = pll->max_ref_div;
994 /* determine allowed post divider range */
995 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
996 post_div_min = pll->post_div;
997 post_div_max = pll->post_div;
999 unsigned vco_min, vco_max;
1001 if (pll->flags & RADEON_PLL_IS_LCD) {
1002 vco_min = pll->lcd_pll_out_min;
1003 vco_max = pll->lcd_pll_out_max;
1005 vco_min = pll->pll_out_min;
1006 vco_max = pll->pll_out_max;
1009 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1014 post_div_min = vco_min / target_clock;
1015 if ((target_clock * post_div_min) < vco_min)
1017 if (post_div_min < pll->min_post_div)
1018 post_div_min = pll->min_post_div;
1020 post_div_max = vco_max / target_clock;
1021 if ((target_clock * post_div_max) > vco_max)
1023 if (post_div_max > pll->max_post_div)
1024 post_div_max = pll->max_post_div;
1027 /* represent the searched ratio as fractional number */
1029 den = pll->reference_freq;
1031 /* reduce the numbers to a simpler ratio */
1032 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1034 /* now search for a post divider */
1035 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1036 post_div_best = post_div_min;
1038 post_div_best = post_div_max;
1041 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1043 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1044 ref_div_max, &fb_div, &ref_div);
1045 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1046 (ref_div * post_div));
1048 if (diff < diff_best || (diff == diff_best &&
1049 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1051 post_div_best = post_div;
1055 post_div = post_div_best;
1057 /* get the feedback and reference divider for the optimal value */
1058 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1061 /* reduce the numbers to a simpler ratio once more */
1062 /* this also makes sure that the reference divider is large enough */
1063 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1065 /* avoid high jitter with small fractional dividers */
1066 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1067 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1068 if (fb_div < fb_div_min) {
1069 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1075 /* and finally save the result */
1076 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1077 *fb_div_p = fb_div / 10;
1078 *frac_fb_div_p = fb_div % 10;
1084 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1085 (pll->reference_freq * *frac_fb_div_p)) /
1086 (ref_div * post_div * 10);
1087 *ref_div_p = ref_div;
1088 *post_div_p = post_div;
1090 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1091 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1096 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1106 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1108 uint32_t *dot_clock_p,
1110 uint32_t *frac_fb_div_p,
1111 uint32_t *ref_div_p,
1112 uint32_t *post_div_p)
1114 uint32_t min_ref_div = pll->min_ref_div;
1115 uint32_t max_ref_div = pll->max_ref_div;
1116 uint32_t min_post_div = pll->min_post_div;
1117 uint32_t max_post_div = pll->max_post_div;
1118 uint32_t min_fractional_feed_div = 0;
1119 uint32_t max_fractional_feed_div = 0;
1120 uint32_t best_vco = pll->best_vco;
1121 uint32_t best_post_div = 1;
1122 uint32_t best_ref_div = 1;
1123 uint32_t best_feedback_div = 1;
1124 uint32_t best_frac_feedback_div = 0;
1125 uint32_t best_freq = -1;
1126 uint32_t best_error = 0xffffffff;
1127 uint32_t best_vco_diff = 1;
1129 u32 pll_out_min, pll_out_max;
1131 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1134 if (pll->flags & RADEON_PLL_IS_LCD) {
1135 pll_out_min = pll->lcd_pll_out_min;
1136 pll_out_max = pll->lcd_pll_out_max;
1138 pll_out_min = pll->pll_out_min;
1139 pll_out_max = pll->pll_out_max;
1142 if (pll_out_min > 64800)
1143 pll_out_min = 64800;
1145 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1146 min_ref_div = max_ref_div = pll->reference_div;
1148 while (min_ref_div < max_ref_div-1) {
1149 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1150 uint32_t pll_in = pll->reference_freq / mid;
1151 if (pll_in < pll->pll_in_min)
1153 else if (pll_in > pll->pll_in_max)
1160 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1161 min_post_div = max_post_div = pll->post_div;
1163 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1164 min_fractional_feed_div = pll->min_frac_feedback_div;
1165 max_fractional_feed_div = pll->max_frac_feedback_div;
1168 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1171 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1174 /* legacy radeons only have a few post_divs */
1175 if (pll->flags & RADEON_PLL_LEGACY) {
1176 if ((post_div == 5) ||
1187 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1188 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1189 uint32_t pll_in = pll->reference_freq / ref_div;
1190 uint32_t min_feed_div = pll->min_feedback_div;
1191 uint32_t max_feed_div = pll->max_feedback_div + 1;
1193 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1196 while (min_feed_div < max_feed_div) {
1198 uint32_t min_frac_feed_div = min_fractional_feed_div;
1199 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1200 uint32_t frac_feedback_div;
1203 feedback_div = (min_feed_div + max_feed_div) / 2;
1205 tmp = (uint64_t)pll->reference_freq * feedback_div;
1206 vco = radeon_div(tmp, ref_div);
1208 if (vco < pll_out_min) {
1209 min_feed_div = feedback_div + 1;
1211 } else if (vco > pll_out_max) {
1212 max_feed_div = feedback_div;
1216 while (min_frac_feed_div < max_frac_feed_div) {
1217 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1218 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1219 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1220 current_freq = radeon_div(tmp, ref_div * post_div);
1222 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1223 if (freq < current_freq)
1226 error = freq - current_freq;
1228 error = abs(current_freq - freq);
1229 vco_diff = abs(vco - best_vco);
1231 if ((best_vco == 0 && error < best_error) ||
1233 ((best_error > 100 && error < best_error - 100) ||
1234 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1235 best_post_div = post_div;
1236 best_ref_div = ref_div;
1237 best_feedback_div = feedback_div;
1238 best_frac_feedback_div = frac_feedback_div;
1239 best_freq = current_freq;
1241 best_vco_diff = vco_diff;
1242 } else if (current_freq == freq) {
1243 if (best_freq == -1) {
1244 best_post_div = post_div;
1245 best_ref_div = ref_div;
1246 best_feedback_div = feedback_div;
1247 best_frac_feedback_div = frac_feedback_div;
1248 best_freq = current_freq;
1250 best_vco_diff = vco_diff;
1251 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1252 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1253 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1254 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1255 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1256 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1257 best_post_div = post_div;
1258 best_ref_div = ref_div;
1259 best_feedback_div = feedback_div;
1260 best_frac_feedback_div = frac_feedback_div;
1261 best_freq = current_freq;
1263 best_vco_diff = vco_diff;
1266 if (current_freq < freq)
1267 min_frac_feed_div = frac_feedback_div + 1;
1269 max_frac_feed_div = frac_feedback_div;
1271 if (current_freq < freq)
1272 min_feed_div = feedback_div + 1;
1274 max_feed_div = feedback_div;
1279 *dot_clock_p = best_freq / 10000;
1280 *fb_div_p = best_feedback_div;
1281 *frac_fb_div_p = best_frac_feedback_div;
1282 *ref_div_p = best_ref_div;
1283 *post_div_p = best_post_div;
1284 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1286 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1287 best_ref_div, best_post_div);
1291 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1292 .destroy = drm_gem_fb_destroy,
1293 .create_handle = drm_gem_fb_create_handle,
1297 radeon_framebuffer_init(struct drm_device *dev,
1298 struct drm_framebuffer *fb,
1299 const struct drm_mode_fb_cmd2 *mode_cmd,
1300 struct drm_gem_object *obj)
1304 drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd);
1305 ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs);
1313 static struct drm_framebuffer *
1314 radeon_user_framebuffer_create(struct drm_device *dev,
1315 struct drm_file *file_priv,
1316 const struct drm_mode_fb_cmd2 *mode_cmd)
1318 struct drm_gem_object *obj;
1319 struct drm_framebuffer *fb;
1322 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1324 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1325 "can't create framebuffer\n", mode_cmd->handles[0]);
1326 return ERR_PTR(-ENOENT);
1329 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1330 if (obj->import_attach) {
1331 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1332 return ERR_PTR(-EINVAL);
1335 fb = kzalloc(sizeof(*fb), GFP_KERNEL);
1337 drm_gem_object_put(obj);
1338 return ERR_PTR(-ENOMEM);
1341 ret = radeon_framebuffer_init(dev, fb, mode_cmd, obj);
1344 drm_gem_object_put(obj);
1345 return ERR_PTR(ret);
1351 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1352 .fb_create = radeon_user_framebuffer_create,
1353 .output_poll_changed = drm_fb_helper_output_poll_changed,
1356 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1361 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1362 { { TV_STD_NTSC, "ntsc" },
1363 { TV_STD_PAL, "pal" },
1364 { TV_STD_PAL_M, "pal-m" },
1365 { TV_STD_PAL_60, "pal-60" },
1366 { TV_STD_NTSC_J, "ntsc-j" },
1367 { TV_STD_SCART_PAL, "scart-pal" },
1368 { TV_STD_PAL_CN, "pal-cn" },
1369 { TV_STD_SECAM, "secam" },
1372 static const struct drm_prop_enum_list radeon_underscan_enum_list[] =
1373 { { UNDERSCAN_OFF, "off" },
1374 { UNDERSCAN_ON, "on" },
1375 { UNDERSCAN_AUTO, "auto" },
1378 static const struct drm_prop_enum_list radeon_audio_enum_list[] =
1379 { { RADEON_AUDIO_DISABLE, "off" },
1380 { RADEON_AUDIO_ENABLE, "on" },
1381 { RADEON_AUDIO_AUTO, "auto" },
1384 /* XXX support different dither options? spatial, temporal, both, etc. */
1385 static const struct drm_prop_enum_list radeon_dither_enum_list[] =
1386 { { RADEON_FMT_DITHER_DISABLE, "off" },
1387 { RADEON_FMT_DITHER_ENABLE, "on" },
1390 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1391 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1392 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1393 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1394 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1397 static int radeon_modeset_create_props(struct radeon_device *rdev)
1401 if (rdev->is_atom_bios) {
1402 rdev->mode_info.coherent_mode_property =
1403 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1404 if (!rdev->mode_info.coherent_mode_property)
1408 if (!ASIC_IS_AVIVO(rdev)) {
1409 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1410 rdev->mode_info.tmds_pll_property =
1411 drm_property_create_enum(rdev->ddev, 0,
1413 radeon_tmds_pll_enum_list, sz);
1416 rdev->mode_info.load_detect_property =
1417 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1418 if (!rdev->mode_info.load_detect_property)
1421 drm_mode_create_scaling_mode_property(rdev->ddev);
1423 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1424 rdev->mode_info.tv_std_property =
1425 drm_property_create_enum(rdev->ddev, 0,
1427 radeon_tv_std_enum_list, sz);
1429 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1430 rdev->mode_info.underscan_property =
1431 drm_property_create_enum(rdev->ddev, 0,
1433 radeon_underscan_enum_list, sz);
1435 rdev->mode_info.underscan_hborder_property =
1436 drm_property_create_range(rdev->ddev, 0,
1437 "underscan hborder", 0, 128);
1438 if (!rdev->mode_info.underscan_hborder_property)
1441 rdev->mode_info.underscan_vborder_property =
1442 drm_property_create_range(rdev->ddev, 0,
1443 "underscan vborder", 0, 128);
1444 if (!rdev->mode_info.underscan_vborder_property)
1447 sz = ARRAY_SIZE(radeon_audio_enum_list);
1448 rdev->mode_info.audio_property =
1449 drm_property_create_enum(rdev->ddev, 0,
1451 radeon_audio_enum_list, sz);
1453 sz = ARRAY_SIZE(radeon_dither_enum_list);
1454 rdev->mode_info.dither_property =
1455 drm_property_create_enum(rdev->ddev, 0,
1457 radeon_dither_enum_list, sz);
1459 sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1460 rdev->mode_info.output_csc_property =
1461 drm_property_create_enum(rdev->ddev, 0,
1463 radeon_output_csc_enum_list, sz);
1468 void radeon_update_display_priority(struct radeon_device *rdev)
1470 /* adjustment options for the display watermarks */
1471 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1472 /* set display priority to high for r3xx, rv515 chips
1473 * this avoids flickering due to underflow to the
1474 * display controllers during heavy acceleration.
1475 * Don't force high on rs4xx igp chips as it seems to
1476 * affect the sound card. See kernel bug 15982.
1478 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1479 !(rdev->flags & RADEON_IS_IGP))
1480 rdev->disp_priority = 2;
1482 rdev->disp_priority = 0;
1484 rdev->disp_priority = radeon_disp_priority;
1489 * Allocate hdmi structs and determine register offsets
1491 static void radeon_afmt_init(struct radeon_device *rdev)
1495 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1496 rdev->mode_info.afmt[i] = NULL;
1498 if (ASIC_IS_NODCE(rdev)) {
1500 } else if (ASIC_IS_DCE4(rdev)) {
1501 static uint32_t eg_offsets[] = {
1502 EVERGREEN_CRTC0_REGISTER_OFFSET,
1503 EVERGREEN_CRTC1_REGISTER_OFFSET,
1504 EVERGREEN_CRTC2_REGISTER_OFFSET,
1505 EVERGREEN_CRTC3_REGISTER_OFFSET,
1506 EVERGREEN_CRTC4_REGISTER_OFFSET,
1507 EVERGREEN_CRTC5_REGISTER_OFFSET,
1512 /* DCE8 has 7 audio blocks tied to DIG encoders */
1513 /* DCE6 has 6 audio blocks tied to DIG encoders */
1514 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1515 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1516 if (ASIC_IS_DCE8(rdev))
1518 else if (ASIC_IS_DCE6(rdev))
1520 else if (ASIC_IS_DCE5(rdev))
1522 else if (ASIC_IS_DCE41(rdev))
1527 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1528 for (i = 0; i < num_afmt; i++) {
1529 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1530 if (rdev->mode_info.afmt[i]) {
1531 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1532 rdev->mode_info.afmt[i]->id = i;
1535 } else if (ASIC_IS_DCE3(rdev)) {
1536 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1537 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1538 if (rdev->mode_info.afmt[0]) {
1539 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1540 rdev->mode_info.afmt[0]->id = 0;
1542 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1543 if (rdev->mode_info.afmt[1]) {
1544 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1545 rdev->mode_info.afmt[1]->id = 1;
1547 } else if (ASIC_IS_DCE2(rdev)) {
1548 /* DCE2 has at least 1 routable audio block */
1549 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1550 if (rdev->mode_info.afmt[0]) {
1551 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1552 rdev->mode_info.afmt[0]->id = 0;
1554 /* r6xx has 2 routable audio blocks */
1555 if (rdev->family >= CHIP_R600) {
1556 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1557 if (rdev->mode_info.afmt[1]) {
1558 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1559 rdev->mode_info.afmt[1]->id = 1;
1565 static void radeon_afmt_fini(struct radeon_device *rdev)
1569 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1570 kfree(rdev->mode_info.afmt[i]);
1571 rdev->mode_info.afmt[i] = NULL;
1575 int radeon_modeset_init(struct radeon_device *rdev)
1580 drm_mode_config_init(rdev->ddev);
1581 rdev->mode_info.mode_config_initialized = true;
1583 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1585 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1586 rdev->ddev->mode_config.async_page_flip = true;
1588 if (ASIC_IS_DCE5(rdev)) {
1589 rdev->ddev->mode_config.max_width = 16384;
1590 rdev->ddev->mode_config.max_height = 16384;
1591 } else if (ASIC_IS_AVIVO(rdev)) {
1592 rdev->ddev->mode_config.max_width = 8192;
1593 rdev->ddev->mode_config.max_height = 8192;
1595 rdev->ddev->mode_config.max_width = 4096;
1596 rdev->ddev->mode_config.max_height = 4096;
1599 rdev->ddev->mode_config.preferred_depth = 24;
1600 rdev->ddev->mode_config.prefer_shadow = 1;
1602 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1604 ret = radeon_modeset_create_props(rdev);
1609 /* init i2c buses */
1610 radeon_i2c_init(rdev);
1612 /* check combios for a valid hardcoded EDID - Sun servers */
1613 if (!rdev->is_atom_bios) {
1614 /* check for hardcoded EDID in BIOS */
1615 radeon_combios_check_hardcoded_edid(rdev);
1618 /* allocate crtcs */
1619 for (i = 0; i < rdev->num_crtc; i++) {
1620 radeon_crtc_init(rdev->ddev, i);
1623 /* okay we should have all the bios connectors */
1624 ret = radeon_setup_enc_conn(rdev->ddev);
1629 /* init dig PHYs, disp eng pll */
1630 if (rdev->is_atom_bios) {
1631 radeon_atom_encoder_init(rdev);
1632 radeon_atom_disp_eng_pll_init(rdev);
1635 /* initialize hpd */
1636 radeon_hpd_init(rdev);
1639 radeon_afmt_init(rdev);
1641 radeon_fbdev_init(rdev);
1642 drm_kms_helper_poll_init(rdev->ddev);
1644 /* do pm late init */
1645 ret = radeon_pm_late_init(rdev);
1650 void radeon_modeset_fini(struct radeon_device *rdev)
1652 if (rdev->mode_info.mode_config_initialized) {
1653 drm_kms_helper_poll_fini(rdev->ddev);
1654 radeon_hpd_fini(rdev);
1655 drm_helper_force_disable_all(rdev->ddev);
1656 radeon_fbdev_fini(rdev);
1657 radeon_afmt_fini(rdev);
1658 drm_mode_config_cleanup(rdev->ddev);
1659 rdev->mode_info.mode_config_initialized = false;
1662 kfree(rdev->mode_info.bios_hardcoded_edid);
1664 /* free i2c buses */
1665 radeon_i2c_fini(rdev);
1668 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1670 /* try and guess if this is a tv or a monitor */
1671 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1672 (mode->vdisplay == 576) || /* 576p */
1673 (mode->vdisplay == 720) || /* 720p */
1674 (mode->vdisplay == 1080)) /* 1080p */
1680 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1681 const struct drm_display_mode *mode,
1682 struct drm_display_mode *adjusted_mode)
1684 struct drm_device *dev = crtc->dev;
1685 struct radeon_device *rdev = dev->dev_private;
1686 struct drm_encoder *encoder;
1687 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1688 struct radeon_encoder *radeon_encoder;
1689 struct drm_connector *connector;
1691 u32 src_v = 1, dst_v = 1;
1692 u32 src_h = 1, dst_h = 1;
1694 radeon_crtc->h_border = 0;
1695 radeon_crtc->v_border = 0;
1697 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1698 if (encoder->crtc != crtc)
1700 radeon_encoder = to_radeon_encoder(encoder);
1701 connector = radeon_get_connector_for_encoder(encoder);
1705 if (radeon_encoder->rmx_type == RMX_OFF)
1706 radeon_crtc->rmx_type = RMX_OFF;
1707 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1708 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1709 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1711 radeon_crtc->rmx_type = RMX_OFF;
1712 /* copy native mode */
1713 memcpy(&radeon_crtc->native_mode,
1714 &radeon_encoder->native_mode,
1715 sizeof(struct drm_display_mode));
1716 src_v = crtc->mode.vdisplay;
1717 dst_v = radeon_crtc->native_mode.vdisplay;
1718 src_h = crtc->mode.hdisplay;
1719 dst_h = radeon_crtc->native_mode.hdisplay;
1721 /* fix up for overscan on hdmi */
1722 if (ASIC_IS_AVIVO(rdev) &&
1723 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1724 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1725 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1726 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1727 is_hdtv_mode(mode)))) {
1728 if (radeon_encoder->underscan_hborder != 0)
1729 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1731 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1732 if (radeon_encoder->underscan_vborder != 0)
1733 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1735 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1736 radeon_crtc->rmx_type = RMX_FULL;
1737 src_v = crtc->mode.vdisplay;
1738 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1739 src_h = crtc->mode.hdisplay;
1740 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1744 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1745 /* WARNING: Right now this can't happen but
1746 * in the future we need to check that scaling
1747 * are consistent across different encoder
1748 * (ie all encoder can work with the same
1751 DRM_ERROR("Scaling not consistent across encoder.\n");
1756 if (radeon_crtc->rmx_type != RMX_OFF) {
1758 a.full = dfixed_const(src_v);
1759 b.full = dfixed_const(dst_v);
1760 radeon_crtc->vsc.full = dfixed_div(a, b);
1761 a.full = dfixed_const(src_h);
1762 b.full = dfixed_const(dst_h);
1763 radeon_crtc->hsc.full = dfixed_div(a, b);
1765 radeon_crtc->vsc.full = dfixed_const(1);
1766 radeon_crtc->hsc.full = dfixed_const(1);
1772 * Retrieve current video scanout position of crtc on a given gpu, and
1773 * an optional accurate timestamp of when query happened.
1775 * \param dev Device to query.
1776 * \param crtc Crtc to query.
1777 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1778 * For driver internal use only also supports these flags:
1780 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1781 * of a fudged earlier start of vblank.
1783 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1784 * fudged earlier start of vblank in *vpos and the distance
1785 * to true start of vblank in *hpos.
1787 * \param *vpos Location where vertical scanout position should be stored.
1788 * \param *hpos Location where horizontal scanout position should go.
1789 * \param *stime Target location for timestamp taken immediately before
1790 * scanout position query. Can be NULL to skip timestamp.
1791 * \param *etime Target location for timestamp taken immediately after
1792 * scanout position query. Can be NULL to skip timestamp.
1794 * Returns vpos as a positive number while in active scanout area.
1795 * Returns vpos as a negative number inside vblank, counting the number
1796 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1797 * until start of active scanout / end of vblank."
1799 * \return Flags, or'ed together as follows:
1801 * DRM_SCANOUTPOS_VALID = Query successful.
1802 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1803 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1804 * this flag means that returned position may be offset by a constant but
1805 * unknown small number of scanlines wrt. real scanout position.
1808 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1809 unsigned int flags, int *vpos, int *hpos,
1810 ktime_t *stime, ktime_t *etime,
1811 const struct drm_display_mode *mode)
1813 u32 stat_crtc = 0, vbl = 0, position = 0;
1814 int vbl_start, vbl_end, vtotal, ret = 0;
1817 struct radeon_device *rdev = dev->dev_private;
1819 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1821 /* Get optional system timestamp before query. */
1823 *stime = ktime_get();
1825 if (ASIC_IS_DCE4(rdev)) {
1827 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1828 EVERGREEN_CRTC0_REGISTER_OFFSET);
1829 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1830 EVERGREEN_CRTC0_REGISTER_OFFSET);
1831 ret |= DRM_SCANOUTPOS_VALID;
1834 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1835 EVERGREEN_CRTC1_REGISTER_OFFSET);
1836 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1837 EVERGREEN_CRTC1_REGISTER_OFFSET);
1838 ret |= DRM_SCANOUTPOS_VALID;
1841 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1842 EVERGREEN_CRTC2_REGISTER_OFFSET);
1843 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1844 EVERGREEN_CRTC2_REGISTER_OFFSET);
1845 ret |= DRM_SCANOUTPOS_VALID;
1848 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1849 EVERGREEN_CRTC3_REGISTER_OFFSET);
1850 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1851 EVERGREEN_CRTC3_REGISTER_OFFSET);
1852 ret |= DRM_SCANOUTPOS_VALID;
1855 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1856 EVERGREEN_CRTC4_REGISTER_OFFSET);
1857 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1858 EVERGREEN_CRTC4_REGISTER_OFFSET);
1859 ret |= DRM_SCANOUTPOS_VALID;
1862 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1863 EVERGREEN_CRTC5_REGISTER_OFFSET);
1864 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1865 EVERGREEN_CRTC5_REGISTER_OFFSET);
1866 ret |= DRM_SCANOUTPOS_VALID;
1868 } else if (ASIC_IS_AVIVO(rdev)) {
1870 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1871 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1872 ret |= DRM_SCANOUTPOS_VALID;
1875 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1876 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1877 ret |= DRM_SCANOUTPOS_VALID;
1880 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1882 /* Assume vbl_end == 0, get vbl_start from
1885 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1886 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1887 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1888 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1889 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1890 if (!(stat_crtc & 1))
1893 ret |= DRM_SCANOUTPOS_VALID;
1896 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1897 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1898 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1899 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1900 if (!(stat_crtc & 1))
1903 ret |= DRM_SCANOUTPOS_VALID;
1907 /* Get optional system timestamp after query. */
1909 *etime = ktime_get();
1911 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1913 /* Decode into vertical and horizontal scanout position. */
1914 *vpos = position & 0x1fff;
1915 *hpos = (position >> 16) & 0x1fff;
1917 /* Valid vblank area boundaries from gpu retrieved? */
1920 ret |= DRM_SCANOUTPOS_ACCURATE;
1921 vbl_start = vbl & 0x1fff;
1922 vbl_end = (vbl >> 16) & 0x1fff;
1925 /* No: Fake something reasonable which gives at least ok results. */
1926 vbl_start = mode->crtc_vdisplay;
1930 /* Called from driver internal vblank counter query code? */
1931 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1932 /* Caller wants distance from real vbl_start in *hpos */
1933 *hpos = *vpos - vbl_start;
1936 /* Fudge vblank to start a few scanlines earlier to handle the
1937 * problem that vblank irqs fire a few scanlines before start
1938 * of vblank. Some driver internal callers need the true vblank
1939 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1941 * The cause of the "early" vblank irq is that the irq is triggered
1942 * by the line buffer logic when the line buffer read position enters
1943 * the vblank, whereas our crtc scanout position naturally lags the
1944 * line buffer read position.
1946 if (!(flags & USE_REAL_VBLANKSTART))
1947 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1949 /* Test scanout position against vblank region. */
1950 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1955 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1957 /* Called from driver internal vblank counter query code? */
1958 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1959 /* Caller wants distance from fudged earlier vbl_start */
1964 /* Check if inside vblank area and apply corrective offsets:
1965 * vpos will then be >=0 in video scanout area, but negative
1966 * within vblank area, counting down the number of lines until
1970 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1971 if (in_vbl && (*vpos >= vbl_start)) {
1972 vtotal = mode->crtc_vtotal;
1973 *vpos = *vpos - vtotal;
1976 /* Correct for shifted end of vbl at vbl_end. */
1977 *vpos = *vpos - vbl_end;
1983 radeon_get_crtc_scanout_position(struct drm_crtc *crtc,
1984 bool in_vblank_irq, int *vpos, int *hpos,
1985 ktime_t *stime, ktime_t *etime,
1986 const struct drm_display_mode *mode)
1988 struct drm_device *dev = crtc->dev;
1989 unsigned int pipe = crtc->index;
1991 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1992 stime, etime, mode);