2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <ttm/ttm_bo_api.h>
33 #include <ttm/ttm_bo_driver.h>
34 #include <ttm/ttm_placement.h>
35 #include <ttm/ttm_module.h>
36 #include <ttm/ttm_page_alloc.h>
38 #include <drm/radeon_drm.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include "radeon_reg.h"
44 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
46 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
48 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
50 struct radeon_mman *mman;
51 struct radeon_device *rdev;
53 mman = container_of(bdev, struct radeon_mman, bdev);
54 rdev = container_of(mman, struct radeon_device, mman);
62 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
64 return ttm_mem_global_init(ref->object);
67 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
69 ttm_mem_global_release(ref->object);
72 static int radeon_ttm_global_init(struct radeon_device *rdev)
74 struct drm_global_reference *global_ref;
77 rdev->mman.mem_global_referenced = false;
78 global_ref = &rdev->mman.mem_global_ref;
79 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
80 global_ref->size = sizeof(struct ttm_mem_global);
81 global_ref->init = &radeon_ttm_mem_global_init;
82 global_ref->release = &radeon_ttm_mem_global_release;
83 r = drm_global_item_ref(global_ref);
85 DRM_ERROR("Failed setting up TTM memory accounting "
90 rdev->mman.bo_global_ref.mem_glob =
91 rdev->mman.mem_global_ref.object;
92 global_ref = &rdev->mman.bo_global_ref.ref;
93 global_ref->global_type = DRM_GLOBAL_TTM_BO;
94 global_ref->size = sizeof(struct ttm_bo_global);
95 global_ref->init = &ttm_bo_global_init;
96 global_ref->release = &ttm_bo_global_release;
97 r = drm_global_item_ref(global_ref);
99 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
100 drm_global_item_unref(&rdev->mman.mem_global_ref);
104 rdev->mman.mem_global_referenced = true;
108 static void radeon_ttm_global_fini(struct radeon_device *rdev)
110 if (rdev->mman.mem_global_referenced) {
111 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
112 drm_global_item_unref(&rdev->mman.mem_global_ref);
113 rdev->mman.mem_global_referenced = false;
117 struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev);
119 static struct ttm_backend*
120 radeon_create_ttm_backend_entry(struct ttm_bo_device *bdev)
122 struct radeon_device *rdev;
124 rdev = radeon_get_rdev(bdev);
126 if (rdev->flags & RADEON_IS_AGP) {
127 return ttm_agp_backend_init(bdev, rdev->ddev->agp->bridge);
131 return radeon_ttm_backend_create(rdev);
135 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
140 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
141 struct ttm_mem_type_manager *man)
143 struct radeon_device *rdev;
145 rdev = radeon_get_rdev(bdev);
150 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
151 man->available_caching = TTM_PL_MASK_CACHING;
152 man->default_caching = TTM_PL_FLAG_CACHED;
155 man->func = &ttm_bo_manager_func;
156 man->gpu_offset = rdev->mc.gtt_start;
157 man->available_caching = TTM_PL_MASK_CACHING;
158 man->default_caching = TTM_PL_FLAG_CACHED;
159 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
161 if (rdev->flags & RADEON_IS_AGP) {
162 if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) {
163 DRM_ERROR("AGP is not enabled for memory type %u\n",
167 if (!rdev->ddev->agp->cant_use_aperture)
168 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
169 man->available_caching = TTM_PL_FLAG_UNCACHED |
171 man->default_caching = TTM_PL_FLAG_WC;
176 /* "On-card" video ram */
177 man->func = &ttm_bo_manager_func;
178 man->gpu_offset = rdev->mc.vram_start;
179 man->flags = TTM_MEMTYPE_FLAG_FIXED |
180 TTM_MEMTYPE_FLAG_MAPPABLE;
181 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
182 man->default_caching = TTM_PL_FLAG_WC;
185 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
191 static void radeon_evict_flags(struct ttm_buffer_object *bo,
192 struct ttm_placement *placement)
194 struct radeon_bo *rbo;
195 static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
197 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
200 placement->placement = &placements;
201 placement->busy_placement = &placements;
202 placement->num_placement = 1;
203 placement->num_busy_placement = 1;
206 rbo = container_of(bo, struct radeon_bo, tbo);
207 switch (bo->mem.mem_type) {
209 if (rbo->rdev->cp.ready == false)
210 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
212 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
216 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
218 *placement = rbo->placement;
221 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
226 static void radeon_move_null(struct ttm_buffer_object *bo,
227 struct ttm_mem_reg *new_mem)
229 struct ttm_mem_reg *old_mem = &bo->mem;
231 BUG_ON(old_mem->mm_node != NULL);
233 new_mem->mm_node = NULL;
236 static int radeon_move_blit(struct ttm_buffer_object *bo,
237 bool evict, int no_wait_reserve, bool no_wait_gpu,
238 struct ttm_mem_reg *new_mem,
239 struct ttm_mem_reg *old_mem)
241 struct radeon_device *rdev;
242 uint64_t old_start, new_start;
243 struct radeon_fence *fence;
246 rdev = radeon_get_rdev(bo->bdev);
247 r = radeon_fence_create(rdev, &fence);
251 old_start = old_mem->start << PAGE_SHIFT;
252 new_start = new_mem->start << PAGE_SHIFT;
254 switch (old_mem->mem_type) {
256 old_start += rdev->mc.vram_start;
259 old_start += rdev->mc.gtt_start;
262 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
265 switch (new_mem->mem_type) {
267 new_start += rdev->mc.vram_start;
270 new_start += rdev->mc.gtt_start;
273 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
276 if (!rdev->cp.ready) {
277 DRM_ERROR("Trying to move memory with CP turned off.\n");
281 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
283 r = radeon_copy(rdev, old_start, new_start,
284 new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */
286 /* FIXME: handle copy error */
287 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL,
288 evict, no_wait_reserve, no_wait_gpu, new_mem);
289 radeon_fence_unref(&fence);
293 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
294 bool evict, bool interruptible,
295 bool no_wait_reserve, bool no_wait_gpu,
296 struct ttm_mem_reg *new_mem)
298 struct radeon_device *rdev;
299 struct ttm_mem_reg *old_mem = &bo->mem;
300 struct ttm_mem_reg tmp_mem;
302 struct ttm_placement placement;
305 rdev = radeon_get_rdev(bo->bdev);
307 tmp_mem.mm_node = NULL;
310 placement.num_placement = 1;
311 placement.placement = &placements;
312 placement.num_busy_placement = 1;
313 placement.busy_placement = &placements;
314 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
315 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
316 interruptible, no_wait_reserve, no_wait_gpu);
321 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
326 r = ttm_tt_bind(bo->ttm, &tmp_mem);
330 r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem, old_mem);
334 r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
336 ttm_bo_mem_put(bo, &tmp_mem);
340 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
341 bool evict, bool interruptible,
342 bool no_wait_reserve, bool no_wait_gpu,
343 struct ttm_mem_reg *new_mem)
345 struct radeon_device *rdev;
346 struct ttm_mem_reg *old_mem = &bo->mem;
347 struct ttm_mem_reg tmp_mem;
348 struct ttm_placement placement;
352 rdev = radeon_get_rdev(bo->bdev);
354 tmp_mem.mm_node = NULL;
357 placement.num_placement = 1;
358 placement.placement = &placements;
359 placement.num_busy_placement = 1;
360 placement.busy_placement = &placements;
361 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
362 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait_reserve, no_wait_gpu);
366 r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
370 r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
375 ttm_bo_mem_put(bo, &tmp_mem);
379 static int radeon_bo_move(struct ttm_buffer_object *bo,
380 bool evict, bool interruptible,
381 bool no_wait_reserve, bool no_wait_gpu,
382 struct ttm_mem_reg *new_mem)
384 struct radeon_device *rdev;
385 struct ttm_mem_reg *old_mem = &bo->mem;
388 rdev = radeon_get_rdev(bo->bdev);
389 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
390 radeon_move_null(bo, new_mem);
393 if ((old_mem->mem_type == TTM_PL_TT &&
394 new_mem->mem_type == TTM_PL_SYSTEM) ||
395 (old_mem->mem_type == TTM_PL_SYSTEM &&
396 new_mem->mem_type == TTM_PL_TT)) {
398 radeon_move_null(bo, new_mem);
401 if (!rdev->cp.ready || rdev->asic->copy == NULL) {
406 if (old_mem->mem_type == TTM_PL_VRAM &&
407 new_mem->mem_type == TTM_PL_SYSTEM) {
408 r = radeon_move_vram_ram(bo, evict, interruptible,
409 no_wait_reserve, no_wait_gpu, new_mem);
410 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
411 new_mem->mem_type == TTM_PL_VRAM) {
412 r = radeon_move_ram_vram(bo, evict, interruptible,
413 no_wait_reserve, no_wait_gpu, new_mem);
415 r = radeon_move_blit(bo, evict, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
420 r = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
425 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
427 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
428 struct radeon_device *rdev = radeon_get_rdev(bdev);
430 mem->bus.addr = NULL;
432 mem->bus.size = mem->num_pages << PAGE_SHIFT;
434 mem->bus.is_iomem = false;
435 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
437 switch (mem->mem_type) {
443 if (rdev->flags & RADEON_IS_AGP) {
444 /* RADEON_IS_AGP is set only if AGP is active */
445 mem->bus.offset = mem->start << PAGE_SHIFT;
446 mem->bus.base = rdev->mc.agp_base;
447 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
452 mem->bus.offset = mem->start << PAGE_SHIFT;
453 /* check if it's visible */
454 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
456 mem->bus.base = rdev->mc.aper_base;
457 mem->bus.is_iomem = true;
465 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
469 static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg,
470 bool lazy, bool interruptible)
472 return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
475 static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg)
480 static void radeon_sync_obj_unref(void **sync_obj)
482 radeon_fence_unref((struct radeon_fence **)sync_obj);
485 static void *radeon_sync_obj_ref(void *sync_obj)
487 return radeon_fence_ref((struct radeon_fence *)sync_obj);
490 static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg)
492 return radeon_fence_signaled((struct radeon_fence *)sync_obj);
495 static struct ttm_bo_driver radeon_bo_driver = {
496 .create_ttm_backend_entry = &radeon_create_ttm_backend_entry,
497 .invalidate_caches = &radeon_invalidate_caches,
498 .init_mem_type = &radeon_init_mem_type,
499 .evict_flags = &radeon_evict_flags,
500 .move = &radeon_bo_move,
501 .verify_access = &radeon_verify_access,
502 .sync_obj_signaled = &radeon_sync_obj_signaled,
503 .sync_obj_wait = &radeon_sync_obj_wait,
504 .sync_obj_flush = &radeon_sync_obj_flush,
505 .sync_obj_unref = &radeon_sync_obj_unref,
506 .sync_obj_ref = &radeon_sync_obj_ref,
507 .move_notify = &radeon_bo_move_notify,
508 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
509 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
510 .io_mem_free = &radeon_ttm_io_mem_free,
513 int radeon_ttm_init(struct radeon_device *rdev)
517 r = radeon_ttm_global_init(rdev);
521 /* No others user of address space so set it to 0 */
522 r = ttm_bo_device_init(&rdev->mman.bdev,
523 rdev->mman.bo_global_ref.ref.object,
524 &radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
527 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
530 rdev->mman.initialized = true;
531 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
532 rdev->mc.real_vram_size >> PAGE_SHIFT);
534 DRM_ERROR("Failed initializing VRAM heap.\n");
537 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
538 RADEON_GEM_DOMAIN_VRAM,
539 &rdev->stollen_vga_memory);
543 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
546 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
547 radeon_bo_unreserve(rdev->stollen_vga_memory);
549 radeon_bo_unref(&rdev->stollen_vga_memory);
552 DRM_INFO("radeon: %uM of VRAM memory ready\n",
553 (unsigned)rdev->mc.real_vram_size / (1024 * 1024));
554 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
555 rdev->mc.gtt_size >> PAGE_SHIFT);
557 DRM_ERROR("Failed initializing GTT heap.\n");
560 DRM_INFO("radeon: %uM of GTT memory ready.\n",
561 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
562 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
563 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
566 r = radeon_ttm_debugfs_init(rdev);
568 DRM_ERROR("Failed to init debugfs\n");
574 void radeon_ttm_fini(struct radeon_device *rdev)
578 if (!rdev->mman.initialized)
580 if (rdev->stollen_vga_memory) {
581 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
583 radeon_bo_unpin(rdev->stollen_vga_memory);
584 radeon_bo_unreserve(rdev->stollen_vga_memory);
586 radeon_bo_unref(&rdev->stollen_vga_memory);
588 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
589 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
590 ttm_bo_device_release(&rdev->mman.bdev);
591 radeon_gart_fini(rdev);
592 radeon_ttm_global_fini(rdev);
593 rdev->mman.initialized = false;
594 DRM_INFO("radeon: ttm finalized\n");
597 /* this should only be called at bootup or when userspace
599 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
601 struct ttm_mem_type_manager *man;
603 if (!rdev->mman.initialized)
606 man = &rdev->mman.bdev.man[TTM_PL_VRAM];
607 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
608 man->size = size >> PAGE_SHIFT;
611 static struct vm_operations_struct radeon_ttm_vm_ops;
612 static const struct vm_operations_struct *ttm_vm_ops = NULL;
614 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
616 struct ttm_buffer_object *bo;
617 struct radeon_device *rdev;
620 bo = (struct ttm_buffer_object *)vma->vm_private_data;
622 return VM_FAULT_NOPAGE;
624 rdev = radeon_get_rdev(bo->bdev);
625 mutex_lock(&rdev->vram_mutex);
626 r = ttm_vm_ops->fault(vma, vmf);
627 mutex_unlock(&rdev->vram_mutex);
631 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
633 struct drm_file *file_priv;
634 struct radeon_device *rdev;
637 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
638 return drm_mmap(filp, vma);
641 file_priv = filp->private_data;
642 rdev = file_priv->minor->dev->dev_private;
646 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
647 if (unlikely(r != 0)) {
650 if (unlikely(ttm_vm_ops == NULL)) {
651 ttm_vm_ops = vma->vm_ops;
652 radeon_ttm_vm_ops = *ttm_vm_ops;
653 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
655 vma->vm_ops = &radeon_ttm_vm_ops;
661 * TTM backend functions.
663 struct radeon_ttm_backend {
664 struct ttm_backend backend;
665 struct radeon_device *rdev;
666 unsigned long num_pages;
668 struct page *dummy_read_page;
669 dma_addr_t *dma_addrs;
675 static int radeon_ttm_backend_populate(struct ttm_backend *backend,
676 unsigned long num_pages,
678 struct page *dummy_read_page,
679 dma_addr_t *dma_addrs)
681 struct radeon_ttm_backend *gtt;
683 gtt = container_of(backend, struct radeon_ttm_backend, backend);
685 gtt->dma_addrs = dma_addrs;
686 gtt->num_pages = num_pages;
687 gtt->dummy_read_page = dummy_read_page;
688 gtt->populated = true;
692 static void radeon_ttm_backend_clear(struct ttm_backend *backend)
694 struct radeon_ttm_backend *gtt;
696 gtt = container_of(backend, struct radeon_ttm_backend, backend);
698 gtt->dma_addrs = NULL;
700 gtt->dummy_read_page = NULL;
701 gtt->populated = false;
706 static int radeon_ttm_backend_bind(struct ttm_backend *backend,
707 struct ttm_mem_reg *bo_mem)
709 struct radeon_ttm_backend *gtt;
712 gtt = container_of(backend, struct radeon_ttm_backend, backend);
713 gtt->offset = bo_mem->start << PAGE_SHIFT;
714 if (!gtt->num_pages) {
715 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
716 gtt->num_pages, bo_mem, backend);
718 r = radeon_gart_bind(gtt->rdev, gtt->offset,
719 gtt->num_pages, gtt->pages, gtt->dma_addrs);
721 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
722 gtt->num_pages, gtt->offset);
729 static int radeon_ttm_backend_unbind(struct ttm_backend *backend)
731 struct radeon_ttm_backend *gtt;
733 gtt = container_of(backend, struct radeon_ttm_backend, backend);
734 radeon_gart_unbind(gtt->rdev, gtt->offset, gtt->num_pages);
739 static void radeon_ttm_backend_destroy(struct ttm_backend *backend)
741 struct radeon_ttm_backend *gtt;
743 gtt = container_of(backend, struct radeon_ttm_backend, backend);
745 radeon_ttm_backend_unbind(backend);
750 static struct ttm_backend_func radeon_backend_func = {
751 .populate = &radeon_ttm_backend_populate,
752 .clear = &radeon_ttm_backend_clear,
753 .bind = &radeon_ttm_backend_bind,
754 .unbind = &radeon_ttm_backend_unbind,
755 .destroy = &radeon_ttm_backend_destroy,
758 struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev)
760 struct radeon_ttm_backend *gtt;
762 gtt = kzalloc(sizeof(struct radeon_ttm_backend), GFP_KERNEL);
766 gtt->backend.bdev = &rdev->mman.bdev;
767 gtt->backend.flags = 0;
768 gtt->backend.func = &radeon_backend_func;
772 gtt->dummy_read_page = NULL;
773 gtt->populated = false;
775 return >t->backend;
778 #define RADEON_DEBUGFS_MEM_TYPES 2
780 #if defined(CONFIG_DEBUG_FS)
781 static int radeon_mm_dump_table(struct seq_file *m, void *data)
783 struct drm_info_node *node = (struct drm_info_node *)m->private;
784 struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
785 struct drm_device *dev = node->minor->dev;
786 struct radeon_device *rdev = dev->dev_private;
788 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
790 spin_lock(&glob->lru_lock);
791 ret = drm_mm_dump_table(m, mm);
792 spin_unlock(&glob->lru_lock);
797 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
799 #if defined(CONFIG_DEBUG_FS)
800 static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+1];
801 static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+1][32];
804 for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
806 sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
808 sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
809 radeon_mem_types_list[i].name = radeon_mem_types_names[i];
810 radeon_mem_types_list[i].show = &radeon_mm_dump_table;
811 radeon_mem_types_list[i].driver_features = 0;
813 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv;
815 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv;
818 /* Add ttm page pool to debugfs */
819 sprintf(radeon_mem_types_names[i], "ttm_page_pool");
820 radeon_mem_types_list[i].name = radeon_mem_types_names[i];
821 radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs;
822 radeon_mem_types_list[i].driver_features = 0;
823 radeon_mem_types_list[i].data = NULL;
824 return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES+1);