drivers/gpu/drm/radeon/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include "radeon.h"
  26 #include "radeon_asic.h"
  27 #include "sid.h"
  28 #include "r600_dpm.h"
  29 #include "si_dpm.h"
  30 #include "atom.h"
  31 #include <linux/math64.h>
  32 #include <linux/seq_file.h>
  33
  34 #define MC_CG_ARB_FREQ_F0           0x0a
  35 #define MC_CG_ARB_FREQ_F1           0x0b
  36 #define MC_CG_ARB_FREQ_F2           0x0c
  37 #define MC_CG_ARB_FREQ_F3           0x0d
  38
  39 #define SMC_RAM_END                 0x20000
  40
  41 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  42
  43 static const struct si_cac_config_reg cac_weights_tahiti[] =
  44 {
  45         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
  46         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  47         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
  48         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
  49         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  50         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  51         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  52         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  53         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  54         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
  55         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  56         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
  57         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
  58         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
  59         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
  60         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  61         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  62         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
  63         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  64         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
  65         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
  66         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
  67         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  68         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  69         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  70         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  71         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  72         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  73         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  74         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  75         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
  76         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  77         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  78         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  79         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
  80         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  81         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  82         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
  83         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  84         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
  85         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  86         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  87         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  88         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  89         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  90         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  91         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  92         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  93         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  94         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  95         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  96         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  97         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  98         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  99         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 100         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 101         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 102         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 103         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 104         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 105         { 0xFFFFFFFF }
 106 };
 107
 108 static const struct si_cac_config_reg lcac_tahiti[] =
 109 {
 110         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 111         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 112         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 113         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 114         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 115         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 116         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 117         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 118         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 119         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 120         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 121         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 122         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 123         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 124         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 125         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 126         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 127         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 128         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 129         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 130         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 131         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 132         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 133         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 134         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 135         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 136         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 137         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 138         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 139         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 140         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 141         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 142         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 143         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 144         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 145         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 146         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 147         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 148         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 149         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 150         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 151         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 152         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 153         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 154         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 155         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 156         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 157         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 158         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 159         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 160         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 161         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 162         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 163         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 164         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 165         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 166         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 167         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 168         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 169         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 172         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 173         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 174         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 175         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 176         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 177         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 178         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 179         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 180         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 181         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 182         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 183         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 184         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 185         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 186         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 187         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 188         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 189         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 190         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 191         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 192         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 193         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 194         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 195         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 196         { 0xFFFFFFFF }
 197
 198 };
 199
 200 static const struct si_cac_config_reg cac_override_tahiti[] =
 201 {
 202         { 0xFFFFFFFF }
 203 };
 204
 205 static const struct si_powertune_data powertune_data_tahiti =
 206 {
 207         ((1 << 16) | 27027),
 208         6,
 209         0,
 210         4,
 211         95,
 212         {
 213                 0UL,
 214                 0UL,
 215                 4521550UL,
 216                 309631529UL,
 217                 -1270850L,
 218                 4513710L,
 219                 40
 220         },
 221         595000000UL,
 222         12,
 223         {
 224                 0,
 225                 0,
 226                 0,
 227                 0,
 228                 0,
 229                 0,
 230                 0,
 231                 0
 232         },
 233         true
 234 };
 235
 236 static const struct si_dte_data dte_data_tahiti =
 237 {
 238         { 1159409, 0, 0, 0, 0 },
 239         { 777, 0, 0, 0, 0 },
 240         2,
 241         54000,
 242         127000,
 243         25,
 244         2,
 245         10,
 246         13,
 247         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 248         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 249         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 250         85,
 251         false
 252 };
 253
 254 static const struct si_dte_data dte_data_tahiti_le =
 255 {
 256         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 257         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 258         0x5,
 259         0xAFC8,
 260         0x64,
 261         0x32,
 262         1,
 263         0,
 264         0x10,
 265         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 266         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 267         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 268         85,
 269         true
 270 };
 271
 272 static const struct si_dte_data dte_data_tahiti_pro =
 273 {
 274         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 275         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 276         5,
 277         45000,
 278         100,
 279         0xA,
 280         1,
 281         0,
 282         0x10,
 283         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 284         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 285         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 286         90,
 287         true
 288 };
 289
 290 static const struct si_dte_data dte_data_new_zealand =
 291 {
 292         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 293         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 294         0x5,
 295         0xAFC8,
 296         0x69,
 297         0x32,
 298         1,
 299         0,
 300         0x10,
 301         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 302         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 303         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 304         85,
 305         true
 306 };
 307
 308 static const struct si_dte_data dte_data_aruba_pro =
 309 {
 310         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 311         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 312         5,
 313         45000,
 314         100,
 315         0xA,
 316         1,
 317         0,
 318         0x10,
 319         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 320         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 321         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 322         90,
 323         true
 324 };
 325
 326 static const struct si_dte_data dte_data_malta =
 327 {
 328         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 329         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 330         5,
 331         45000,
 332         100,
 333         0xA,
 334         1,
 335         0,
 336         0x10,
 337         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 338         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 339         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 340         90,
 341         true
 342 };
 343
 344 struct si_cac_config_reg cac_weights_pitcairn[] =
 345 {
 346         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 347         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 348         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 349         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 350         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 351         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 352         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 353         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 354         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 355         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 356         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 357         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 358         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 359         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 360         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 361         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 362         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 363         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 364         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 365         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 366         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 367         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 368         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 369         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 370         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 371         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 372         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 373         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 374         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 375         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 376         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 377         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 378         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 379         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 380         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 381         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 382         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 383         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 384         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 385         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 386         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 387         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 388         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 389         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 390         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 391         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 392         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 393         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 394         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 395         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 396         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 397         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 398         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 399         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 400         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 401         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 402         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 403         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 404         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 405         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 406         { 0xFFFFFFFF }
 407 };
 408
 409 static const struct si_cac_config_reg lcac_pitcairn[] =
 410 {
 411         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 412         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 413         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 414         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 415         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 416         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 417         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 418         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 419         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 420         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 421         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 422         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 423         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 424         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 425         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 426         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 427         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 428         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 429         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 430         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 431         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 432         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 433         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 434         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 435         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 436         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 437         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 438         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 439         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 440         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 441         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 442         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 443         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 444         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 445         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 446         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 447         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 448         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 449         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 450         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 451         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 452         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 453         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 454         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 455         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 456         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 457         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 458         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 459         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 460         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 461         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 462         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 463         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 464         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 465         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 466         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 467         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 468         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 469         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 470         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 471         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 472         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 473         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 474         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 475         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 476         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 477         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 478         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 479         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 480         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 481         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 482         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 483         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 484         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 485         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 486         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 487         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 488         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 489         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 490         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 491         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 492         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 493         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 494         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 495         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 496         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 497         { 0xFFFFFFFF }
 498 };
 499
 500 static const struct si_cac_config_reg cac_override_pitcairn[] =
 501 {
 502         { 0xFFFFFFFF }
 503 };
 504
 505 static const struct si_powertune_data powertune_data_pitcairn =
 506 {
 507         ((1 << 16) | 27027),
 508         5,
 509         0,
 510         6,
 511         100,
 512         {
 513                 51600000UL,
 514                 1800000UL,
 515                 7194395UL,
 516                 309631529UL,
 517                 -1270850L,
 518                 4513710L,
 519                 100
 520         },
 521         117830498UL,
 522         12,
 523         {
 524                 0,
 525                 0,
 526                 0,
 527                 0,
 528                 0,
 529                 0,
 530                 0,
 531                 0
 532         },
 533         true
 534 };
 535
 536 static const struct si_dte_data dte_data_pitcairn =
 537 {
 538         { 0, 0, 0, 0, 0 },
 539         { 0, 0, 0, 0, 0 },
 540         0,
 541         0,
 542         0,
 543         0,
 544         0,
 545         0,
 546         0,
 547         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 548         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 549         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 550         0,
 551         false
 552 };
 553
 554 static const struct si_dte_data dte_data_curacao_xt =
 555 {
 556         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 557         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 558         5,
 559         45000,
 560         100,
 561         0xA,
 562         1,
 563         0,
 564         0x10,
 565         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 566         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 567         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 568         90,
 569         true
 570 };
 571
 572 static const struct si_dte_data dte_data_curacao_pro =
 573 {
 574         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 575         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 576         5,
 577         45000,
 578         100,
 579         0xA,
 580         1,
 581         0,
 582         0x10,
 583         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 584         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 585         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 586         90,
 587         true
 588 };
 589
 590 static const struct si_dte_data dte_data_neptune_xt =
 591 {
 592         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 593         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 594         5,
 595         45000,
 596         100,
 597         0xA,
 598         1,
 599         0,
 600         0x10,
 601         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 602         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 603         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 604         90,
 605         true
 606 };
 607
 608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 609 {
 610         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 611         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 612         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 613         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 614         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 615         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 616         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 617         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 618         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 619         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 620         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 621         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 622         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 623         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 624         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 625         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 626         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 627         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 628         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 629         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 630         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 631         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 632         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 633         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 634         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 635         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 636         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 637         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 638         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 639         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 640         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 641         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 642         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 643         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 644         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 645         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 646         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 647         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 648         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 649         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 650         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 651         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 652         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 653         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 654         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 655         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 656         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 657         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 658         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 659         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 660         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 661         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 662         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 663         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 664         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 665         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 666         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 667         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 668         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 669         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 670         { 0xFFFFFFFF }
 671 };
 672
 673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 674 {
 675         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 676         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 677         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 678         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 679         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 680         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 681         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 682         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 683         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 684         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 685         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 686         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 687         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 688         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 689         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 690         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 691         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 692         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 693         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 694         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 695         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 696         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 697         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 698         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 699         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 700         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 701         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 702         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 703         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 704         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 705         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 706         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 707         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 708         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 709         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 710         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 711         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 712         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 713         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 714         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 715         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 716         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 717         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 718         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 719         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 720         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 721         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 722         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 724         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 725         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 726         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 727         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 733         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 734         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 735         { 0xFFFFFFFF }
 736 };
 737
 738 static const struct si_cac_config_reg cac_weights_heathrow[] =
 739 {
 740         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 741         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 742         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 743         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 744         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 746         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 747         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 748         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 749         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 750         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 751         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 752         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 753         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 754         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 755         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 756         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 757         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 758         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 759         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 760         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 761         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 762         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 763         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 764         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 765         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 766         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 767         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 768         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 769         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 770         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 771         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 772         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 773         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 774         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 775         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 776         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 777         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 778         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 779         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 780         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 781         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 782         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 783         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 784         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 785         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 786         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 787         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 789         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 790         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 791         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 792         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 798         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 799         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 800         { 0xFFFFFFFF }
 801 };
 802
 803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 804 {
 805         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 806         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 807         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 808         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 809         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 811         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 812         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 813         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 814         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 815         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 816         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 817         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 818         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 819         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 820         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 821         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 822         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 823         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 824         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 825         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 826         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 827         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 828         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 829         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 830         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 831         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 832         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 833         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 834         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 835         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 836         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 837         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 838         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 839         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 840         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 841         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 842         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 843         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 844         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 845         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 846         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 847         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 848         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 849         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 850         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 851         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 852         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 854         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 855         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 856         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 857         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 863         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 864         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 865         { 0xFFFFFFFF }
 866 };
 867
 868 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 869 {
 870         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 871         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 872         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 873         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 874         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 876         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 877         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 878         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 879         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 880         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 881         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 882         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 883         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 884         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 885         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 886         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 887         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 888         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 889         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 890         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 891         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 892         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 893         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 894         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 895         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 896         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 897         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 898         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 899         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 900         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 901         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 902         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 903         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 904         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 905         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 906         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 907         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 908         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 909         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 910         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 911         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 912         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 913         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 914         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 915         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 916         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 917         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 919         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 920         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 921         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 922         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 928         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 929         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 930         { 0xFFFFFFFF }
 931 };
 932
 933 static const struct si_cac_config_reg lcac_cape_verde[] =
 934 {
 935         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 936         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 937         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 938         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 939         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 940         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 941         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 942         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 943         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 944         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 945         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 946         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 947         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 948         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 949         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 950         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 951         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 952         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 953         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 954         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 955         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 956         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 957         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 958         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 959         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 960         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 961         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 962         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 963         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 964         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 965         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 966         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 967         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 968         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 969         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 970         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 971         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 972         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 973         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 974         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 975         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 976         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 977         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 978         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 979         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 980         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 981         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 982         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 983         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 984         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 985         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 986         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 987         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 988         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 989         { 0xFFFFFFFF }
 990 };
 991
 992 static const struct si_cac_config_reg cac_override_cape_verde[] =
 993 {
 994         { 0xFFFFFFFF }
 995 };
 996
 997 static const struct si_powertune_data powertune_data_cape_verde =
 998 {
 999         ((1 << 16) | 0x6993),
1000         5,
1001         0,
1002         7,
1003         105,
1004         {
1005                 0UL,
1006                 0UL,
1007                 7194395UL,
1008                 309631529UL,
1009                 -1270850L,
1010                 4513710L,
1011                 100
1012         },
1013         117830498UL,
1014         12,
1015         {
1016                 0,
1017                 0,
1018                 0,
1019                 0,
1020                 0,
1021                 0,
1022                 0,
1023                 0
1024         },
1025         true
1026 };
1027
1028 static const struct si_dte_data dte_data_cape_verde =
1029 {
1030         { 0, 0, 0, 0, 0 },
1031         { 0, 0, 0, 0, 0 },
1032         0,
1033         0,
1034         0,
1035         0,
1036         0,
1037         0,
1038         0,
1039         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042         0,
1043         false
1044 };
1045
1046 static const struct si_dte_data dte_data_venus_xtx =
1047 {
1048         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1050         5,
1051         55000,
1052         0x69,
1053         0xA,
1054         1,
1055         0,
1056         0x3,
1057         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060         90,
1061         true
1062 };
1063
1064 static const struct si_dte_data dte_data_venus_xt =
1065 {
1066         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1068         5,
1069         55000,
1070         0x69,
1071         0xA,
1072         1,
1073         0,
1074         0x3,
1075         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078         90,
1079         true
1080 };
1081
1082 static const struct si_dte_data dte_data_venus_pro =
1083 {
1084         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1086         5,
1087         55000,
1088         0x69,
1089         0xA,
1090         1,
1091         0,
1092         0x3,
1093         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096         90,
1097         true
1098 };
1099
1100 struct si_cac_config_reg cac_weights_oland[] =
1101 {
1102         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1162         { 0xFFFFFFFF }
1163 };
1164
1165 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166 {
1167         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1227         { 0xFFFFFFFF }
1228 };
1229
1230 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231 {
1232         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1292         { 0xFFFFFFFF }
1293 };
1294
1295 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296 {
1297         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1357         { 0xFFFFFFFF }
1358 };
1359
1360 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361 {
1362         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1422         { 0xFFFFFFFF }
1423 };
1424
1425 static const struct si_cac_config_reg lcac_oland[] =
1426 {
1427         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469         { 0xFFFFFFFF }
1470 };
1471
1472 static const struct si_cac_config_reg lcac_mars_pro[] =
1473 {
1474         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516         { 0xFFFFFFFF }
1517 };
1518
1519 static const struct si_cac_config_reg cac_override_oland[] =
1520 {
1521         { 0xFFFFFFFF }
1522 };
1523
1524 static const struct si_powertune_data powertune_data_oland =
1525 {
1526         ((1 << 16) | 0x6993),
1527         5,
1528         0,
1529         7,
1530         105,
1531         {
1532                 0UL,
1533                 0UL,
1534                 7194395UL,
1535                 309631529UL,
1536                 -1270850L,
1537                 4513710L,
1538                 100
1539         },
1540         117830498UL,
1541         12,
1542         {
1543                 0,
1544                 0,
1545                 0,
1546                 0,
1547                 0,
1548                 0,
1549                 0,
1550                 0
1551         },
1552         true
1553 };
1554
1555 static const struct si_powertune_data powertune_data_mars_pro =
1556 {
1557         ((1 << 16) | 0x6993),
1558         5,
1559         0,
1560         7,
1561         105,
1562         {
1563                 0UL,
1564                 0UL,
1565                 7194395UL,
1566                 309631529UL,
1567                 -1270850L,
1568                 4513710L,
1569                 100
1570         },
1571         117830498UL,
1572         12,
1573         {
1574                 0,
1575                 0,
1576                 0,
1577                 0,
1578                 0,
1579                 0,
1580                 0,
1581                 0
1582         },
1583         true
1584 };
1585
1586 static const struct si_dte_data dte_data_oland =
1587 {
1588         { 0, 0, 0, 0, 0 },
1589         { 0, 0, 0, 0, 0 },
1590         0,
1591         0,
1592         0,
1593         0,
1594         0,
1595         0,
1596         0,
1597         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600         0,
1601         false
1602 };
1603
1604 static const struct si_dte_data dte_data_mars_pro =
1605 {
1606         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1608         5,
1609         55000,
1610         105,
1611         0xA,
1612         1,
1613         0,
1614         0x10,
1615         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1618         90,
1619         true
1620 };
1621
1622 static const struct si_dte_data dte_data_sun_xt =
1623 {
1624         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1626         5,
1627         55000,
1628         105,
1629         0xA,
1630         1,
1631         0,
1632         0x10,
1633         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1636         90,
1637         true
1638 };
1639
1640
1641 static const struct si_cac_config_reg cac_weights_hainan[] =
1642 {
1643         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1703         { 0xFFFFFFFF }
1704 };
1705
1706 static const struct si_powertune_data powertune_data_hainan =
1707 {
1708         ((1 << 16) | 0x6993),
1709         5,
1710         0,
1711         9,
1712         105,
1713         {
1714                 0UL,
1715                 0UL,
1716                 7194395UL,
1717                 309631529UL,
1718                 -1270850L,
1719                 4513710L,
1720                 100
1721         },
1722         117830498UL,
1723         12,
1724         {
1725                 0,
1726                 0,
1727                 0,
1728                 0,
1729                 0,
1730                 0,
1731                 0,
1732                 0
1733         },
1734         true
1735 };
1736
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1743 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1744
1745 static int si_populate_voltage_value(struct radeon_device *rdev,
1746                                      const struct atom_voltage_table *table,
1747                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1748 static int si_get_std_voltage_value(struct radeon_device *rdev,
1749                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1750                                     u16 *std_voltage);
1751 static int si_write_smc_soft_register(struct radeon_device *rdev,
1752                                       u16 reg_offset, u32 value);
1753 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1754                                          struct rv7xx_pl *pl,
1755                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1756 static int si_calculate_sclk_params(struct radeon_device *rdev,
1757                                     u32 engine_clock,
1758                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1759
1760 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1761 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1762
1763 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1764 {
1765         struct si_power_info *pi = rdev->pm.dpm.priv;
1766
1767         return pi;
1768 }
1769
1770 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1771                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1772 {
1773         s64 kt, kv, leakage_w, i_leakage, vddc;
1774         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1775         s64 tmp;
1776
1777         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1778         vddc = div64_s64(drm_int2fixp(v), 1000);
1779         temperature = div64_s64(drm_int2fixp(t), 1000);
1780
1781         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1782         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1783         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1784         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1785         t_ref = drm_int2fixp(coeff->t_ref);
1786
1787         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1788         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1789         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1790         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1791
1792         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1793
1794         *leakage = drm_fixp2int(leakage_w * 1000);
1795 }
1796
1797 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1798                                              const struct ni_leakage_coeffients *coeff,
1799                                              u16 v,
1800                                              s32 t,
1801                                              u32 i_leakage,
1802                                              u32 *leakage)
1803 {
1804         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1805 }
1806
1807 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1808                                                const u32 fixed_kt, u16 v,
1809                                                u32 ileakage, u32 *leakage)
1810 {
1811         s64 kt, kv, leakage_w, i_leakage, vddc;
1812
1813         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1814         vddc = div64_s64(drm_int2fixp(v), 1000);
1815
1816         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1817         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1818                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1819
1820         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1821
1822         *leakage = drm_fixp2int(leakage_w * 1000);
1823 }
1824
1825 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1826                                        const struct ni_leakage_coeffients *coeff,
1827                                        const u32 fixed_kt,
1828                                        u16 v,
1829                                        u32 i_leakage,
1830                                        u32 *leakage)
1831 {
1832         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1833 }
1834
1835
1836 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1837                                    struct si_dte_data *dte_data)
1838 {
1839         u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1840         u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1841         u32 k = dte_data->k;
1842         u32 t_max = dte_data->max_t;
1843         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1844         u32 t_0 = dte_data->t0;
1845         u32 i;
1846
1847         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1848                 dte_data->tdep_count = 3;
1849
1850                 for (i = 0; i < k; i++) {
1851                         dte_data->r[i] =
1852                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1853                                 (p_limit2  * (u32)100);
1854                 }
1855
1856                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1857
1858                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1859                         dte_data->tdep_r[i] = dte_data->r[4];
1860                 }
1861         } else {
1862                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1863         }
1864 }
1865
1866 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1867 {
1868         struct ni_power_info *ni_pi = ni_get_pi(rdev);
1869         struct si_power_info *si_pi = si_get_pi(rdev);
1870         bool update_dte_from_pl2 = false;
1871
1872         if (rdev->family == CHIP_TAHITI) {
1873                 si_pi->cac_weights = cac_weights_tahiti;
1874                 si_pi->lcac_config = lcac_tahiti;
1875                 si_pi->cac_override = cac_override_tahiti;
1876                 si_pi->powertune_data = &powertune_data_tahiti;
1877                 si_pi->dte_data = dte_data_tahiti;
1878
1879                 switch (rdev->pdev->device) {
1880                 case 0x6798:
1881                         si_pi->dte_data.enable_dte_by_default = true;
1882                         break;
1883                 case 0x6799:
1884                         si_pi->dte_data = dte_data_new_zealand;
1885                         break;
1886                 case 0x6790:
1887                 case 0x6791:
1888                 case 0x6792:
1889                 case 0x679E:
1890                         si_pi->dte_data = dte_data_aruba_pro;
1891                         update_dte_from_pl2 = true;
1892                         break;
1893                 case 0x679B:
1894                         si_pi->dte_data = dte_data_malta;
1895                         update_dte_from_pl2 = true;
1896                         break;
1897                 case 0x679A:
1898                         si_pi->dte_data = dte_data_tahiti_pro;
1899                         update_dte_from_pl2 = true;
1900                         break;
1901                 default:
1902                         if (si_pi->dte_data.enable_dte_by_default == true)
1903                                 DRM_ERROR("DTE is not enabled!\n");
1904                         break;
1905                 }
1906         } else if (rdev->family == CHIP_PITCAIRN) {
1907                 switch (rdev->pdev->device) {
1908                 case 0x6810:
1909                 case 0x6818:
1910                         si_pi->cac_weights = cac_weights_pitcairn;
1911                         si_pi->lcac_config = lcac_pitcairn;
1912                         si_pi->cac_override = cac_override_pitcairn;
1913                         si_pi->powertune_data = &powertune_data_pitcairn;
1914                         si_pi->dte_data = dte_data_curacao_xt;
1915                         update_dte_from_pl2 = true;
1916                         break;
1917                 case 0x6819:
1918                 case 0x6811:
1919                         si_pi->cac_weights = cac_weights_pitcairn;
1920                         si_pi->lcac_config = lcac_pitcairn;
1921                         si_pi->cac_override = cac_override_pitcairn;
1922                         si_pi->powertune_data = &powertune_data_pitcairn;
1923                         si_pi->dte_data = dte_data_curacao_pro;
1924                         update_dte_from_pl2 = true;
1925                         break;
1926                 case 0x6800:
1927                 case 0x6806:
1928                         si_pi->cac_weights = cac_weights_pitcairn;
1929                         si_pi->lcac_config = lcac_pitcairn;
1930                         si_pi->cac_override = cac_override_pitcairn;
1931                         si_pi->powertune_data = &powertune_data_pitcairn;
1932                         si_pi->dte_data = dte_data_neptune_xt;
1933                         update_dte_from_pl2 = true;
1934                         break;
1935                 default:
1936                         si_pi->cac_weights = cac_weights_pitcairn;
1937                         si_pi->lcac_config = lcac_pitcairn;
1938                         si_pi->cac_override = cac_override_pitcairn;
1939                         si_pi->powertune_data = &powertune_data_pitcairn;
1940                         si_pi->dte_data = dte_data_pitcairn;
1941                         break;
1942                 }
1943         } else if (rdev->family == CHIP_VERDE) {
1944                 si_pi->lcac_config = lcac_cape_verde;
1945                 si_pi->cac_override = cac_override_cape_verde;
1946                 si_pi->powertune_data = &powertune_data_cape_verde;
1947
1948                 switch (rdev->pdev->device) {
1949                 case 0x683B:
1950                 case 0x683F:
1951                 case 0x6829:
1952                 case 0x6835:
1953                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1954                         si_pi->dte_data = dte_data_cape_verde;
1955                         break;
1956                 case 0x682C:
1957                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1958                         si_pi->dte_data = dte_data_sun_xt;
1959                         break;
1960                 case 0x6825:
1961                 case 0x6827:
1962                         si_pi->cac_weights = cac_weights_heathrow;
1963                         si_pi->dte_data = dte_data_cape_verde;
1964                         break;
1965                 case 0x6824:
1966                 case 0x682D:
1967                         si_pi->cac_weights = cac_weights_chelsea_xt;
1968                         si_pi->dte_data = dte_data_cape_verde;
1969                         break;
1970                 case 0x682F:
1971                         si_pi->cac_weights = cac_weights_chelsea_pro;
1972                         si_pi->dte_data = dte_data_cape_verde;
1973                         break;
1974                 case 0x6820:
1975                         si_pi->cac_weights = cac_weights_heathrow;
1976                         si_pi->dte_data = dte_data_venus_xtx;
1977                         break;
1978                 case 0x6821:
1979                         si_pi->cac_weights = cac_weights_heathrow;
1980                         si_pi->dte_data = dte_data_venus_xt;
1981                         break;
1982                 case 0x6823:
1983                 case 0x682B:
1984                 case 0x6822:
1985                 case 0x682A:
1986                         si_pi->cac_weights = cac_weights_chelsea_pro;
1987                         si_pi->dte_data = dte_data_venus_pro;
1988                         break;
1989                 default:
1990                         si_pi->cac_weights = cac_weights_cape_verde;
1991                         si_pi->dte_data = dte_data_cape_verde;
1992                         break;
1993                 }
1994         } else if (rdev->family == CHIP_OLAND) {
1995                 switch (rdev->pdev->device) {
1996                 case 0x6601:
1997                 case 0x6621:
1998                 case 0x6603:
1999                 case 0x6605:
2000                         si_pi->cac_weights = cac_weights_mars_pro;
2001                         si_pi->lcac_config = lcac_mars_pro;
2002                         si_pi->cac_override = cac_override_oland;
2003                         si_pi->powertune_data = &powertune_data_mars_pro;
2004                         si_pi->dte_data = dte_data_mars_pro;
2005                         update_dte_from_pl2 = true;
2006                         break;
2007                 case 0x6600:
2008                 case 0x6606:
2009                 case 0x6620:
2010                 case 0x6604:
2011                         si_pi->cac_weights = cac_weights_mars_xt;
2012                         si_pi->lcac_config = lcac_mars_pro;
2013                         si_pi->cac_override = cac_override_oland;
2014                         si_pi->powertune_data = &powertune_data_mars_pro;
2015                         si_pi->dte_data = dte_data_mars_pro;
2016                         update_dte_from_pl2 = true;
2017                         break;
2018                 case 0x6611:
2019                 case 0x6613:
2020                 case 0x6608:
2021                         si_pi->cac_weights = cac_weights_oland_pro;
2022                         si_pi->lcac_config = lcac_mars_pro;
2023                         si_pi->cac_override = cac_override_oland;
2024                         si_pi->powertune_data = &powertune_data_mars_pro;
2025                         si_pi->dte_data = dte_data_mars_pro;
2026                         update_dte_from_pl2 = true;
2027                         break;
2028                 case 0x6610:
2029                         si_pi->cac_weights = cac_weights_oland_xt;
2030                         si_pi->lcac_config = lcac_mars_pro;
2031                         si_pi->cac_override = cac_override_oland;
2032                         si_pi->powertune_data = &powertune_data_mars_pro;
2033                         si_pi->dte_data = dte_data_mars_pro;
2034                         update_dte_from_pl2 = true;
2035                         break;
2036                 default:
2037                         si_pi->cac_weights = cac_weights_oland;
2038                         si_pi->lcac_config = lcac_oland;
2039                         si_pi->cac_override = cac_override_oland;
2040                         si_pi->powertune_data = &powertune_data_oland;
2041                         si_pi->dte_data = dte_data_oland;
2042                         break;
2043                 }
2044         } else if (rdev->family == CHIP_HAINAN) {
2045                 si_pi->cac_weights = cac_weights_hainan;
2046                 si_pi->lcac_config = lcac_oland;
2047                 si_pi->cac_override = cac_override_oland;
2048                 si_pi->powertune_data = &powertune_data_hainan;
2049                 si_pi->dte_data = dte_data_sun_xt;
2050                 update_dte_from_pl2 = true;
2051         } else {
2052                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2053                 return;
2054         }
2055
2056         ni_pi->enable_power_containment = false;
2057         ni_pi->enable_cac = false;
2058         ni_pi->enable_sq_ramping = false;
2059         si_pi->enable_dte = false;
2060
2061         if (si_pi->powertune_data->enable_powertune_by_default) {
2062                 ni_pi->enable_power_containment= true;
2063                 ni_pi->enable_cac = true;
2064                 if (si_pi->dte_data.enable_dte_by_default) {
2065                         si_pi->enable_dte = true;
2066                         if (update_dte_from_pl2)
2067                                 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2068
2069                 }
2070                 ni_pi->enable_sq_ramping = true;
2071         }
2072
2073         ni_pi->driver_calculate_cac_leakage = true;
2074         ni_pi->cac_configuration_required = true;
2075
2076         if (ni_pi->cac_configuration_required) {
2077                 ni_pi->support_cac_long_term_average = true;
2078                 si_pi->dyn_powertune_data.l2_lta_window_size =
2079                         si_pi->powertune_data->l2_lta_window_size_default;
2080                 si_pi->dyn_powertune_data.lts_truncate =
2081                         si_pi->powertune_data->lts_truncate_default;
2082         } else {
2083                 ni_pi->support_cac_long_term_average = false;
2084                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2085                 si_pi->dyn_powertune_data.lts_truncate = 0;
2086         }
2087
2088         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2089 }
2090
2091 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2092 {
2093         return 1;
2094 }
2095
2096 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2097 {
2098         u32 xclk;
2099         u32 wintime;
2100         u32 cac_window;
2101         u32 cac_window_size;
2102
2103         xclk = radeon_get_xclk(rdev);
2104
2105         if (xclk == 0)
2106                 return 0;
2107
2108         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2109         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2110
2111         wintime = (cac_window_size * 100) / xclk;
2112
2113         return wintime;
2114 }
2115
2116 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2117 {
2118         return power_in_watts;
2119 }
2120
2121 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2122                                             bool adjust_polarity,
2123                                             u32 tdp_adjustment,
2124                                             u32 *tdp_limit,
2125                                             u32 *near_tdp_limit)
2126 {
2127         u32 adjustment_delta, max_tdp_limit;
2128
2129         if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2130                 return -EINVAL;
2131
2132         max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2133
2134         if (adjust_polarity) {
2135                 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2136                 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2137         } else {
2138                 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2139                 adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2140                 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2141                         *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2142                 else
2143                         *near_tdp_limit = 0;
2144         }
2145
2146         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2147                 return -EINVAL;
2148         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2149                 return -EINVAL;
2150
2151         return 0;
2152 }
2153
2154 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2155                                       struct radeon_ps *radeon_state)
2156 {
2157         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2158         struct si_power_info *si_pi = si_get_pi(rdev);
2159
2160         if (ni_pi->enable_power_containment) {
2161                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2162                 PP_SIslands_PAPMParameters *papm_parm;
2163                 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2164                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2165                 u32 tdp_limit;
2166                 u32 near_tdp_limit;
2167                 int ret;
2168
2169                 if (scaling_factor == 0)
2170                         return -EINVAL;
2171
2172                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2173
2174                 ret = si_calculate_adjusted_tdp_limits(rdev,
2175                                                        false, /* ??? */
2176                                                        rdev->pm.dpm.tdp_adjustment,
2177                                                        &tdp_limit,
2178                                                        &near_tdp_limit);
2179                 if (ret)
2180                         return ret;
2181
2182                 smc_table->dpm2Params.TDPLimit =
2183                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2184                 smc_table->dpm2Params.NearTDPLimit =
2185                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2186                 smc_table->dpm2Params.SafePowerLimit =
2187                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2188
2189                 ret = si_copy_bytes_to_smc(rdev,
2190                                            (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2191                                                  offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2192                                            (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2193                                            sizeof(u32) * 3,
2194                                            si_pi->sram_end);
2195                 if (ret)
2196                         return ret;
2197
2198                 if (si_pi->enable_ppm) {
2199                         papm_parm = &si_pi->papm_parm;
2200                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2201                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2202                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2203                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2204                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2205                         papm_parm->PlatformPowerLimit = 0xffffffff;
2206                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2207
2208                         ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2209                                                    (u8 *)papm_parm,
2210                                                    sizeof(PP_SIslands_PAPMParameters),
2211                                                    si_pi->sram_end);
2212                         if (ret)
2213                                 return ret;
2214                 }
2215         }
2216         return 0;
2217 }
2218
2219 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2220                                         struct radeon_ps *radeon_state)
2221 {
2222         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2223         struct si_power_info *si_pi = si_get_pi(rdev);
2224
2225         if (ni_pi->enable_power_containment) {
2226                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2227                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2228                 int ret;
2229
2230                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2231
2232                 smc_table->dpm2Params.NearTDPLimit =
2233                         cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2234                 smc_table->dpm2Params.SafePowerLimit =
2235                         cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2236
2237                 ret = si_copy_bytes_to_smc(rdev,
2238                                            (si_pi->state_table_start +
2239                                             offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2240                                             offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2241                                            (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2242                                            sizeof(u32) * 2,
2243                                            si_pi->sram_end);
2244                 if (ret)
2245                         return ret;
2246         }
2247
2248         return 0;
2249 }
2250
2251 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2252                                                const u16 prev_std_vddc,
2253                                                const u16 curr_std_vddc)
2254 {
2255         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2256         u64 prev_vddc = (u64)prev_std_vddc;
2257         u64 curr_vddc = (u64)curr_std_vddc;
2258         u64 pwr_efficiency_ratio, n, d;
2259
2260         if ((prev_vddc == 0) || (curr_vddc == 0))
2261                 return 0;
2262
2263         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2264         d = prev_vddc * prev_vddc;
2265         pwr_efficiency_ratio = div64_u64(n, d);
2266
2267         if (pwr_efficiency_ratio > (u64)0xFFFF)
2268                 return 0;
2269
2270         return (u16)pwr_efficiency_ratio;
2271 }
2272
2273 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2274                                             struct radeon_ps *radeon_state)
2275 {
2276         struct si_power_info *si_pi = si_get_pi(rdev);
2277
2278         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2279             radeon_state->vclk && radeon_state->dclk)
2280                 return true;
2281
2282         return false;
2283 }
2284
2285 static int si_populate_power_containment_values(struct radeon_device *rdev,
2286                                                 struct radeon_ps *radeon_state,
2287                                                 SISLANDS_SMC_SWSTATE *smc_state)
2288 {
2289         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2290         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2291         struct ni_ps *state = ni_get_ps(radeon_state);
2292         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2293         u32 prev_sclk;
2294         u32 max_sclk;
2295         u32 min_sclk;
2296         u16 prev_std_vddc;
2297         u16 curr_std_vddc;
2298         int i;
2299         u16 pwr_efficiency_ratio;
2300         u8 max_ps_percent;
2301         bool disable_uvd_power_tune;
2302         int ret;
2303
2304         if (ni_pi->enable_power_containment == false)
2305                 return 0;
2306
2307         if (state->performance_level_count == 0)
2308                 return -EINVAL;
2309
2310         if (smc_state->levelCount != state->performance_level_count)
2311                 return -EINVAL;
2312
2313         disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2314
2315         smc_state->levels[0].dpm2.MaxPS = 0;
2316         smc_state->levels[0].dpm2.NearTDPDec = 0;
2317         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2318         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2319         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2320
2321         for (i = 1; i < state->performance_level_count; i++) {
2322                 prev_sclk = state->performance_levels[i-1].sclk;
2323                 max_sclk  = state->performance_levels[i].sclk;
2324                 if (i == 1)
2325                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2326                 else
2327                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2328
2329                 if (prev_sclk > max_sclk)
2330                         return -EINVAL;
2331
2332                 if ((max_ps_percent == 0) ||
2333                     (prev_sclk == max_sclk) ||
2334                     disable_uvd_power_tune) {
2335                         min_sclk = max_sclk;
2336                 } else if (i == 1) {
2337                         min_sclk = prev_sclk;
2338                 } else {
2339                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2340                 }
2341
2342                 if (min_sclk < state->performance_levels[0].sclk)
2343                         min_sclk = state->performance_levels[0].sclk;
2344
2345                 if (min_sclk == 0)
2346                         return -EINVAL;
2347
2348                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2349                                                 state->performance_levels[i-1].vddc, &vddc);
2350                 if (ret)
2351                         return ret;
2352
2353                 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2354                 if (ret)
2355                         return ret;
2356
2357                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2358                                                 state->performance_levels[i].vddc, &vddc);
2359                 if (ret)
2360                         return ret;
2361
2362                 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2363                 if (ret)
2364                         return ret;
2365
2366                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2367                                                                            prev_std_vddc, curr_std_vddc);
2368
2369                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2370                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2371                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2372                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2373                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2374         }
2375
2376         return 0;
2377 }
2378
2379 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2380                                          struct radeon_ps *radeon_state,
2381                                          SISLANDS_SMC_SWSTATE *smc_state)
2382 {
2383         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2384         struct ni_ps *state = ni_get_ps(radeon_state);
2385         u32 sq_power_throttle, sq_power_throttle2;
2386         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2387         int i;
2388
2389         if (state->performance_level_count == 0)
2390                 return -EINVAL;
2391
2392         if (smc_state->levelCount != state->performance_level_count)
2393                 return -EINVAL;
2394
2395         if (rdev->pm.dpm.sq_ramping_threshold == 0)
2396                 return -EINVAL;
2397
2398         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2399                 enable_sq_ramping = false;
2400
2401         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2402                 enable_sq_ramping = false;
2403
2404         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2405                 enable_sq_ramping = false;
2406
2407         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2408                 enable_sq_ramping = false;
2409
2410         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2411                 enable_sq_ramping = false;
2412
2413         for (i = 0; i < state->performance_level_count; i++) {
2414                 sq_power_throttle = 0;
2415                 sq_power_throttle2 = 0;
2416
2417                 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2418                     enable_sq_ramping) {
2419                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2420                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2421                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2422                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2423                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2424                 } else {
2425                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2426                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2427                 }
2428
2429                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2430                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2431         }
2432
2433         return 0;
2434 }
2435
2436 static int si_enable_power_containment(struct radeon_device *rdev,
2437                                        struct radeon_ps *radeon_new_state,
2438                                        bool enable)
2439 {
2440         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2441         PPSMC_Result smc_result;
2442         int ret = 0;
2443
2444         if (ni_pi->enable_power_containment) {
2445                 if (enable) {
2446                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2447                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2448                                 if (smc_result != PPSMC_Result_OK) {
2449                                         ret = -EINVAL;
2450                                         ni_pi->pc_enabled = false;
2451                                 } else {
2452                                         ni_pi->pc_enabled = true;
2453                                 }
2454                         }
2455                 } else {
2456                         smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2457                         if (smc_result != PPSMC_Result_OK)
2458                                 ret = -EINVAL;
2459                         ni_pi->pc_enabled = false;
2460                 }
2461         }
2462
2463         return ret;
2464 }
2465
2466 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2467 {
2468         struct si_power_info *si_pi = si_get_pi(rdev);
2469         int ret = 0;
2470         struct si_dte_data *dte_data = &si_pi->dte_data;
2471         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2472         u32 table_size;
2473         u8 tdep_count;
2474         u32 i;
2475
2476         if (dte_data == NULL)
2477                 si_pi->enable_dte = false;
2478
2479         if (si_pi->enable_dte == false)
2480                 return 0;
2481
2482         if (dte_data->k <= 0)
2483                 return -EINVAL;
2484
2485         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2486         if (dte_tables == NULL) {
2487                 si_pi->enable_dte = false;
2488                 return -ENOMEM;
2489         }
2490
2491         table_size = dte_data->k;
2492
2493         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2494                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2495
2496         tdep_count = dte_data->tdep_count;
2497         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2498                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2499
2500         dte_tables->K = cpu_to_be32(table_size);
2501         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2502         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2503         dte_tables->WindowSize = dte_data->window_size;
2504         dte_tables->temp_select = dte_data->temp_select;
2505         dte_tables->DTE_mode = dte_data->dte_mode;
2506         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2507
2508         if (tdep_count > 0)
2509                 table_size--;
2510
2511         for (i = 0; i < table_size; i++) {
2512                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2513                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2514         }
2515
2516         dte_tables->Tdep_count = tdep_count;
2517
2518         for (i = 0; i < (u32)tdep_count; i++) {
2519                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2520                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2521                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2522         }
2523
2524         ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2525                                    sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2526         kfree(dte_tables);
2527
2528         return ret;
2529 }
2530
2531 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2532                                           u16 *max, u16 *min)
2533 {
2534         struct si_power_info *si_pi = si_get_pi(rdev);
2535         struct radeon_cac_leakage_table *table =
2536                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2537         u32 i;
2538         u32 v0_loadline;
2539
2540
2541         if (table == NULL)
2542                 return -EINVAL;
2543
2544         *max = 0;
2545         *min = 0xFFFF;
2546
2547         for (i = 0; i < table->count; i++) {
2548                 if (table->entries[i].vddc > *max)
2549                         *max = table->entries[i].vddc;
2550                 if (table->entries[i].vddc < *min)
2551                         *min = table->entries[i].vddc;
2552         }
2553
2554         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2555                 return -EINVAL;
2556
2557         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2558
2559         if (v0_loadline > 0xFFFFUL)
2560                 return -EINVAL;
2561
2562         *min = (u16)v0_loadline;
2563
2564         if ((*min > *max) || (*max == 0) || (*min == 0))
2565                 return -EINVAL;
2566
2567         return 0;
2568 }
2569
2570 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2571 {
2572         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2573                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2574 }
2575
2576 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2577                                      PP_SIslands_CacConfig *cac_tables,
2578                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2579                                      u16 t0, u16 t_step)
2580 {
2581         struct si_power_info *si_pi = si_get_pi(rdev);
2582         u32 leakage;
2583         unsigned int i, j;
2584         s32 t;
2585         u32 smc_leakage;
2586         u32 scaling_factor;
2587         u16 voltage;
2588
2589         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2590
2591         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2592                 t = (1000 * (i * t_step + t0));
2593
2594                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2595                         voltage = vddc_max - (vddc_step * j);
2596
2597                         si_calculate_leakage_for_v_and_t(rdev,
2598                                                          &si_pi->powertune_data->leakage_coefficients,
2599                                                          voltage,
2600                                                          t,
2601                                                          si_pi->dyn_powertune_data.cac_leakage,
2602                                                          &leakage);
2603
2604                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2605
2606                         if (smc_leakage > 0xFFFF)
2607                                 smc_leakage = 0xFFFF;
2608
2609                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2610                                 cpu_to_be16((u16)smc_leakage);
2611                 }
2612         }
2613         return 0;
2614 }
2615
2616 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2617                                             PP_SIslands_CacConfig *cac_tables,
2618                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2619 {
2620         struct si_power_info *si_pi = si_get_pi(rdev);
2621         u32 leakage;
2622         unsigned int i, j;
2623         u32 smc_leakage;
2624         u32 scaling_factor;
2625         u16 voltage;
2626
2627         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2628
2629         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2630                 voltage = vddc_max - (vddc_step * j);
2631
2632                 si_calculate_leakage_for_v(rdev,
2633                                            &si_pi->powertune_data->leakage_coefficients,
2634                                            si_pi->powertune_data->fixed_kt,
2635                                            voltage,
2636                                            si_pi->dyn_powertune_data.cac_leakage,
2637                                            &leakage);
2638
2639                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2640
2641                 if (smc_leakage > 0xFFFF)
2642                         smc_leakage = 0xFFFF;
2643
2644                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2645                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2646                                 cpu_to_be16((u16)smc_leakage);
2647         }
2648         return 0;
2649 }
2650
2651 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2652 {
2653         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2654         struct si_power_info *si_pi = si_get_pi(rdev);
2655         PP_SIslands_CacConfig *cac_tables = NULL;
2656         u16 vddc_max, vddc_min, vddc_step;
2657         u16 t0, t_step;
2658         u32 load_line_slope, reg;
2659         int ret = 0;
2660         u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2661
2662         if (ni_pi->enable_cac == false)
2663                 return 0;
2664
2665         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2666         if (!cac_tables)
2667                 return -ENOMEM;
2668
2669         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2670         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2671         WREG32(CG_CAC_CTRL, reg);
2672
2673         si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2674         si_pi->dyn_powertune_data.dc_pwr_value =
2675                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2676         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2677         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2678
2679         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2680
2681         ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2682         if (ret)
2683                 goto done_free;
2684
2685         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2686         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2687         t_step = 4;
2688         t0 = 60;
2689
2690         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2691                 ret = si_init_dte_leakage_table(rdev, cac_tables,
2692                                                 vddc_max, vddc_min, vddc_step,
2693                                                 t0, t_step);
2694         else
2695                 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2696                                                        vddc_max, vddc_min, vddc_step);
2697         if (ret)
2698                 goto done_free;
2699
2700         load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2701
2702         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2703         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2704         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2705         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2706         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2707         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2708         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2709         cac_tables->calculation_repeats = cpu_to_be32(2);
2710         cac_tables->dc_cac = cpu_to_be32(0);
2711         cac_tables->log2_PG_LKG_SCALE = 12;
2712         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2713         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2714         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2715
2716         ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2717                                    sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2718
2719         if (ret)
2720                 goto done_free;
2721
2722         ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2723
2724 done_free:
2725         if (ret) {
2726                 ni_pi->enable_cac = false;
2727                 ni_pi->enable_power_containment = false;
2728         }
2729
2730         kfree(cac_tables);
2731
2732         return 0;
2733 }
2734
2735 static int si_program_cac_config_registers(struct radeon_device *rdev,
2736                                            const struct si_cac_config_reg *cac_config_regs)
2737 {
2738         const struct si_cac_config_reg *config_regs = cac_config_regs;
2739         u32 data = 0, offset;
2740
2741         if (!config_regs)
2742                 return -EINVAL;
2743
2744         while (config_regs->offset != 0xFFFFFFFF) {
2745                 switch (config_regs->type) {
2746                 case SISLANDS_CACCONFIG_CGIND:
2747                         offset = SMC_CG_IND_START + config_regs->offset;
2748                         if (offset < SMC_CG_IND_END)
2749                                 data = RREG32_SMC(offset);
2750                         break;
2751                 default:
2752                         data = RREG32(config_regs->offset << 2);
2753                         break;
2754                 }
2755
2756                 data &= ~config_regs->mask;
2757                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2758
2759                 switch (config_regs->type) {
2760                 case SISLANDS_CACCONFIG_CGIND:
2761                         offset = SMC_CG_IND_START + config_regs->offset;
2762                         if (offset < SMC_CG_IND_END)
2763                                 WREG32_SMC(offset, data);
2764                         break;
2765                 default:
2766                         WREG32(config_regs->offset << 2, data);
2767                         break;
2768                 }
2769                 config_regs++;
2770         }
2771         return 0;
2772 }
2773
2774 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2775 {
2776         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2777         struct si_power_info *si_pi = si_get_pi(rdev);
2778         int ret;
2779
2780         if ((ni_pi->enable_cac == false) ||
2781             (ni_pi->cac_configuration_required == false))
2782                 return 0;
2783
2784         ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2785         if (ret)
2786                 return ret;
2787         ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2788         if (ret)
2789                 return ret;
2790         ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2791         if (ret)
2792                 return ret;
2793
2794         return 0;
2795 }
2796
2797 static int si_enable_smc_cac(struct radeon_device *rdev,
2798                              struct radeon_ps *radeon_new_state,
2799                              bool enable)
2800 {
2801         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2802         struct si_power_info *si_pi = si_get_pi(rdev);
2803         PPSMC_Result smc_result;
2804         int ret = 0;
2805
2806         if (ni_pi->enable_cac) {
2807                 if (enable) {
2808                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2809                                 if (ni_pi->support_cac_long_term_average) {
2810                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2811                                         if (smc_result != PPSMC_Result_OK)
2812                                                 ni_pi->support_cac_long_term_average = false;
2813                                 }
2814
2815                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2816                                 if (smc_result != PPSMC_Result_OK) {
2817                                         ret = -EINVAL;
2818                                         ni_pi->cac_enabled = false;
2819                                 } else {
2820                                         ni_pi->cac_enabled = true;
2821                                 }
2822
2823                                 if (si_pi->enable_dte) {
2824                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2825                                         if (smc_result != PPSMC_Result_OK)
2826                                                 ret = -EINVAL;
2827                                 }
2828                         }
2829                 } else if (ni_pi->cac_enabled) {
2830                         if (si_pi->enable_dte)
2831                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2832
2833                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2834
2835                         ni_pi->cac_enabled = false;
2836
2837                         if (ni_pi->support_cac_long_term_average)
2838                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2839                 }
2840         }
2841         return ret;
2842 }
2843
2844 static int si_init_smc_spll_table(struct radeon_device *rdev)
2845 {
2846         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2847         struct si_power_info *si_pi = si_get_pi(rdev);
2848         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2849         SISLANDS_SMC_SCLK_VALUE sclk_params;
2850         u32 fb_div, p_div;
2851         u32 clk_s, clk_v;
2852         u32 sclk = 0;
2853         int ret = 0;
2854         u32 tmp;
2855         int i;
2856
2857         if (si_pi->spll_table_start == 0)
2858                 return -EINVAL;
2859
2860         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2861         if (spll_table == NULL)
2862                 return -ENOMEM;
2863
2864         for (i = 0; i < 256; i++) {
2865                 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2866                 if (ret)
2867                         break;
2868
2869                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2870                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2871                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2872                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2873
2874                 fb_div &= ~0x00001FFF;
2875                 fb_div >>= 1;
2876                 clk_v >>= 6;
2877
2878                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2879                         ret = -EINVAL;
2880                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2881                         ret = -EINVAL;
2882                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2883                         ret = -EINVAL;
2884                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2885                         ret = -EINVAL;
2886
2887                 if (ret)
2888                         break;
2889
2890                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2891                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2892                 spll_table->freq[i] = cpu_to_be32(tmp);
2893
2894                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2895                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2896                 spll_table->ss[i] = cpu_to_be32(tmp);
2897
2898                 sclk += 512;
2899         }
2900
2901
2902         if (!ret)
2903                 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2904                                            (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2905                                            si_pi->sram_end);
2906
2907         if (ret)
2908                 ni_pi->enable_power_containment = false;
2909
2910         kfree(spll_table);
2911
2912         return ret;
2913 }
2914
2915 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2916                                                    u16 vce_voltage)
2917 {
2918         u16 highest_leakage = 0;
2919         struct si_power_info *si_pi = si_get_pi(rdev);
2920         int i;
2921
2922         for (i = 0; i < si_pi->leakage_voltage.count; i++){
2923                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2924                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2925         }
2926
2927         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2928                 return highest_leakage;
2929
2930         return vce_voltage;
2931 }
2932
2933 static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2934                                     u32 evclk, u32 ecclk, u16 *voltage)
2935 {
2936         u32 i;
2937         int ret = -EINVAL;
2938         struct radeon_vce_clock_voltage_dependency_table *table =
2939                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2940
2941         if (((evclk == 0) && (ecclk == 0)) ||
2942             (table && (table->count == 0))) {
2943                 *voltage = 0;
2944                 return 0;
2945         }
2946
2947         for (i = 0; i < table->count; i++) {
2948                 if ((evclk <= table->entries[i].evclk) &&
2949                     (ecclk <= table->entries[i].ecclk)) {
2950                         *voltage = table->entries[i].v;
2951                         ret = 0;
2952                         break;
2953                 }
2954         }
2955
2956         /* if no match return the highest voltage */
2957         if (ret)
2958                 *voltage = table->entries[table->count - 1].v;
2959
2960         *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2961
2962         return ret;
2963 }
2964
2965 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2966                                         struct radeon_ps *rps)
2967 {
2968         struct ni_ps *ps = ni_get_ps(rps);
2969         struct radeon_clock_and_voltage_limits *max_limits;
2970         bool disable_mclk_switching = false;
2971         bool disable_sclk_switching = false;
2972         u32 mclk, sclk;
2973         u16 vddc, vddci, min_vce_voltage = 0;
2974         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2975         u32 max_sclk = 0, max_mclk = 0;
2976         int i;
2977
2978         if (rdev->family == CHIP_HAINAN) {
2979                 if ((rdev->pdev->revision == 0x81) ||
2980                     (rdev->pdev->revision == 0x83) ||
2981                     (rdev->pdev->revision == 0xC3) ||
2982                     (rdev->pdev->device == 0x6664) ||
2983                     (rdev->pdev->device == 0x6665) ||
2984                     (rdev->pdev->device == 0x6667)) {
2985                         max_sclk = 75000;
2986                 }
2987                 if ((rdev->pdev->revision == 0xC3) ||
2988                     (rdev->pdev->device == 0x6665)) {
2989                         max_sclk = 60000;
2990                         max_mclk = 80000;
2991                 }
2992         } else if (rdev->family == CHIP_OLAND) {
2993                 if ((rdev->pdev->revision == 0xC7) ||
2994                     (rdev->pdev->revision == 0x80) ||
2995                     (rdev->pdev->revision == 0x81) ||
2996                     (rdev->pdev->revision == 0x83) ||
2997                     (rdev->pdev->revision == 0x87) ||
2998                     (rdev->pdev->device == 0x6604) ||
2999                     (rdev->pdev->device == 0x6605)) {
3000                         max_sclk = 75000;
3001                 }
3002         }
3003
3004         if (rps->vce_active) {
3005                 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
3006                 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
3007                 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3008                                          &min_vce_voltage);
3009         } else {
3010                 rps->evclk = 0;
3011                 rps->ecclk = 0;
3012         }
3013
3014         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3015             ni_dpm_vblank_too_short(rdev))
3016                 disable_mclk_switching = true;
3017
3018         if (rps->vclk || rps->dclk) {
3019                 disable_mclk_switching = true;
3020                 disable_sclk_switching = true;
3021         }
3022
3023         if (rdev->pm.dpm.ac_power)
3024                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3025         else
3026                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3027
3028         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3029                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3030                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3031         }
3032         if (rdev->pm.dpm.ac_power == false) {
3033                 for (i = 0; i < ps->performance_level_count; i++) {
3034                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3035                                 ps->performance_levels[i].mclk = max_limits->mclk;
3036                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3037                                 ps->performance_levels[i].sclk = max_limits->sclk;
3038                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3039                                 ps->performance_levels[i].vddc = max_limits->vddc;
3040                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3041                                 ps->performance_levels[i].vddci = max_limits->vddci;
3042                 }
3043         }
3044
3045         /* limit clocks to max supported clocks based on voltage dependency tables */
3046         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3047                                                         &max_sclk_vddc);
3048         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3049                                                         &max_mclk_vddci);
3050         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3051                                                         &max_mclk_vddc);
3052
3053         for (i = 0; i < ps->performance_level_count; i++) {
3054                 if (max_sclk_vddc) {
3055                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3056                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3057                 }
3058                 if (max_mclk_vddci) {
3059                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3060                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3061                 }
3062                 if (max_mclk_vddc) {
3063                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3064                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3065                 }
3066                 if (max_mclk) {
3067                         if (ps->performance_levels[i].mclk > max_mclk)
3068                                 ps->performance_levels[i].mclk = max_mclk;
3069                 }
3070                 if (max_sclk) {
3071                         if (ps->performance_levels[i].sclk > max_sclk)
3072                                 ps->performance_levels[i].sclk = max_sclk;
3073                 }
3074         }
3075
3076         /* XXX validate the min clocks required for display */
3077
3078         if (disable_mclk_switching) {
3079                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3080                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3081         } else {
3082                 mclk = ps->performance_levels[0].mclk;
3083                 vddci = ps->performance_levels[0].vddci;
3084         }
3085
3086         if (disable_sclk_switching) {
3087                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3088                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3089         } else {
3090                 sclk = ps->performance_levels[0].sclk;
3091                 vddc = ps->performance_levels[0].vddc;
3092         }
3093
3094         if (rps->vce_active) {
3095                 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3096                         sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3097                 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3098                         mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3099         }
3100
3101         /* adjusted low state */
3102         ps->performance_levels[0].sclk = sclk;
3103         ps->performance_levels[0].mclk = mclk;
3104         ps->performance_levels[0].vddc = vddc;
3105         ps->performance_levels[0].vddci = vddci;
3106
3107         if (disable_sclk_switching) {
3108                 sclk = ps->performance_levels[0].sclk;
3109                 for (i = 1; i < ps->performance_level_count; i++) {
3110                         if (sclk < ps->performance_levels[i].sclk)
3111                                 sclk = ps->performance_levels[i].sclk;
3112                 }
3113                 for (i = 0; i < ps->performance_level_count; i++) {
3114                         ps->performance_levels[i].sclk = sclk;
3115                         ps->performance_levels[i].vddc = vddc;
3116                 }
3117         } else {
3118                 for (i = 1; i < ps->performance_level_count; i++) {
3119                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3120                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3121                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3122                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3123                 }
3124         }
3125
3126         if (disable_mclk_switching) {
3127                 mclk = ps->performance_levels[0].mclk;
3128                 for (i = 1; i < ps->performance_level_count; i++) {
3129                         if (mclk < ps->performance_levels[i].mclk)
3130                                 mclk = ps->performance_levels[i].mclk;
3131                 }
3132                 for (i = 0; i < ps->performance_level_count; i++) {
3133                         ps->performance_levels[i].mclk = mclk;
3134                         ps->performance_levels[i].vddci = vddci;
3135                 }
3136         } else {
3137                 for (i = 1; i < ps->performance_level_count; i++) {
3138                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3139                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3140                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3141                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3142                 }
3143         }
3144
3145         for (i = 0; i < ps->performance_level_count; i++)
3146                 btc_adjust_clock_combinations(rdev, max_limits,
3147                                               &ps->performance_levels[i]);
3148
3149         for (i = 0; i < ps->performance_level_count; i++) {
3150                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3151                         ps->performance_levels[i].vddc = min_vce_voltage;
3152                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3153                                                    ps->performance_levels[i].sclk,
3154                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3155                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3156                                                    ps->performance_levels[i].mclk,
3157                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3158                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3159                                                    ps->performance_levels[i].mclk,
3160                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3161                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3162                                                    rdev->clock.current_dispclk,
3163                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3164         }
3165
3166         for (i = 0; i < ps->performance_level_count; i++) {
3167                 btc_apply_voltage_delta_rules(rdev,
3168                                               max_limits->vddc, max_limits->vddci,
3169                                               &ps->performance_levels[i].vddc,
3170                                               &ps->performance_levels[i].vddci);
3171         }
3172
3173         ps->dc_compatible = true;
3174         for (i = 0; i < ps->performance_level_count; i++) {
3175                 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3176                         ps->dc_compatible = false;
3177         }
3178 }
3179
3180 #if 0
3181 static int si_read_smc_soft_register(struct radeon_device *rdev,
3182                                      u16 reg_offset, u32 *value)
3183 {
3184         struct si_power_info *si_pi = si_get_pi(rdev);
3185
3186         return si_read_smc_sram_dword(rdev,
3187                                       si_pi->soft_regs_start + reg_offset, value,
3188                                       si_pi->sram_end);
3189 }
3190 #endif
3191
3192 static int si_write_smc_soft_register(struct radeon_device *rdev,
3193                                       u16 reg_offset, u32 value)
3194 {
3195         struct si_power_info *si_pi = si_get_pi(rdev);
3196
3197         return si_write_smc_sram_dword(rdev,
3198                                        si_pi->soft_regs_start + reg_offset,
3199                                        value, si_pi->sram_end);
3200 }
3201
3202 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3203 {
3204         bool ret = false;
3205         u32 tmp, width, row, column, bank, density;
3206         bool is_memory_gddr5, is_special;
3207
3208         tmp = RREG32(MC_SEQ_MISC0);
3209         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3210         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3211                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3212
3213         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3214         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3215
3216         tmp = RREG32(MC_ARB_RAMCFG);
3217         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3218         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3219         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3220
3221         density = (1 << (row + column - 20 + bank)) * width;
3222
3223         if ((rdev->pdev->device == 0x6819) &&
3224             is_memory_gddr5 && is_special && (density == 0x400))
3225                 ret = true;
3226
3227         return ret;
3228 }
3229
3230 static void si_get_leakage_vddc(struct radeon_device *rdev)
3231 {
3232         struct si_power_info *si_pi = si_get_pi(rdev);
3233         u16 vddc, count = 0;
3234         int i, ret;
3235
3236         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3237                 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3238
3239                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3240                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3241                         si_pi->leakage_voltage.entries[count].leakage_index =
3242                                 SISLANDS_LEAKAGE_INDEX0 + i;
3243                         count++;
3244                 }
3245         }
3246         si_pi->leakage_voltage.count = count;
3247 }
3248
3249 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3250                                                      u32 index, u16 *leakage_voltage)
3251 {
3252         struct si_power_info *si_pi = si_get_pi(rdev);
3253         int i;
3254
3255         if (leakage_voltage == NULL)
3256                 return -EINVAL;
3257
3258         if ((index & 0xff00) != 0xff00)
3259                 return -EINVAL;
3260
3261         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3262                 return -EINVAL;
3263
3264         if (index < SISLANDS_LEAKAGE_INDEX0)
3265                 return -EINVAL;
3266
3267         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3268                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3269                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3270                         return 0;
3271                 }
3272         }
3273         return -EAGAIN;
3274 }
3275
3276 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3277 {
3278         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3279         bool want_thermal_protection;
3280         enum radeon_dpm_event_src dpm_event_src;
3281
3282         switch (sources) {
3283         case 0:
3284         default:
3285                 want_thermal_protection = false;
3286                 break;
3287         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3288                 want_thermal_protection = true;
3289                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3290                 break;
3291         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3292                 want_thermal_protection = true;
3293                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3294                 break;
3295         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3296               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3297                 want_thermal_protection = true;
3298                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3299                 break;
3300         }
3301
3302         if (want_thermal_protection) {
3303                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3304                 if (pi->thermal_protection)
3305                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3306         } else {
3307                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3308         }
3309 }
3310
3311 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3312                                            enum radeon_dpm_auto_throttle_src source,
3313                                            bool enable)
3314 {
3315         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3316
3317         if (enable) {
3318                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3319                         pi->active_auto_throttle_sources |= 1 << source;
3320                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3321                 }
3322         } else {
3323                 if (pi->active_auto_throttle_sources & (1 << source)) {
3324                         pi->active_auto_throttle_sources &= ~(1 << source);
3325                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3326                 }
3327         }
3328 }
3329
3330 static void si_start_dpm(struct radeon_device *rdev)
3331 {
3332         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3333 }
3334
3335 static void si_stop_dpm(struct radeon_device *rdev)
3336 {
3337         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3338 }
3339
3340 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3341 {
3342         if (enable)
3343                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3344         else
3345                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3346
3347 }
3348
3349 #if 0
3350 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3351                                                u32 thermal_level)
3352 {
3353         PPSMC_Result ret;
3354
3355         if (thermal_level == 0) {
3356                 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3357                 if (ret == PPSMC_Result_OK)
3358                         return 0;
3359                 else
3360                         return -EINVAL;
3361         }
3362         return 0;
3363 }
3364
3365 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3366 {
3367         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3368 }
3369 #endif
3370
3371 #if 0
3372 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3373 {
3374         if (ac_power)
3375                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3376                         0 : -EINVAL;
3377
3378         return 0;
3379 }
3380 #endif
3381
3382 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3383                                                       PPSMC_Msg msg, u32 parameter)
3384 {
3385         WREG32(SMC_SCRATCH0, parameter);
3386         return si_send_msg_to_smc(rdev, msg);
3387 }
3388
3389 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3390 {
3391         if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3392                 return -EINVAL;
3393
3394         return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3395                 0 : -EINVAL;
3396 }
3397
3398 int si_dpm_force_performance_level(struct radeon_device *rdev,
3399                                    enum radeon_dpm_forced_level level)
3400 {
3401         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3402         struct ni_ps *ps = ni_get_ps(rps);
3403         u32 levels = ps->performance_level_count;
3404
3405         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3406                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3407                         return -EINVAL;
3408
3409                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3410                         return -EINVAL;
3411         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3412                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3413                         return -EINVAL;
3414
3415                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3416                         return -EINVAL;
3417         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3418                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3419                         return -EINVAL;
3420
3421                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3422                         return -EINVAL;
3423         }
3424
3425         rdev->pm.dpm.forced_level = level;
3426
3427         return 0;
3428 }
3429
3430 #if 0
3431 static int si_set_boot_state(struct radeon_device *rdev)
3432 {
3433         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3434                 0 : -EINVAL;
3435 }
3436 #endif
3437
3438 static int si_set_sw_state(struct radeon_device *rdev)
3439 {
3440         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3441                 0 : -EINVAL;
3442 }
3443
3444 static int si_halt_smc(struct radeon_device *rdev)
3445 {
3446         if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3447                 return -EINVAL;
3448
3449         return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3450                 0 : -EINVAL;
3451 }
3452
3453 static int si_resume_smc(struct radeon_device *rdev)
3454 {
3455         if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3456                 return -EINVAL;
3457
3458         return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3459                 0 : -EINVAL;
3460 }
3461
3462 static void si_dpm_start_smc(struct radeon_device *rdev)
3463 {
3464         si_program_jump_on_start(rdev);
3465         si_start_smc(rdev);
3466         si_start_smc_clock(rdev);
3467 }
3468
3469 static void si_dpm_stop_smc(struct radeon_device *rdev)
3470 {
3471         si_reset_smc(rdev);
3472         si_stop_smc_clock(rdev);
3473 }
3474
3475 static int si_process_firmware_header(struct radeon_device *rdev)
3476 {
3477         struct si_power_info *si_pi = si_get_pi(rdev);
3478         u32 tmp;
3479         int ret;
3480
3481         ret = si_read_smc_sram_dword(rdev,
3482                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3483                                      SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3484                                      &tmp, si_pi->sram_end);
3485         if (ret)
3486                 return ret;
3487
3488         si_pi->state_table_start = tmp;
3489
3490         ret = si_read_smc_sram_dword(rdev,
3491                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3492                                      SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3493                                      &tmp, si_pi->sram_end);
3494         if (ret)
3495                 return ret;
3496
3497         si_pi->soft_regs_start = tmp;
3498
3499         ret = si_read_smc_sram_dword(rdev,
3500                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3501                                      SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3502                                      &tmp, si_pi->sram_end);
3503         if (ret)
3504                 return ret;
3505
3506         si_pi->mc_reg_table_start = tmp;
3507
3508         ret = si_read_smc_sram_dword(rdev,
3509                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3510                                      SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3511                                      &tmp, si_pi->sram_end);
3512         if (ret)
3513                 return ret;
3514
3515         si_pi->fan_table_start = tmp;
3516
3517         ret = si_read_smc_sram_dword(rdev,
3518                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3519                                      SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3520                                      &tmp, si_pi->sram_end);
3521         if (ret)
3522                 return ret;
3523
3524         si_pi->arb_table_start = tmp;
3525
3526         ret = si_read_smc_sram_dword(rdev,
3527                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3528                                      SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3529                                      &tmp, si_pi->sram_end);
3530         if (ret)
3531                 return ret;
3532
3533         si_pi->cac_table_start = tmp;
3534
3535         ret = si_read_smc_sram_dword(rdev,
3536                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3537                                      SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3538                                      &tmp, si_pi->sram_end);
3539         if (ret)
3540                 return ret;
3541
3542         si_pi->dte_table_start = tmp;
3543
3544         ret = si_read_smc_sram_dword(rdev,
3545                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3546                                      SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3547                                      &tmp, si_pi->sram_end);
3548         if (ret)
3549                 return ret;
3550
3551         si_pi->spll_table_start = tmp;
3552
3553         ret = si_read_smc_sram_dword(rdev,
3554                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3555                                      SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3556                                      &tmp, si_pi->sram_end);
3557         if (ret)
3558                 return ret;
3559
3560         si_pi->papm_cfg_table_start = tmp;
3561
3562         return ret;
3563 }
3564
3565 static void si_read_clock_registers(struct radeon_device *rdev)
3566 {
3567         struct si_power_info *si_pi = si_get_pi(rdev);
3568
3569         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3570         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3571         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3572         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3573         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3574         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3575         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3576         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3577         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3578         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3579         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3580         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3581         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3582         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3583         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3584 }
3585
3586 static void si_enable_thermal_protection(struct radeon_device *rdev,
3587                                           bool enable)
3588 {
3589         if (enable)
3590                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3591         else
3592                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3593 }
3594
3595 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3596 {
3597         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3598 }
3599
3600 #if 0
3601 static int si_enter_ulp_state(struct radeon_device *rdev)
3602 {
3603         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3604
3605         udelay(25000);
3606
3607         return 0;
3608 }
3609
3610 static int si_exit_ulp_state(struct radeon_device *rdev)
3611 {
3612         int i;
3613
3614         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3615
3616         udelay(7000);
3617
3618         for (i = 0; i < rdev->usec_timeout; i++) {
3619                 if (RREG32(SMC_RESP_0) == 1)
3620                         break;
3621                 udelay(1000);
3622         }
3623
3624         return 0;
3625 }
3626 #endif
3627
3628 static int si_notify_smc_display_change(struct radeon_device *rdev,
3629                                      bool has_display)
3630 {
3631         PPSMC_Msg msg = has_display ?
3632                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3633
3634         return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3635                 0 : -EINVAL;
3636 }
3637
3638 static void si_program_response_times(struct radeon_device *rdev)
3639 {
3640         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3641         u32 vddc_dly, acpi_dly, vbi_dly;
3642         u32 reference_clock;
3643
3644         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3645
3646         voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3647         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3648
3649         if (voltage_response_time == 0)
3650                 voltage_response_time = 1000;
3651
3652         acpi_delay_time = 15000;
3653         vbi_time_out = 100000;
3654
3655         reference_clock = radeon_get_xclk(rdev);
3656
3657         vddc_dly = (voltage_response_time  * reference_clock) / 100;
3658         acpi_dly = (acpi_delay_time * reference_clock) / 100;
3659         vbi_dly  = (vbi_time_out * reference_clock) / 100;
3660
3661         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3662         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3663         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3664         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3665 }
3666
3667 static void si_program_ds_registers(struct radeon_device *rdev)
3668 {
3669         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3670         u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3671
3672         if (eg_pi->sclk_deep_sleep) {
3673                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3674                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3675                          ~AUTOSCALE_ON_SS_CLEAR);
3676         }
3677 }
3678
3679 static void si_program_display_gap(struct radeon_device *rdev)
3680 {
3681         u32 tmp, pipe;
3682         int i;
3683
3684         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3685         if (rdev->pm.dpm.new_active_crtc_count > 0)
3686                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3687         else
3688                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3689
3690         if (rdev->pm.dpm.new_active_crtc_count > 1)
3691                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3692         else
3693                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3694
3695         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3696
3697         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3698         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3699
3700         if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3701             (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3702                 /* find the first active crtc */
3703                 for (i = 0; i < rdev->num_crtc; i++) {
3704                         if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3705                                 break;
3706                 }
3707                 if (i == rdev->num_crtc)
3708                         pipe = 0;
3709                 else
3710                         pipe = i;
3711
3712                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3713                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3714                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3715         }
3716
3717         /* Setting this to false forces the performance state to low if the crtcs are disabled.
3718          * This can be a problem on PowerXpress systems or if you want to use the card
3719          * for offscreen rendering or compute if there are no crtcs enabled.
3720          */
3721         si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3722 }
3723
3724 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3725 {
3726         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3727
3728         if (enable) {
3729                 if (pi->sclk_ss)
3730                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3731         } else {
3732                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3733                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3734         }
3735 }
3736
3737 static void si_setup_bsp(struct radeon_device *rdev)
3738 {
3739         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3740         u32 xclk = radeon_get_xclk(rdev);
3741
3742         r600_calculate_u_and_p(pi->asi,
3743                                xclk,
3744                                16,
3745                                &pi->bsp,
3746                                &pi->bsu);
3747
3748         r600_calculate_u_and_p(pi->pasi,
3749                                xclk,
3750                                16,
3751                                &pi->pbsp,
3752                                &pi->pbsu);
3753
3754
3755         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3756         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3757
3758         WREG32(CG_BSP, pi->dsp);
3759 }
3760
3761 static void si_program_git(struct radeon_device *rdev)
3762 {
3763         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3764 }
3765
3766 static void si_program_tp(struct radeon_device *rdev)
3767 {
3768         int i;
3769         enum r600_td td = R600_TD_DFLT;
3770
3771         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3772                 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3773
3774         if (td == R600_TD_AUTO)
3775                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3776         else
3777                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3778
3779         if (td == R600_TD_UP)
3780                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3781
3782         if (td == R600_TD_DOWN)
3783                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3784 }
3785
3786 static void si_program_tpp(struct radeon_device *rdev)
3787 {
3788         WREG32(CG_TPC, R600_TPC_DFLT);
3789 }
3790
3791 static void si_program_sstp(struct radeon_device *rdev)
3792 {
3793         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3794 }
3795
3796 static void si_enable_display_gap(struct radeon_device *rdev)
3797 {
3798         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3799
3800         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3801         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3802                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3803
3804         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3805         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3806                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3807         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3808 }
3809
3810 static void si_program_vc(struct radeon_device *rdev)
3811 {
3812         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3813
3814         WREG32(CG_FTV, pi->vrc);
3815 }
3816
3817 static void si_clear_vc(struct radeon_device *rdev)
3818 {
3819         WREG32(CG_FTV, 0);
3820 }
3821
3822 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3823 {
3824         u8 mc_para_index;
3825
3826         if (memory_clock < 10000)
3827                 mc_para_index = 0;
3828         else if (memory_clock >= 80000)
3829                 mc_para_index = 0x0f;
3830         else
3831                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3832         return mc_para_index;
3833 }
3834
3835 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3836 {
3837         u8 mc_para_index;
3838
3839         if (strobe_mode) {
3840                 if (memory_clock < 12500)
3841                         mc_para_index = 0x00;
3842                 else if (memory_clock > 47500)
3843                         mc_para_index = 0x0f;
3844                 else
3845                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
3846         } else {
3847                 if (memory_clock < 65000)
3848                         mc_para_index = 0x00;
3849                 else if (memory_clock > 135000)
3850                         mc_para_index = 0x0f;
3851                 else
3852                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
3853         }
3854         return mc_para_index;
3855 }
3856
3857 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3858 {
3859         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3860         bool strobe_mode = false;
3861         u8 result = 0;
3862
3863         if (mclk <= pi->mclk_strobe_mode_threshold)
3864                 strobe_mode = true;
3865
3866         if (pi->mem_gddr5)
3867                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3868         else
3869                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3870
3871         if (strobe_mode)
3872                 result |= SISLANDS_SMC_STROBE_ENABLE;
3873
3874         return result;
3875 }
3876
3877 static int si_upload_firmware(struct radeon_device *rdev)
3878 {
3879         struct si_power_info *si_pi = si_get_pi(rdev);
3880         int ret;
3881
3882         si_reset_smc(rdev);
3883         si_stop_smc_clock(rdev);
3884
3885         ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3886
3887         return ret;
3888 }
3889
3890 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3891                                               const struct atom_voltage_table *table,
3892                                               const struct radeon_phase_shedding_limits_table *limits)
3893 {
3894         u32 data, num_bits, num_levels;
3895
3896         if ((table == NULL) || (limits == NULL))
3897                 return false;
3898
3899         data = table->mask_low;
3900
3901         num_bits = hweight32(data);
3902
3903         if (num_bits == 0)
3904                 return false;
3905
3906         num_levels = (1 << num_bits);
3907
3908         if (table->count != num_levels)
3909                 return false;
3910
3911         if (limits->count != (num_levels - 1))
3912                 return false;
3913
3914         return true;
3915 }
3916
3917 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3918                                               u32 max_voltage_steps,
3919                                               struct atom_voltage_table *voltage_table)
3920 {
3921         unsigned int i, diff;
3922
3923         if (voltage_table->count <= max_voltage_steps)
3924                 return;
3925
3926         diff = voltage_table->count - max_voltage_steps;
3927
3928         for (i= 0; i < max_voltage_steps; i++)
3929                 voltage_table->entries[i] = voltage_table->entries[i + diff];
3930
3931         voltage_table->count = max_voltage_steps;
3932 }
3933
3934 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3935                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3936                                      struct atom_voltage_table *voltage_table)
3937 {
3938         u32 i;
3939
3940         if (voltage_dependency_table == NULL)
3941                 return -EINVAL;
3942
3943         voltage_table->mask_low = 0;
3944         voltage_table->phase_delay = 0;
3945
3946         voltage_table->count = voltage_dependency_table->count;
3947         for (i = 0; i < voltage_table->count; i++) {
3948                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3949                 voltage_table->entries[i].smio_low = 0;
3950         }
3951
3952         return 0;
3953 }
3954
3955 static int si_construct_voltage_tables(struct radeon_device *rdev)
3956 {
3957         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3958         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3959         struct si_power_info *si_pi = si_get_pi(rdev);
3960         int ret;
3961
3962         if (pi->voltage_control) {
3963                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3964                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3965                 if (ret)
3966                         return ret;
3967
3968                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3969                         si_trim_voltage_table_to_fit_state_table(rdev,
3970                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3971                                                                  &eg_pi->vddc_voltage_table);
3972         } else if (si_pi->voltage_control_svi2) {
3973                 ret = si_get_svi2_voltage_table(rdev,
3974                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3975                                                 &eg_pi->vddc_voltage_table);
3976                 if (ret)
3977                         return ret;
3978         } else {
3979                 return -EINVAL;
3980         }
3981
3982         if (eg_pi->vddci_control) {
3983                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3984                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3985                 if (ret)
3986                         return ret;
3987
3988                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3989                         si_trim_voltage_table_to_fit_state_table(rdev,
3990                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3991                                                                  &eg_pi->vddci_voltage_table);
3992         }
3993         if (si_pi->vddci_control_svi2) {
3994                 ret = si_get_svi2_voltage_table(rdev,
3995                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3996                                                 &eg_pi->vddci_voltage_table);
3997                 if (ret)
3998                         return ret;
3999         }
4000
4001         if (pi->mvdd_control) {
4002                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
4003                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4004
4005                 if (ret) {
4006                         pi->mvdd_control = false;
4007                         return ret;
4008                 }
4009
4010                 if (si_pi->mvdd_voltage_table.count == 0) {
4011                         pi->mvdd_control = false;
4012                         return -EINVAL;
4013                 }
4014
4015                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4016                         si_trim_voltage_table_to_fit_state_table(rdev,
4017                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4018                                                                  &si_pi->mvdd_voltage_table);
4019         }
4020
4021         if (si_pi->vddc_phase_shed_control) {
4022                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4023                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4024                 if (ret)
4025                         si_pi->vddc_phase_shed_control = false;
4026
4027                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4028                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4029                         si_pi->vddc_phase_shed_control = false;
4030         }
4031
4032         return 0;
4033 }
4034
4035 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4036                                           const struct atom_voltage_table *voltage_table,
4037                                           SISLANDS_SMC_STATETABLE *table)
4038 {
4039         unsigned int i;
4040
4041         for (i = 0; i < voltage_table->count; i++)
4042                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4043 }
4044
4045 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4046                                           SISLANDS_SMC_STATETABLE *table)
4047 {
4048         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4049         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4050         struct si_power_info *si_pi = si_get_pi(rdev);
4051         u8 i;
4052
4053         if (si_pi->voltage_control_svi2) {
4054                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4055                         si_pi->svc_gpio_id);
4056                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4057                         si_pi->svd_gpio_id);
4058                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4059                                            2);
4060         } else {
4061                 if (eg_pi->vddc_voltage_table.count) {
4062                         si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4063                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4064                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4065
4066                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4067                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4068                                         table->maxVDDCIndexInPPTable = i;
4069                                         break;
4070                                 }
4071                         }
4072                 }
4073
4074                 if (eg_pi->vddci_voltage_table.count) {
4075                         si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4076
4077                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4078                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4079                 }
4080
4081
4082                 if (si_pi->mvdd_voltage_table.count) {
4083                         si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4084
4085                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4086                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4087                 }
4088
4089                 if (si_pi->vddc_phase_shed_control) {
4090                         if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4091                                                               &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4092                                 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4093
4094                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4095                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4096
4097                                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4098                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4099                         } else {
4100                                 si_pi->vddc_phase_shed_control = false;
4101                         }
4102                 }
4103         }
4104
4105         return 0;
4106 }
4107
4108 static int si_populate_voltage_value(struct radeon_device *rdev,
4109                                      const struct atom_voltage_table *table,
4110                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4111 {
4112         unsigned int i;
4113
4114         for (i = 0; i < table->count; i++) {
4115                 if (value <= table->entries[i].value) {
4116                         voltage->index = (u8)i;
4117                         voltage->value = cpu_to_be16(table->entries[i].value);
4118                         break;
4119                 }
4120         }
4121
4122         if (i >= table->count)
4123                 return -EINVAL;
4124
4125         return 0;
4126 }
4127
4128 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4129                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4130 {
4131         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4132         struct si_power_info *si_pi = si_get_pi(rdev);
4133
4134         if (pi->mvdd_control) {
4135                 if (mclk <= pi->mvdd_split_frequency)
4136                         voltage->index = 0;
4137                 else
4138                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4139
4140                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4141         }
4142         return 0;
4143 }
4144
4145 static int si_get_std_voltage_value(struct radeon_device *rdev,
4146                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4147                                     u16 *std_voltage)
4148 {
4149         u16 v_index;
4150         bool voltage_found = false;
4151         *std_voltage = be16_to_cpu(voltage->value);
4152
4153         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4154                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4155                         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4156                                 return -EINVAL;
4157
4158                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4159                                 if (be16_to_cpu(voltage->value) ==
4160                                     (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4161                                         voltage_found = true;
4162                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4163                                                 *std_voltage =
4164                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4165                                         else
4166                                                 *std_voltage =
4167                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4168                                         break;
4169                                 }
4170                         }
4171
4172                         if (!voltage_found) {
4173                                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4174                                         if (be16_to_cpu(voltage->value) <=
4175                                             (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4176                                                 voltage_found = true;
4177                                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4178                                                         *std_voltage =
4179                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4180                                                 else
4181                                                         *std_voltage =
4182                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4183                                                 break;
4184                                         }
4185                                 }
4186                         }
4187                 } else {
4188                         if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4189                                 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4190                 }
4191         }
4192
4193         return 0;
4194 }
4195
4196 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4197                                          u16 value, u8 index,
4198                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4199 {
4200         voltage->index = index;
4201         voltage->value = cpu_to_be16(value);
4202
4203         return 0;
4204 }
4205
4206 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4207                                             const struct radeon_phase_shedding_limits_table *limits,
4208                                             u16 voltage, u32 sclk, u32 mclk,
4209                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4210 {
4211         unsigned int i;
4212
4213         for (i = 0; i < limits->count; i++) {
4214                 if ((voltage <= limits->entries[i].voltage) &&
4215                     (sclk <= limits->entries[i].sclk) &&
4216                     (mclk <= limits->entries[i].mclk))
4217                         break;
4218         }
4219
4220         smc_voltage->phase_settings = (u8)i;
4221
4222         return 0;
4223 }
4224
4225 static int si_init_arb_table_index(struct radeon_device *rdev)
4226 {
4227         struct si_power_info *si_pi = si_get_pi(rdev);
4228         u32 tmp;
4229         int ret;
4230
4231         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4232         if (ret)
4233                 return ret;
4234
4235         tmp &= 0x00FFFFFF;
4236         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4237
4238         return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4239 }
4240
4241 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4242 {
4243         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4244 }
4245
4246 static int si_reset_to_default(struct radeon_device *rdev)
4247 {
4248         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4249                 0 : -EINVAL;
4250 }
4251
4252 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4253 {
4254         struct si_power_info *si_pi = si_get_pi(rdev);
4255         u32 tmp;
4256         int ret;
4257
4258         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4259                                      &tmp, si_pi->sram_end);
4260         if (ret)
4261                 return ret;
4262
4263         tmp = (tmp >> 24) & 0xff;
4264
4265         if (tmp == MC_CG_ARB_FREQ_F0)
4266                 return 0;
4267
4268         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4269 }
4270
4271 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4272                                             u32 engine_clock)
4273 {
4274         u32 dram_rows;
4275         u32 dram_refresh_rate;
4276         u32 mc_arb_rfsh_rate;
4277         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4278
4279         if (tmp >= 4)
4280                 dram_rows = 16384;
4281         else
4282                 dram_rows = 1 << (tmp + 10);
4283
4284         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4285         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4286
4287         return mc_arb_rfsh_rate;
4288 }
4289
4290 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4291                                                 struct rv7xx_pl *pl,
4292                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4293 {
4294         u32 dram_timing;
4295         u32 dram_timing2;
4296         u32 burst_time;
4297
4298         arb_regs->mc_arb_rfsh_rate =
4299                 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4300
4301         radeon_atom_set_engine_dram_timings(rdev,
4302                                             pl->sclk,
4303                                             pl->mclk);
4304
4305         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4306         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4307         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4308
4309         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4310         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4311         arb_regs->mc_arb_burst_time = (u8)burst_time;
4312
4313         return 0;
4314 }
4315
4316 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4317                                                   struct radeon_ps *radeon_state,
4318                                                   unsigned int first_arb_set)
4319 {
4320         struct si_power_info *si_pi = si_get_pi(rdev);
4321         struct ni_ps *state = ni_get_ps(radeon_state);
4322         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4323         int i, ret = 0;
4324
4325         for (i = 0; i < state->performance_level_count; i++) {
4326                 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4327                 if (ret)
4328                         break;
4329                 ret = si_copy_bytes_to_smc(rdev,
4330                                            si_pi->arb_table_start +
4331                                            offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4332                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4333                                            (u8 *)&arb_regs,
4334                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4335                                            si_pi->sram_end);
4336                 if (ret)
4337                         break;
4338         }
4339
4340         return ret;
4341 }
4342
4343 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4344                                                struct radeon_ps *radeon_new_state)
4345 {
4346         return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4347                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4348 }
4349
4350 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4351                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4352 {
4353         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4354         struct si_power_info *si_pi = si_get_pi(rdev);
4355
4356         if (pi->mvdd_control)
4357                 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4358                                                  si_pi->mvdd_bootup_value, voltage);
4359
4360         return 0;
4361 }
4362
4363 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4364                                          struct radeon_ps *radeon_initial_state,
4365                                          SISLANDS_SMC_STATETABLE *table)
4366 {
4367         struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4368         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4369         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4370         struct si_power_info *si_pi = si_get_pi(rdev);
4371         u32 reg;
4372         int ret;
4373
4374         table->initialState.levels[0].mclk.vDLL_CNTL =
4375                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4376         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4377                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4378         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4379                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4380         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4381                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4382         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4383                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4384         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4385                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4386         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4387                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4388         table->initialState.levels[0].mclk.vMPLL_SS =
4389                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4390         table->initialState.levels[0].mclk.vMPLL_SS2 =
4391                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4392
4393         table->initialState.levels[0].mclk.mclk_value =
4394                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4395
4396         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4397                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4398         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4399                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4400         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4401                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4402         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4403                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4404         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4405                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4406         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4407                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4408
4409         table->initialState.levels[0].sclk.sclk_value =
4410                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4411
4412         table->initialState.levels[0].arbRefreshState =
4413                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4414
4415         table->initialState.levels[0].ACIndex = 0;
4416
4417         ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4418                                         initial_state->performance_levels[0].vddc,
4419                                         &table->initialState.levels[0].vddc);
4420
4421         if (!ret) {
4422                 u16 std_vddc;
4423
4424                 ret = si_get_std_voltage_value(rdev,
4425                                                &table->initialState.levels[0].vddc,
4426                                                &std_vddc);
4427                 if (!ret)
4428                         si_populate_std_voltage_value(rdev, std_vddc,
4429                                                       table->initialState.levels[0].vddc.index,
4430                                                       &table->initialState.levels[0].std_vddc);
4431         }
4432
4433         if (eg_pi->vddci_control)
4434                 si_populate_voltage_value(rdev,
4435                                           &eg_pi->vddci_voltage_table,
4436                                           initial_state->performance_levels[0].vddci,
4437                                           &table->initialState.levels[0].vddci);
4438
4439         if (si_pi->vddc_phase_shed_control)
4440                 si_populate_phase_shedding_value(rdev,
4441                                                  &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4442                                                  initial_state->performance_levels[0].vddc,
4443                                                  initial_state->performance_levels[0].sclk,
4444                                                  initial_state->performance_levels[0].mclk,
4445                                                  &table->initialState.levels[0].vddc);
4446
4447         si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4448
4449         reg = CG_R(0xffff) | CG_L(0);
4450         table->initialState.levels[0].aT = cpu_to_be32(reg);
4451
4452         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4453
4454         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4455
4456         if (pi->mem_gddr5) {
4457                 table->initialState.levels[0].strobeMode =
4458                         si_get_strobe_mode_settings(rdev,
4459                                                     initial_state->performance_levels[0].mclk);
4460
4461                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4462                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4463                 else
4464                         table->initialState.levels[0].mcFlags =  0;
4465         }
4466
4467         table->initialState.levelCount = 1;
4468
4469         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4470
4471         table->initialState.levels[0].dpm2.MaxPS = 0;
4472         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4473         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4474         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4475         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4476
4477         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4478         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4479
4480         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4481         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4482
4483         return 0;
4484 }
4485
4486 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4487                                       SISLANDS_SMC_STATETABLE *table)
4488 {
4489         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4490         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4491         struct si_power_info *si_pi = si_get_pi(rdev);
4492         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4493         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4494         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4495         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4496         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4497         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4498         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4499         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4500         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4501         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4502         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4503         u32 reg;
4504         int ret;
4505
4506         table->ACPIState = table->initialState;
4507
4508         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4509
4510         if (pi->acpi_vddc) {
4511                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4512                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4513                 if (!ret) {
4514                         u16 std_vddc;
4515
4516                         ret = si_get_std_voltage_value(rdev,
4517                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4518                         if (!ret)
4519                                 si_populate_std_voltage_value(rdev, std_vddc,
4520                                                               table->ACPIState.levels[0].vddc.index,
4521                                                               &table->ACPIState.levels[0].std_vddc);
4522                 }
4523                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4524
4525                 if (si_pi->vddc_phase_shed_control) {
4526                         si_populate_phase_shedding_value(rdev,
4527                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4528                                                          pi->acpi_vddc,
4529                                                          0,
4530                                                          0,
4531                                                          &table->ACPIState.levels[0].vddc);
4532                 }
4533         } else {
4534                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4535                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4536                 if (!ret) {
4537                         u16 std_vddc;
4538
4539                         ret = si_get_std_voltage_value(rdev,
4540                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4541
4542                         if (!ret)
4543                                 si_populate_std_voltage_value(rdev, std_vddc,
4544                                                               table->ACPIState.levels[0].vddc.index,
4545                                                               &table->ACPIState.levels[0].std_vddc);
4546                 }
4547                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4548                                                                                     si_pi->sys_pcie_mask,
4549                                                                                     si_pi->boot_pcie_gen,
4550                                                                                     RADEON_PCIE_GEN1);
4551
4552                 if (si_pi->vddc_phase_shed_control)
4553                         si_populate_phase_shedding_value(rdev,
4554                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4555                                                          pi->min_vddc_in_table,
4556                                                          0,
4557                                                          0,
4558                                                          &table->ACPIState.levels[0].vddc);
4559         }
4560
4561         if (pi->acpi_vddc) {
4562                 if (eg_pi->acpi_vddci)
4563                         si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4564                                                   eg_pi->acpi_vddci,
4565                                                   &table->ACPIState.levels[0].vddci);
4566         }
4567
4568         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4569         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4570
4571         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4572
4573         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4574         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4575
4576         table->ACPIState.levels[0].mclk.vDLL_CNTL =
4577                 cpu_to_be32(dll_cntl);
4578         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4579                 cpu_to_be32(mclk_pwrmgt_cntl);
4580         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4581                 cpu_to_be32(mpll_ad_func_cntl);
4582         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4583                 cpu_to_be32(mpll_dq_func_cntl);
4584         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4585                 cpu_to_be32(mpll_func_cntl);
4586         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4587                 cpu_to_be32(mpll_func_cntl_1);
4588         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4589                 cpu_to_be32(mpll_func_cntl_2);
4590         table->ACPIState.levels[0].mclk.vMPLL_SS =
4591                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4592         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4593                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4594
4595         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4596                 cpu_to_be32(spll_func_cntl);
4597         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4598                 cpu_to_be32(spll_func_cntl_2);
4599         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4600                 cpu_to_be32(spll_func_cntl_3);
4601         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4602                 cpu_to_be32(spll_func_cntl_4);
4603
4604         table->ACPIState.levels[0].mclk.mclk_value = 0;
4605         table->ACPIState.levels[0].sclk.sclk_value = 0;
4606
4607         si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4608
4609         if (eg_pi->dynamic_ac_timing)
4610                 table->ACPIState.levels[0].ACIndex = 0;
4611
4612         table->ACPIState.levels[0].dpm2.MaxPS = 0;
4613         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4614         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4615         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4616         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4617
4618         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4619         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4620
4621         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4622         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4623
4624         return 0;
4625 }
4626
4627 static int si_populate_ulv_state(struct radeon_device *rdev,
4628                                  SISLANDS_SMC_SWSTATE *state)
4629 {
4630         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4631         struct si_power_info *si_pi = si_get_pi(rdev);
4632         struct si_ulv_param *ulv = &si_pi->ulv;
4633         u32 sclk_in_sr = 1350; /* ??? */
4634         int ret;
4635
4636         ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4637                                             &state->levels[0]);
4638         if (!ret) {
4639                 if (eg_pi->sclk_deep_sleep) {
4640                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4641                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4642                         else
4643                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4644                 }
4645                 if (ulv->one_pcie_lane_in_ulv)
4646                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4647                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4648                 state->levels[0].ACIndex = 1;
4649                 state->levels[0].std_vddc = state->levels[0].vddc;
4650                 state->levelCount = 1;
4651
4652                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4653         }
4654
4655         return ret;
4656 }
4657
4658 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4659 {
4660         struct si_power_info *si_pi = si_get_pi(rdev);
4661         struct si_ulv_param *ulv = &si_pi->ulv;
4662         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4663         int ret;
4664
4665         ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4666                                                    &arb_regs);
4667         if (ret)
4668                 return ret;
4669
4670         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4671                                    ulv->volt_change_delay);
4672
4673         ret = si_copy_bytes_to_smc(rdev,
4674                                    si_pi->arb_table_start +
4675                                    offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4676                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4677                                    (u8 *)&arb_regs,
4678                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4679                                    si_pi->sram_end);
4680
4681         return ret;
4682 }
4683
4684 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4685 {
4686         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4687
4688         pi->mvdd_split_frequency = 30000;
4689 }
4690
4691 static int si_init_smc_table(struct radeon_device *rdev)
4692 {
4693         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4694         struct si_power_info *si_pi = si_get_pi(rdev);
4695         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4696         const struct si_ulv_param *ulv = &si_pi->ulv;
4697         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4698         int ret;
4699         u32 lane_width;
4700         u32 vr_hot_gpio;
4701
4702         si_populate_smc_voltage_tables(rdev, table);
4703
4704         switch (rdev->pm.int_thermal_type) {
4705         case THERMAL_TYPE_SI:
4706         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4707                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4708                 break;
4709         case THERMAL_TYPE_NONE:
4710                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4711                 break;
4712         default:
4713                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4714                 break;
4715         }
4716
4717         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4718                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4719
4720         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4721                 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4722                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4723         }
4724
4725         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4726                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4727
4728         if (pi->mem_gddr5)
4729                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4730
4731         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4732                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4733
4734         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4735                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4736                 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4737                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4738                                            vr_hot_gpio);
4739         }
4740
4741         ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4742         if (ret)
4743                 return ret;
4744
4745         ret = si_populate_smc_acpi_state(rdev, table);
4746         if (ret)
4747                 return ret;
4748
4749         table->driverState = table->initialState;
4750
4751         ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4752                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
4753         if (ret)
4754                 return ret;
4755
4756         if (ulv->supported && ulv->pl.vddc) {
4757                 ret = si_populate_ulv_state(rdev, &table->ULVState);
4758                 if (ret)
4759                         return ret;
4760
4761                 ret = si_program_ulv_memory_timing_parameters(rdev);
4762                 if (ret)
4763                         return ret;
4764
4765                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4766                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4767
4768                 lane_width = radeon_get_pcie_lanes(rdev);
4769                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4770         } else {
4771                 table->ULVState = table->initialState;
4772         }
4773
4774         return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4775                                     (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4776                                     si_pi->sram_end);
4777 }
4778
4779 static int si_calculate_sclk_params(struct radeon_device *rdev,
4780                                     u32 engine_clock,
4781                                     SISLANDS_SMC_SCLK_VALUE *sclk)
4782 {
4783         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4784         struct si_power_info *si_pi = si_get_pi(rdev);
4785         struct atom_clock_dividers dividers;
4786         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4787         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4788         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4789         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4790         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4791         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4792         u64 tmp;
4793         u32 reference_clock = rdev->clock.spll.reference_freq;
4794         u32 reference_divider;
4795         u32 fbdiv;
4796         int ret;
4797
4798         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4799                                              engine_clock, false, &dividers);
4800         if (ret)
4801                 return ret;
4802
4803         reference_divider = 1 + dividers.ref_div;
4804
4805         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4806         do_div(tmp, reference_clock);
4807         fbdiv = (u32) tmp;
4808
4809         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4810         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4811         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4812
4813         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4814         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4815
4816         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4817         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4818         spll_func_cntl_3 |= SPLL_DITHEN;
4819
4820         if (pi->sclk_ss) {
4821                 struct radeon_atom_ss ss;
4822                 u32 vco_freq = engine_clock * dividers.post_div;
4823
4824                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4825                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4826                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4827                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4828
4829                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
4830                         cg_spll_spread_spectrum |= CLK_S(clk_s);
4831                         cg_spll_spread_spectrum |= SSEN;
4832
4833                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4834                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4835                 }
4836         }
4837
4838         sclk->sclk_value = engine_clock;
4839         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4840         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4841         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4842         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4843         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4844         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4845
4846         return 0;
4847 }
4848
4849 static int si_populate_sclk_value(struct radeon_device *rdev,
4850                                   u32 engine_clock,
4851                                   SISLANDS_SMC_SCLK_VALUE *sclk)
4852 {
4853         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4854         int ret;
4855
4856         ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4857         if (!ret) {
4858                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4859                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4860                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4861                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4862                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4863                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4864                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4865         }
4866
4867         return ret;
4868 }
4869
4870 static int si_populate_mclk_value(struct radeon_device *rdev,
4871                                   u32 engine_clock,
4872                                   u32 memory_clock,
4873                                   SISLANDS_SMC_MCLK_VALUE *mclk,
4874                                   bool strobe_mode,
4875                                   bool dll_state_on)
4876 {
4877         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4878         struct si_power_info *si_pi = si_get_pi(rdev);
4879         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4880         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4881         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4882         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4883         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4884         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4885         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4886         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4887         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4888         struct atom_mpll_param mpll_param;
4889         int ret;
4890
4891         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4892         if (ret)
4893                 return ret;
4894
4895         mpll_func_cntl &= ~BWCTRL_MASK;
4896         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4897
4898         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4899         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4900                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4901
4902         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4903         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4904
4905         if (pi->mem_gddr5) {
4906                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4907                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4908                         YCLK_POST_DIV(mpll_param.post_div);
4909         }
4910
4911         if (pi->mclk_ss) {
4912                 struct radeon_atom_ss ss;
4913                 u32 freq_nom;
4914                 u32 tmp;
4915                 u32 reference_clock = rdev->clock.mpll.reference_freq;
4916
4917                 if (pi->mem_gddr5)
4918                         freq_nom = memory_clock * 4;
4919                 else
4920                         freq_nom = memory_clock * 2;
4921
4922                 tmp = freq_nom / reference_clock;
4923                 tmp = tmp * tmp;
4924                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4925                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4926                         u32 clks = reference_clock * 5 / ss.rate;
4927                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4928
4929                         mpll_ss1 &= ~CLKV_MASK;
4930                         mpll_ss1 |= CLKV(clkv);
4931
4932                         mpll_ss2 &= ~CLKS_MASK;
4933                         mpll_ss2 |= CLKS(clks);
4934                 }
4935         }
4936
4937         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4938         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4939
4940         if (dll_state_on)
4941                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4942         else
4943                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4944
4945         mclk->mclk_value = cpu_to_be32(memory_clock);
4946         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4947         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4948         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4949         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4950         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4951         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4952         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4953         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4954         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4955
4956         return 0;
4957 }
4958
4959 static void si_populate_smc_sp(struct radeon_device *rdev,
4960                                struct radeon_ps *radeon_state,
4961                                SISLANDS_SMC_SWSTATE *smc_state)
4962 {
4963         struct ni_ps *ps = ni_get_ps(radeon_state);
4964         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4965         int i;
4966
4967         for (i = 0; i < ps->performance_level_count - 1; i++)
4968                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4969
4970         smc_state->levels[ps->performance_level_count - 1].bSP =
4971                 cpu_to_be32(pi->psp);
4972 }
4973
4974 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4975                                          struct rv7xx_pl *pl,
4976                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4977 {
4978         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4979         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4980         struct si_power_info *si_pi = si_get_pi(rdev);
4981         int ret;
4982         bool dll_state_on;
4983         u16 std_vddc;
4984         bool gmc_pg = false;
4985
4986         if (eg_pi->pcie_performance_request &&
4987             (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4988                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4989         else
4990                 level->gen2PCIE = (u8)pl->pcie_gen;
4991
4992         ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4993         if (ret)
4994                 return ret;
4995
4996         level->mcFlags =  0;
4997
4998         if (pi->mclk_stutter_mode_threshold &&
4999             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5000             !eg_pi->uvd_enabled &&
5001             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5002             (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5003                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5004
5005                 if (gmc_pg)
5006                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5007         }
5008
5009         if (pi->mem_gddr5) {
5010                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5011                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5012
5013                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5014                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5015
5016                 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5017
5018                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5019                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5020                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5021                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5022                         else
5023                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5024                 } else {
5025                         dll_state_on = false;
5026                 }
5027         } else {
5028                 level->strobeMode = si_get_strobe_mode_settings(rdev,
5029                                                                 pl->mclk);
5030
5031                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5032         }
5033
5034         ret = si_populate_mclk_value(rdev,
5035                                      pl->sclk,
5036                                      pl->mclk,
5037                                      &level->mclk,
5038                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5039         if (ret)
5040                 return ret;
5041
5042         ret = si_populate_voltage_value(rdev,
5043                                         &eg_pi->vddc_voltage_table,
5044                                         pl->vddc, &level->vddc);
5045         if (ret)
5046                 return ret;
5047
5048
5049         ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5050         if (ret)
5051                 return ret;
5052
5053         ret = si_populate_std_voltage_value(rdev, std_vddc,
5054                                             level->vddc.index, &level->std_vddc);
5055         if (ret)
5056                 return ret;
5057
5058         if (eg_pi->vddci_control) {
5059                 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5060                                                 pl->vddci, &level->vddci);
5061                 if (ret)
5062                         return ret;
5063         }
5064
5065         if (si_pi->vddc_phase_shed_control) {
5066                 ret = si_populate_phase_shedding_value(rdev,
5067                                                        &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5068                                                        pl->vddc,
5069                                                        pl->sclk,
5070                                                        pl->mclk,
5071                                                        &level->vddc);
5072                 if (ret)
5073                         return ret;
5074         }
5075
5076         level->MaxPoweredUpCU = si_pi->max_cu;
5077
5078         ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5079
5080         return ret;
5081 }
5082
5083 static int si_populate_smc_t(struct radeon_device *rdev,
5084                              struct radeon_ps *radeon_state,
5085                              SISLANDS_SMC_SWSTATE *smc_state)
5086 {
5087         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5088         struct ni_ps *state = ni_get_ps(radeon_state);
5089         u32 a_t;
5090         u32 t_l, t_h;
5091         u32 high_bsp;
5092         int i, ret;
5093
5094         if (state->performance_level_count >= 9)
5095                 return -EINVAL;
5096
5097         if (state->performance_level_count < 2) {
5098                 a_t = CG_R(0xffff) | CG_L(0);
5099                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5100                 return 0;
5101         }
5102
5103         smc_state->levels[0].aT = cpu_to_be32(0);
5104
5105         for (i = 0; i <= state->performance_level_count - 2; i++) {
5106                 ret = r600_calculate_at(
5107                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5108                         100 * R600_AH_DFLT,
5109                         state->performance_levels[i + 1].sclk,
5110                         state->performance_levels[i].sclk,
5111                         &t_l,
5112                         &t_h);
5113
5114                 if (ret) {
5115                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5116                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5117                 }
5118
5119                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5120                 a_t |= CG_R(t_l * pi->bsp / 20000);
5121                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5122
5123                 high_bsp = (i == state->performance_level_count - 2) ?
5124                         pi->pbsp : pi->bsp;
5125                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5126                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5127         }
5128
5129         return 0;
5130 }
5131
5132 static int si_disable_ulv(struct radeon_device *rdev)
5133 {
5134         struct si_power_info *si_pi = si_get_pi(rdev);
5135         struct si_ulv_param *ulv = &si_pi->ulv;
5136
5137         if (ulv->supported)
5138                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5139                         0 : -EINVAL;
5140
5141         return 0;
5142 }
5143
5144 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5145                                        struct radeon_ps *radeon_state)
5146 {
5147         const struct si_power_info *si_pi = si_get_pi(rdev);
5148         const struct si_ulv_param *ulv = &si_pi->ulv;
5149         const struct ni_ps *state = ni_get_ps(radeon_state);
5150         int i;
5151
5152         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5153                 return false;
5154
5155         /* XXX validate against display requirements! */
5156
5157         for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5158                 if (rdev->clock.current_dispclk <=
5159                     rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5160                         if (ulv->pl.vddc <
5161                             rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5162                                 return false;
5163                 }
5164         }
5165
5166         if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5167                 return false;
5168
5169         return true;
5170 }
5171
5172 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5173                                                        struct radeon_ps *radeon_new_state)
5174 {
5175         const struct si_power_info *si_pi = si_get_pi(rdev);
5176         const struct si_ulv_param *ulv = &si_pi->ulv;
5177
5178         if (ulv->supported) {
5179                 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5180                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5181                                 0 : -EINVAL;
5182         }
5183         return 0;
5184 }
5185
5186 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5187                                          struct radeon_ps *radeon_state,
5188                                          SISLANDS_SMC_SWSTATE *smc_state)
5189 {
5190         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5191         struct ni_power_info *ni_pi = ni_get_pi(rdev);
5192         struct si_power_info *si_pi = si_get_pi(rdev);
5193         struct ni_ps *state = ni_get_ps(radeon_state);
5194         int i, ret;
5195         u32 threshold;
5196         u32 sclk_in_sr = 1350; /* ??? */
5197
5198         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5199                 return -EINVAL;
5200
5201         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5202
5203         if (radeon_state->vclk && radeon_state->dclk) {
5204                 eg_pi->uvd_enabled = true;
5205                 if (eg_pi->smu_uvd_hs)
5206                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5207         } else {
5208                 eg_pi->uvd_enabled = false;
5209         }
5210
5211         if (state->dc_compatible)
5212                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5213
5214         smc_state->levelCount = 0;
5215         for (i = 0; i < state->performance_level_count; i++) {
5216                 if (eg_pi->sclk_deep_sleep) {
5217                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5218                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5219                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5220                                 else
5221                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5222                         }
5223                 }
5224
5225                 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5226                                                     &smc_state->levels[i]);
5227                 smc_state->levels[i].arbRefreshState =
5228                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5229
5230                 if (ret)
5231                         return ret;
5232
5233                 if (ni_pi->enable_power_containment)
5234                         smc_state->levels[i].displayWatermark =
5235                                 (state->performance_levels[i].sclk < threshold) ?
5236                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5237                 else
5238                         smc_state->levels[i].displayWatermark = (i < 2) ?
5239                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5240
5241                 if (eg_pi->dynamic_ac_timing)
5242                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5243                 else
5244                         smc_state->levels[i].ACIndex = 0;
5245
5246                 smc_state->levelCount++;
5247         }
5248
5249         si_write_smc_soft_register(rdev,
5250                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5251                                    threshold / 512);
5252
5253         si_populate_smc_sp(rdev, radeon_state, smc_state);
5254
5255         ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5256         if (ret)
5257                 ni_pi->enable_power_containment = false;
5258
5259         ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5260         if (ret)
5261                 ni_pi->enable_sq_ramping = false;
5262
5263         return si_populate_smc_t(rdev, radeon_state, smc_state);
5264 }
5265
5266 static int si_upload_sw_state(struct radeon_device *rdev,
5267                               struct radeon_ps *radeon_new_state)
5268 {
5269         struct si_power_info *si_pi = si_get_pi(rdev);
5270         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5271         int ret;
5272         u32 address = si_pi->state_table_start +
5273                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5274         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5275                 ((new_state->performance_level_count - 1) *
5276                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5277         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5278
5279         memset(smc_state, 0, state_size);
5280
5281         ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5282         if (ret)
5283                 return ret;
5284
5285         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5286                                    state_size, si_pi->sram_end);
5287
5288         return ret;
5289 }
5290
5291 static int si_upload_ulv_state(struct radeon_device *rdev)
5292 {
5293         struct si_power_info *si_pi = si_get_pi(rdev);
5294         struct si_ulv_param *ulv = &si_pi->ulv;
5295         int ret = 0;
5296
5297         if (ulv->supported && ulv->pl.vddc) {
5298                 u32 address = si_pi->state_table_start +
5299                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5300                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5301                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5302
5303                 memset(smc_state, 0, state_size);
5304
5305                 ret = si_populate_ulv_state(rdev, smc_state);
5306                 if (!ret)
5307                         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5308                                                    state_size, si_pi->sram_end);
5309         }
5310
5311         return ret;
5312 }
5313
5314 static int si_upload_smc_data(struct radeon_device *rdev)
5315 {
5316         struct radeon_crtc *radeon_crtc = NULL;
5317         int i;
5318
5319         if (rdev->pm.dpm.new_active_crtc_count == 0)
5320                 return 0;
5321
5322         for (i = 0; i < rdev->num_crtc; i++) {
5323                 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5324                         radeon_crtc = rdev->mode_info.crtcs[i];
5325                         break;
5326                 }
5327         }
5328
5329         if (radeon_crtc == NULL)
5330                 return 0;
5331
5332         if (radeon_crtc->line_time <= 0)
5333                 return 0;
5334
5335         if (si_write_smc_soft_register(rdev,
5336                                        SI_SMC_SOFT_REGISTER_crtc_index,
5337                                        radeon_crtc->crtc_id) != PPSMC_Result_OK)
5338                 return 0;
5339
5340         if (si_write_smc_soft_register(rdev,
5341                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5342                                        radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5343                 return 0;
5344
5345         if (si_write_smc_soft_register(rdev,
5346                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5347                                        radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5348                 return 0;
5349
5350         return 0;
5351 }
5352
5353 static int si_set_mc_special_registers(struct radeon_device *rdev,
5354                                        struct si_mc_reg_table *table)
5355 {
5356         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5357         u8 i, j, k;
5358         u32 temp_reg;
5359
5360         for (i = 0, j = table->last; i < table->last; i++) {
5361                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5362                         return -EINVAL;
5363                 switch (table->mc_reg_address[i].s1 << 2) {
5364                 case MC_SEQ_MISC1:
5365                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5366                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5367                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5368                         for (k = 0; k < table->num_entries; k++)
5369                                 table->mc_reg_table_entry[k].mc_data[j] =
5370                                         ((temp_reg & 0xffff0000)) |
5371                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5372                         j++;
5373                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5374                                 return -EINVAL;
5375
5376                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5377                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5378                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5379                         for (k = 0; k < table->num_entries; k++) {
5380                                 table->mc_reg_table_entry[k].mc_data[j] =
5381                                         (temp_reg & 0xffff0000) |
5382                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5383                                 if (!pi->mem_gddr5)
5384                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5385                         }
5386                         j++;
5387                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5388                                 return -EINVAL;
5389
5390                         if (!pi->mem_gddr5) {
5391                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5392                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5393                                 for (k = 0; k < table->num_entries; k++)
5394                                         table->mc_reg_table_entry[k].mc_data[j] =
5395                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5396                                 j++;
5397                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5398                                         return -EINVAL;
5399                         }
5400                         break;
5401                 case MC_SEQ_RESERVE_M:
5402                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5403                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5404                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5405                         for(k = 0; k < table->num_entries; k++)
5406                                 table->mc_reg_table_entry[k].mc_data[j] =
5407                                         (temp_reg & 0xffff0000) |
5408                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5409                         j++;
5410                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5411                                 return -EINVAL;
5412                         break;
5413                 default:
5414                         break;
5415                 }
5416         }
5417
5418         table->last = j;
5419
5420         return 0;
5421 }
5422
5423 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5424 {
5425         bool result = true;
5426
5427         switch (in_reg) {
5428         case  MC_SEQ_RAS_TIMING >> 2:
5429                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5430                 break;
5431         case MC_SEQ_CAS_TIMING >> 2:
5432                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5433                 break;
5434         case MC_SEQ_MISC_TIMING >> 2:
5435                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5436                 break;
5437         case MC_SEQ_MISC_TIMING2 >> 2:
5438                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5439                 break;
5440         case MC_SEQ_RD_CTL_D0 >> 2:
5441                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5442                 break;
5443         case MC_SEQ_RD_CTL_D1 >> 2:
5444                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5445                 break;
5446         case MC_SEQ_WR_CTL_D0 >> 2:
5447                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5448                 break;
5449         case MC_SEQ_WR_CTL_D1 >> 2:
5450                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5451                 break;
5452         case MC_PMG_CMD_EMRS >> 2:
5453                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5454                 break;
5455         case MC_PMG_CMD_MRS >> 2:
5456                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5457                 break;
5458         case MC_PMG_CMD_MRS1 >> 2:
5459                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5460                 break;
5461         case MC_SEQ_PMG_TIMING >> 2:
5462                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5463                 break;
5464         case MC_PMG_CMD_MRS2 >> 2:
5465                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5466                 break;
5467         case MC_SEQ_WR_CTL_2 >> 2:
5468                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5469                 break;
5470         default:
5471                 result = false;
5472                 break;
5473         }
5474
5475         return result;
5476 }
5477
5478 static void si_set_valid_flag(struct si_mc_reg_table *table)
5479 {
5480         u8 i, j;
5481
5482         for (i = 0; i < table->last; i++) {
5483                 for (j = 1; j < table->num_entries; j++) {
5484                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5485                                 table->valid_flag |= 1 << i;
5486                                 break;
5487                         }
5488                 }
5489         }
5490 }
5491
5492 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5493 {
5494         u32 i;
5495         u16 address;
5496
5497         for (i = 0; i < table->last; i++)
5498                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5499                         address : table->mc_reg_address[i].s1;
5500
5501 }
5502
5503 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5504                                       struct si_mc_reg_table *si_table)
5505 {
5506         u8 i, j;
5507
5508         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5509                 return -EINVAL;
5510         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5511                 return -EINVAL;
5512
5513         for (i = 0; i < table->last; i++)
5514                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5515         si_table->last = table->last;
5516
5517         for (i = 0; i < table->num_entries; i++) {
5518                 si_table->mc_reg_table_entry[i].mclk_max =
5519                         table->mc_reg_table_entry[i].mclk_max;
5520                 for (j = 0; j < table->last; j++) {
5521                         si_table->mc_reg_table_entry[i].mc_data[j] =
5522                                 table->mc_reg_table_entry[i].mc_data[j];
5523                 }
5524         }
5525         si_table->num_entries = table->num_entries;
5526
5527         return 0;
5528 }
5529
5530 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5531 {
5532         struct si_power_info *si_pi = si_get_pi(rdev);
5533         struct atom_mc_reg_table *table;
5534         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5535         u8 module_index = rv770_get_memory_module_index(rdev);
5536         int ret;
5537
5538         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5539         if (!table)
5540                 return -ENOMEM;
5541
5542         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5543         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5544         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5545         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5546         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5547         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5548         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5549         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5550         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5551         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5552         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5553         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5554         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5555         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5556
5557         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5558         if (ret)
5559                 goto init_mc_done;
5560
5561         ret = si_copy_vbios_mc_reg_table(table, si_table);
5562         if (ret)
5563                 goto init_mc_done;
5564
5565         si_set_s0_mc_reg_index(si_table);
5566
5567         ret = si_set_mc_special_registers(rdev, si_table);
5568         if (ret)
5569                 goto init_mc_done;
5570
5571         si_set_valid_flag(si_table);
5572
5573 init_mc_done:
5574         kfree(table);
5575
5576         return ret;
5577
5578 }
5579
5580 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5581                                          SMC_SIslands_MCRegisters *mc_reg_table)
5582 {
5583         struct si_power_info *si_pi = si_get_pi(rdev);
5584         u32 i, j;
5585
5586         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5587                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5588                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5589                                 break;
5590                         mc_reg_table->address[i].s0 =
5591                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5592                         mc_reg_table->address[i].s1 =
5593                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5594                         i++;
5595                 }
5596         }
5597         mc_reg_table->last = (u8)i;
5598 }
5599
5600 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5601                                     SMC_SIslands_MCRegisterSet *data,
5602                                     u32 num_entries, u32 valid_flag)
5603 {
5604         u32 i, j;
5605
5606         for(i = 0, j = 0; j < num_entries; j++) {
5607                 if (valid_flag & (1 << j)) {
5608                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
5609                         i++;
5610                 }
5611         }
5612 }
5613
5614 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5615                                                  struct rv7xx_pl *pl,
5616                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5617 {
5618         struct si_power_info *si_pi = si_get_pi(rdev);
5619         u32 i = 0;
5620
5621         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5622                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5623                         break;
5624         }
5625
5626         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5627                 --i;
5628
5629         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5630                                 mc_reg_table_data, si_pi->mc_reg_table.last,
5631                                 si_pi->mc_reg_table.valid_flag);
5632 }
5633
5634 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5635                                            struct radeon_ps *radeon_state,
5636                                            SMC_SIslands_MCRegisters *mc_reg_table)
5637 {
5638         struct ni_ps *state = ni_get_ps(radeon_state);
5639         int i;
5640
5641         for (i = 0; i < state->performance_level_count; i++) {
5642                 si_convert_mc_reg_table_entry_to_smc(rdev,
5643                                                      &state->performance_levels[i],
5644                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5645         }
5646 }
5647
5648 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5649                                     struct radeon_ps *radeon_boot_state)
5650 {
5651         struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5652         struct si_power_info *si_pi = si_get_pi(rdev);
5653         struct si_ulv_param *ulv = &si_pi->ulv;
5654         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5655
5656         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5657
5658         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5659
5660         si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5661
5662         si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5663                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5664
5665         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5666                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5667                                 si_pi->mc_reg_table.last,
5668                                 si_pi->mc_reg_table.valid_flag);
5669
5670         if (ulv->supported && ulv->pl.vddc != 0)
5671                 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5672                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5673         else
5674                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5675                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5676                                         si_pi->mc_reg_table.last,
5677                                         si_pi->mc_reg_table.valid_flag);
5678
5679         si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5680
5681         return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5682                                     (u8 *)smc_mc_reg_table,
5683                                     sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5684 }
5685
5686 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5687                                   struct radeon_ps *radeon_new_state)
5688 {
5689         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5690         struct si_power_info *si_pi = si_get_pi(rdev);
5691         u32 address = si_pi->mc_reg_table_start +
5692                 offsetof(SMC_SIslands_MCRegisters,
5693                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5694         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5695
5696         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5697
5698         si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5699
5700
5701         return si_copy_bytes_to_smc(rdev, address,
5702                                     (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5703                                     sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5704                                     si_pi->sram_end);
5705
5706 }
5707
5708 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5709 {
5710         if (enable)
5711                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5712         else
5713                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5714 }
5715
5716 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5717                                                       struct radeon_ps *radeon_state)
5718 {
5719         struct ni_ps *state = ni_get_ps(radeon_state);
5720         int i;
5721         u16 pcie_speed, max_speed = 0;
5722
5723         for (i = 0; i < state->performance_level_count; i++) {
5724                 pcie_speed = state->performance_levels[i].pcie_gen;
5725                 if (max_speed < pcie_speed)
5726                         max_speed = pcie_speed;
5727         }
5728         return max_speed;
5729 }
5730
5731 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5732 {
5733         u32 speed_cntl;
5734
5735         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5736         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5737
5738         return (u16)speed_cntl;
5739 }
5740
5741 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5742                                                              struct radeon_ps *radeon_new_state,
5743                                                              struct radeon_ps *radeon_current_state)
5744 {
5745         struct si_power_info *si_pi = si_get_pi(rdev);
5746         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5747         enum radeon_pcie_gen current_link_speed;
5748
5749         if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5750                 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5751         else
5752                 current_link_speed = si_pi->force_pcie_gen;
5753
5754         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5755         si_pi->pspp_notify_required = false;
5756         if (target_link_speed > current_link_speed) {
5757                 switch (target_link_speed) {
5758 #if defined(CONFIG_ACPI)
5759                 case RADEON_PCIE_GEN3:
5760                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5761                                 break;
5762                         si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5763                         if (current_link_speed == RADEON_PCIE_GEN2)
5764                                 break;
5765                 case RADEON_PCIE_GEN2:
5766                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5767                                 break;
5768 #endif
5769                 default:
5770                         si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5771                         break;
5772                 }
5773         } else {
5774                 if (target_link_speed < current_link_speed)
5775                         si_pi->pspp_notify_required = true;
5776         }
5777 }
5778
5779 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5780                                                            struct radeon_ps *radeon_new_state,
5781                                                            struct radeon_ps *radeon_current_state)
5782 {
5783         struct si_power_info *si_pi = si_get_pi(rdev);
5784         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5785         u8 request;
5786
5787         if (si_pi->pspp_notify_required) {
5788                 if (target_link_speed == RADEON_PCIE_GEN3)
5789                         request = PCIE_PERF_REQ_PECI_GEN3;
5790                 else if (target_link_speed == RADEON_PCIE_GEN2)
5791                         request = PCIE_PERF_REQ_PECI_GEN2;
5792                 else
5793                         request = PCIE_PERF_REQ_PECI_GEN1;
5794
5795                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5796                     (si_get_current_pcie_speed(rdev) > 0))
5797                         return;
5798
5799 #if defined(CONFIG_ACPI)
5800                 radeon_acpi_pcie_performance_request(rdev, request, false);
5801 #endif
5802         }
5803 }
5804
5805 #if 0
5806 static int si_ds_request(struct radeon_device *rdev,
5807                          bool ds_status_on, u32 count_write)
5808 {
5809         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5810
5811         if (eg_pi->sclk_deep_sleep) {
5812                 if (ds_status_on)
5813                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5814                                 PPSMC_Result_OK) ?
5815                                 0 : -EINVAL;
5816                 else
5817                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5818                                 PPSMC_Result_OK) ? 0 : -EINVAL;
5819         }
5820         return 0;
5821 }
5822 #endif
5823
5824 static void si_set_max_cu_value(struct radeon_device *rdev)
5825 {
5826         struct si_power_info *si_pi = si_get_pi(rdev);
5827
5828         if (rdev->family == CHIP_VERDE) {
5829                 switch (rdev->pdev->device) {
5830                 case 0x6820:
5831                 case 0x6825:
5832                 case 0x6821:
5833                 case 0x6823:
5834                 case 0x6827:
5835                         si_pi->max_cu = 10;
5836                         break;
5837                 case 0x682D:
5838                 case 0x6824:
5839                 case 0x682F:
5840                 case 0x6826:
5841                         si_pi->max_cu = 8;
5842                         break;
5843                 case 0x6828:
5844                 case 0x6830:
5845                 case 0x6831:
5846                 case 0x6838:
5847                 case 0x6839:
5848                 case 0x683D:
5849                         si_pi->max_cu = 10;
5850                         break;
5851                 case 0x683B:
5852                 case 0x683F:
5853                 case 0x6829:
5854                         si_pi->max_cu = 8;
5855                         break;
5856                 default:
5857                         si_pi->max_cu = 0;
5858                         break;
5859                 }
5860         } else {
5861                 si_pi->max_cu = 0;
5862         }
5863 }
5864
5865 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5866                                                              struct radeon_clock_voltage_dependency_table *table)
5867 {
5868         u32 i;
5869         int j;
5870         u16 leakage_voltage;
5871
5872         if (table) {
5873                 for (i = 0; i < table->count; i++) {
5874                         switch (si_get_leakage_voltage_from_leakage_index(rdev,
5875                                                                           table->entries[i].v,
5876                                                                           &leakage_voltage)) {
5877                         case 0:
5878                                 table->entries[i].v = leakage_voltage;
5879                                 break;
5880                         case -EAGAIN:
5881                                 return -EINVAL;
5882                         case -EINVAL:
5883                         default:
5884                                 break;
5885                         }
5886                 }
5887
5888                 for (j = (table->count - 2); j >= 0; j--) {
5889                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5890                                 table->entries[j].v : table->entries[j + 1].v;
5891                 }
5892         }
5893         return 0;
5894 }
5895
5896 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5897 {
5898         int ret = 0;
5899
5900         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5901                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5902         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5903                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5904         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5905                                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5906         return ret;
5907 }
5908
5909 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5910                                           struct radeon_ps *radeon_new_state,
5911                                           struct radeon_ps *radeon_current_state)
5912 {
5913         u32 lane_width;
5914         u32 new_lane_width =
5915                 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
5916         u32 current_lane_width =
5917                 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
5918
5919         if (new_lane_width != current_lane_width) {
5920                 radeon_set_pcie_lanes(rdev, new_lane_width);
5921                 lane_width = radeon_get_pcie_lanes(rdev);
5922                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5923         }
5924 }
5925
5926 static void si_set_vce_clock(struct radeon_device *rdev,
5927                              struct radeon_ps *new_rps,
5928                              struct radeon_ps *old_rps)
5929 {
5930         if ((old_rps->evclk != new_rps->evclk) ||
5931             (old_rps->ecclk != new_rps->ecclk)) {
5932                 /* turn the clocks on when encoding, off otherwise */
5933                 if (new_rps->evclk || new_rps->ecclk)
5934                         vce_v1_0_enable_mgcg(rdev, false);
5935                 else
5936                         vce_v1_0_enable_mgcg(rdev, true);
5937                 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5938         }
5939 }
5940
5941 void si_dpm_setup_asic(struct radeon_device *rdev)
5942 {
5943         int r;
5944
5945         r = si_mc_load_microcode(rdev);
5946         if (r)
5947                 DRM_ERROR("Failed to load MC firmware!\n");
5948         rv770_get_memory_type(rdev);
5949         si_read_clock_registers(rdev);
5950         si_enable_acpi_power_management(rdev);
5951 }
5952
5953 static int si_thermal_enable_alert(struct radeon_device *rdev,
5954                                    bool enable)
5955 {
5956         u32 thermal_int = RREG32(CG_THERMAL_INT);
5957
5958         if (enable) {
5959                 PPSMC_Result result;
5960
5961                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5962                 WREG32(CG_THERMAL_INT, thermal_int);
5963                 rdev->irq.dpm_thermal = false;
5964                 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5965                 if (result != PPSMC_Result_OK) {
5966                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5967                         return -EINVAL;
5968                 }
5969         } else {
5970                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5971                 WREG32(CG_THERMAL_INT, thermal_int);
5972                 rdev->irq.dpm_thermal = true;
5973         }
5974
5975         return 0;
5976 }
5977
5978 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5979                                             int min_temp, int max_temp)
5980 {
5981         int low_temp = 0 * 1000;
5982         int high_temp = 255 * 1000;
5983
5984         if (low_temp < min_temp)
5985                 low_temp = min_temp;
5986         if (high_temp > max_temp)
5987                 high_temp = max_temp;
5988         if (high_temp < low_temp) {
5989                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5990                 return -EINVAL;
5991         }
5992
5993         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5994         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5995         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5996
5997         rdev->pm.dpm.thermal.min_temp = low_temp;
5998         rdev->pm.dpm.thermal.max_temp = high_temp;
5999
6000         return 0;
6001 }
6002
6003 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
6004 {
6005         struct si_power_info *si_pi = si_get_pi(rdev);
6006         u32 tmp;
6007
6008         if (si_pi->fan_ctrl_is_in_default_mode) {
6009                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6010                 si_pi->fan_ctrl_default_mode = tmp;
6011                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6012                 si_pi->t_min = tmp;
6013                 si_pi->fan_ctrl_is_in_default_mode = false;
6014         }
6015
6016         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6017         tmp |= TMIN(0);
6018         WREG32(CG_FDO_CTRL2, tmp);
6019
6020         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6021         tmp |= FDO_PWM_MODE(mode);
6022         WREG32(CG_FDO_CTRL2, tmp);
6023 }
6024
6025 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6026 {
6027         struct si_power_info *si_pi = si_get_pi(rdev);
6028         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6029         u32 duty100;
6030         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6031         u16 fdo_min, slope1, slope2;
6032         u32 reference_clock, tmp;
6033         int ret;
6034         u64 tmp64;
6035
6036         if (!si_pi->fan_table_start) {
6037                 rdev->pm.dpm.fan.ucode_fan_control = false;
6038                 return 0;
6039         }
6040
6041         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6042
6043         if (duty100 == 0) {
6044                 rdev->pm.dpm.fan.ucode_fan_control = false;
6045                 return 0;
6046         }
6047
6048         tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6049         do_div(tmp64, 10000);
6050         fdo_min = (u16)tmp64;
6051
6052         t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6053         t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6054
6055         pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6056         pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6057
6058         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6059         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6060
6061         fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6062         fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6063         fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6064
6065         fan_table.slope1 = cpu_to_be16(slope1);
6066         fan_table.slope2 = cpu_to_be16(slope2);
6067
6068         fan_table.fdo_min = cpu_to_be16(fdo_min);
6069
6070         fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6071
6072         fan_table.hys_up = cpu_to_be16(1);
6073
6074         fan_table.hys_slope = cpu_to_be16(1);
6075
6076         fan_table.temp_resp_lim = cpu_to_be16(5);
6077
6078         reference_clock = radeon_get_xclk(rdev);
6079
6080         fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6081                                                 reference_clock) / 1600);
6082
6083         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6084
6085         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6086         fan_table.temp_src = (uint8_t)tmp;
6087
6088         ret = si_copy_bytes_to_smc(rdev,
6089                                    si_pi->fan_table_start,
6090                                    (u8 *)(&fan_table),
6091                                    sizeof(fan_table),
6092                                    si_pi->sram_end);
6093
6094         if (ret) {
6095                 DRM_ERROR("Failed to load fan table to the SMC.");
6096                 rdev->pm.dpm.fan.ucode_fan_control = false;
6097         }
6098
6099         return 0;
6100 }
6101
6102 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6103 {
6104         struct si_power_info *si_pi = si_get_pi(rdev);
6105         PPSMC_Result ret;
6106
6107         ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6108         if (ret == PPSMC_Result_OK) {
6109                 si_pi->fan_is_controlled_by_smc = true;
6110                 return 0;
6111         } else {
6112                 return -EINVAL;
6113         }
6114 }
6115
6116 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6117 {
6118         struct si_power_info *si_pi = si_get_pi(rdev);
6119         PPSMC_Result ret;
6120
6121         ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6122
6123         if (ret == PPSMC_Result_OK) {
6124                 si_pi->fan_is_controlled_by_smc = false;
6125                 return 0;
6126         } else {
6127                 return -EINVAL;
6128         }
6129 }
6130
6131 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6132                                       u32 *speed)
6133 {
6134         u32 duty, duty100;
6135         u64 tmp64;
6136
6137         if (rdev->pm.no_fan)
6138                 return -ENOENT;
6139
6140         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6141         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6142
6143         if (duty100 == 0)
6144                 return -EINVAL;
6145
6146         tmp64 = (u64)duty * 100;
6147         do_div(tmp64, duty100);
6148         *speed = (u32)tmp64;
6149
6150         if (*speed > 100)
6151                 *speed = 100;
6152
6153         return 0;
6154 }
6155
6156 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6157                                       u32 speed)
6158 {
6159         struct si_power_info *si_pi = si_get_pi(rdev);
6160         u32 tmp;
6161         u32 duty, duty100;
6162         u64 tmp64;
6163
6164         if (rdev->pm.no_fan)
6165                 return -ENOENT;
6166
6167         if (si_pi->fan_is_controlled_by_smc)
6168                 return -EINVAL;
6169
6170         if (speed > 100)
6171                 return -EINVAL;
6172
6173         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6174
6175         if (duty100 == 0)
6176                 return -EINVAL;
6177
6178         tmp64 = (u64)speed * duty100;
6179         do_div(tmp64, 100);
6180         duty = (u32)tmp64;
6181
6182         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6183         tmp |= FDO_STATIC_DUTY(duty);
6184         WREG32(CG_FDO_CTRL0, tmp);
6185
6186         return 0;
6187 }
6188
6189 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6190 {
6191         if (mode) {
6192                 /* stop auto-manage */
6193                 if (rdev->pm.dpm.fan.ucode_fan_control)
6194                         si_fan_ctrl_stop_smc_fan_control(rdev);
6195                 si_fan_ctrl_set_static_mode(rdev, mode);
6196         } else {
6197                 /* restart auto-manage */
6198                 if (rdev->pm.dpm.fan.ucode_fan_control)
6199                         si_thermal_start_smc_fan_control(rdev);
6200                 else
6201                         si_fan_ctrl_set_default_mode(rdev);
6202         }
6203 }
6204
6205 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6206 {
6207         struct si_power_info *si_pi = si_get_pi(rdev);
6208         u32 tmp;
6209
6210         if (si_pi->fan_is_controlled_by_smc)
6211                 return 0;
6212
6213         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6214         return (tmp >> FDO_PWM_MODE_SHIFT);
6215 }
6216
6217 #if 0
6218 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6219                                          u32 *speed)
6220 {
6221         u32 tach_period;
6222         u32 xclk = radeon_get_xclk(rdev);
6223
6224         if (rdev->pm.no_fan)
6225                 return -ENOENT;
6226
6227         if (rdev->pm.fan_pulses_per_revolution == 0)
6228                 return -ENOENT;
6229
6230         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6231         if (tach_period == 0)
6232                 return -ENOENT;
6233
6234         *speed = 60 * xclk * 10000 / tach_period;
6235
6236         return 0;
6237 }
6238
6239 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6240                                          u32 speed)
6241 {
6242         u32 tach_period, tmp;
6243         u32 xclk = radeon_get_xclk(rdev);
6244
6245         if (rdev->pm.no_fan)
6246                 return -ENOENT;
6247
6248         if (rdev->pm.fan_pulses_per_revolution == 0)
6249                 return -ENOENT;
6250
6251         if ((speed < rdev->pm.fan_min_rpm) ||
6252             (speed > rdev->pm.fan_max_rpm))
6253                 return -EINVAL;
6254
6255         if (rdev->pm.dpm.fan.ucode_fan_control)
6256                 si_fan_ctrl_stop_smc_fan_control(rdev);
6257
6258         tach_period = 60 * xclk * 10000 / (8 * speed);
6259         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6260         tmp |= TARGET_PERIOD(tach_period);
6261         WREG32(CG_TACH_CTRL, tmp);
6262
6263         si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6264
6265         return 0;
6266 }
6267 #endif
6268
6269 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6270 {
6271         struct si_power_info *si_pi = si_get_pi(rdev);
6272         u32 tmp;
6273
6274         if (!si_pi->fan_ctrl_is_in_default_mode) {
6275                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6276                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6277                 WREG32(CG_FDO_CTRL2, tmp);
6278
6279                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6280                 tmp |= TMIN(si_pi->t_min);
6281                 WREG32(CG_FDO_CTRL2, tmp);
6282                 si_pi->fan_ctrl_is_in_default_mode = true;
6283         }
6284 }
6285
6286 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6287 {
6288         if (rdev->pm.dpm.fan.ucode_fan_control) {
6289                 si_fan_ctrl_start_smc_fan_control(rdev);
6290                 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6291         }
6292 }
6293
6294 static void si_thermal_initialize(struct radeon_device *rdev)
6295 {
6296         u32 tmp;
6297
6298         if (rdev->pm.fan_pulses_per_revolution) {
6299                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6300                 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6301                 WREG32(CG_TACH_CTRL, tmp);
6302         }
6303
6304         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6305         tmp |= TACH_PWM_RESP_RATE(0x28);
6306         WREG32(CG_FDO_CTRL2, tmp);
6307 }
6308
6309 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6310 {
6311         int ret;
6312
6313         si_thermal_initialize(rdev);
6314         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6315         if (ret)
6316                 return ret;
6317         ret = si_thermal_enable_alert(rdev, true);
6318         if (ret)
6319                 return ret;
6320         if (rdev->pm.dpm.fan.ucode_fan_control) {
6321                 ret = si_halt_smc(rdev);
6322                 if (ret)
6323                         return ret;
6324                 ret = si_thermal_setup_fan_table(rdev);
6325                 if (ret)
6326                         return ret;
6327                 ret = si_resume_smc(rdev);
6328                 if (ret)
6329                         return ret;
6330                 si_thermal_start_smc_fan_control(rdev);
6331         }
6332
6333         return 0;
6334 }
6335
6336 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6337 {
6338         if (!rdev->pm.no_fan) {
6339                 si_fan_ctrl_set_default_mode(rdev);
6340                 si_fan_ctrl_stop_smc_fan_control(rdev);
6341         }
6342 }
6343
6344 int si_dpm_enable(struct radeon_device *rdev)
6345 {
6346         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6347         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6348         struct si_power_info *si_pi = si_get_pi(rdev);
6349         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6350         int ret;
6351
6352         if (si_is_smc_running(rdev))
6353                 return -EINVAL;
6354         if (pi->voltage_control || si_pi->voltage_control_svi2)
6355                 si_enable_voltage_control(rdev, true);
6356         if (pi->mvdd_control)
6357                 si_get_mvdd_configuration(rdev);
6358         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6359                 ret = si_construct_voltage_tables(rdev);
6360                 if (ret) {
6361                         DRM_ERROR("si_construct_voltage_tables failed\n");
6362                         return ret;
6363                 }
6364         }
6365         if (eg_pi->dynamic_ac_timing) {
6366                 ret = si_initialize_mc_reg_table(rdev);
6367                 if (ret)
6368                         eg_pi->dynamic_ac_timing = false;
6369         }
6370         if (pi->dynamic_ss)
6371                 si_enable_spread_spectrum(rdev, true);
6372         if (pi->thermal_protection)
6373                 si_enable_thermal_protection(rdev, true);
6374         si_setup_bsp(rdev);
6375         si_program_git(rdev);
6376         si_program_tp(rdev);
6377         si_program_tpp(rdev);
6378         si_program_sstp(rdev);
6379         si_enable_display_gap(rdev);
6380         si_program_vc(rdev);
6381         ret = si_upload_firmware(rdev);
6382         if (ret) {
6383                 DRM_ERROR("si_upload_firmware failed\n");
6384                 return ret;
6385         }
6386         ret = si_process_firmware_header(rdev);
6387         if (ret) {
6388                 DRM_ERROR("si_process_firmware_header failed\n");
6389                 return ret;
6390         }
6391         ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6392         if (ret) {
6393                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6394                 return ret;
6395         }
6396         ret = si_init_smc_table(rdev);
6397         if (ret) {
6398                 DRM_ERROR("si_init_smc_table failed\n");
6399                 return ret;
6400         }
6401         ret = si_init_smc_spll_table(rdev);
6402         if (ret) {
6403                 DRM_ERROR("si_init_smc_spll_table failed\n");
6404                 return ret;
6405         }
6406         ret = si_init_arb_table_index(rdev);
6407         if (ret) {
6408                 DRM_ERROR("si_init_arb_table_index failed\n");
6409                 return ret;
6410         }
6411         if (eg_pi->dynamic_ac_timing) {
6412                 ret = si_populate_mc_reg_table(rdev, boot_ps);
6413                 if (ret) {
6414                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6415                         return ret;
6416                 }
6417         }
6418         ret = si_initialize_smc_cac_tables(rdev);
6419         if (ret) {
6420                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6421                 return ret;
6422         }
6423         ret = si_initialize_hardware_cac_manager(rdev);
6424         if (ret) {
6425                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6426                 return ret;
6427         }
6428         ret = si_initialize_smc_dte_tables(rdev);
6429         if (ret) {
6430                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6431                 return ret;
6432         }
6433         ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6434         if (ret) {
6435                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6436                 return ret;
6437         }
6438         ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6439         if (ret) {
6440                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6441                 return ret;
6442         }
6443         si_program_response_times(rdev);
6444         si_program_ds_registers(rdev);
6445         si_dpm_start_smc(rdev);
6446         ret = si_notify_smc_display_change(rdev, false);
6447         if (ret) {
6448                 DRM_ERROR("si_notify_smc_display_change failed\n");
6449                 return ret;
6450         }
6451         si_enable_sclk_control(rdev, true);
6452         si_start_dpm(rdev);
6453
6454         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6455
6456         si_thermal_start_thermal_controller(rdev);
6457
6458         ni_update_current_ps(rdev, boot_ps);
6459
6460         return 0;
6461 }
6462
6463 static int si_set_temperature_range(struct radeon_device *rdev)
6464 {
6465         int ret;
6466
6467         ret = si_thermal_enable_alert(rdev, false);
6468         if (ret)
6469                 return ret;
6470         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6471         if (ret)
6472                 return ret;
6473         ret = si_thermal_enable_alert(rdev, true);
6474         if (ret)
6475                 return ret;
6476
6477         return ret;
6478 }
6479
6480 int si_dpm_late_enable(struct radeon_device *rdev)
6481 {
6482         int ret;
6483
6484         ret = si_set_temperature_range(rdev);
6485         if (ret)
6486                 return ret;
6487
6488         return ret;
6489 }
6490
6491 void si_dpm_disable(struct radeon_device *rdev)
6492 {
6493         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6494         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6495
6496         if (!si_is_smc_running(rdev))
6497                 return;
6498         si_thermal_stop_thermal_controller(rdev);
6499         si_disable_ulv(rdev);
6500         si_clear_vc(rdev);
6501         if (pi->thermal_protection)
6502                 si_enable_thermal_protection(rdev, false);
6503         si_enable_power_containment(rdev, boot_ps, false);
6504         si_enable_smc_cac(rdev, boot_ps, false);
6505         si_enable_spread_spectrum(rdev, false);
6506         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6507         si_stop_dpm(rdev);
6508         si_reset_to_default(rdev);
6509         si_dpm_stop_smc(rdev);
6510         si_force_switch_to_arb_f0(rdev);
6511
6512         ni_update_current_ps(rdev, boot_ps);
6513 }
6514
6515 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6516 {
6517         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6518         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6519         struct radeon_ps *new_ps = &requested_ps;
6520
6521         ni_update_requested_ps(rdev, new_ps);
6522
6523         si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6524
6525         return 0;
6526 }
6527
6528 static int si_power_control_set_level(struct radeon_device *rdev)
6529 {
6530         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6531         int ret;
6532
6533         ret = si_restrict_performance_levels_before_switch(rdev);
6534         if (ret)
6535                 return ret;
6536         ret = si_halt_smc(rdev);
6537         if (ret)
6538                 return ret;
6539         ret = si_populate_smc_tdp_limits(rdev, new_ps);
6540         if (ret)
6541                 return ret;
6542         ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6543         if (ret)
6544                 return ret;
6545         ret = si_resume_smc(rdev);
6546         if (ret)
6547                 return ret;
6548         ret = si_set_sw_state(rdev);
6549         if (ret)
6550                 return ret;
6551         return 0;
6552 }
6553
6554 int si_dpm_set_power_state(struct radeon_device *rdev)
6555 {
6556         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6557         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6558         struct radeon_ps *old_ps = &eg_pi->current_rps;
6559         int ret;
6560
6561         ret = si_disable_ulv(rdev);
6562         if (ret) {
6563                 DRM_ERROR("si_disable_ulv failed\n");
6564                 return ret;
6565         }
6566         ret = si_restrict_performance_levels_before_switch(rdev);
6567         if (ret) {
6568                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6569                 return ret;
6570         }
6571         if (eg_pi->pcie_performance_request)
6572                 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6573         ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6574         ret = si_enable_power_containment(rdev, new_ps, false);
6575         if (ret) {
6576                 DRM_ERROR("si_enable_power_containment failed\n");
6577                 return ret;
6578         }
6579         ret = si_enable_smc_cac(rdev, new_ps, false);
6580         if (ret) {
6581                 DRM_ERROR("si_enable_smc_cac failed\n");
6582                 return ret;
6583         }
6584         ret = si_halt_smc(rdev);
6585         if (ret) {
6586                 DRM_ERROR("si_halt_smc failed\n");
6587                 return ret;
6588         }
6589         ret = si_upload_sw_state(rdev, new_ps);
6590         if (ret) {
6591                 DRM_ERROR("si_upload_sw_state failed\n");
6592                 return ret;
6593         }
6594         ret = si_upload_smc_data(rdev);
6595         if (ret) {
6596                 DRM_ERROR("si_upload_smc_data failed\n");
6597                 return ret;
6598         }
6599         ret = si_upload_ulv_state(rdev);
6600         if (ret) {
6601                 DRM_ERROR("si_upload_ulv_state failed\n");
6602                 return ret;
6603         }
6604         if (eg_pi->dynamic_ac_timing) {
6605                 ret = si_upload_mc_reg_table(rdev, new_ps);
6606                 if (ret) {
6607                         DRM_ERROR("si_upload_mc_reg_table failed\n");
6608                         return ret;
6609                 }
6610         }
6611         ret = si_program_memory_timing_parameters(rdev, new_ps);
6612         if (ret) {
6613                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6614                 return ret;
6615         }
6616         si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6617
6618         ret = si_resume_smc(rdev);
6619         if (ret) {
6620                 DRM_ERROR("si_resume_smc failed\n");
6621                 return ret;
6622         }
6623         ret = si_set_sw_state(rdev);
6624         if (ret) {
6625                 DRM_ERROR("si_set_sw_state failed\n");
6626                 return ret;
6627         }
6628         ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6629         si_set_vce_clock(rdev, new_ps, old_ps);
6630         if (eg_pi->pcie_performance_request)
6631                 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6632         ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6633         if (ret) {
6634                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6635                 return ret;
6636         }
6637         ret = si_enable_smc_cac(rdev, new_ps, true);
6638         if (ret) {
6639                 DRM_ERROR("si_enable_smc_cac failed\n");
6640                 return ret;
6641         }
6642         ret = si_enable_power_containment(rdev, new_ps, true);
6643         if (ret) {
6644                 DRM_ERROR("si_enable_power_containment failed\n");
6645                 return ret;
6646         }
6647
6648         ret = si_power_control_set_level(rdev);
6649         if (ret) {
6650                 DRM_ERROR("si_power_control_set_level failed\n");
6651                 return ret;
6652         }
6653
6654         return 0;
6655 }
6656
6657 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6658 {
6659         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6660         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6661
6662         ni_update_current_ps(rdev, new_ps);
6663 }
6664
6665 #if 0
6666 void si_dpm_reset_asic(struct radeon_device *rdev)
6667 {
6668         si_restrict_performance_levels_before_switch(rdev);
6669         si_disable_ulv(rdev);
6670         si_set_boot_state(rdev);
6671 }
6672 #endif
6673
6674 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6675 {
6676         si_program_display_gap(rdev);
6677 }
6678
6679 union power_info {
6680         struct _ATOM_POWERPLAY_INFO info;
6681         struct _ATOM_POWERPLAY_INFO_V2 info_2;
6682         struct _ATOM_POWERPLAY_INFO_V3 info_3;
6683         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6684         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6685         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6686 };
6687
6688 union pplib_clock_info {
6689         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6690         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6691         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6692         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6693         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6694 };
6695
6696 union pplib_power_state {
6697         struct _ATOM_PPLIB_STATE v1;
6698         struct _ATOM_PPLIB_STATE_V2 v2;
6699 };
6700
6701 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6702                                           struct radeon_ps *rps,
6703                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6704                                           u8 table_rev)
6705 {
6706         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6707         rps->class = le16_to_cpu(non_clock_info->usClassification);
6708         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6709
6710         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6711                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6712                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6713         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6714                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6715                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6716         } else {
6717                 rps->vclk = 0;
6718                 rps->dclk = 0;
6719         }
6720
6721         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6722                 rdev->pm.dpm.boot_ps = rps;
6723         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6724                 rdev->pm.dpm.uvd_ps = rps;
6725 }
6726
6727 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6728                                       struct radeon_ps *rps, int index,
6729                                       union pplib_clock_info *clock_info)
6730 {
6731         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6732         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6733         struct si_power_info *si_pi = si_get_pi(rdev);
6734         struct ni_ps *ps = ni_get_ps(rps);
6735         u16 leakage_voltage;
6736         struct rv7xx_pl *pl = &ps->performance_levels[index];
6737         int ret;
6738
6739         ps->performance_level_count = index + 1;
6740
6741         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6742         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6743         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6744         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6745
6746         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6747         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6748         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6749         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6750                                                  si_pi->sys_pcie_mask,
6751                                                  si_pi->boot_pcie_gen,
6752                                                  clock_info->si.ucPCIEGen);
6753
6754         /* patch up vddc if necessary */
6755         ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6756                                                         &leakage_voltage);
6757         if (ret == 0)
6758                 pl->vddc = leakage_voltage;
6759
6760         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6761                 pi->acpi_vddc = pl->vddc;
6762                 eg_pi->acpi_vddci = pl->vddci;
6763                 si_pi->acpi_pcie_gen = pl->pcie_gen;
6764         }
6765
6766         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6767             index == 0) {
6768                 /* XXX disable for A0 tahiti */
6769                 si_pi->ulv.supported = false;
6770                 si_pi->ulv.pl = *pl;
6771                 si_pi->ulv.one_pcie_lane_in_ulv = false;
6772                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6773                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6774                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6775         }
6776
6777         if (pi->min_vddc_in_table > pl->vddc)
6778                 pi->min_vddc_in_table = pl->vddc;
6779
6780         if (pi->max_vddc_in_table < pl->vddc)
6781                 pi->max_vddc_in_table = pl->vddc;
6782
6783         /* patch up boot state */
6784         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6785                 u16 vddc, vddci, mvdd;
6786                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6787                 pl->mclk = rdev->clock.default_mclk;
6788                 pl->sclk = rdev->clock.default_sclk;
6789                 pl->vddc = vddc;
6790                 pl->vddci = vddci;
6791                 si_pi->mvdd_bootup_value = mvdd;
6792         }
6793
6794         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6795             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6796                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6797                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6798                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6799                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6800         }
6801 }
6802
6803 static int si_parse_power_table(struct radeon_device *rdev)
6804 {
6805         struct radeon_mode_info *mode_info = &rdev->mode_info;
6806         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6807         union pplib_power_state *power_state;
6808         int i, j, k, non_clock_array_index, clock_array_index;
6809         union pplib_clock_info *clock_info;
6810         struct _StateArray *state_array;
6811         struct _ClockInfoArray *clock_info_array;
6812         struct _NonClockInfoArray *non_clock_info_array;
6813         union power_info *power_info;
6814         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6815         u16 data_offset;
6816         u8 frev, crev;
6817         u8 *power_state_offset;
6818         struct ni_ps *ps;
6819
6820         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6821                                    &frev, &crev, &data_offset))
6822                 return -EINVAL;
6823         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6824
6825         state_array = (struct _StateArray *)
6826                 (mode_info->atom_context->bios + data_offset +
6827                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
6828         clock_info_array = (struct _ClockInfoArray *)
6829                 (mode_info->atom_context->bios + data_offset +
6830                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6831         non_clock_info_array = (struct _NonClockInfoArray *)
6832                 (mode_info->atom_context->bios + data_offset +
6833                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6834
6835         rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
6836                                   sizeof(struct radeon_ps),
6837                                   GFP_KERNEL);
6838         if (!rdev->pm.dpm.ps)
6839                 return -ENOMEM;
6840         power_state_offset = (u8 *)state_array->states;
6841         for (i = 0; i < state_array->ucNumEntries; i++) {
6842                 u8 *idx;
6843                 power_state = (union pplib_power_state *)power_state_offset;
6844                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6845                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6846                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
6847                 if (!rdev->pm.power_state[i].clock_info)
6848                         return -EINVAL;
6849                 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6850                 if (ps == NULL) {
6851                         kfree(rdev->pm.dpm.ps);
6852                         return -ENOMEM;
6853                 }
6854                 rdev->pm.dpm.ps[i].ps_priv = ps;
6855                 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6856                                               non_clock_info,
6857                                               non_clock_info_array->ucEntrySize);
6858                 k = 0;
6859                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6860                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6861                         clock_array_index = idx[j];
6862                         if (clock_array_index >= clock_info_array->ucNumEntries)
6863                                 continue;
6864                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6865                                 break;
6866                         clock_info = (union pplib_clock_info *)
6867                                 ((u8 *)&clock_info_array->clockInfo[0] +
6868                                  (clock_array_index * clock_info_array->ucEntrySize));
6869                         si_parse_pplib_clock_info(rdev,
6870                                                   &rdev->pm.dpm.ps[i], k,
6871                                                   clock_info);
6872                         k++;
6873                 }
6874                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6875         }
6876         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6877
6878         /* fill in the vce power states */
6879         for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6880                 u32 sclk, mclk;
6881                 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6882                 clock_info = (union pplib_clock_info *)
6883                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6884                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6885                 sclk |= clock_info->si.ucEngineClockHigh << 16;
6886                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6887                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
6888                 rdev->pm.dpm.vce_states[i].sclk = sclk;
6889                 rdev->pm.dpm.vce_states[i].mclk = mclk;
6890         }
6891
6892         return 0;
6893 }
6894
6895 int si_dpm_init(struct radeon_device *rdev)
6896 {
6897         struct rv7xx_power_info *pi;
6898         struct evergreen_power_info *eg_pi;
6899         struct ni_power_info *ni_pi;
6900         struct si_power_info *si_pi;
6901         struct atom_clock_dividers dividers;
6902         enum pci_bus_speed speed_cap;
6903         struct pci_dev *root = rdev->pdev->bus->self;
6904         int ret;
6905
6906         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6907         if (si_pi == NULL)
6908                 return -ENOMEM;
6909         rdev->pm.dpm.priv = si_pi;
6910         ni_pi = &si_pi->ni;
6911         eg_pi = &ni_pi->eg;
6912         pi = &eg_pi->rv7xx;
6913
6914         speed_cap = pcie_get_speed_cap(root);
6915         if (speed_cap == PCI_SPEED_UNKNOWN) {
6916                 si_pi->sys_pcie_mask = 0;
6917         } else {
6918                 if (speed_cap == PCIE_SPEED_8_0GT)
6919                         si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
6920                                 RADEON_PCIE_SPEED_50 |
6921                                 RADEON_PCIE_SPEED_80;
6922                 else if (speed_cap == PCIE_SPEED_5_0GT)
6923                         si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
6924                                 RADEON_PCIE_SPEED_50;
6925                 else
6926                         si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25;
6927         }
6928         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6929         si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6930
6931         si_set_max_cu_value(rdev);
6932
6933         rv770_get_max_vddc(rdev);
6934         si_get_leakage_vddc(rdev);
6935         si_patch_dependency_tables_based_on_leakage(rdev);
6936
6937         pi->acpi_vddc = 0;
6938         eg_pi->acpi_vddci = 0;
6939         pi->min_vddc_in_table = 0;
6940         pi->max_vddc_in_table = 0;
6941
6942         ret = r600_get_platform_caps(rdev);
6943         if (ret)
6944                 return ret;
6945
6946         ret = r600_parse_extended_power_table(rdev);
6947         if (ret)
6948                 return ret;
6949
6950         ret = si_parse_power_table(rdev);
6951         if (ret)
6952                 return ret;
6953
6954         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6955                 kcalloc(4,
6956                         sizeof(struct radeon_clock_voltage_dependency_entry),
6957                         GFP_KERNEL);
6958         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6959                 r600_free_extended_power_table(rdev);
6960                 return -ENOMEM;
6961         }
6962         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6963         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6964         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6965         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6966         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6967         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6968         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6969         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6970         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6971
6972         if (rdev->pm.dpm.voltage_response_time == 0)
6973                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6974         if (rdev->pm.dpm.backbias_response_time == 0)
6975                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6976
6977         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6978                                              0, false, &dividers);
6979         if (ret)
6980                 pi->ref_div = dividers.ref_div + 1;
6981         else
6982                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6983
6984         eg_pi->smu_uvd_hs = false;
6985
6986         pi->mclk_strobe_mode_threshold = 40000;
6987         if (si_is_special_1gb_platform(rdev))
6988                 pi->mclk_stutter_mode_threshold = 0;
6989         else
6990                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6991         pi->mclk_edc_enable_threshold = 40000;
6992         eg_pi->mclk_edc_wr_enable_threshold = 40000;
6993
6994         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6995
6996         pi->voltage_control =
6997                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6998                                             VOLTAGE_OBJ_GPIO_LUT);
6999         if (!pi->voltage_control) {
7000                 si_pi->voltage_control_svi2 =
7001                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7002                                                     VOLTAGE_OBJ_SVID2);
7003                 if (si_pi->voltage_control_svi2)
7004                         radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7005                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7006         }
7007
7008         pi->mvdd_control =
7009                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7010                                             VOLTAGE_OBJ_GPIO_LUT);
7011
7012         eg_pi->vddci_control =
7013                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7014                                             VOLTAGE_OBJ_GPIO_LUT);
7015         if (!eg_pi->vddci_control)
7016                 si_pi->vddci_control_svi2 =
7017                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7018                                                     VOLTAGE_OBJ_SVID2);
7019
7020         si_pi->vddc_phase_shed_control =
7021                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7022                                             VOLTAGE_OBJ_PHASE_LUT);
7023
7024         rv770_get_engine_memory_ss(rdev);
7025
7026         pi->asi = RV770_ASI_DFLT;
7027         pi->pasi = CYPRESS_HASI_DFLT;
7028         pi->vrc = SISLANDS_VRC_DFLT;
7029
7030         pi->gfx_clock_gating = true;
7031
7032         eg_pi->sclk_deep_sleep = true;
7033         si_pi->sclk_deep_sleep_above_low = false;
7034
7035         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7036                 pi->thermal_protection = true;
7037         else
7038                 pi->thermal_protection = false;
7039
7040         eg_pi->dynamic_ac_timing = true;
7041
7042         eg_pi->light_sleep = true;
7043 #if defined(CONFIG_ACPI)
7044         eg_pi->pcie_performance_request =
7045                 radeon_acpi_is_pcie_performance_request_supported(rdev);
7046 #else
7047         eg_pi->pcie_performance_request = false;
7048 #endif
7049
7050         si_pi->sram_end = SMC_RAM_END;
7051
7052         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7053         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7054         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7055         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7056         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7057         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7058         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7059
7060         si_initialize_powertune_defaults(rdev);
7061
7062         /* make sure dc limits are valid */
7063         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7064             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7065                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7066                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7067
7068         si_pi->fan_ctrl_is_in_default_mode = true;
7069
7070         return 0;
7071 }
7072
7073 void si_dpm_fini(struct radeon_device *rdev)
7074 {
7075         int i;
7076
7077         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7078                 kfree(rdev->pm.dpm.ps[i].ps_priv);
7079         }
7080         kfree(rdev->pm.dpm.ps);
7081         kfree(rdev->pm.dpm.priv);
7082         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7083         r600_free_extended_power_table(rdev);
7084 }
7085
7086 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7087                                                     struct seq_file *m)
7088 {
7089         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7090         struct radeon_ps *rps = &eg_pi->current_rps;
7091         struct ni_ps *ps = ni_get_ps(rps);
7092         struct rv7xx_pl *pl;
7093         u32 current_index =
7094                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7095                 CURRENT_STATE_INDEX_SHIFT;
7096
7097         if (current_index >= ps->performance_level_count) {
7098                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7099         } else {
7100                 pl = &ps->performance_levels[current_index];
7101                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7102                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7103                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7104         }
7105 }
7106
7107 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7108 {
7109         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7110         struct radeon_ps *rps = &eg_pi->current_rps;
7111         struct ni_ps *ps = ni_get_ps(rps);
7112         struct rv7xx_pl *pl;
7113         u32 current_index =
7114                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7115                 CURRENT_STATE_INDEX_SHIFT;
7116
7117         if (current_index >= ps->performance_level_count) {
7118                 return 0;
7119         } else {
7120                 pl = &ps->performance_levels[current_index];
7121                 return pl->sclk;
7122         }
7123 }
7124
7125 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7126 {
7127         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7128         struct radeon_ps *rps = &eg_pi->current_rps;
7129         struct ni_ps *ps = ni_get_ps(rps);
7130         struct rv7xx_pl *pl;
7131         u32 current_index =
7132                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7133                 CURRENT_STATE_INDEX_SHIFT;
7134
7135         if (current_index >= ps->performance_level_count) {
7136                 return 0;
7137         } else {
7138                 pl = &ps->performance_levels[current_index];
7139                 return pl->mclk;
7140         }
7141 }