drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_crtc.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/clk.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/component.h>
  29
  30 #include <linux/reset.h>
  31 #include <linux/delay.h>
  32
  33 #include "rockchip_drm_drv.h"
  34 #include "rockchip_drm_gem.h"
  35 #include "rockchip_drm_fb.h"
  36 #include "rockchip_drm_vop.h"
  37
  38 #define VOP_REG(off, _mask, s) \
  39                 {.offset = off, \
  40                  .mask = _mask, \
  41                  .shift = s,}
  42
  43 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
  44                 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
  45 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
  46                 vop_mask_write(x, off, (mask) << shift, (v) << shift)
  47
  48 #define REG_SET(x, base, reg, v, mode) \
  49                 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
  50
  51 #define VOP_WIN_SET(x, win, name, v) \
  52                 REG_SET(x, win->base, win->phy->name, v, RELAXED)
  53 #define VOP_CTRL_SET(x, name, v) \
  54                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  55
  56 #define VOP_WIN_GET(x, win, name) \
  57                 vop_read_reg(x, win->base, &win->phy->name)
  58
  59 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  60                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  61
  62 #define to_vop(x) container_of(x, struct vop, crtc)
  63 #define to_vop_win(x) container_of(x, struct vop_win, base)
  64
  65 struct vop_win_state {
  66         struct list_head head;
  67         struct drm_framebuffer *fb;
  68         dma_addr_t yrgb_mst;
  69         struct drm_pending_vblank_event *event;
  70 };
  71
  72 struct vop_win {
  73         struct drm_plane base;
  74         const struct vop_win_data *data;
  75         struct vop *vop;
  76
  77         struct list_head pending;
  78         struct vop_win_state *active;
  79 };
  80
  81 struct vop {
  82         struct drm_crtc crtc;
  83         struct device *dev;
  84         struct drm_device *drm_dev;
  85         bool is_enabled;
  86
  87         int connector_type;
  88         int connector_out_mode;
  89
  90         /* mutex vsync_ work */
  91         struct mutex vsync_mutex;
  92         bool vsync_work_pending;
  93         struct completion dsp_hold_completion;
  94
  95         const struct vop_data *data;
  96
  97         uint32_t *regsbak;
  98         void __iomem *regs;
  99
 100         /* physical map length of vop register */
 101         uint32_t len;
 102
 103         /* one time only one process allowed to config the register */
 104         spinlock_t reg_lock;
 105         /* lock vop irq reg */
 106         spinlock_t irq_lock;
 107
 108         unsigned int irq;
 109
 110         /* vop AHP clk */
 111         struct clk *hclk;
 112         /* vop dclk */
 113         struct clk *dclk;
 114         /* vop share memory frequency */
 115         struct clk *aclk;
 116
 117         /* vop dclk reset */
 118         struct reset_control *dclk_rst;
 119
 120         int pipe;
 121
 122         struct vop_win win[];
 123 };
 124
 125 enum vop_data_format {
 126         VOP_FMT_ARGB8888 = 0,
 127         VOP_FMT_RGB888,
 128         VOP_FMT_RGB565,
 129         VOP_FMT_YUV420SP = 4,
 130         VOP_FMT_YUV422SP,
 131         VOP_FMT_YUV444SP,
 132 };
 133
 134 struct vop_reg_data {
 135         uint32_t offset;
 136         uint32_t value;
 137 };
 138
 139 struct vop_reg {
 140         uint32_t offset;
 141         uint32_t shift;
 142         uint32_t mask;
 143 };
 144
 145 struct vop_ctrl {
 146         struct vop_reg standby;
 147         struct vop_reg data_blank;
 148         struct vop_reg gate_en;
 149         struct vop_reg mmu_en;
 150         struct vop_reg rgb_en;
 151         struct vop_reg edp_en;
 152         struct vop_reg hdmi_en;
 153         struct vop_reg mipi_en;
 154         struct vop_reg out_mode;
 155         struct vop_reg dither_down;
 156         struct vop_reg dither_up;
 157         struct vop_reg pin_pol;
 158
 159         struct vop_reg htotal_pw;
 160         struct vop_reg hact_st_end;
 161         struct vop_reg vtotal_pw;
 162         struct vop_reg vact_st_end;
 163         struct vop_reg hpost_st_end;
 164         struct vop_reg vpost_st_end;
 165 };
 166
 167 struct vop_win_phy {
 168         const uint32_t *data_formats;
 169         uint32_t nformats;
 170
 171         struct vop_reg enable;
 172         struct vop_reg format;
 173         struct vop_reg act_info;
 174         struct vop_reg dsp_info;
 175         struct vop_reg dsp_st;
 176         struct vop_reg yrgb_mst;
 177         struct vop_reg uv_mst;
 178         struct vop_reg yrgb_vir;
 179         struct vop_reg uv_vir;
 180
 181         struct vop_reg dst_alpha_ctl;
 182         struct vop_reg src_alpha_ctl;
 183 };
 184
 185 struct vop_win_data {
 186         uint32_t base;
 187         const struct vop_win_phy *phy;
 188         enum drm_plane_type type;
 189 };
 190
 191 struct vop_data {
 192         const struct vop_reg_data *init_table;
 193         unsigned int table_size;
 194         const struct vop_ctrl *ctrl;
 195         const struct vop_win_data *win;
 196         unsigned int win_size;
 197 };
 198
 199 static const uint32_t formats_01[] = {
 200         DRM_FORMAT_XRGB8888,
 201         DRM_FORMAT_ARGB8888,
 202         DRM_FORMAT_RGB888,
 203         DRM_FORMAT_RGB565,
 204         DRM_FORMAT_NV12,
 205         DRM_FORMAT_NV16,
 206         DRM_FORMAT_NV24,
 207 };
 208
 209 static const uint32_t formats_234[] = {
 210         DRM_FORMAT_XRGB8888,
 211         DRM_FORMAT_ARGB8888,
 212         DRM_FORMAT_RGB888,
 213         DRM_FORMAT_RGB565,
 214 };
 215
 216 static const struct vop_win_phy win01_data = {
 217         .data_formats = formats_01,
 218         .nformats = ARRAY_SIZE(formats_01),
 219         .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
 220         .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
 221         .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
 222         .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
 223         .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
 224         .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
 225         .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
 226         .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
 227         .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
 228         .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
 229         .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
 230 };
 231
 232 static const struct vop_win_phy win23_data = {
 233         .data_formats = formats_234,
 234         .nformats = ARRAY_SIZE(formats_234),
 235         .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
 236         .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
 237         .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
 238         .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
 239         .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
 240         .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
 241         .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 242         .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
 243 };
 244
 245 static const struct vop_win_phy cursor_data = {
 246         .data_formats = formats_234,
 247         .nformats = ARRAY_SIZE(formats_234),
 248         .enable = VOP_REG(HWC_CTRL0, 0x1, 0),
 249         .format = VOP_REG(HWC_CTRL0, 0x7, 1),
 250         .dsp_st = VOP_REG(HWC_DSP_ST, 0x1fff1fff, 0),
 251         .yrgb_mst = VOP_REG(HWC_MST, 0xffffffff, 0),
 252 };
 253
 254 static const struct vop_ctrl ctrl_data = {
 255         .standby = VOP_REG(SYS_CTRL, 0x1, 22),
 256         .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
 257         .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
 258         .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
 259         .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
 260         .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
 261         .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
 262         .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
 263         .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
 264         .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
 265         .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
 266         .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
 267         .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 268         .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
 269         .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 270         .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
 271         .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 272         .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 273 };
 274
 275 static const struct vop_reg_data vop_init_reg_table[] = {
 276         {SYS_CTRL, 0x00c00000},
 277         {DSP_CTRL0, 0x00000000},
 278         {WIN0_CTRL0, 0x00000080},
 279         {WIN1_CTRL0, 0x00000080},
 280 };
 281
 282 /*
 283  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 284  * special support to get alpha blending working.  For now, just use overlay
 285  * window 1 for the drm cursor.
 286  */
 287 static const struct vop_win_data rk3288_vop_win_data[] = {
 288         { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
 289         { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_CURSOR },
 290         { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
 291         { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
 292         { .base = 0x00, .phy = &cursor_data, .type = DRM_PLANE_TYPE_OVERLAY },
 293 };
 294
 295 static const struct vop_data rk3288_vop = {
 296         .init_table = vop_init_reg_table,
 297         .table_size = ARRAY_SIZE(vop_init_reg_table),
 298         .ctrl = &ctrl_data,
 299         .win = rk3288_vop_win_data,
 300         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 301 };
 302
 303 static const struct of_device_id vop_driver_dt_match[] = {
 304         { .compatible = "rockchip,rk3288-vop",
 305           .data = &rk3288_vop },
 306         {},
 307 };
 308
 309 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 310 {
 311         writel(v, vop->regs + offset);
 312         vop->regsbak[offset >> 2] = v;
 313 }
 314
 315 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 316 {
 317         return readl(vop->regs + offset);
 318 }
 319
 320 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 321                                     const struct vop_reg *reg)
 322 {
 323         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 324 }
 325
 326 static inline void vop_cfg_done(struct vop *vop)
 327 {
 328         writel(0x01, vop->regs + REG_CFG_DONE);
 329 }
 330
 331 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 332                                   uint32_t mask, uint32_t v)
 333 {
 334         if (mask) {
 335                 uint32_t cached_val = vop->regsbak[offset >> 2];
 336
 337                 cached_val = (cached_val & ~mask) | v;
 338                 writel(cached_val, vop->regs + offset);
 339                 vop->regsbak[offset >> 2] = cached_val;
 340         }
 341 }
 342
 343 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
 344                                           uint32_t mask, uint32_t v)
 345 {
 346         if (mask) {
 347                 uint32_t cached_val = vop->regsbak[offset >> 2];
 348
 349                 cached_val = (cached_val & ~mask) | v;
 350                 writel_relaxed(cached_val, vop->regs + offset);
 351                 vop->regsbak[offset >> 2] = cached_val;
 352         }
 353 }
 354
 355 static enum vop_data_format vop_convert_format(uint32_t format)
 356 {
 357         switch (format) {
 358         case DRM_FORMAT_XRGB8888:
 359         case DRM_FORMAT_ARGB8888:
 360                 return VOP_FMT_ARGB8888;
 361         case DRM_FORMAT_RGB888:
 362                 return VOP_FMT_RGB888;
 363         case DRM_FORMAT_RGB565:
 364                 return VOP_FMT_RGB565;
 365         case DRM_FORMAT_NV12:
 366                 return VOP_FMT_YUV420SP;
 367         case DRM_FORMAT_NV16:
 368                 return VOP_FMT_YUV422SP;
 369         case DRM_FORMAT_NV24:
 370                 return VOP_FMT_YUV444SP;
 371         default:
 372                 DRM_ERROR("unsupport format[%08x]\n", format);
 373                 return -EINVAL;
 374         }
 375 }
 376
 377 static bool is_alpha_support(uint32_t format)
 378 {
 379         switch (format) {
 380         case DRM_FORMAT_ARGB8888:
 381                 return true;
 382         default:
 383                 return false;
 384         }
 385 }
 386
 387 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 388 {
 389         unsigned long flags;
 390
 391         if (WARN_ON(!vop->is_enabled))
 392                 return;
 393
 394         spin_lock_irqsave(&vop->irq_lock, flags);
 395
 396         vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
 397                        DSP_HOLD_VALID_INTR_EN(1));
 398
 399         spin_unlock_irqrestore(&vop->irq_lock, flags);
 400 }
 401
 402 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 403 {
 404         unsigned long flags;
 405
 406         if (WARN_ON(!vop->is_enabled))
 407                 return;
 408
 409         spin_lock_irqsave(&vop->irq_lock, flags);
 410
 411         vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
 412                        DSP_HOLD_VALID_INTR_EN(0));
 413
 414         spin_unlock_irqrestore(&vop->irq_lock, flags);
 415 }
 416
 417 static void vop_enable(struct drm_crtc *crtc)
 418 {
 419         struct vop *vop = to_vop(crtc);
 420         int ret;
 421
 422         if (vop->is_enabled)
 423                 return;
 424
 425         ret = pm_runtime_get_sync(vop->dev);
 426         if (ret < 0) {
 427                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 428                 return;
 429         }
 430
 431         ret = clk_enable(vop->hclk);
 432         if (ret < 0) {
 433                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 434                 return;
 435         }
 436
 437         ret = clk_enable(vop->dclk);
 438         if (ret < 0) {
 439                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 440                 goto err_disable_hclk;
 441         }
 442
 443         ret = clk_enable(vop->aclk);
 444         if (ret < 0) {
 445                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 446                 goto err_disable_dclk;
 447         }
 448
 449         /*
 450          * Slave iommu shares power, irq and clock with vop.  It was associated
 451          * automatically with this master device via common driver code.
 452          * Now that we have enabled the clock we attach it to the shared drm
 453          * mapping.
 454          */
 455         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 456         if (ret) {
 457                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 458                 goto err_disable_aclk;
 459         }
 460
 461         /*
 462          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 463          */
 464         vop->is_enabled = true;
 465
 466         spin_lock(&vop->reg_lock);
 467
 468         VOP_CTRL_SET(vop, standby, 0);
 469
 470         spin_unlock(&vop->reg_lock);
 471
 472         enable_irq(vop->irq);
 473
 474         drm_vblank_on(vop->drm_dev, vop->pipe);
 475
 476         return;
 477
 478 err_disable_aclk:
 479         clk_disable(vop->aclk);
 480 err_disable_dclk:
 481         clk_disable(vop->dclk);
 482 err_disable_hclk:
 483         clk_disable(vop->hclk);
 484 }
 485
 486 static void vop_disable(struct drm_crtc *crtc)
 487 {
 488         struct vop *vop = to_vop(crtc);
 489
 490         if (!vop->is_enabled)
 491                 return;
 492
 493         drm_vblank_off(crtc->dev, vop->pipe);
 494
 495         /*
 496          * Vop standby will take effect at end of current frame,
 497          * if dsp hold valid irq happen, it means standby complete.
 498          *
 499          * we must wait standby complete when we want to disable aclk,
 500          * if not, memory bus maybe dead.
 501          */
 502         reinit_completion(&vop->dsp_hold_completion);
 503         vop_dsp_hold_valid_irq_enable(vop);
 504
 505         spin_lock(&vop->reg_lock);
 506
 507         VOP_CTRL_SET(vop, standby, 1);
 508
 509         spin_unlock(&vop->reg_lock);
 510
 511         wait_for_completion(&vop->dsp_hold_completion);
 512
 513         vop_dsp_hold_valid_irq_disable(vop);
 514
 515         disable_irq(vop->irq);
 516
 517         vop->is_enabled = false;
 518
 519         /*
 520          * vop standby complete, so iommu detach is safe.
 521          */
 522         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 523
 524         clk_disable(vop->dclk);
 525         clk_disable(vop->aclk);
 526         clk_disable(vop->hclk);
 527         pm_runtime_put(vop->dev);
 528 }
 529
 530 /*
 531  * Caller must hold vsync_mutex.
 532  */
 533 static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win)
 534 {
 535         struct vop_win_state *last;
 536         struct vop_win_state *active = vop_win->active;
 537
 538         if (list_empty(&vop_win->pending))
 539                 return active ? active->fb : NULL;
 540
 541         last = list_last_entry(&vop_win->pending, struct vop_win_state, head);
 542         return last ? last->fb : NULL;
 543 }
 544
 545 /*
 546  * Caller must hold vsync_mutex.
 547  */
 548 static int vop_win_queue_fb(struct vop_win *vop_win,
 549                             struct drm_framebuffer *fb, dma_addr_t yrgb_mst,
 550                             struct drm_pending_vblank_event *event)
 551 {
 552         struct vop_win_state *state;
 553
 554         state = kzalloc(sizeof(*state), GFP_KERNEL);
 555         if (!state)
 556                 return -ENOMEM;
 557
 558         state->fb = fb;
 559         state->yrgb_mst = yrgb_mst;
 560         state->event = event;
 561
 562         list_add_tail(&state->head, &vop_win->pending);
 563
 564         return 0;
 565 }
 566
 567 static int vop_update_plane_event(struct drm_plane *plane,
 568                                   struct drm_crtc *crtc,
 569                                   struct drm_framebuffer *fb, int crtc_x,
 570                                   int crtc_y, unsigned int crtc_w,
 571                                   unsigned int crtc_h, uint32_t src_x,
 572                                   uint32_t src_y, uint32_t src_w,
 573                                   uint32_t src_h,
 574                                   struct drm_pending_vblank_event *event)
 575 {
 576         struct vop_win *vop_win = to_vop_win(plane);
 577         const struct vop_win_data *win = vop_win->data;
 578         struct vop *vop = to_vop(crtc);
 579         struct drm_gem_object *obj;
 580         struct rockchip_gem_object *rk_obj;
 581         unsigned long offset;
 582         unsigned int actual_w;
 583         unsigned int actual_h;
 584         unsigned int dsp_stx;
 585         unsigned int dsp_sty;
 586         unsigned int y_vir_stride;
 587         dma_addr_t yrgb_mst;
 588         enum vop_data_format format;
 589         uint32_t val;
 590         bool is_alpha;
 591         bool visible;
 592         int ret;
 593         struct drm_rect dest = {
 594                 .x1 = crtc_x,
 595                 .y1 = crtc_y,
 596                 .x2 = crtc_x + crtc_w,
 597                 .y2 = crtc_y + crtc_h,
 598         };
 599         struct drm_rect src = {
 600                 /* 16.16 fixed point */
 601                 .x1 = src_x,
 602                 .y1 = src_y,
 603                 .x2 = src_x + src_w,
 604                 .y2 = src_y + src_h,
 605         };
 606         const struct drm_rect clip = {
 607                 .x2 = crtc->mode.hdisplay,
 608                 .y2 = crtc->mode.vdisplay,
 609         };
 610         bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
 611
 612         ret = drm_plane_helper_check_update(plane, crtc, fb,
 613                                             &src, &dest, &clip,
 614                                             DRM_PLANE_HELPER_NO_SCALING,
 615                                             DRM_PLANE_HELPER_NO_SCALING,
 616                                             can_position, false, &visible);
 617         if (ret)
 618                 return ret;
 619
 620         if (!visible)
 621                 return 0;
 622
 623         is_alpha = is_alpha_support(fb->pixel_format);
 624         format = vop_convert_format(fb->pixel_format);
 625         if (format < 0)
 626                 return format;
 627
 628         obj = rockchip_fb_get_gem_obj(fb, 0);
 629         if (!obj) {
 630                 DRM_ERROR("fail to get rockchip gem object from framebuffer\n");
 631                 return -EINVAL;
 632         }
 633
 634         rk_obj = to_rockchip_obj(obj);
 635
 636         actual_w = (src.x2 - src.x1) >> 16;
 637         actual_h = (src.y2 - src.y1) >> 16;
 638         crtc_x = max(0, crtc_x);
 639         crtc_y = max(0, crtc_y);
 640
 641         dsp_stx = crtc_x + crtc->mode.htotal - crtc->mode.hsync_start;
 642         dsp_sty = crtc_y + crtc->mode.vtotal - crtc->mode.vsync_start;
 643
 644         offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3);
 645         offset += (src.y1 >> 16) * fb->pitches[0];
 646         yrgb_mst = rk_obj->dma_addr + offset;
 647
 648         y_vir_stride = fb->pitches[0] / (fb->bits_per_pixel >> 3);
 649
 650         /*
 651          * If this plane update changes the plane's framebuffer, (or more
 652          * precisely, if this update has a different framebuffer than the last
 653          * update), enqueue it so we can track when it completes.
 654          *
 655          * Only when we discover that this update has completed, can we
 656          * unreference any previous framebuffers.
 657          */
 658         mutex_lock(&vop->vsync_mutex);
 659         if (fb != vop_win_last_pending_fb(vop_win)) {
 660                 ret = drm_vblank_get(plane->dev, vop->pipe);
 661                 if (ret) {
 662                         DRM_ERROR("failed to get vblank, %d\n", ret);
 663                         mutex_unlock(&vop->vsync_mutex);
 664                         return ret;
 665                 }
 666
 667                 drm_framebuffer_reference(fb);
 668
 669                 ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event);
 670                 if (ret) {
 671                         drm_vblank_put(plane->dev, vop->pipe);
 672                         mutex_unlock(&vop->vsync_mutex);
 673                         return ret;
 674                 }
 675
 676                 vop->vsync_work_pending = true;
 677         }
 678         mutex_unlock(&vop->vsync_mutex);
 679
 680         spin_lock(&vop->reg_lock);
 681
 682         VOP_WIN_SET(vop, win, format, format);
 683         VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride);
 684         VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst);
 685         val = (actual_h - 1) << 16;
 686         val |= (actual_w - 1) & 0xffff;
 687         VOP_WIN_SET(vop, win, act_info, val);
 688         VOP_WIN_SET(vop, win, dsp_info, val);
 689         val = (dsp_sty - 1) << 16;
 690         val |= (dsp_stx - 1) & 0xffff;
 691         VOP_WIN_SET(vop, win, dsp_st, val);
 692
 693         if (is_alpha) {
 694                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 695                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 696                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 697                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 698                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 699                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 700                         SRC_FACTOR_M0(ALPHA_ONE);
 701                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 702         } else {
 703                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 704         }
 705
 706         VOP_WIN_SET(vop, win, enable, 1);
 707
 708         vop_cfg_done(vop);
 709         spin_unlock(&vop->reg_lock);
 710
 711         return 0;
 712 }
 713
 714 static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 715                             struct drm_framebuffer *fb, int crtc_x, int crtc_y,
 716                             unsigned int crtc_w, unsigned int crtc_h,
 717                             uint32_t src_x, uint32_t src_y, uint32_t src_w,
 718                             uint32_t src_h)
 719 {
 720         return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w,
 721                                       crtc_h, src_x, src_y, src_w, src_h,
 722                                       NULL);
 723 }
 724
 725 static int vop_update_primary_plane(struct drm_crtc *crtc,
 726                                     struct drm_pending_vblank_event *event)
 727 {
 728         unsigned int crtc_w, crtc_h;
 729
 730         crtc_w = crtc->primary->fb->width - crtc->x;
 731         crtc_h = crtc->primary->fb->height - crtc->y;
 732
 733         return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb,
 734                                       0, 0, crtc_w, crtc_h, crtc->x << 16,
 735                                       crtc->y << 16, crtc_w << 16,
 736                                       crtc_h << 16, event);
 737 }
 738
 739 static int vop_disable_plane(struct drm_plane *plane)
 740 {
 741         struct vop_win *vop_win = to_vop_win(plane);
 742         const struct vop_win_data *win = vop_win->data;
 743         struct vop *vop;
 744         int ret;
 745
 746         if (!plane->crtc)
 747                 return 0;
 748
 749         vop = to_vop(plane->crtc);
 750
 751         ret = drm_vblank_get(plane->dev, vop->pipe);
 752         if (ret) {
 753                 DRM_ERROR("failed to get vblank, %d\n", ret);
 754                 return ret;
 755         }
 756
 757         mutex_lock(&vop->vsync_mutex);
 758
 759         ret = vop_win_queue_fb(vop_win, NULL, 0, NULL);
 760         if (ret) {
 761                 drm_vblank_put(plane->dev, vop->pipe);
 762                 mutex_unlock(&vop->vsync_mutex);
 763                 return ret;
 764         }
 765
 766         vop->vsync_work_pending = true;
 767         mutex_unlock(&vop->vsync_mutex);
 768
 769         spin_lock(&vop->reg_lock);
 770         VOP_WIN_SET(vop, win, enable, 0);
 771         vop_cfg_done(vop);
 772         spin_unlock(&vop->reg_lock);
 773
 774         return 0;
 775 }
 776
 777 static void vop_plane_destroy(struct drm_plane *plane)
 778 {
 779         vop_disable_plane(plane);
 780         drm_plane_cleanup(plane);
 781 }
 782
 783 static const struct drm_plane_funcs vop_plane_funcs = {
 784         .update_plane = vop_update_plane,
 785         .disable_plane = vop_disable_plane,
 786         .destroy = vop_plane_destroy,
 787 };
 788
 789 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
 790                                   int connector_type,
 791                                   int out_mode)
 792 {
 793         struct vop *vop = to_vop(crtc);
 794
 795         vop->connector_type = connector_type;
 796         vop->connector_out_mode = out_mode;
 797
 798         return 0;
 799 }
 800 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
 801
 802 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 803 {
 804         struct vop *vop = to_vop(crtc);
 805         unsigned long flags;
 806
 807         if (!vop->is_enabled)
 808                 return -EPERM;
 809
 810         spin_lock_irqsave(&vop->irq_lock, flags);
 811
 812         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1));
 813
 814         spin_unlock_irqrestore(&vop->irq_lock, flags);
 815
 816         return 0;
 817 }
 818
 819 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 820 {
 821         struct vop *vop = to_vop(crtc);
 822         unsigned long flags;
 823
 824         if (!vop->is_enabled)
 825                 return;
 826
 827         spin_lock_irqsave(&vop->irq_lock, flags);
 828         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0));
 829         spin_unlock_irqrestore(&vop->irq_lock, flags);
 830 }
 831
 832 static const struct rockchip_crtc_funcs private_crtc_funcs = {
 833         .enable_vblank = vop_crtc_enable_vblank,
 834         .disable_vblank = vop_crtc_disable_vblank,
 835 };
 836
 837 static void vop_crtc_dpms(struct drm_crtc *crtc, int mode)
 838 {
 839         DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode);
 840
 841         switch (mode) {
 842         case DRM_MODE_DPMS_ON:
 843                 vop_enable(crtc);
 844                 break;
 845         case DRM_MODE_DPMS_STANDBY:
 846         case DRM_MODE_DPMS_SUSPEND:
 847         case DRM_MODE_DPMS_OFF:
 848                 vop_disable(crtc);
 849                 break;
 850         default:
 851                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 852                 break;
 853         }
 854 }
 855
 856 static void vop_crtc_prepare(struct drm_crtc *crtc)
 857 {
 858         vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 859 }
 860
 861 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
 862                                 const struct drm_display_mode *mode,
 863                                 struct drm_display_mode *adjusted_mode)
 864 {
 865         if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
 866                 return false;
 867
 868         return true;
 869 }
 870
 871 static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 872                                   struct drm_framebuffer *old_fb)
 873 {
 874         int ret;
 875
 876         crtc->x = x;
 877         crtc->y = y;
 878
 879         ret = vop_update_primary_plane(crtc, NULL);
 880         if (ret < 0) {
 881                 DRM_ERROR("fail to update plane\n");
 882                 return ret;
 883         }
 884
 885         return 0;
 886 }
 887
 888 static int vop_crtc_mode_set(struct drm_crtc *crtc,
 889                              struct drm_display_mode *mode,
 890                              struct drm_display_mode *adjusted_mode,
 891                              int x, int y, struct drm_framebuffer *fb)
 892 {
 893         struct vop *vop = to_vop(crtc);
 894         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 895         u16 hdisplay = adjusted_mode->hdisplay;
 896         u16 htotal = adjusted_mode->htotal;
 897         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
 898         u16 hact_end = hact_st + hdisplay;
 899         u16 vdisplay = adjusted_mode->vdisplay;
 900         u16 vtotal = adjusted_mode->vtotal;
 901         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 902         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
 903         u16 vact_end = vact_st + vdisplay;
 904         int ret, ret_clk;
 905         uint32_t val;
 906
 907         /*
 908          * disable dclk to stop frame scan, so that we can safe config mode and
 909          * enable iommu.
 910          */
 911         clk_disable(vop->dclk);
 912
 913         switch (vop->connector_type) {
 914         case DRM_MODE_CONNECTOR_LVDS:
 915                 VOP_CTRL_SET(vop, rgb_en, 1);
 916                 break;
 917         case DRM_MODE_CONNECTOR_eDP:
 918                 VOP_CTRL_SET(vop, edp_en, 1);
 919                 break;
 920         case DRM_MODE_CONNECTOR_HDMIA:
 921                 VOP_CTRL_SET(vop, hdmi_en, 1);
 922                 break;
 923         default:
 924                 DRM_ERROR("unsupport connector_type[%d]\n",
 925                           vop->connector_type);
 926                 ret = -EINVAL;
 927                 goto out;
 928         };
 929         VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode);
 930
 931         val = 0x8;
 932         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
 933         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
 934         VOP_CTRL_SET(vop, pin_pol, val);
 935
 936         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
 937         val = hact_st << 16;
 938         val |= hact_end;
 939         VOP_CTRL_SET(vop, hact_st_end, val);
 940         VOP_CTRL_SET(vop, hpost_st_end, val);
 941
 942         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
 943         val = vact_st << 16;
 944         val |= vact_end;
 945         VOP_CTRL_SET(vop, vact_st_end, val);
 946         VOP_CTRL_SET(vop, vpost_st_end, val);
 947
 948         ret = vop_crtc_mode_set_base(crtc, x, y, fb);
 949         if (ret)
 950                 goto out;
 951
 952         /*
 953          * reset dclk, take all mode config affect, so the clk would run in
 954          * correct frame.
 955          */
 956         reset_control_assert(vop->dclk_rst);
 957         usleep_range(10, 20);
 958         reset_control_deassert(vop->dclk_rst);
 959
 960         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
 961 out:
 962         ret_clk = clk_enable(vop->dclk);
 963         if (ret_clk < 0) {
 964                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret_clk);
 965                 return ret_clk;
 966         }
 967
 968         return ret;
 969 }
 970
 971 static void vop_crtc_commit(struct drm_crtc *crtc)
 972 {
 973 }
 974
 975 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
 976         .dpms = vop_crtc_dpms,
 977         .prepare = vop_crtc_prepare,
 978         .mode_fixup = vop_crtc_mode_fixup,
 979         .mode_set = vop_crtc_mode_set,
 980         .mode_set_base = vop_crtc_mode_set_base,
 981         .commit = vop_crtc_commit,
 982 };
 983
 984 static int vop_crtc_page_flip(struct drm_crtc *crtc,
 985                               struct drm_framebuffer *fb,
 986                               struct drm_pending_vblank_event *event,
 987                               uint32_t page_flip_flags)
 988 {
 989         struct vop *vop = to_vop(crtc);
 990         struct drm_framebuffer *old_fb = crtc->primary->fb;
 991         int ret;
 992
 993         /* when the page flip is requested, crtc should be on */
 994         if (!vop->is_enabled) {
 995                 DRM_DEBUG("page flip request rejected because crtc is off.\n");
 996                 return 0;
 997         }
 998
 999         crtc->primary->fb = fb;
1000
1001         ret = vop_update_primary_plane(crtc, event);
1002         if (ret)
1003                 crtc->primary->fb = old_fb;
1004
1005         return ret;
1006 }
1007
1008 static void vop_win_state_complete(struct vop_win *vop_win,
1009                                    struct vop_win_state *state)
1010 {
1011         struct vop *vop = vop_win->vop;
1012         struct drm_crtc *crtc = &vop->crtc;
1013         struct drm_device *drm = crtc->dev;
1014         unsigned long flags;
1015
1016         if (state->event) {
1017                 spin_lock_irqsave(&drm->event_lock, flags);
1018                 drm_send_vblank_event(drm, -1, state->event);
1019                 spin_unlock_irqrestore(&drm->event_lock, flags);
1020         }
1021
1022         list_del(&state->head);
1023         drm_vblank_put(crtc->dev, vop->pipe);
1024 }
1025
1026 static void vop_crtc_destroy(struct drm_crtc *crtc)
1027 {
1028         drm_crtc_cleanup(crtc);
1029 }
1030
1031 static const struct drm_crtc_funcs vop_crtc_funcs = {
1032         .set_config = drm_crtc_helper_set_config,
1033         .page_flip = vop_crtc_page_flip,
1034         .destroy = vop_crtc_destroy,
1035 };
1036
1037 static bool vop_win_state_is_active(struct vop_win *vop_win,
1038                                     struct vop_win_state *state)
1039 {
1040         bool active = false;
1041
1042         if (state->fb) {
1043                 dma_addr_t yrgb_mst;
1044
1045                 /* check yrgb_mst to tell if pending_fb is now front */
1046                 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1047
1048                 active = (yrgb_mst == state->yrgb_mst);
1049         } else {
1050                 bool enabled;
1051
1052                 /* if enable bit is clear, plane is now disabled */
1053                 enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable);
1054
1055                 active = (enabled == 0);
1056         }
1057
1058         return active;
1059 }
1060
1061 static void vop_win_state_destroy(struct vop_win_state *state)
1062 {
1063         struct drm_framebuffer *fb = state->fb;
1064
1065         if (fb)
1066                 drm_framebuffer_unreference(fb);
1067
1068         kfree(state);
1069 }
1070
1071 static void vop_win_update_state(struct vop_win *vop_win)
1072 {
1073         struct vop_win_state *state, *n, *new_active = NULL;
1074
1075         /* Check if any pending states are now active */
1076         list_for_each_entry(state, &vop_win->pending, head)
1077                 if (vop_win_state_is_active(vop_win, state)) {
1078                         new_active = state;
1079                         break;
1080                 }
1081
1082         if (!new_active)
1083                 return;
1084
1085         /*
1086          * Destroy any 'skipped' pending states - states that were queued
1087          * before the newly active state.
1088          */
1089         list_for_each_entry_safe(state, n, &vop_win->pending, head) {
1090                 if (state == new_active)
1091                         break;
1092                 vop_win_state_complete(vop_win, state);
1093                 vop_win_state_destroy(state);
1094         }
1095
1096         vop_win_state_complete(vop_win, new_active);
1097
1098         if (vop_win->active)
1099                 vop_win_state_destroy(vop_win->active);
1100         vop_win->active = new_active;
1101 }
1102
1103 static bool vop_win_has_pending_state(struct vop_win *vop_win)
1104 {
1105         return !list_empty(&vop_win->pending);
1106 }
1107
1108 static irqreturn_t vop_isr_thread(int irq, void *data)
1109 {
1110         struct vop *vop = data;
1111         const struct vop_data *vop_data = vop->data;
1112         unsigned int i;
1113
1114         mutex_lock(&vop->vsync_mutex);
1115
1116         if (!vop->vsync_work_pending)
1117                 goto done;
1118
1119         vop->vsync_work_pending = false;
1120
1121         for (i = 0; i < vop_data->win_size; i++) {
1122                 struct vop_win *vop_win = &vop->win[i];
1123
1124                 vop_win_update_state(vop_win);
1125                 if (vop_win_has_pending_state(vop_win))
1126                         vop->vsync_work_pending = true;
1127         }
1128
1129 done:
1130         mutex_unlock(&vop->vsync_mutex);
1131
1132         return IRQ_HANDLED;
1133 }
1134
1135 static irqreturn_t vop_isr(int irq, void *data)
1136 {
1137         struct vop *vop = data;
1138         uint32_t intr0_reg, active_irqs;
1139         unsigned long flags;
1140         int ret = IRQ_NONE;
1141
1142         /*
1143          * INTR_CTRL0 register has interrupt status, enable and clear bits, we
1144          * must hold irq_lock to avoid a race with enable/disable_vblank().
1145         */
1146         spin_lock_irqsave(&vop->irq_lock, flags);
1147         intr0_reg = vop_readl(vop, INTR_CTRL0);
1148         active_irqs = intr0_reg & INTR_MASK;
1149         /* Clear all active interrupt sources */
1150         if (active_irqs)
1151                 vop_writel(vop, INTR_CTRL0,
1152                            intr0_reg | (active_irqs << INTR_CLR_SHIFT));
1153         spin_unlock_irqrestore(&vop->irq_lock, flags);
1154
1155         /* This is expected for vop iommu irqs, since the irq is shared */
1156         if (!active_irqs)
1157                 return IRQ_NONE;
1158
1159         if (active_irqs & DSP_HOLD_VALID_INTR) {
1160                 complete(&vop->dsp_hold_completion);
1161                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1162                 ret = IRQ_HANDLED;
1163         }
1164
1165         if (active_irqs & FS_INTR) {
1166                 drm_handle_vblank(vop->drm_dev, vop->pipe);
1167                 active_irqs &= ~FS_INTR;
1168                 ret = (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
1169         }
1170
1171         /* Unhandled irqs are spurious. */
1172         if (active_irqs)
1173                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1174
1175         return ret;
1176 }
1177
1178 static int vop_create_crtc(struct vop *vop)
1179 {
1180         const struct vop_data *vop_data = vop->data;
1181         struct device *dev = vop->dev;
1182         struct drm_device *drm_dev = vop->drm_dev;
1183         struct drm_plane *primary = NULL, *cursor = NULL, *plane;
1184         struct drm_crtc *crtc = &vop->crtc;
1185         struct device_node *port;
1186         int ret;
1187         int i;
1188
1189         /*
1190          * Create drm_plane for primary and cursor planes first, since we need
1191          * to pass them to drm_crtc_init_with_planes, which sets the
1192          * "possible_crtcs" to the newly initialized crtc.
1193          */
1194         for (i = 0; i < vop_data->win_size; i++) {
1195                 struct vop_win *vop_win = &vop->win[i];
1196                 const struct vop_win_data *win_data = vop_win->data;
1197
1198                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1199                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1200                         continue;
1201
1202                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1203                                                0, &vop_plane_funcs,
1204                                                win_data->phy->data_formats,
1205                                                win_data->phy->nformats,
1206                                                win_data->type);
1207                 if (ret) {
1208                         DRM_ERROR("failed to initialize plane\n");
1209                         goto err_cleanup_planes;
1210                 }
1211
1212                 plane = &vop_win->base;
1213                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1214                         primary = plane;
1215                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1216                         cursor = plane;
1217         }
1218
1219         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1220                                         &vop_crtc_funcs);
1221         if (ret)
1222                 return ret;
1223
1224         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1225
1226         /*
1227          * Create drm_planes for overlay windows with possible_crtcs restricted
1228          * to the newly created crtc.
1229          */
1230         for (i = 0; i < vop_data->win_size; i++) {
1231                 struct vop_win *vop_win = &vop->win[i];
1232                 const struct vop_win_data *win_data = vop_win->data;
1233                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1234
1235                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1236                         continue;
1237
1238                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1239                                                possible_crtcs,
1240                                                &vop_plane_funcs,
1241                                                win_data->phy->data_formats,
1242                                                win_data->phy->nformats,
1243                                                win_data->type);
1244                 if (ret) {
1245                         DRM_ERROR("failed to initialize overlay plane\n");
1246                         goto err_cleanup_crtc;
1247                 }
1248         }
1249
1250         port = of_get_child_by_name(dev->of_node, "port");
1251         if (!port) {
1252                 DRM_ERROR("no port node found in %s\n",
1253                           dev->of_node->full_name);
1254                 goto err_cleanup_crtc;
1255         }
1256
1257         init_completion(&vop->dsp_hold_completion);
1258         crtc->port = port;
1259         vop->pipe = drm_crtc_index(crtc);
1260         rockchip_register_crtc_funcs(drm_dev, &private_crtc_funcs, vop->pipe);
1261
1262         return 0;
1263
1264 err_cleanup_crtc:
1265         drm_crtc_cleanup(crtc);
1266 err_cleanup_planes:
1267         list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
1268                 drm_plane_cleanup(plane);
1269         return ret;
1270 }
1271
1272 static void vop_destroy_crtc(struct vop *vop)
1273 {
1274         struct drm_crtc *crtc = &vop->crtc;
1275
1276         rockchip_unregister_crtc_funcs(vop->drm_dev, vop->pipe);
1277         of_node_put(crtc->port);
1278         drm_crtc_cleanup(crtc);
1279 }
1280
1281 static int vop_initial(struct vop *vop)
1282 {
1283         const struct vop_data *vop_data = vop->data;
1284         const struct vop_reg_data *init_table = vop_data->init_table;
1285         struct reset_control *ahb_rst;
1286         int i, ret;
1287
1288         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1289         if (IS_ERR(vop->hclk)) {
1290                 dev_err(vop->dev, "failed to get hclk source\n");
1291                 return PTR_ERR(vop->hclk);
1292         }
1293         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1294         if (IS_ERR(vop->aclk)) {
1295                 dev_err(vop->dev, "failed to get aclk source\n");
1296                 return PTR_ERR(vop->aclk);
1297         }
1298         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1299         if (IS_ERR(vop->dclk)) {
1300                 dev_err(vop->dev, "failed to get dclk source\n");
1301                 return PTR_ERR(vop->dclk);
1302         }
1303
1304         ret = clk_prepare(vop->hclk);
1305         if (ret < 0) {
1306                 dev_err(vop->dev, "failed to prepare hclk\n");
1307                 return ret;
1308         }
1309
1310         ret = clk_prepare(vop->dclk);
1311         if (ret < 0) {
1312                 dev_err(vop->dev, "failed to prepare dclk\n");
1313                 goto err_unprepare_hclk;
1314         }
1315
1316         ret = clk_prepare(vop->aclk);
1317         if (ret < 0) {
1318                 dev_err(vop->dev, "failed to prepare aclk\n");
1319                 goto err_unprepare_dclk;
1320         }
1321
1322         /*
1323          * enable hclk, so that we can config vop register.
1324          */
1325         ret = clk_enable(vop->hclk);
1326         if (ret < 0) {
1327                 dev_err(vop->dev, "failed to prepare aclk\n");
1328                 goto err_unprepare_aclk;
1329         }
1330         /*
1331          * do hclk_reset, reset all vop registers.
1332          */
1333         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1334         if (IS_ERR(ahb_rst)) {
1335                 dev_err(vop->dev, "failed to get ahb reset\n");
1336                 ret = PTR_ERR(ahb_rst);
1337                 goto err_disable_hclk;
1338         }
1339         reset_control_assert(ahb_rst);
1340         usleep_range(10, 20);
1341         reset_control_deassert(ahb_rst);
1342
1343         memcpy(vop->regsbak, vop->regs, vop->len);
1344
1345         for (i = 0; i < vop_data->table_size; i++)
1346                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1347
1348         for (i = 0; i < vop_data->win_size; i++) {
1349                 const struct vop_win_data *win = &vop_data->win[i];
1350
1351                 VOP_WIN_SET(vop, win, enable, 0);
1352         }
1353
1354         vop_cfg_done(vop);
1355
1356         /*
1357          * do dclk_reset, let all config take affect.
1358          */
1359         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1360         if (IS_ERR(vop->dclk_rst)) {
1361                 dev_err(vop->dev, "failed to get dclk reset\n");
1362                 ret = PTR_ERR(vop->dclk_rst);
1363                 goto err_unprepare_aclk;
1364         }
1365         reset_control_assert(vop->dclk_rst);
1366         usleep_range(10, 20);
1367         reset_control_deassert(vop->dclk_rst);
1368
1369         clk_disable(vop->hclk);
1370
1371         vop->is_enabled = false;
1372
1373         return 0;
1374
1375 err_disable_hclk:
1376         clk_disable(vop->hclk);
1377 err_unprepare_aclk:
1378         clk_unprepare(vop->aclk);
1379 err_unprepare_dclk:
1380         clk_unprepare(vop->dclk);
1381 err_unprepare_hclk:
1382         clk_unprepare(vop->hclk);
1383         return ret;
1384 }
1385
1386 /*
1387  * Initialize the vop->win array elements.
1388  */
1389 static void vop_win_init(struct vop *vop)
1390 {
1391         const struct vop_data *vop_data = vop->data;
1392         unsigned int i;
1393
1394         for (i = 0; i < vop_data->win_size; i++) {
1395                 struct vop_win *vop_win = &vop->win[i];
1396                 const struct vop_win_data *win_data = &vop_data->win[i];
1397
1398                 vop_win->data = win_data;
1399                 vop_win->vop = vop;
1400                 INIT_LIST_HEAD(&vop_win->pending);
1401         }
1402 }
1403
1404 static int vop_bind(struct device *dev, struct device *master, void *data)
1405 {
1406         struct platform_device *pdev = to_platform_device(dev);
1407         const struct of_device_id *of_id;
1408         const struct vop_data *vop_data;
1409         struct drm_device *drm_dev = data;
1410         struct vop *vop;
1411         struct resource *res;
1412         size_t alloc_size;
1413         int ret, irq;
1414
1415         of_id = of_match_device(vop_driver_dt_match, dev);
1416         vop_data = of_id->data;
1417         if (!vop_data)
1418                 return -ENODEV;
1419
1420         /* Allocate vop struct and its vop_win array */
1421         alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1422         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1423         if (!vop)
1424                 return -ENOMEM;
1425
1426         vop->dev = dev;
1427         vop->data = vop_data;
1428         vop->drm_dev = drm_dev;
1429         dev_set_drvdata(dev, vop);
1430
1431         vop_win_init(vop);
1432
1433         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1434         vop->len = resource_size(res);
1435         vop->regs = devm_ioremap_resource(dev, res);
1436         if (IS_ERR(vop->regs))
1437                 return PTR_ERR(vop->regs);
1438
1439         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1440         if (!vop->regsbak)
1441                 return -ENOMEM;
1442
1443         ret = vop_initial(vop);
1444         if (ret < 0) {
1445                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1446                 return ret;
1447         }
1448
1449         irq = platform_get_irq(pdev, 0);
1450         if (irq < 0) {
1451                 dev_err(dev, "cannot find irq for vop\n");
1452                 return irq;
1453         }
1454         vop->irq = (unsigned int)irq;
1455
1456         spin_lock_init(&vop->reg_lock);
1457         spin_lock_init(&vop->irq_lock);
1458
1459         mutex_init(&vop->vsync_mutex);
1460
1461         ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread,
1462                                         IRQF_SHARED, dev_name(dev), vop);
1463         if (ret)
1464                 return ret;
1465
1466         /* IRQ is initially disabled; it gets enabled in power_on */
1467         disable_irq(vop->irq);
1468
1469         ret = vop_create_crtc(vop);
1470         if (ret)
1471                 return ret;
1472
1473         pm_runtime_enable(&pdev->dev);
1474         return 0;
1475 }
1476
1477 static void vop_unbind(struct device *dev, struct device *master, void *data)
1478 {
1479         struct vop *vop = dev_get_drvdata(dev);
1480
1481         pm_runtime_disable(dev);
1482         vop_destroy_crtc(vop);
1483 }
1484
1485 static const struct component_ops vop_component_ops = {
1486         .bind = vop_bind,
1487         .unbind = vop_unbind,
1488 };
1489
1490 static int vop_probe(struct platform_device *pdev)
1491 {
1492         struct device *dev = &pdev->dev;
1493
1494         if (!dev->of_node) {
1495                 dev_err(dev, "can't find vop devices\n");
1496                 return -ENODEV;
1497         }
1498
1499         return component_add(dev, &vop_component_ops);
1500 }
1501
1502 static int vop_remove(struct platform_device *pdev)
1503 {
1504         component_del(&pdev->dev, &vop_component_ops);
1505
1506         return 0;
1507 }
1508
1509 struct platform_driver vop_platform_driver = {
1510         .probe = vop_probe,
1511         .remove = vop_remove,
1512         .driver = {
1513                 .name = "rockchip-vop",
1514                 .owner = THIS_MODULE,
1515                 .of_match_table = of_match_ptr(vop_driver_dt_match),
1516         },
1517 };
1518
1519 module_platform_driver(vop_platform_driver);
1520
1521 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1522 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1523 MODULE_LICENSE("GPL v2");