drivers/i2c/busses/i2c-designware-master.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Synopsys DesignWare I2C adapter driver (master only).
   4  *
   5  * Based on the TI DAVINCI I2C adapter driver.
   6  *
   7  * Copyright (C) 2006 Texas Instruments.
   8  * Copyright (C) 2007 MontaVista Software Inc.
   9  * Copyright (C) 2009 Provigent Ltd.
  10  */
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/export.h>
  15 #include <linux/gpio/consumer.h>
  16 #include <linux/i2c.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/pinctrl/consumer.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset.h>
  24
  25 #include "i2c-designware-core.h"
  26
  27 #define AMD_TIMEOUT_MIN_US      25
  28 #define AMD_TIMEOUT_MAX_US      250
  29 #define AMD_MASTERCFG_MASK      GENMASK(15, 0)
  30
  31 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
  32 {
  33         /* Configure Tx/Rx FIFO threshold levels */
  34         regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
  35         regmap_write(dev->map, DW_IC_RX_TL, 0);
  36
  37         /* Configure the I2C master */
  38         regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
  39 }
  40
  41 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
  42 {
  43         unsigned int comp_param1;
  44         u32 sda_falling_time, scl_falling_time;
  45         struct i2c_timings *t = &dev->timings;
  46         const char *fp_str = "";
  47         u32 ic_clk;
  48         int ret;
  49
  50         ret = i2c_dw_acquire_lock(dev);
  51         if (ret)
  52                 return ret;
  53
  54         ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
  55         i2c_dw_release_lock(dev);
  56         if (ret)
  57                 return ret;
  58
  59         /* Set standard and fast speed dividers for high/low periods */
  60         sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
  61         scl_falling_time = t->scl_fall_ns ?: 300; /* ns */
  62
  63         /* Calculate SCL timing parameters for standard mode if not set */
  64         if (!dev->ss_hcnt || !dev->ss_lcnt) {
  65                 ic_clk = i2c_dw_clk_rate(dev);
  66                 dev->ss_hcnt =
  67                         i2c_dw_scl_hcnt(ic_clk,
  68                                         4000,   /* tHD;STA = tHIGH = 4.0 us */
  69                                         sda_falling_time,
  70                                         0,      /* 0: DW default, 1: Ideal */
  71                                         0);     /* No offset */
  72                 dev->ss_lcnt =
  73                         i2c_dw_scl_lcnt(ic_clk,
  74                                         4700,   /* tLOW = 4.7 us */
  75                                         scl_falling_time,
  76                                         0);     /* No offset */
  77         }
  78         dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
  79                 dev->ss_hcnt, dev->ss_lcnt);
  80
  81         /*
  82          * Set SCL timing parameters for fast mode or fast mode plus. Only
  83          * difference is the timing parameter values since the registers are
  84          * the same.
  85          */
  86         if (t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) {
  87                 /*
  88                  * Check are Fast Mode Plus parameters available. Calculate
  89                  * SCL timing parameters for Fast Mode Plus if not set.
  90                  */
  91                 if (dev->fp_hcnt && dev->fp_lcnt) {
  92                         dev->fs_hcnt = dev->fp_hcnt;
  93                         dev->fs_lcnt = dev->fp_lcnt;
  94                 } else {
  95                         ic_clk = i2c_dw_clk_rate(dev);
  96                         dev->fs_hcnt =
  97                                 i2c_dw_scl_hcnt(ic_clk,
  98                                                 260,    /* tHIGH = 260 ns */
  99                                                 sda_falling_time,
 100                                                 0,      /* DW default */
 101                                                 0);     /* No offset */
 102                         dev->fs_lcnt =
 103                                 i2c_dw_scl_lcnt(ic_clk,
 104                                                 500,    /* tLOW = 500 ns */
 105                                                 scl_falling_time,
 106                                                 0);     /* No offset */
 107                 }
 108                 fp_str = " Plus";
 109         }
 110         /*
 111          * Calculate SCL timing parameters for fast mode if not set. They are
 112          * needed also in high speed mode.
 113          */
 114         if (!dev->fs_hcnt || !dev->fs_lcnt) {
 115                 ic_clk = i2c_dw_clk_rate(dev);
 116                 dev->fs_hcnt =
 117                         i2c_dw_scl_hcnt(ic_clk,
 118                                         600,    /* tHD;STA = tHIGH = 0.6 us */
 119                                         sda_falling_time,
 120                                         0,      /* 0: DW default, 1: Ideal */
 121                                         0);     /* No offset */
 122                 dev->fs_lcnt =
 123                         i2c_dw_scl_lcnt(ic_clk,
 124                                         1300,   /* tLOW = 1.3 us */
 125                                         scl_falling_time,
 126                                         0);     /* No offset */
 127         }
 128         dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
 129                 fp_str, dev->fs_hcnt, dev->fs_lcnt);
 130
 131         /* Check is high speed possible and fall back to fast mode if not */
 132         if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
 133                 DW_IC_CON_SPEED_HIGH) {
 134                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 135                         != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
 136                         dev_err(dev->dev, "High Speed not supported!\n");
 137                         t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
 138                         dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
 139                         dev->master_cfg |= DW_IC_CON_SPEED_FAST;
 140                         dev->hs_hcnt = 0;
 141                         dev->hs_lcnt = 0;
 142                 } else if (!dev->hs_hcnt || !dev->hs_lcnt) {
 143                         ic_clk = i2c_dw_clk_rate(dev);
 144                         dev->hs_hcnt =
 145                                 i2c_dw_scl_hcnt(ic_clk,
 146                                                 160,    /* tHIGH = 160 ns */
 147                                                 sda_falling_time,
 148                                                 0,      /* DW default */
 149                                                 0);     /* No offset */
 150                         dev->hs_lcnt =
 151                                 i2c_dw_scl_lcnt(ic_clk,
 152                                                 320,    /* tLOW = 320 ns */
 153                                                 scl_falling_time,
 154                                                 0);     /* No offset */
 155                 }
 156                 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
 157                         dev->hs_hcnt, dev->hs_lcnt);
 158         }
 159
 160         ret = i2c_dw_set_sda_hold(dev);
 161         if (ret)
 162                 return ret;
 163
 164         dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz));
 165         return 0;
 166 }
 167
 168 /**
 169  * i2c_dw_init_master() - Initialize the designware I2C master hardware
 170  * @dev: device private data
 171  *
 172  * This functions configures and enables the I2C master.
 173  * This function is called during I2C init function, and in case of timeout at
 174  * run time.
 175  */
 176 static int i2c_dw_init_master(struct dw_i2c_dev *dev)
 177 {
 178         int ret;
 179
 180         ret = i2c_dw_acquire_lock(dev);
 181         if (ret)
 182                 return ret;
 183
 184         /* Disable the adapter */
 185         __i2c_dw_disable(dev);
 186
 187         /* Write standard speed timing parameters */
 188         regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
 189         regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
 190
 191         /* Write fast mode/fast mode plus timing parameters */
 192         regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
 193         regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
 194
 195         /* Write high speed timing parameters if supported */
 196         if (dev->hs_hcnt && dev->hs_lcnt) {
 197                 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
 198                 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
 199         }
 200
 201         /* Write SDA hold time if supported */
 202         if (dev->sda_hold_time)
 203                 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
 204
 205         i2c_dw_configure_fifo_master(dev);
 206         i2c_dw_release_lock(dev);
 207
 208         return 0;
 209 }
 210
 211 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 212 {
 213         struct i2c_msg *msgs = dev->msgs;
 214         u32 ic_con = 0, ic_tar = 0;
 215         unsigned int dummy;
 216
 217         /* Disable the adapter */
 218         __i2c_dw_disable(dev);
 219
 220         /* If the slave address is ten bit address, enable 10BITADDR */
 221         if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
 222                 ic_con = DW_IC_CON_10BITADDR_MASTER;
 223                 /*
 224                  * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
 225                  * mode has to be enabled via bit 12 of IC_TAR register.
 226                  * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
 227                  * detected from registers.
 228                  */
 229                 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
 230         }
 231
 232         regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
 233                            ic_con);
 234
 235         /*
 236          * Set the slave (target) address and enable 10-bit addressing mode
 237          * if applicable.
 238          */
 239         regmap_write(dev->map, DW_IC_TAR,
 240                      msgs[dev->msg_write_idx].addr | ic_tar);
 241
 242         /* Enforce disabled interrupts (due to HW issues) */
 243         regmap_write(dev->map, DW_IC_INTR_MASK, 0);
 244
 245         /* Enable the adapter */
 246         __i2c_dw_enable(dev);
 247
 248         /* Dummy read to avoid the register getting stuck on Bay Trail */
 249         regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
 250
 251         /* Clear and enable interrupts */
 252         regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
 253         regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
 254 }
 255
 256 static int i2c_dw_check_stopbit(struct dw_i2c_dev *dev)
 257 {
 258         u32 val;
 259         int ret;
 260
 261         ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val,
 262                                        !(val & DW_IC_INTR_STOP_DET),
 263                                         1100, 20000);
 264         if (ret)
 265                 dev_err(dev->dev, "i2c timeout error %d\n", ret);
 266
 267         return ret;
 268 }
 269
 270 static int i2c_dw_status(struct dw_i2c_dev *dev)
 271 {
 272         int status;
 273
 274         status = i2c_dw_wait_bus_not_busy(dev);
 275         if (status)
 276                 return status;
 277
 278         return i2c_dw_check_stopbit(dev);
 279 }
 280
 281 /*
 282  * Initiate and continue master read/write transaction with polling
 283  * based transfer routine afterward write messages into the Tx buffer.
 284  */
 285 static int amd_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs)
 286 {
 287         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 288         int msg_wrt_idx, msg_itr_lmt, buf_len, data_idx;
 289         int cmd = 0, status;
 290         u8 *tx_buf;
 291         unsigned int val;
 292
 293         /*
 294          * In order to enable the interrupt for UCSI i.e. AMD NAVI GPU card,
 295          * it is mandatory to set the right value in specific register
 296          * (offset:0x474) as per the hardware IP specification.
 297          */
 298         regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN);
 299
 300         dev->msgs = msgs;
 301         dev->msgs_num = num_msgs;
 302         i2c_dw_xfer_init(dev);
 303         regmap_write(dev->map, DW_IC_INTR_MASK, 0);
 304
 305         /* Initiate messages read/write transaction */
 306         for (msg_wrt_idx = 0; msg_wrt_idx < num_msgs; msg_wrt_idx++) {
 307                 tx_buf = msgs[msg_wrt_idx].buf;
 308                 buf_len = msgs[msg_wrt_idx].len;
 309
 310                 if (!(msgs[msg_wrt_idx].flags & I2C_M_RD))
 311                         regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1);
 312                 /*
 313                  * Initiate the i2c read/write transaction of buffer length,
 314                  * and poll for bus busy status. For the last message transfer,
 315                  * update the command with stopbit enable.
 316                  */
 317                 for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) {
 318                         if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1)
 319                                 cmd |= BIT(9);
 320
 321                         if (msgs[msg_wrt_idx].flags & I2C_M_RD) {
 322                                 /* Due to hardware bug, need to write the same command twice. */
 323                                 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100);
 324                                 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd);
 325                                 if (cmd) {
 326                                         regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1));
 327                                         regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1));
 328                                         /*
 329                                          * Need to check the stop bit. However, it cannot be
 330                                          * detected from the registers so we check it always
 331                                          * when read/write the last byte.
 332                                          */
 333                                         status = i2c_dw_status(dev);
 334                                         if (status)
 335                                                 return status;
 336
 337                                         for (data_idx = 0; data_idx < buf_len; data_idx++) {
 338                                                 regmap_read(dev->map, DW_IC_DATA_CMD, &val);
 339                                                 tx_buf[data_idx] = val;
 340                                         }
 341                                         status = i2c_dw_check_stopbit(dev);
 342                                         if (status)
 343                                                 return status;
 344                                 }
 345                         } else {
 346                                 regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd);
 347                                 usleep_range(AMD_TIMEOUT_MIN_US, AMD_TIMEOUT_MAX_US);
 348                         }
 349                 }
 350                 status = i2c_dw_check_stopbit(dev);
 351                 if (status)
 352                         return status;
 353         }
 354
 355         return 0;
 356 }
 357
 358 static int i2c_dw_poll_tx_empty(struct dw_i2c_dev *dev)
 359 {
 360         u32 val;
 361
 362         return regmap_read_poll_timeout(dev->map, DW_IC_RAW_INTR_STAT, val,
 363                                         val & DW_IC_INTR_TX_EMPTY,
 364                                         100, 1000);
 365 }
 366
 367 static int i2c_dw_poll_rx_full(struct dw_i2c_dev *dev)
 368 {
 369         u32 val;
 370
 371         return regmap_read_poll_timeout(dev->map, DW_IC_RAW_INTR_STAT, val,
 372                                         val & DW_IC_INTR_RX_FULL,
 373                                         100, 1000);
 374 }
 375
 376 static int txgbe_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs,
 377                                    int num_msgs)
 378 {
 379         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 380         int msg_idx, buf_len, data_idx, ret;
 381         unsigned int val, stop = 0;
 382         u8 *buf;
 383
 384         dev->msgs = msgs;
 385         dev->msgs_num = num_msgs;
 386         i2c_dw_xfer_init(dev);
 387         regmap_write(dev->map, DW_IC_INTR_MASK, 0);
 388
 389         for (msg_idx = 0; msg_idx < num_msgs; msg_idx++) {
 390                 buf = msgs[msg_idx].buf;
 391                 buf_len = msgs[msg_idx].len;
 392
 393                 for (data_idx = 0; data_idx < buf_len; data_idx++) {
 394                         if (msg_idx == num_msgs - 1 && data_idx == buf_len - 1)
 395                                 stop |= BIT(9);
 396
 397                         if (msgs[msg_idx].flags & I2C_M_RD) {
 398                                 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | stop);
 399
 400                                 ret = i2c_dw_poll_rx_full(dev);
 401                                 if (ret)
 402                                         return ret;
 403
 404                                 regmap_read(dev->map, DW_IC_DATA_CMD, &val);
 405                                 buf[data_idx] = val;
 406                         } else {
 407                                 ret = i2c_dw_poll_tx_empty(dev);
 408                                 if (ret)
 409                                         return ret;
 410
 411                                 regmap_write(dev->map, DW_IC_DATA_CMD,
 412                                              buf[data_idx] | stop);
 413                         }
 414                 }
 415         }
 416
 417         return num_msgs;
 418 }
 419
 420 /*
 421  * Initiate (and continue) low level master read/write transaction.
 422  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 423  * messages into the tx buffer.  Even if the size of i2c_msg data is
 424  * longer than the size of the tx buffer, it handles everything.
 425  */
 426 static void
 427 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 428 {
 429         struct i2c_msg *msgs = dev->msgs;
 430         u32 intr_mask;
 431         int tx_limit, rx_limit;
 432         u32 addr = msgs[dev->msg_write_idx].addr;
 433         u32 buf_len = dev->tx_buf_len;
 434         u8 *buf = dev->tx_buf;
 435         bool need_restart = false;
 436         unsigned int flr;
 437
 438         intr_mask = DW_IC_INTR_MASTER_MASK;
 439
 440         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 441                 u32 flags = msgs[dev->msg_write_idx].flags;
 442
 443                 /*
 444                  * If target address has changed, we need to
 445                  * reprogram the target address in the I2C
 446                  * adapter when we are done with this transfer.
 447                  */
 448                 if (msgs[dev->msg_write_idx].addr != addr) {
 449                         dev_err(dev->dev,
 450                                 "%s: invalid target address\n", __func__);
 451                         dev->msg_err = -EINVAL;
 452                         break;
 453                 }
 454
 455                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 456                         /* new i2c_msg */
 457                         buf = msgs[dev->msg_write_idx].buf;
 458                         buf_len = msgs[dev->msg_write_idx].len;
 459
 460                         /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
 461                          * IC_RESTART_EN are set, we must manually
 462                          * set restart bit between messages.
 463                          */
 464                         if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
 465                                         (dev->msg_write_idx > 0))
 466                                 need_restart = true;
 467                 }
 468
 469                 regmap_read(dev->map, DW_IC_TXFLR, &flr);
 470                 tx_limit = dev->tx_fifo_depth - flr;
 471
 472                 regmap_read(dev->map, DW_IC_RXFLR, &flr);
 473                 rx_limit = dev->rx_fifo_depth - flr;
 474
 475                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 476                         u32 cmd = 0;
 477
 478                         /*
 479                          * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
 480                          * manually set the stop bit. However, it cannot be
 481                          * detected from the registers so we set it always
 482                          * when writing/reading the last byte.
 483                          */
 484
 485                         /*
 486                          * i2c-core always sets the buffer length of
 487                          * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
 488                          * be adjusted when receiving the first byte.
 489                          * Thus we can't stop the transaction here.
 490                          */
 491                         if (dev->msg_write_idx == dev->msgs_num - 1 &&
 492                             buf_len == 1 && !(flags & I2C_M_RECV_LEN))
 493                                 cmd |= BIT(9);
 494
 495                         if (need_restart) {
 496                                 cmd |= BIT(10);
 497                                 need_restart = false;
 498                         }
 499
 500                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 501
 502                                 /* Avoid rx buffer overrun */
 503                                 if (dev->rx_outstanding >= dev->rx_fifo_depth)
 504                                         break;
 505
 506                                 regmap_write(dev->map, DW_IC_DATA_CMD,
 507                                              cmd | 0x100);
 508                                 rx_limit--;
 509                                 dev->rx_outstanding++;
 510                         } else {
 511                                 regmap_write(dev->map, DW_IC_DATA_CMD,
 512                                              cmd | *buf++);
 513                         }
 514                         tx_limit--; buf_len--;
 515                 }
 516
 517                 dev->tx_buf = buf;
 518                 dev->tx_buf_len = buf_len;
 519
 520                 /*
 521                  * Because we don't know the buffer length in the
 522                  * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
 523                  * the transaction here.
 524                  */
 525                 if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
 526                         /* more bytes to be written */
 527                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 528                         break;
 529                 } else
 530                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 531         }
 532
 533         /*
 534          * If i2c_msg index search is completed, we don't need TX_EMPTY
 535          * interrupt any more.
 536          */
 537         if (dev->msg_write_idx == dev->msgs_num)
 538                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 539
 540         if (dev->msg_err)
 541                 intr_mask = 0;
 542
 543         regmap_write(dev->map,  DW_IC_INTR_MASK, intr_mask);
 544 }
 545
 546 static u8
 547 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
 548 {
 549         struct i2c_msg *msgs = dev->msgs;
 550         u32 flags = msgs[dev->msg_read_idx].flags;
 551
 552         /*
 553          * Adjust the buffer length and mask the flag
 554          * after receiving the first byte.
 555          */
 556         len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
 557         dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
 558         msgs[dev->msg_read_idx].len = len;
 559         msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
 560
 561         return len;
 562 }
 563
 564 static void
 565 i2c_dw_read(struct dw_i2c_dev *dev)
 566 {
 567         struct i2c_msg *msgs = dev->msgs;
 568         unsigned int rx_valid;
 569
 570         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 571                 unsigned int tmp;
 572                 u32 len;
 573                 u8 *buf;
 574
 575                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 576                         continue;
 577
 578                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 579                         len = msgs[dev->msg_read_idx].len;
 580                         buf = msgs[dev->msg_read_idx].buf;
 581                 } else {
 582                         len = dev->rx_buf_len;
 583                         buf = dev->rx_buf;
 584                 }
 585
 586                 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
 587
 588                 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
 589                         u32 flags = msgs[dev->msg_read_idx].flags;
 590
 591                         regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
 592                         tmp &= DW_IC_DATA_CMD_DAT;
 593                         /* Ensure length byte is a valid value */
 594                         if (flags & I2C_M_RECV_LEN) {
 595                                 /*
 596                                  * if IC_EMPTYFIFO_HOLD_MASTER_EN is set, which cannot be
 597                                  * detected from the registers, the controller can be
 598                                  * disabled if the STOP bit is set. But it is only set
 599                                  * after receiving block data response length in
 600                                  * I2C_FUNC_SMBUS_BLOCK_DATA case. That needs to read
 601                                  * another byte with STOP bit set when the block data
 602                                  * response length is invalid to complete the transaction.
 603                                  */
 604                                 if (!tmp || tmp > I2C_SMBUS_BLOCK_MAX)
 605                                         tmp = 1;
 606
 607                                 len = i2c_dw_recv_len(dev, tmp);
 608                         }
 609                         *buf++ = tmp;
 610                         dev->rx_outstanding--;
 611                 }
 612
 613                 if (len > 0) {
 614                         dev->status |= STATUS_READ_IN_PROGRESS;
 615                         dev->rx_buf_len = len;
 616                         dev->rx_buf = buf;
 617                         return;
 618                 } else
 619                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 620         }
 621 }
 622
 623 /*
 624  * Prepare controller for a transaction and call i2c_dw_xfer_msg.
 625  */
 626 static int
 627 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 628 {
 629         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 630         int ret;
 631
 632         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 633
 634         pm_runtime_get_sync(dev->dev);
 635
 636         /*
 637          * Initiate I2C message transfer when polling mode is enabled,
 638          * As it is polling based transfer mechanism, which does not support
 639          * interrupt based functionalities of existing DesignWare driver.
 640          */
 641         switch (dev->flags & MODEL_MASK) {
 642         case MODEL_AMD_NAVI_GPU:
 643                 ret = amd_i2c_dw_xfer_quirk(adap, msgs, num);
 644                 goto done_nolock;
 645         case MODEL_WANGXUN_SP:
 646                 ret = txgbe_i2c_dw_xfer_quirk(adap, msgs, num);
 647                 goto done_nolock;
 648         default:
 649                 break;
 650         }
 651
 652         reinit_completion(&dev->cmd_complete);
 653         dev->msgs = msgs;
 654         dev->msgs_num = num;
 655         dev->cmd_err = 0;
 656         dev->msg_write_idx = 0;
 657         dev->msg_read_idx = 0;
 658         dev->msg_err = 0;
 659         dev->status = 0;
 660         dev->abort_source = 0;
 661         dev->rx_outstanding = 0;
 662
 663         ret = i2c_dw_acquire_lock(dev);
 664         if (ret)
 665                 goto done_nolock;
 666
 667         ret = i2c_dw_wait_bus_not_busy(dev);
 668         if (ret < 0)
 669                 goto done;
 670
 671         /* Start the transfers */
 672         i2c_dw_xfer_init(dev);
 673
 674         /* Wait for tx to complete */
 675         if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
 676                 dev_err(dev->dev, "controller timed out\n");
 677                 /* i2c_dw_init implicitly disables the adapter */
 678                 i2c_recover_bus(&dev->adapter);
 679                 i2c_dw_init_master(dev);
 680                 ret = -ETIMEDOUT;
 681                 goto done;
 682         }
 683
 684         /*
 685          * We must disable the adapter before returning and signaling the end
 686          * of the current transfer. Otherwise the hardware might continue
 687          * generating interrupts which in turn causes a race condition with
 688          * the following transfer.  Needs some more investigation if the
 689          * additional interrupts are a hardware bug or this driver doesn't
 690          * handle them correctly yet.
 691          */
 692         __i2c_dw_disable_nowait(dev);
 693
 694         if (dev->msg_err) {
 695                 ret = dev->msg_err;
 696                 goto done;
 697         }
 698
 699         /* No error */
 700         if (likely(!dev->cmd_err && !dev->status)) {
 701                 ret = num;
 702                 goto done;
 703         }
 704
 705         /* We have an error */
 706         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 707                 ret = i2c_dw_handle_tx_abort(dev);
 708                 goto done;
 709         }
 710
 711         if (dev->status)
 712                 dev_err(dev->dev,
 713                         "transfer terminated early - interrupt latency too high?\n");
 714
 715         ret = -EIO;
 716
 717 done:
 718         i2c_dw_release_lock(dev);
 719
 720 done_nolock:
 721         pm_runtime_mark_last_busy(dev->dev);
 722         pm_runtime_put_autosuspend(dev->dev);
 723
 724         return ret;
 725 }
 726
 727 static const struct i2c_algorithm i2c_dw_algo = {
 728         .master_xfer = i2c_dw_xfer,
 729         .functionality = i2c_dw_func,
 730 };
 731
 732 static const struct i2c_adapter_quirks i2c_dw_quirks = {
 733         .flags = I2C_AQ_NO_ZERO_LEN,
 734 };
 735
 736 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 737 {
 738         unsigned int stat, dummy;
 739
 740         /*
 741          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 742          * The unmasked raw version of interrupt status bits is available
 743          * in the IC_RAW_INTR_STAT register.
 744          *
 745          * That is,
 746          *   stat = readl(IC_INTR_STAT);
 747          * equals to,
 748          *   stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
 749          *
 750          * The raw version might be useful for debugging purposes.
 751          */
 752         regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
 753
 754         /*
 755          * Do not use the IC_CLR_INTR register to clear interrupts, or
 756          * you'll miss some interrupts, triggered during the period from
 757          * readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
 758          *
 759          * Instead, use the separately-prepared IC_CLR_* registers.
 760          */
 761         if (stat & DW_IC_INTR_RX_UNDER)
 762                 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
 763         if (stat & DW_IC_INTR_RX_OVER)
 764                 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
 765         if (stat & DW_IC_INTR_TX_OVER)
 766                 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
 767         if (stat & DW_IC_INTR_RD_REQ)
 768                 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
 769         if (stat & DW_IC_INTR_TX_ABRT) {
 770                 /*
 771                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 772                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 773                  */
 774                 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
 775                 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
 776         }
 777         if (stat & DW_IC_INTR_RX_DONE)
 778                 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
 779         if (stat & DW_IC_INTR_ACTIVITY)
 780                 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
 781         if ((stat & DW_IC_INTR_STOP_DET) &&
 782             ((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL)))
 783                 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
 784         if (stat & DW_IC_INTR_START_DET)
 785                 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
 786         if (stat & DW_IC_INTR_GEN_CALL)
 787                 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
 788
 789         return stat;
 790 }
 791
 792 /*
 793  * Interrupt service routine. This gets called whenever an I2C master interrupt
 794  * occurs.
 795  */
 796 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 797 {
 798         struct dw_i2c_dev *dev = dev_id;
 799         unsigned int stat, enabled;
 800
 801         regmap_read(dev->map, DW_IC_ENABLE, &enabled);
 802         regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
 803         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 804                 return IRQ_NONE;
 805         if (pm_runtime_suspended(dev->dev) || stat == GENMASK(31, 0))
 806                 return IRQ_NONE;
 807         dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
 808
 809         stat = i2c_dw_read_clear_intrbits(dev);
 810
 811         if (!(dev->status & STATUS_ACTIVE)) {
 812                 /*
 813                  * Unexpected interrupt in driver point of view. State
 814                  * variables are either unset or stale so acknowledge and
 815                  * disable interrupts for suppressing further interrupts if
 816                  * interrupt really came from this HW (E.g. firmware has left
 817                  * the HW active).
 818                  */
 819                 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
 820                 return IRQ_HANDLED;
 821         }
 822
 823         if (stat & DW_IC_INTR_TX_ABRT) {
 824                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 825                 dev->status &= ~STATUS_MASK;
 826                 dev->rx_outstanding = 0;
 827
 828                 /*
 829                  * Anytime TX_ABRT is set, the contents of the tx/rx
 830                  * buffers are flushed. Make sure to skip them.
 831                  */
 832                 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
 833                 goto tx_aborted;
 834         }
 835
 836         if (stat & DW_IC_INTR_RX_FULL)
 837                 i2c_dw_read(dev);
 838
 839         if (stat & DW_IC_INTR_TX_EMPTY)
 840                 i2c_dw_xfer_msg(dev);
 841
 842         /*
 843          * No need to modify or disable the interrupt mask here.
 844          * i2c_dw_xfer_msg() will take care of it according to
 845          * the current transmit status.
 846          */
 847
 848 tx_aborted:
 849         if (((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) &&
 850              (dev->rx_outstanding == 0))
 851                 complete(&dev->cmd_complete);
 852         else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
 853                 /* Workaround to trigger pending interrupt */
 854                 regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
 855                 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
 856                 regmap_write(dev->map, DW_IC_INTR_MASK, stat);
 857         }
 858
 859         return IRQ_HANDLED;
 860 }
 861
 862 void i2c_dw_configure_master(struct dw_i2c_dev *dev)
 863 {
 864         struct i2c_timings *t = &dev->timings;
 865
 866         dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
 867
 868         dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
 869                           DW_IC_CON_RESTART_EN;
 870
 871         dev->mode = DW_IC_MASTER;
 872
 873         switch (t->bus_freq_hz) {
 874         case I2C_MAX_STANDARD_MODE_FREQ:
 875                 dev->master_cfg |= DW_IC_CON_SPEED_STD;
 876                 break;
 877         case I2C_MAX_HIGH_SPEED_MODE_FREQ:
 878                 dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
 879                 break;
 880         default:
 881                 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
 882         }
 883 }
 884 EXPORT_SYMBOL_GPL(i2c_dw_configure_master);
 885
 886 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
 887 {
 888         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 889
 890         i2c_dw_disable(dev);
 891         reset_control_assert(dev->rst);
 892         i2c_dw_prepare_clk(dev, false);
 893 }
 894
 895 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
 896 {
 897         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 898
 899         i2c_dw_prepare_clk(dev, true);
 900         reset_control_deassert(dev->rst);
 901         i2c_dw_init_master(dev);
 902 }
 903
 904 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
 905 {
 906         struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
 907         struct i2c_adapter *adap = &dev->adapter;
 908         struct gpio_desc *gpio;
 909
 910         gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
 911         if (IS_ERR_OR_NULL(gpio))
 912                 return PTR_ERR_OR_ZERO(gpio);
 913
 914         rinfo->scl_gpiod = gpio;
 915
 916         gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
 917         if (IS_ERR(gpio))
 918                 return PTR_ERR(gpio);
 919         rinfo->sda_gpiod = gpio;
 920
 921         rinfo->pinctrl = devm_pinctrl_get(dev->dev);
 922         if (IS_ERR(rinfo->pinctrl)) {
 923                 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER)
 924                         return PTR_ERR(rinfo->pinctrl);
 925
 926                 rinfo->pinctrl = NULL;
 927                 dev_err(dev->dev, "getting pinctrl info failed: bus recovery might not work\n");
 928         } else if (!rinfo->pinctrl) {
 929                 dev_dbg(dev->dev, "pinctrl is disabled, bus recovery might not work\n");
 930         }
 931
 932         rinfo->recover_bus = i2c_generic_scl_recovery;
 933         rinfo->prepare_recovery = i2c_dw_prepare_recovery;
 934         rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
 935         adap->bus_recovery_info = rinfo;
 936
 937         dev_info(dev->dev, "running with gpio recovery mode! scl%s",
 938                  rinfo->sda_gpiod ? ",sda" : "");
 939
 940         return 0;
 941 }
 942
 943 static int i2c_dw_poll_adap_quirk(struct dw_i2c_dev *dev)
 944 {
 945         struct i2c_adapter *adap = &dev->adapter;
 946         int ret;
 947
 948         pm_runtime_get_noresume(dev->dev);
 949         ret = i2c_add_numbered_adapter(adap);
 950         if (ret)
 951                 dev_err(dev->dev, "Failed to add adapter: %d\n", ret);
 952         pm_runtime_put_noidle(dev->dev);
 953
 954         return ret;
 955 }
 956
 957 static bool i2c_dw_is_model_poll(struct dw_i2c_dev *dev)
 958 {
 959         switch (dev->flags & MODEL_MASK) {
 960         case MODEL_AMD_NAVI_GPU:
 961         case MODEL_WANGXUN_SP:
 962                 return true;
 963         default:
 964                 return false;
 965         }
 966 }
 967
 968 int i2c_dw_probe_master(struct dw_i2c_dev *dev)
 969 {
 970         struct i2c_adapter *adap = &dev->adapter;
 971         unsigned long irq_flags;
 972         unsigned int ic_con;
 973         int ret;
 974
 975         init_completion(&dev->cmd_complete);
 976
 977         dev->init = i2c_dw_init_master;
 978         dev->disable = i2c_dw_disable;
 979
 980         ret = i2c_dw_init_regmap(dev);
 981         if (ret)
 982                 return ret;
 983
 984         ret = i2c_dw_set_timings_master(dev);
 985         if (ret)
 986                 return ret;
 987
 988         ret = i2c_dw_set_fifo_size(dev);
 989         if (ret)
 990                 return ret;
 991
 992         /* Lock the bus for accessing DW_IC_CON */
 993         ret = i2c_dw_acquire_lock(dev);
 994         if (ret)
 995                 return ret;
 996
 997         /*
 998          * On AMD platforms BIOS advertises the bus clear feature
 999          * and enables the SCL/SDA stuck low. SMU FW does the
1000          * bus recovery process. Driver should not ignore this BIOS
1001          * advertisement of bus clear feature.
1002          */
1003         ret = regmap_read(dev->map, DW_IC_CON, &ic_con);
1004         i2c_dw_release_lock(dev);
1005         if (ret)
1006                 return ret;
1007
1008         if (ic_con & DW_IC_CON_BUS_CLEAR_CTRL)
1009                 dev->master_cfg |= DW_IC_CON_BUS_CLEAR_CTRL;
1010
1011         ret = dev->init(dev);
1012         if (ret)
1013                 return ret;
1014
1015         snprintf(adap->name, sizeof(adap->name),
1016                  "Synopsys DesignWare I2C adapter");
1017         adap->retries = 3;
1018         adap->algo = &i2c_dw_algo;
1019         adap->quirks = &i2c_dw_quirks;
1020         adap->dev.parent = dev->dev;
1021         i2c_set_adapdata(adap, dev);
1022
1023         if (i2c_dw_is_model_poll(dev))
1024                 return i2c_dw_poll_adap_quirk(dev);
1025
1026         if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
1027                 irq_flags = IRQF_NO_SUSPEND;
1028         } else {
1029                 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
1030         }
1031
1032         ret = i2c_dw_acquire_lock(dev);
1033         if (ret)
1034                 return ret;
1035
1036         regmap_write(dev->map, DW_IC_INTR_MASK, 0);
1037         i2c_dw_release_lock(dev);
1038
1039         ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
1040                                dev_name(dev->dev), dev);
1041         if (ret) {
1042                 dev_err(dev->dev, "failure requesting irq %i: %d\n",
1043                         dev->irq, ret);
1044                 return ret;
1045         }
1046
1047         ret = i2c_dw_init_recovery_info(dev);
1048         if (ret)
1049                 return ret;
1050
1051         /*
1052          * Increment PM usage count during adapter registration in order to
1053          * avoid possible spurious runtime suspend when adapter device is
1054          * registered to the device core and immediate resume in case bus has
1055          * registered I2C slaves that do I2C transfers in their probe.
1056          */
1057         pm_runtime_get_noresume(dev->dev);
1058         ret = i2c_add_numbered_adapter(adap);
1059         if (ret)
1060                 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
1061         pm_runtime_put_noidle(dev->dev);
1062
1063         return ret;
1064 }
1065 EXPORT_SYMBOL_GPL(i2c_dw_probe_master);
1066
1067 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
1068 MODULE_LICENSE("GPL");