drivers/i2c/busses/i2c-i801.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   4     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   5     <mdsxyz123@yahoo.com>
   6     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   7     Copyright (C) 2010         Intel Corporation,
   8                                David Woodhouse <dwmw2@infradead.org>
   9
  10 */
  11
  12 /*
  13  * Supports the following Intel I/O Controller Hubs (ICH):
  14  *
  15  *                                      I/O                     Block   I2C
  16  *                                      region  SMBus   Block   proc.   block
  17  * Chip name                    PCI ID  size    PEC     buffer  call    read
  18  * ---------------------------------------------------------------------------
  19  * 82801AA (ICH)                0x2413  16      no      no      no      no
  20  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  21  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  22  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  23  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  24  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  25  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  26  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  27  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  28  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  29  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  30  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  31  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  32  * ICH10                        0x3a30  32      hard    yes     yes     yes
  33  * ICH10                        0x3a60  32      hard    yes     yes     yes
  34  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  35  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  36  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  37  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  38  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  39  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  40  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  41  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  42  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  43  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  44  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  45  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  46  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  47  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  48  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  49  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  50  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  51  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  52  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  53  * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  54  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  55  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  56  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  57  * Emmitsburg (PCH)             0x1bc9  32      hard    yes     yes     yes
  58  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  59  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  60  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  61  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  62  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  63  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  64  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  65  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  66  * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  67  * Ice Lake-N (PCH)             0x38a3  32      hard    yes     yes     yes
  68  * Comet Lake (PCH)             0x02a3  32      hard    yes     yes     yes
  69  * Comet Lake-H (PCH)           0x06a3  32      hard    yes     yes     yes
  70  * Elkhart Lake (PCH)           0x4b23  32      hard    yes     yes     yes
  71  * Tiger Lake-LP (PCH)          0xa0a3  32      hard    yes     yes     yes
  72  * Tiger Lake-H (PCH)           0x43a3  32      hard    yes     yes     yes
  73  * Jasper Lake (SOC)            0x4da3  32      hard    yes     yes     yes
  74  * Comet Lake-V (PCH)           0xa3a3  32      hard    yes     yes     yes
  75  * Alder Lake-S (PCH)           0x7aa3  32      hard    yes     yes     yes
  76  * Alder Lake-P (PCH)           0x51a3  32      hard    yes     yes     yes
  77  * Alder Lake-M (PCH)           0x54a3  32      hard    yes     yes     yes
  78  * Raptor Lake-S (PCH)          0x7a23  32      hard    yes     yes     yes
  79  * Meteor Lake-P (SOC)          0x7e22  32      hard    yes     yes     yes
  80  * Meteor Lake SoC-S (SOC)      0xae22  32      hard    yes     yes     yes
  81  * Meteor Lake PCH-S (PCH)      0x7f23  32      hard    yes     yes     yes
  82  *
  83  * Features supported by this driver:
  84  * Software PEC                         no
  85  * Hardware PEC                         yes
  86  * Block buffer                         yes
  87  * Block process call transaction       yes
  88  * I2C block read transaction           yes (doesn't use the block buffer)
  89  * Slave mode                           no
  90  * SMBus Host Notify                    yes
  91  * Interrupt processing                 yes
  92  *
  93  * See the file Documentation/i2c/busses/i2c-i801.rst for details.
  94  */
  95
  96 #define DRV_NAME        "i801_smbus"
  97
  98 #include <linux/interrupt.h>
  99 #include <linux/module.h>
 100 #include <linux/pci.h>
 101 #include <linux/kernel.h>
 102 #include <linux/stddef.h>
 103 #include <linux/delay.h>
 104 #include <linux/ioport.h>
 105 #include <linux/init.h>
 106 #include <linux/i2c.h>
 107 #include <linux/i2c-smbus.h>
 108 #include <linux/acpi.h>
 109 #include <linux/io.h>
 110 #include <linux/dmi.h>
 111 #include <linux/slab.h>
 112 #include <linux/string.h>
 113 #include <linux/completion.h>
 114 #include <linux/err.h>
 115 #include <linux/platform_device.h>
 116 #include <linux/platform_data/itco_wdt.h>
 117 #include <linux/platform_data/x86/p2sb.h>
 118 #include <linux/pm_runtime.h>
 119 #include <linux/mutex.h>
 120
 121 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 122 #include <linux/gpio/machine.h>
 123 #include <linux/platform_data/i2c-mux-gpio.h>
 124 #endif
 125
 126 /* I801 SMBus address offsets */
 127 #define SMBHSTSTS(p)    (0 + (p)->smba)
 128 #define SMBHSTCNT(p)    (2 + (p)->smba)
 129 #define SMBHSTCMD(p)    (3 + (p)->smba)
 130 #define SMBHSTADD(p)    (4 + (p)->smba)
 131 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 132 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 133 #define SMBBLKDAT(p)    (7 + (p)->smba)
 134 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 135 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 136 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 137 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 138 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 139 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 140
 141 /* PCI Address Constants */
 142 #define SMBBAR          4
 143 #define SMBHSTCFG       0x040
 144 #define TCOBASE         0x050
 145 #define TCOCTL          0x054
 146
 147 #define SBREG_SMBCTRL           0xc6000c
 148 #define SBREG_SMBCTRL_DNV       0xcf000c
 149
 150 /* Host configuration bits for SMBHSTCFG */
 151 #define SMBHSTCFG_HST_EN        BIT(0)
 152 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 153 #define SMBHSTCFG_I2C_EN        BIT(2)
 154 #define SMBHSTCFG_SPD_WD        BIT(4)
 155
 156 /* TCO configuration bits for TCOCTL */
 157 #define TCOCTL_EN               BIT(8)
 158
 159 /* Auxiliary status register bits, ICH4+ only */
 160 #define SMBAUXSTS_CRCE          BIT(0)
 161 #define SMBAUXSTS_STCO          BIT(1)
 162
 163 /* Auxiliary control register bits, ICH4+ only */
 164 #define SMBAUXCTL_CRC           BIT(0)
 165 #define SMBAUXCTL_E32B          BIT(1)
 166
 167 /* I801 command constants */
 168 #define I801_QUICK              0x00
 169 #define I801_BYTE               0x04
 170 #define I801_BYTE_DATA          0x08
 171 #define I801_WORD_DATA          0x0C
 172 #define I801_PROC_CALL          0x10
 173 #define I801_BLOCK_DATA         0x14
 174 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 175 #define I801_BLOCK_PROC_CALL    0x1C
 176
 177 /* I801 Host Control register bits */
 178 #define SMBHSTCNT_INTREN        BIT(0)
 179 #define SMBHSTCNT_KILL          BIT(1)
 180 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 181 #define SMBHSTCNT_START         BIT(6)
 182 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 183
 184 /* I801 Hosts Status register bits */
 185 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 186 #define SMBHSTSTS_INUSE_STS     BIT(6)
 187 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 188 #define SMBHSTSTS_FAILED        BIT(4)
 189 #define SMBHSTSTS_BUS_ERR       BIT(3)
 190 #define SMBHSTSTS_DEV_ERR       BIT(2)
 191 #define SMBHSTSTS_INTR          BIT(1)
 192 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 193
 194 /* Host Notify Status register bits */
 195 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 196
 197 /* Host Notify Command register bits */
 198 #define SMBSLVCMD_SMBALERT_DISABLE      BIT(2)
 199 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 200
 201 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 202                                  SMBHSTSTS_DEV_ERR)
 203
 204 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 205                                  STATUS_ERROR_FLAGS)
 206
 207 /* Older devices have their ID defined in <linux/pci_ids.h> */
 208 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS             0x02a3
 209 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS           0x06a3
 210 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 211 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 212 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 213 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS                   0x1bc9
 214 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 216 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 220 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 221 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 222 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 223 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 224 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 225 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 226 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 227 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS             0x38a3
 228 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 229 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS           0x43a3
 230 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS          0x4b23
 231 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS           0x4da3
 232 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS          0x51a3
 233 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS          0x54a3
 234 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 235 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS         0x7a23
 236 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS          0x7aa3
 237 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS         0x7e22
 238 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS     0x7f23
 239 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 240 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 241 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 242 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 243 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 244 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 245 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 246 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 247 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 248 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 249 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS          0xa0a3
 250 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 251 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 252 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 253 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 254 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 255 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS           0xa3a3
 256 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS     0xae22
 257
 258 struct i801_mux_config {
 259         char *gpio_chip;
 260         unsigned values[3];
 261         int n_values;
 262         unsigned classes[3];
 263         unsigned gpios[2];              /* Relative to gpio_chip->base */
 264         int n_gpios;
 265 };
 266
 267 struct i801_priv {
 268         struct i2c_adapter adapter;
 269         unsigned long smba;
 270         unsigned char original_hstcfg;
 271         unsigned char original_hstcnt;
 272         unsigned char original_slvcmd;
 273         struct pci_dev *pci_dev;
 274         unsigned int features;
 275
 276         /* isr processing */
 277         struct completion done;
 278         u8 status;
 279
 280         /* Command state used by isr for byte-by-byte block transactions */
 281         u8 cmd;
 282         bool is_read;
 283         int count;
 284         int len;
 285         u8 *data;
 286
 287 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 288         const struct i801_mux_config *mux_drvdata;
 289         struct platform_device *mux_pdev;
 290         struct gpiod_lookup_table *lookup;
 291 #endif
 292         struct platform_device *tco_pdev;
 293
 294         /*
 295          * If set to true the host controller registers are reserved for
 296          * ACPI AML use. Protected by acpi_lock.
 297          */
 298         bool acpi_reserved;
 299         struct mutex acpi_lock;
 300 };
 301
 302 #define FEATURE_SMBUS_PEC       BIT(0)
 303 #define FEATURE_BLOCK_BUFFER    BIT(1)
 304 #define FEATURE_BLOCK_PROC      BIT(2)
 305 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 306 #define FEATURE_IRQ             BIT(4)
 307 #define FEATURE_HOST_NOTIFY     BIT(5)
 308 /* Not really a feature, but it's convenient to handle it as such */
 309 #define FEATURE_IDF             BIT(15)
 310 #define FEATURE_TCO_SPT         BIT(16)
 311 #define FEATURE_TCO_CNL         BIT(17)
 312
 313 static const char *i801_feature_names[] = {
 314         "SMBus PEC",
 315         "Block buffer",
 316         "Block process call",
 317         "I2C block read",
 318         "Interrupt",
 319         "SMBus Host Notify",
 320 };
 321
 322 static unsigned int disable_features;
 323 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 324 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 325         "\t\t  0x01  disable SMBus PEC\n"
 326         "\t\t  0x02  disable the block buffer\n"
 327         "\t\t  0x08  disable the I2C block read functionality\n"
 328         "\t\t  0x10  don't use interrupts\n"
 329         "\t\t  0x20  disable SMBus Host Notify ");
 330
 331 /* Make sure the SMBus host is ready to start transmitting.
 332    Return 0 if it is, -EBUSY if it is not. */
 333 static int i801_check_pre(struct i801_priv *priv)
 334 {
 335         int status;
 336
 337         status = inb_p(SMBHSTSTS(priv));
 338         if (status & SMBHSTSTS_HOST_BUSY) {
 339                 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n");
 340                 return -EBUSY;
 341         }
 342
 343         status &= STATUS_FLAGS;
 344         if (status) {
 345                 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status);
 346                 outb_p(status, SMBHSTSTS(priv));
 347         }
 348
 349         /*
 350          * Clear CRC status if needed.
 351          * During normal operation, i801_check_post() takes care
 352          * of it after every operation.  We do it here only in case
 353          * the hardware was already in this state when the driver
 354          * started.
 355          */
 356         if (priv->features & FEATURE_SMBUS_PEC) {
 357                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 358                 if (status) {
 359                         pci_dbg(priv->pci_dev, "Clearing aux status flags (%02x)\n", status);
 360                         outb_p(status, SMBAUXSTS(priv));
 361                 }
 362         }
 363
 364         return 0;
 365 }
 366
 367 static int i801_check_post(struct i801_priv *priv, int status)
 368 {
 369         int result = 0;
 370
 371         /*
 372          * If the SMBus is still busy, we give up
 373          */
 374         if (unlikely(status < 0)) {
 375                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 376                 /* try to stop the current command */
 377                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 378                 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
 379                 usleep_range(1000, 2000);
 380                 outb_p(0, SMBHSTCNT(priv));
 381
 382                 /* Check if it worked */
 383                 status = inb_p(SMBHSTSTS(priv));
 384                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 385                     !(status & SMBHSTSTS_FAILED))
 386                         dev_err(&priv->pci_dev->dev,
 387                                 "Failed terminating the transaction\n");
 388                 return -ETIMEDOUT;
 389         }
 390
 391         if (status & SMBHSTSTS_FAILED) {
 392                 result = -EIO;
 393                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 394         }
 395         if (status & SMBHSTSTS_DEV_ERR) {
 396                 /*
 397                  * This may be a PEC error, check and clear it.
 398                  *
 399                  * AUXSTS is handled differently from HSTSTS.
 400                  * For HSTSTS, i801_isr() or i801_wait_intr()
 401                  * has already cleared the error bits in hardware,
 402                  * and we are passed a copy of the original value
 403                  * in "status".
 404                  * For AUXSTS, the hardware register is left
 405                  * for us to handle here.
 406                  * This is asymmetric, slightly iffy, but safe,
 407                  * since all this code is serialized and the CRCE
 408                  * bit is harmless as long as it's cleared before
 409                  * the next operation.
 410                  */
 411                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 412                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 413                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 414                         result = -EBADMSG;
 415                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 416                 } else {
 417                         result = -ENXIO;
 418                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 419                 }
 420         }
 421         if (status & SMBHSTSTS_BUS_ERR) {
 422                 result = -EAGAIN;
 423                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 424         }
 425
 426         return result;
 427 }
 428
 429 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 430 static int i801_wait_intr(struct i801_priv *priv)
 431 {
 432         unsigned long timeout = jiffies + priv->adapter.timeout;
 433         int status, busy;
 434
 435         do {
 436                 usleep_range(250, 500);
 437                 status = inb_p(SMBHSTSTS(priv));
 438                 busy = status & SMBHSTSTS_HOST_BUSY;
 439                 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
 440                 if (!busy && status)
 441                         return status & STATUS_ERROR_FLAGS;
 442         } while (time_is_after_eq_jiffies(timeout));
 443
 444         return -ETIMEDOUT;
 445 }
 446
 447 /* Wait for either BYTE_DONE or an error flag being set */
 448 static int i801_wait_byte_done(struct i801_priv *priv)
 449 {
 450         unsigned long timeout = jiffies + priv->adapter.timeout;
 451         int status;
 452
 453         do {
 454                 usleep_range(250, 500);
 455                 status = inb_p(SMBHSTSTS(priv));
 456                 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
 457                         return status & STATUS_ERROR_FLAGS;
 458         } while (time_is_after_eq_jiffies(timeout));
 459
 460         return -ETIMEDOUT;
 461 }
 462
 463 static int i801_transaction(struct i801_priv *priv, int xact)
 464 {
 465         unsigned long result;
 466         const struct i2c_adapter *adap = &priv->adapter;
 467
 468         if (priv->features & FEATURE_IRQ) {
 469                 reinit_completion(&priv->done);
 470                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 471                        SMBHSTCNT(priv));
 472                 result = wait_for_completion_timeout(&priv->done, adap->timeout);
 473                 return result ? priv->status : -ETIMEDOUT;
 474         }
 475
 476         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 477
 478         return i801_wait_intr(priv);
 479 }
 480
 481 static int i801_block_transaction_by_block(struct i801_priv *priv,
 482                                            union i2c_smbus_data *data,
 483                                            char read_write, int command)
 484 {
 485         int i, len, status, xact;
 486
 487         switch (command) {
 488         case I2C_SMBUS_BLOCK_PROC_CALL:
 489                 xact = I801_BLOCK_PROC_CALL;
 490                 break;
 491         case I2C_SMBUS_BLOCK_DATA:
 492                 xact = I801_BLOCK_DATA;
 493                 break;
 494         default:
 495                 return -EOPNOTSUPP;
 496         }
 497
 498         /* Set block buffer mode */
 499         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 500
 501         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 502
 503         if (read_write == I2C_SMBUS_WRITE) {
 504                 len = data->block[0];
 505                 outb_p(len, SMBHSTDAT0(priv));
 506                 for (i = 0; i < len; i++)
 507                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 508         }
 509
 510         status = i801_transaction(priv, xact);
 511         if (status)
 512                 goto out;
 513
 514         if (read_write == I2C_SMBUS_READ ||
 515             command == I2C_SMBUS_BLOCK_PROC_CALL) {
 516                 len = inb_p(SMBHSTDAT0(priv));
 517                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 518                         status = -EPROTO;
 519                         goto out;
 520                 }
 521
 522                 data->block[0] = len;
 523                 for (i = 0; i < len; i++)
 524                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 525         }
 526 out:
 527         outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv));
 528         return status;
 529 }
 530
 531 static void i801_isr_byte_done(struct i801_priv *priv)
 532 {
 533         if (priv->is_read) {
 534                 /* For SMBus block reads, length is received with first byte */
 535                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 536                     (priv->count == 0)) {
 537                         priv->len = inb_p(SMBHSTDAT0(priv));
 538                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 539                                 dev_err(&priv->pci_dev->dev,
 540                                         "Illegal SMBus block read size %d\n",
 541                                         priv->len);
 542                                 /* FIXME: Recover */
 543                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 544                         }
 545                         priv->data[-1] = priv->len;
 546                 }
 547
 548                 /* Read next byte */
 549                 if (priv->count < priv->len)
 550                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 551                 else
 552                         dev_dbg(&priv->pci_dev->dev,
 553                                 "Discarding extra byte on block read\n");
 554
 555                 /* Set LAST_BYTE for last byte of read transaction */
 556                 if (priv->count == priv->len - 1)
 557                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 558                                SMBHSTCNT(priv));
 559         } else if (priv->count < priv->len - 1) {
 560                 /* Write next byte, except for IRQ after last byte */
 561                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 562         }
 563 }
 564
 565 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 566 {
 567         unsigned short addr;
 568
 569         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 570
 571         /*
 572          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 573          * always returns 0. Our current implementation doesn't provide
 574          * data, so we just ignore it.
 575          */
 576         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 577
 578         /* clear Host Notify bit and return */
 579         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 580         return IRQ_HANDLED;
 581 }
 582
 583 /*
 584  * There are three kinds of interrupts:
 585  *
 586  * 1) i801 signals transaction completion with one of these interrupts:
 587  *      INTR - Success
 588  *      DEV_ERR - Invalid command, NAK or communication timeout
 589  *      BUS_ERR - SMI# transaction collision
 590  *      FAILED - transaction was canceled due to a KILL request
 591  *    When any of these occur, update ->status and signal completion.
 592  *
 593  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 594  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 595  *
 596  * 3) Host Notify interrupts
 597  */
 598 static irqreturn_t i801_isr(int irq, void *dev_id)
 599 {
 600         struct i801_priv *priv = dev_id;
 601         u16 pcists;
 602         u8 status;
 603
 604         /* Confirm this is our interrupt */
 605         pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
 606         if (!(pcists & PCI_STATUS_INTERRUPT))
 607                 return IRQ_NONE;
 608
 609         if (priv->features & FEATURE_HOST_NOTIFY) {
 610                 status = inb_p(SMBSLVSTS(priv));
 611                 if (status & SMBSLVSTS_HST_NTFY_STS)
 612                         return i801_host_notify_isr(priv);
 613         }
 614
 615         status = inb_p(SMBHSTSTS(priv));
 616         if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE)
 617                 i801_isr_byte_done(priv);
 618
 619         /*
 620          * Clear IRQ sources: SMB_ALERT status is set after signal assertion
 621          * independently of the interrupt generation being blocked or not
 622          * so clear it always when the status is set.
 623          */
 624         status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS;
 625         outb_p(status, SMBHSTSTS(priv));
 626
 627         status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
 628         if (status) {
 629                 priv->status = status & STATUS_ERROR_FLAGS;
 630                 complete(&priv->done);
 631         }
 632
 633         return IRQ_HANDLED;
 634 }
 635
 636 /*
 637  * For "byte-by-byte" block transactions:
 638  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 639  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 640  */
 641 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 642                                                union i2c_smbus_data *data,
 643                                                char read_write, int command)
 644 {
 645         int i, len;
 646         int smbcmd;
 647         int status;
 648         unsigned long result;
 649         const struct i2c_adapter *adap = &priv->adapter;
 650
 651         if (command == I2C_SMBUS_BLOCK_PROC_CALL)
 652                 return -EOPNOTSUPP;
 653
 654         len = data->block[0];
 655
 656         if (read_write == I2C_SMBUS_WRITE) {
 657                 outb_p(len, SMBHSTDAT0(priv));
 658                 outb_p(data->block[1], SMBBLKDAT(priv));
 659         }
 660
 661         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 662             read_write == I2C_SMBUS_READ)
 663                 smbcmd = I801_I2C_BLOCK_DATA;
 664         else
 665                 smbcmd = I801_BLOCK_DATA;
 666
 667         if (priv->features & FEATURE_IRQ) {
 668                 priv->is_read = (read_write == I2C_SMBUS_READ);
 669                 if (len == 1 && priv->is_read)
 670                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 671                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 672                 priv->len = len;
 673                 priv->count = 0;
 674                 priv->data = &data->block[1];
 675
 676                 reinit_completion(&priv->done);
 677                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 678                 result = wait_for_completion_timeout(&priv->done, adap->timeout);
 679                 return result ? priv->status : -ETIMEDOUT;
 680         }
 681
 682         for (i = 1; i <= len; i++) {
 683                 if (i == len && read_write == I2C_SMBUS_READ)
 684                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 685                 outb_p(smbcmd, SMBHSTCNT(priv));
 686
 687                 if (i == 1)
 688                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 689                                SMBHSTCNT(priv));
 690
 691                 status = i801_wait_byte_done(priv);
 692                 if (status)
 693                         return status;
 694
 695                 if (i == 1 && read_write == I2C_SMBUS_READ
 696                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 697                         len = inb_p(SMBHSTDAT0(priv));
 698                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 699                                 dev_err(&priv->pci_dev->dev,
 700                                         "Illegal SMBus block read size %d\n",
 701                                         len);
 702                                 /* Recover */
 703                                 while (inb_p(SMBHSTSTS(priv)) &
 704                                        SMBHSTSTS_HOST_BUSY)
 705                                         outb_p(SMBHSTSTS_BYTE_DONE,
 706                                                SMBHSTSTS(priv));
 707                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 708                                 return -EPROTO;
 709                         }
 710                         data->block[0] = len;
 711                 }
 712
 713                 /* Retrieve/store value in SMBBLKDAT */
 714                 if (read_write == I2C_SMBUS_READ)
 715                         data->block[i] = inb_p(SMBBLKDAT(priv));
 716                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 717                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 718
 719                 /* signals SMBBLKDAT ready */
 720                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 721         }
 722
 723         return i801_wait_intr(priv);
 724 }
 725
 726 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write)
 727 {
 728         outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv));
 729 }
 730
 731 /* Single value transaction function */
 732 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
 733                                    u8 addr, u8 hstcmd, char read_write, int command)
 734 {
 735         int xact, ret;
 736
 737         switch (command) {
 738         case I2C_SMBUS_QUICK:
 739                 i801_set_hstadd(priv, addr, read_write);
 740                 xact = I801_QUICK;
 741                 break;
 742         case I2C_SMBUS_BYTE:
 743                 i801_set_hstadd(priv, addr, read_write);
 744                 if (read_write == I2C_SMBUS_WRITE)
 745                         outb_p(hstcmd, SMBHSTCMD(priv));
 746                 xact = I801_BYTE;
 747                 break;
 748         case I2C_SMBUS_BYTE_DATA:
 749                 i801_set_hstadd(priv, addr, read_write);
 750                 if (read_write == I2C_SMBUS_WRITE)
 751                         outb_p(data->byte, SMBHSTDAT0(priv));
 752                 outb_p(hstcmd, SMBHSTCMD(priv));
 753                 xact = I801_BYTE_DATA;
 754                 break;
 755         case I2C_SMBUS_WORD_DATA:
 756                 i801_set_hstadd(priv, addr, read_write);
 757                 if (read_write == I2C_SMBUS_WRITE) {
 758                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 759                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 760                 }
 761                 outb_p(hstcmd, SMBHSTCMD(priv));
 762                 xact = I801_WORD_DATA;
 763                 break;
 764         case I2C_SMBUS_PROC_CALL:
 765                 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
 766                 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 767                 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 768                 outb_p(hstcmd, SMBHSTCMD(priv));
 769                 read_write = I2C_SMBUS_READ;
 770                 xact = I801_PROC_CALL;
 771                 break;
 772         default:
 773                 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command);
 774                 return -EOPNOTSUPP;
 775         }
 776
 777         ret = i801_transaction(priv, xact);
 778         if (ret || read_write == I2C_SMBUS_WRITE)
 779                 return ret;
 780
 781         switch (command) {
 782         case I2C_SMBUS_BYTE:
 783         case I2C_SMBUS_BYTE_DATA:
 784                 data->byte = inb_p(SMBHSTDAT0(priv));
 785                 break;
 786         case I2C_SMBUS_WORD_DATA:
 787         case I2C_SMBUS_PROC_CALL:
 788                 data->word = inb_p(SMBHSTDAT0(priv)) +
 789                              (inb_p(SMBHSTDAT1(priv)) << 8);
 790                 break;
 791         }
 792
 793         return 0;
 794 }
 795
 796 /* Block transaction function */
 797 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
 798                                   u8 addr, u8 hstcmd, char read_write, int command)
 799 {
 800         int result = 0;
 801         unsigned char hostc;
 802
 803         if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
 804                 data->block[0] = I2C_SMBUS_BLOCK_MAX;
 805         else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 806                 return -EPROTO;
 807
 808         switch (command) {
 809         case I2C_SMBUS_BLOCK_DATA:
 810                 i801_set_hstadd(priv, addr, read_write);
 811                 outb_p(hstcmd, SMBHSTCMD(priv));
 812                 break;
 813         case I2C_SMBUS_I2C_BLOCK_DATA:
 814                 /*
 815                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 816                  * bit should be cleared here, even when reading.
 817                  * However if SPD Write Disable is set (Lynx Point and later),
 818                  * the read will fail if we don't set the R/#W bit.
 819                  */
 820                 i801_set_hstadd(priv, addr,
 821                                 priv->original_hstcfg & SMBHSTCFG_SPD_WD ?
 822                                 read_write : I2C_SMBUS_WRITE);
 823                 if (read_write == I2C_SMBUS_READ) {
 824                         /* NB: page 240 of ICH5 datasheet also shows
 825                          * that DATA1 is the cmd field when reading
 826                          */
 827                         outb_p(hstcmd, SMBHSTDAT1(priv));
 828                 } else
 829                         outb_p(hstcmd, SMBHSTCMD(priv));
 830
 831                 if (read_write == I2C_SMBUS_WRITE) {
 832                         /* set I2C_EN bit in configuration register */
 833                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 834                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 835                                               hostc | SMBHSTCFG_I2C_EN);
 836                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 837                         dev_err(&priv->pci_dev->dev,
 838                                 "I2C block read is unsupported!\n");
 839                         return -EOPNOTSUPP;
 840                 }
 841                 break;
 842         case I2C_SMBUS_BLOCK_PROC_CALL:
 843                 /* Needs to be flagged as write transaction */
 844                 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
 845                 outb_p(hstcmd, SMBHSTCMD(priv));
 846                 break;
 847         }
 848
 849         /* Experience has shown that the block buffer can only be used for
 850            SMBus (not I2C) block transactions, even though the datasheet
 851            doesn't mention this limitation. */
 852         if ((priv->features & FEATURE_BLOCK_BUFFER) &&
 853             command != I2C_SMBUS_I2C_BLOCK_DATA)
 854                 result = i801_block_transaction_by_block(priv, data,
 855                                                          read_write,
 856                                                          command);
 857         else
 858                 result = i801_block_transaction_byte_by_byte(priv, data,
 859                                                              read_write,
 860                                                              command);
 861
 862         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 863          && read_write == I2C_SMBUS_WRITE) {
 864                 /* restore saved configuration register value */
 865                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 866         }
 867         return result;
 868 }
 869
 870 /* Return negative errno on error. */
 871 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 872                        unsigned short flags, char read_write, u8 command,
 873                        int size, union i2c_smbus_data *data)
 874 {
 875         int hwpec, ret;
 876         struct i801_priv *priv = i2c_get_adapdata(adap);
 877
 878         mutex_lock(&priv->acpi_lock);
 879         if (priv->acpi_reserved) {
 880                 mutex_unlock(&priv->acpi_lock);
 881                 return -EBUSY;
 882         }
 883
 884         pm_runtime_get_sync(&priv->pci_dev->dev);
 885
 886         ret = i801_check_pre(priv);
 887         if (ret)
 888                 goto out;
 889
 890         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 891                 && size != I2C_SMBUS_QUICK
 892                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 893
 894         if (hwpec)      /* enable/disable hardware PEC */
 895                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 896         else
 897                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 898                        SMBAUXCTL(priv));
 899
 900         if (size == I2C_SMBUS_BLOCK_DATA ||
 901             size == I2C_SMBUS_I2C_BLOCK_DATA ||
 902             size == I2C_SMBUS_BLOCK_PROC_CALL)
 903                 ret = i801_block_transaction(priv, data, addr, command, read_write, size);
 904         else
 905                 ret = i801_simple_transaction(priv, data, addr, command, read_write, size);
 906
 907         ret = i801_check_post(priv, ret);
 908
 909         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 910          * time, so we forcibly disable it after every transaction.
 911          */
 912         if (hwpec)
 913                 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv));
 914 out:
 915         /*
 916          * Unlock the SMBus device for use by BIOS/ACPI,
 917          * and clear status flags if not done already.
 918          */
 919         outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv));
 920
 921         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 922         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 923         mutex_unlock(&priv->acpi_lock);
 924         return ret;
 925 }
 926
 927
 928 static u32 i801_func(struct i2c_adapter *adapter)
 929 {
 930         struct i801_priv *priv = i2c_get_adapdata(adapter);
 931
 932         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 933                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 934                I2C_FUNC_SMBUS_PROC_CALL |
 935                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 936                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 937                ((priv->features & FEATURE_BLOCK_PROC) ?
 938                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
 939                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 940                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 941                ((priv->features & FEATURE_HOST_NOTIFY) ?
 942                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 943 }
 944
 945 static void i801_enable_host_notify(struct i2c_adapter *adapter)
 946 {
 947         struct i801_priv *priv = i2c_get_adapdata(adapter);
 948
 949         if (!(priv->features & FEATURE_HOST_NOTIFY))
 950                 return;
 951
 952         /*
 953          * Enable host notify interrupt and block the generation of interrupt
 954          * from the SMB_ALERT signal because the driver does not support
 955          * SMBus Alert.
 956          */
 957         outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
 958                priv->original_slvcmd, SMBSLVCMD(priv));
 959
 960         /* clear Host Notify bit to allow a new notification */
 961         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 962 }
 963
 964 static void i801_disable_host_notify(struct i801_priv *priv)
 965 {
 966         if (!(priv->features & FEATURE_HOST_NOTIFY))
 967                 return;
 968
 969         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
 970 }
 971
 972 static const struct i2c_algorithm smbus_algorithm = {
 973         .smbus_xfer     = i801_access,
 974         .functionality  = i801_func,
 975 };
 976
 977 #define FEATURES_ICH5   (FEATURE_BLOCK_PROC | FEATURE_I2C_BLOCK_READ    | \
 978                          FEATURE_IRQ | FEATURE_SMBUS_PEC                | \
 979                          FEATURE_BLOCK_BUFFER | FEATURE_HOST_NOTIFY)
 980 #define FEATURES_ICH4   (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \
 981                          FEATURE_HOST_NOTIFY)
 982
 983 static const struct pci_device_id i801_ids[] = {
 984         { PCI_DEVICE_DATA(INTEL, 82801AA_3,                     0)                               },
 985         { PCI_DEVICE_DATA(INTEL, 82801AB_3,                     0)                               },
 986         { PCI_DEVICE_DATA(INTEL, 82801BA_2,                     0)                               },
 987         { PCI_DEVICE_DATA(INTEL, 82801CA_3,                     FEATURE_HOST_NOTIFY)             },
 988         { PCI_DEVICE_DATA(INTEL, 82801DB_3,                     FEATURES_ICH4)                   },
 989         { PCI_DEVICE_DATA(INTEL, 82801EB_3,                     FEATURES_ICH5)                   },
 990         { PCI_DEVICE_DATA(INTEL, ESB_4,                         FEATURES_ICH5)                   },
 991         { PCI_DEVICE_DATA(INTEL, ICH6_16,                       FEATURES_ICH5)                   },
 992         { PCI_DEVICE_DATA(INTEL, ICH7_17,                       FEATURES_ICH5)                   },
 993         { PCI_DEVICE_DATA(INTEL, ESB2_17,                       FEATURES_ICH5)                   },
 994         { PCI_DEVICE_DATA(INTEL, ICH8_5,                        FEATURES_ICH5)                   },
 995         { PCI_DEVICE_DATA(INTEL, ICH9_6,                        FEATURES_ICH5)                   },
 996         { PCI_DEVICE_DATA(INTEL, EP80579_1,                     FEATURES_ICH5)                   },
 997         { PCI_DEVICE_DATA(INTEL, ICH10_4,                       FEATURES_ICH5)                   },
 998         { PCI_DEVICE_DATA(INTEL, ICH10_5,                       FEATURES_ICH5)                   },
 999         { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS,           FEATURES_ICH5)                   },
1000         { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS,             FEATURES_ICH5)                   },
1001         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS,                FEATURES_ICH5)                   },
1002         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0,           FEATURES_ICH5 | FEATURE_IDF)     },
1003         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1,           FEATURES_ICH5 | FEATURE_IDF)     },
1004         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2,           FEATURES_ICH5 | FEATURE_IDF)     },
1005         { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS,                FEATURES_ICH5)                   },
1006         { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS,            FEATURES_ICH5)                   },
1007         { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS,               FEATURES_ICH5)                   },
1008         { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS,            FEATURES_ICH5)                   },
1009         { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS,                  FEATURES_ICH5)                   },
1010         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS,               FEATURES_ICH5)                   },
1011         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0,           FEATURES_ICH5 | FEATURE_IDF)     },
1012         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1,           FEATURES_ICH5 | FEATURE_IDF)     },
1013         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2,           FEATURES_ICH5 | FEATURE_IDF)     },
1014         { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS,             FEATURES_ICH5)                   },
1015         { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS,              FEATURES_ICH5)                   },
1016         { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS,            FEATURES_ICH5)                   },
1017         { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS,         FEATURES_ICH5)                   },
1018         { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS,                FEATURES_ICH5)                   },
1019         { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS,                FEATURES_ICH5)                   },
1020         { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS,          FEATURES_ICH5 | FEATURE_TCO_SPT) },
1021         { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS,         FEATURES_ICH5 | FEATURE_TCO_SPT) },
1022         { PCI_DEVICE_DATA(INTEL, CDF_SMBUS,                     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1023         { PCI_DEVICE_DATA(INTEL, DNV_SMBUS,                     FEATURES_ICH5 | FEATURE_TCO_SPT) },
1024         { PCI_DEVICE_DATA(INTEL, EBG_SMBUS,                     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1025         { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS,                 FEATURES_ICH5)                   },
1026         { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS,               FEATURES_ICH5 | FEATURE_TCO_SPT) },
1027         { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS,          FEATURES_ICH5 | FEATURE_TCO_SPT) },
1028         { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS,          FEATURES_ICH5 | FEATURE_TCO_SPT) },
1029         { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1030         { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS,           FEATURES_ICH5 | FEATURE_TCO_CNL) },
1031         { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS,              FEATURES_ICH5 | FEATURE_TCO_CNL) },
1032         { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS,               FEATURES_ICH5 | FEATURE_TCO_CNL) },
1033         { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS,               FEATURES_ICH5 | FEATURE_TCO_CNL) },
1034         { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1035         { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_SPT) },
1036         { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1037         { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1038         { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1039         { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1040         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1041         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1042         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS,            FEATURES_ICH5 | FEATURE_TCO_CNL) },
1043         { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS,           FEATURES_ICH5 | FEATURE_TCO_CNL) },
1044         { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS,           FEATURES_ICH5 | FEATURE_TCO_CNL) },
1045         { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_CNL) },
1046         { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_CNL) },
1047         { 0, }
1048 };
1049
1050 MODULE_DEVICE_TABLE(pci, i801_ids);
1051
1052 #if defined CONFIG_X86 && defined CONFIG_DMI
1053 static unsigned char apanel_addr;
1054
1055 /* Scan the system ROM for the signature "FJKEYINF" */
1056 static __init const void __iomem *bios_signature(const void __iomem *bios)
1057 {
1058         ssize_t offset;
1059         const unsigned char signature[] = "FJKEYINF";
1060
1061         for (offset = 0; offset < 0x10000; offset += 0x10) {
1062                 if (check_signature(bios + offset, signature,
1063                                     sizeof(signature)-1))
1064                         return bios + offset;
1065         }
1066         return NULL;
1067 }
1068
1069 static void __init input_apanel_init(void)
1070 {
1071         void __iomem *bios;
1072         const void __iomem *p;
1073
1074         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1075         p = bios_signature(bios);
1076         if (p) {
1077                 /* just use the first address */
1078                 apanel_addr = readb(p + 8 + 3) >> 1;
1079         }
1080         iounmap(bios);
1081 }
1082
1083 struct dmi_onboard_device_info {
1084         const char *name;
1085         u8 type;
1086         unsigned short i2c_addr;
1087         const char *i2c_type;
1088 };
1089
1090 static const struct dmi_onboard_device_info dmi_devices[] = {
1091         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1092         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1093         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1094 };
1095
1096 static void dmi_check_onboard_device(u8 type, const char *name,
1097                                      struct i2c_adapter *adap)
1098 {
1099         int i;
1100         struct i2c_board_info info;
1101
1102         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1103                 /* & ~0x80, ignore enabled/disabled bit */
1104                 if ((type & ~0x80) != dmi_devices[i].type)
1105                         continue;
1106                 if (strcasecmp(name, dmi_devices[i].name))
1107                         continue;
1108
1109                 memset(&info, 0, sizeof(struct i2c_board_info));
1110                 info.addr = dmi_devices[i].i2c_addr;
1111                 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1112                 i2c_new_client_device(adap, &info);
1113                 break;
1114         }
1115 }
1116
1117 /* We use our own function to check for onboard devices instead of
1118    dmi_find_device() as some buggy BIOS's have the devices we are interested
1119    in marked as disabled */
1120 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1121 {
1122         int i, count;
1123
1124         if (dm->type != 10)
1125                 return;
1126
1127         count = (dm->length - sizeof(struct dmi_header)) / 2;
1128         for (i = 0; i < count; i++) {
1129                 const u8 *d = (char *)(dm + 1) + (i * 2);
1130                 const char *name = ((char *) dm) + dm->length;
1131                 u8 type = d[0];
1132                 u8 s = d[1];
1133
1134                 if (!s)
1135                         continue;
1136                 s--;
1137                 while (s > 0 && name[0]) {
1138                         name += strlen(name) + 1;
1139                         s--;
1140                 }
1141                 if (name[0] == 0) /* Bogus string reference */
1142                         continue;
1143
1144                 dmi_check_onboard_device(type, name, adap);
1145         }
1146 }
1147
1148 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1149 static const char *const acpi_smo8800_ids[] = {
1150         "SMO8800",
1151         "SMO8801",
1152         "SMO8810",
1153         "SMO8811",
1154         "SMO8820",
1155         "SMO8821",
1156         "SMO8830",
1157         "SMO8831",
1158 };
1159
1160 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1161                                              u32 nesting_level,
1162                                              void *context,
1163                                              void **return_value)
1164 {
1165         struct acpi_device_info *info;
1166         acpi_status status;
1167         char *hid;
1168         int i;
1169
1170         status = acpi_get_object_info(obj_handle, &info);
1171         if (ACPI_FAILURE(status))
1172                 return AE_OK;
1173
1174         if (!(info->valid & ACPI_VALID_HID))
1175                 goto smo88xx_not_found;
1176
1177         hid = info->hardware_id.string;
1178         if (!hid)
1179                 goto smo88xx_not_found;
1180
1181         i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1182         if (i < 0)
1183                 goto smo88xx_not_found;
1184
1185         kfree(info);
1186
1187         *return_value = NULL;
1188         return AE_CTRL_TERMINATE;
1189
1190 smo88xx_not_found:
1191         kfree(info);
1192         return AE_OK;
1193 }
1194
1195 static bool is_dell_system_with_lis3lv02d(void)
1196 {
1197         void *err = ERR_PTR(-ENOENT);
1198
1199         if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc."))
1200                 return false;
1201
1202         /*
1203          * Check that ACPI device SMO88xx is present and is functioning.
1204          * Function acpi_get_devices() already filters all ACPI devices
1205          * which are not present or are not functioning.
1206          * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1207          * accelerometer but unfortunately ACPI does not provide any other
1208          * information (like I2C address).
1209          */
1210         acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err);
1211
1212         return !IS_ERR(err);
1213 }
1214
1215 /*
1216  * Accelerometer's I2C address is not specified in DMI nor ACPI,
1217  * so it is needed to define mapping table based on DMI product names.
1218  */
1219 static const struct {
1220         const char *dmi_product_name;
1221         unsigned short i2c_addr;
1222 } dell_lis3lv02d_devices[] = {
1223         /*
1224          * Dell platform team told us that these Latitude devices have
1225          * ST microelectronics accelerometer at I2C address 0x29.
1226          */
1227         { "Latitude E5250",     0x29 },
1228         { "Latitude E5450",     0x29 },
1229         { "Latitude E5550",     0x29 },
1230         { "Latitude E6440",     0x29 },
1231         { "Latitude E6440 ATG", 0x29 },
1232         { "Latitude E6540",     0x29 },
1233         /*
1234          * Additional individual entries were added after verification.
1235          */
1236         { "Latitude 5480",      0x29 },
1237         { "Vostro V131",        0x1d },
1238         { "Vostro 5568",        0x29 },
1239 };
1240
1241 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1242 {
1243         struct i2c_board_info info;
1244         const char *dmi_product_name;
1245         int i;
1246
1247         dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1248         for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1249                 if (strcmp(dmi_product_name,
1250                            dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1251                         break;
1252         }
1253
1254         if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1255                 dev_warn(&priv->pci_dev->dev,
1256                          "Accelerometer lis3lv02d is present on SMBus but its"
1257                          " address is unknown, skipping registration\n");
1258                 return;
1259         }
1260
1261         memset(&info, 0, sizeof(struct i2c_board_info));
1262         info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1263         strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1264         i2c_new_client_device(&priv->adapter, &info);
1265 }
1266
1267 /* Register optional slaves */
1268 static void i801_probe_optional_slaves(struct i801_priv *priv)
1269 {
1270         /* Only register slaves on main SMBus channel */
1271         if (priv->features & FEATURE_IDF)
1272                 return;
1273
1274         if (apanel_addr) {
1275                 struct i2c_board_info info = {
1276                         .addr = apanel_addr,
1277                         .type = "fujitsu_apanel",
1278                 };
1279
1280                 i2c_new_client_device(&priv->adapter, &info);
1281         }
1282
1283         if (dmi_name_in_vendors("FUJITSU"))
1284                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1285
1286         if (is_dell_system_with_lis3lv02d())
1287                 register_dell_lis3lv02d_i2c_device(priv);
1288
1289         /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1290 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1291         if (!priv->mux_drvdata)
1292 #endif
1293                 i2c_register_spd(&priv->adapter);
1294 }
1295 #else
1296 static void __init input_apanel_init(void) {}
1297 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1298 #endif  /* CONFIG_X86 && CONFIG_DMI */
1299
1300 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1301 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1302         .gpio_chip = "gpio_ich",
1303         .values = { 0x02, 0x03 },
1304         .n_values = 2,
1305         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1306         .gpios = { 52, 53 },
1307         .n_gpios = 2,
1308 };
1309
1310 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1311         .gpio_chip = "gpio_ich",
1312         .values = { 0x02, 0x03, 0x01 },
1313         .n_values = 3,
1314         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1315         .gpios = { 52, 53 },
1316         .n_gpios = 2,
1317 };
1318
1319 static const struct dmi_system_id mux_dmi_table[] = {
1320         {
1321                 .matches = {
1322                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1323                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1324                 },
1325                 .driver_data = &i801_mux_config_asus_z8_d12,
1326         },
1327         {
1328                 .matches = {
1329                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1330                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1331                 },
1332                 .driver_data = &i801_mux_config_asus_z8_d12,
1333         },
1334         {
1335                 .matches = {
1336                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1337                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1338                 },
1339                 .driver_data = &i801_mux_config_asus_z8_d12,
1340         },
1341         {
1342                 .matches = {
1343                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1344                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1345                 },
1346                 .driver_data = &i801_mux_config_asus_z8_d12,
1347         },
1348         {
1349                 .matches = {
1350                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1351                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1352                 },
1353                 .driver_data = &i801_mux_config_asus_z8_d12,
1354         },
1355         {
1356                 .matches = {
1357                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1358                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1359                 },
1360                 .driver_data = &i801_mux_config_asus_z8_d12,
1361         },
1362         {
1363                 .matches = {
1364                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1365                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1366                 },
1367                 .driver_data = &i801_mux_config_asus_z8_d18,
1368         },
1369         {
1370                 .matches = {
1371                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1372                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1373                 },
1374                 .driver_data = &i801_mux_config_asus_z8_d18,
1375         },
1376         {
1377                 .matches = {
1378                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1379                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1380                 },
1381                 .driver_data = &i801_mux_config_asus_z8_d12,
1382         },
1383         { }
1384 };
1385
1386 /* Setup multiplexing if needed */
1387 static void i801_add_mux(struct i801_priv *priv)
1388 {
1389         struct device *dev = &priv->adapter.dev;
1390         const struct i801_mux_config *mux_config;
1391         struct i2c_mux_gpio_platform_data gpio_data;
1392         struct gpiod_lookup_table *lookup;
1393         int i;
1394
1395         if (!priv->mux_drvdata)
1396                 return;
1397         mux_config = priv->mux_drvdata;
1398
1399         /* Prepare the platform data */
1400         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1401         gpio_data.parent = priv->adapter.nr;
1402         gpio_data.values = mux_config->values;
1403         gpio_data.n_values = mux_config->n_values;
1404         gpio_data.classes = mux_config->classes;
1405         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1406
1407         /* Register GPIO descriptor lookup table */
1408         lookup = devm_kzalloc(dev,
1409                               struct_size(lookup, table, mux_config->n_gpios + 1),
1410                               GFP_KERNEL);
1411         if (!lookup)
1412                 return;
1413         lookup->dev_id = "i2c-mux-gpio";
1414         for (i = 0; i < mux_config->n_gpios; i++)
1415                 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1416                                                mux_config->gpios[i], "mux", 0);
1417         gpiod_add_lookup_table(lookup);
1418         priv->lookup = lookup;
1419
1420         /*
1421          * Register the mux device, we use PLATFORM_DEVID_NONE here
1422          * because since we are referring to the GPIO chip by name we are
1423          * anyways in deep trouble if there is more than one of these
1424          * devices, and there should likely only be one platform controller
1425          * hub.
1426          */
1427         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1428                                 PLATFORM_DEVID_NONE, &gpio_data,
1429                                 sizeof(struct i2c_mux_gpio_platform_data));
1430         if (IS_ERR(priv->mux_pdev)) {
1431                 gpiod_remove_lookup_table(lookup);
1432                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1433         }
1434 }
1435
1436 static void i801_del_mux(struct i801_priv *priv)
1437 {
1438         platform_device_unregister(priv->mux_pdev);
1439         gpiod_remove_lookup_table(priv->lookup);
1440 }
1441
1442 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1443 {
1444         const struct dmi_system_id *id;
1445         const struct i801_mux_config *mux_config;
1446         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1447         int i;
1448
1449         id = dmi_first_match(mux_dmi_table);
1450         if (id) {
1451                 /* Remove branch classes from trunk */
1452                 mux_config = id->driver_data;
1453                 for (i = 0; i < mux_config->n_values; i++)
1454                         class &= ~mux_config->classes[i];
1455
1456                 /* Remember for later */
1457                 priv->mux_drvdata = mux_config;
1458         }
1459
1460         return class;
1461 }
1462 #else
1463 static inline void i801_add_mux(struct i801_priv *priv) { }
1464 static inline void i801_del_mux(struct i801_priv *priv) { }
1465
1466 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1467 {
1468         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1469 }
1470 #endif
1471
1472 static struct platform_device *
1473 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1474                  struct resource *tco_res)
1475 {
1476         static const struct itco_wdt_platform_data pldata = {
1477                 .name = "Intel PCH",
1478                 .version = 4,
1479         };
1480         struct resource *res;
1481         int ret;
1482
1483         /*
1484          * We must access the NO_REBOOT bit over the Primary to Sideband
1485          * (P2SB) bridge.
1486          */
1487
1488         res = &tco_res[1];
1489         ret = p2sb_bar(pci_dev->bus, 0, res);
1490         if (ret)
1491                 return ERR_PTR(ret);
1492
1493         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1494                 res->start += SBREG_SMBCTRL_DNV;
1495         else
1496                 res->start += SBREG_SMBCTRL;
1497
1498         res->end = res->start + 3;
1499
1500         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1501                                         tco_res, 2, &pldata, sizeof(pldata));
1502 }
1503
1504 static struct platform_device *
1505 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1506                  struct resource *tco_res)
1507 {
1508         static const struct itco_wdt_platform_data pldata = {
1509                 .name = "Intel PCH",
1510                 .version = 6,
1511         };
1512
1513         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1514                                                  tco_res, 1, &pldata, sizeof(pldata));
1515 }
1516
1517 static void i801_add_tco(struct i801_priv *priv)
1518 {
1519         struct pci_dev *pci_dev = priv->pci_dev;
1520         struct resource tco_res[2], *res;
1521         u32 tco_base, tco_ctl;
1522
1523         /* If we have ACPI based watchdog use that instead */
1524         if (acpi_has_watchdog())
1525                 return;
1526
1527         if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1528                 return;
1529
1530         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1531         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1532         if (!(tco_ctl & TCOCTL_EN))
1533                 return;
1534
1535         memset(tco_res, 0, sizeof(tco_res));
1536         /*
1537          * Always populate the main iTCO IO resource here. The second entry
1538          * for NO_REBOOT MMIO is filled by the SPT specific function.
1539          */
1540         res = &tco_res[0];
1541         res->start = tco_base & ~1;
1542         res->end = res->start + 32 - 1;
1543         res->flags = IORESOURCE_IO;
1544
1545         if (priv->features & FEATURE_TCO_CNL)
1546                 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1547         else
1548                 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1549
1550         if (IS_ERR(priv->tco_pdev))
1551                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1552 }
1553
1554 #ifdef CONFIG_ACPI
1555 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1556                                       acpi_physical_address address)
1557 {
1558         return address >= priv->smba &&
1559                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1560 }
1561
1562 static acpi_status
1563 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1564                      u64 *value, void *handler_context, void *region_context)
1565 {
1566         struct i801_priv *priv = handler_context;
1567         struct pci_dev *pdev = priv->pci_dev;
1568         acpi_status status;
1569
1570         /*
1571          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1572          * further access from the driver itself. This device is now owned
1573          * by the system firmware.
1574          */
1575         mutex_lock(&priv->acpi_lock);
1576
1577         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1578                 priv->acpi_reserved = true;
1579
1580                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1581                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1582
1583                 /*
1584                  * BIOS is accessing the host controller so prevent it from
1585                  * suspending automatically from now on.
1586                  */
1587                 pm_runtime_get_sync(&pdev->dev);
1588         }
1589
1590         if ((function & ACPI_IO_MASK) == ACPI_READ)
1591                 status = acpi_os_read_port(address, (u32 *)value, bits);
1592         else
1593                 status = acpi_os_write_port(address, (u32)*value, bits);
1594
1595         mutex_unlock(&priv->acpi_lock);
1596
1597         return status;
1598 }
1599
1600 static int i801_acpi_probe(struct i801_priv *priv)
1601 {
1602         acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1603         acpi_status status;
1604
1605         status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1606                                                     i801_acpi_io_handler, NULL, priv);
1607         if (ACPI_SUCCESS(status))
1608                 return 0;
1609
1610         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1611 }
1612
1613 static void i801_acpi_remove(struct i801_priv *priv)
1614 {
1615         acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1616
1617         acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1618 }
1619 #else
1620 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1621 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1622 #endif
1623
1624 static void i801_setup_hstcfg(struct i801_priv *priv)
1625 {
1626         unsigned char hstcfg = priv->original_hstcfg;
1627
1628         hstcfg &= ~SMBHSTCFG_I2C_EN;    /* SMBus timing */
1629         hstcfg |= SMBHSTCFG_HST_EN;
1630         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1631 }
1632
1633 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1634 {
1635         int err, i;
1636         struct i801_priv *priv;
1637
1638         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1639         if (!priv)
1640                 return -ENOMEM;
1641
1642         i2c_set_adapdata(&priv->adapter, priv);
1643         priv->adapter.owner = THIS_MODULE;
1644         priv->adapter.class = i801_get_adapter_class(priv);
1645         priv->adapter.algo = &smbus_algorithm;
1646         priv->adapter.dev.parent = &dev->dev;
1647         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1648         priv->adapter.retries = 3;
1649         mutex_init(&priv->acpi_lock);
1650
1651         priv->pci_dev = dev;
1652         priv->features = id->driver_data;
1653
1654         /* Disable features on user request */
1655         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1656                 if (priv->features & disable_features & (1 << i))
1657                         dev_notice(&dev->dev, "%s disabled by user\n",
1658                                    i801_feature_names[i]);
1659         }
1660         priv->features &= ~disable_features;
1661
1662         /* The block process call uses block buffer mode */
1663         if (!(priv->features & FEATURE_BLOCK_BUFFER))
1664                 priv->features &= ~FEATURE_BLOCK_PROC;
1665
1666         err = pcim_enable_device(dev);
1667         if (err) {
1668                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1669                         err);
1670                 return err;
1671         }
1672         pcim_pin_device(dev);
1673
1674         /* Determine the address of the SMBus area */
1675         priv->smba = pci_resource_start(dev, SMBBAR);
1676         if (!priv->smba) {
1677                 dev_err(&dev->dev,
1678                         "SMBus base address uninitialized, upgrade BIOS\n");
1679                 return -ENODEV;
1680         }
1681
1682         if (i801_acpi_probe(priv))
1683                 return -ENODEV;
1684
1685         err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME);
1686         if (err) {
1687                 dev_err(&dev->dev,
1688                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1689                         priv->smba,
1690                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1691                 i801_acpi_remove(priv);
1692                 return err;
1693         }
1694
1695         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1696         i801_setup_hstcfg(priv);
1697         if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1698                 dev_info(&dev->dev, "Enabling SMBus device\n");
1699
1700         if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1701                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1702                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1703                 priv->features &= ~FEATURE_IRQ;
1704         }
1705         if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1706                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1707
1708         /* Clear special mode bits */
1709         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1710                 outb_p(inb_p(SMBAUXCTL(priv)) &
1711                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1712
1713         /* Default timeout in interrupt mode: 200 ms */
1714         priv->adapter.timeout = HZ / 5;
1715
1716         if (dev->irq == IRQ_NOTCONNECTED)
1717                 priv->features &= ~FEATURE_IRQ;
1718
1719         if (priv->features & FEATURE_IRQ) {
1720                 u16 pcists;
1721
1722                 /* Complain if an interrupt is already pending */
1723                 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1724                 if (pcists & PCI_STATUS_INTERRUPT)
1725                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1726         }
1727
1728         if (priv->features & FEATURE_IRQ) {
1729                 init_completion(&priv->done);
1730
1731                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1732                                        IRQF_SHARED, DRV_NAME, priv);
1733                 if (err) {
1734                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1735                                 dev->irq, err);
1736                         priv->features &= ~FEATURE_IRQ;
1737                 }
1738         }
1739         dev_info(&dev->dev, "SMBus using %s\n",
1740                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1741
1742         /* Host notification uses an interrupt */
1743         if (!(priv->features & FEATURE_IRQ))
1744                 priv->features &= ~FEATURE_HOST_NOTIFY;
1745
1746         /* Remember original Interrupt and Host Notify settings */
1747         priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1748         if (priv->features & FEATURE_HOST_NOTIFY)
1749                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1750
1751         i801_add_tco(priv);
1752
1753         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1754                 "SMBus I801 adapter at %04lx", priv->smba);
1755         err = i2c_add_adapter(&priv->adapter);
1756         if (err) {
1757                 i801_acpi_remove(priv);
1758                 return err;
1759         }
1760
1761         i801_enable_host_notify(&priv->adapter);
1762
1763         i801_probe_optional_slaves(priv);
1764         /* We ignore errors - multiplexing is optional */
1765         i801_add_mux(priv);
1766
1767         pci_set_drvdata(dev, priv);
1768
1769         dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1770         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1771         pm_runtime_use_autosuspend(&dev->dev);
1772         pm_runtime_put_autosuspend(&dev->dev);
1773         pm_runtime_allow(&dev->dev);
1774
1775         return 0;
1776 }
1777
1778 static void i801_remove(struct pci_dev *dev)
1779 {
1780         struct i801_priv *priv = pci_get_drvdata(dev);
1781
1782         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1783         i801_disable_host_notify(priv);
1784         i801_del_mux(priv);
1785         i2c_del_adapter(&priv->adapter);
1786         i801_acpi_remove(priv);
1787         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1788
1789         platform_device_unregister(priv->tco_pdev);
1790
1791         /* if acpi_reserved is set then usage_count is incremented already */
1792         if (!priv->acpi_reserved)
1793                 pm_runtime_get_noresume(&dev->dev);
1794
1795         /*
1796          * do not call pci_disable_device(dev) since it can cause hard hangs on
1797          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1798          */
1799 }
1800
1801 static void i801_shutdown(struct pci_dev *dev)
1802 {
1803         struct i801_priv *priv = pci_get_drvdata(dev);
1804
1805         /* Restore config registers to avoid hard hang on some systems */
1806         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1807         i801_disable_host_notify(priv);
1808         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1809 }
1810
1811 #ifdef CONFIG_PM_SLEEP
1812 static int i801_suspend(struct device *dev)
1813 {
1814         struct i801_priv *priv = dev_get_drvdata(dev);
1815
1816         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1817         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1818         return 0;
1819 }
1820
1821 static int i801_resume(struct device *dev)
1822 {
1823         struct i801_priv *priv = dev_get_drvdata(dev);
1824
1825         i801_setup_hstcfg(priv);
1826         i801_enable_host_notify(&priv->adapter);
1827
1828         return 0;
1829 }
1830 #endif
1831
1832 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1833
1834 static struct pci_driver i801_driver = {
1835         .name           = DRV_NAME,
1836         .id_table       = i801_ids,
1837         .probe          = i801_probe,
1838         .remove         = i801_remove,
1839         .shutdown       = i801_shutdown,
1840         .driver         = {
1841                 .pm     = &i801_pm_ops,
1842                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1843         },
1844 };
1845
1846 static int __init i2c_i801_init(void)
1847 {
1848         if (dmi_name_in_vendors("FUJITSU"))
1849                 input_apanel_init();
1850         return pci_register_driver(&i801_driver);
1851 }
1852
1853 static void __exit i2c_i801_exit(void)
1854 {
1855         pci_unregister_driver(&i801_driver);
1856 }
1857
1858 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1859 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1860 MODULE_DESCRIPTION("I801 SMBus driver");
1861 MODULE_LICENSE("GPL");
1862
1863 module_init(i2c_i801_init);
1864 module_exit(i2c_i801_exit);