drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  62  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  63  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  64  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  65  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  66  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  67  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  68  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  69  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  70  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  71  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  72  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  73  * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  74  *
  75  * Features supported by this driver:
  76  * Software PEC                         no
  77  * Hardware PEC                         yes
  78  * Block buffer                         yes
  79  * Block process call transaction       no
  80  * I2C block read transaction           yes (doesn't use the block buffer)
  81  * Slave mode                           no
  82  * SMBus Host Notify                    yes
  83  * Interrupt processing                 yes
  84  *
  85  * See the file Documentation/i2c/busses/i2c-i801 for details.
  86  */
  87
  88 #include <linux/interrupt.h>
  89 #include <linux/module.h>
  90 #include <linux/pci.h>
  91 #include <linux/kernel.h>
  92 #include <linux/stddef.h>
  93 #include <linux/delay.h>
  94 #include <linux/ioport.h>
  95 #include <linux/init.h>
  96 #include <linux/i2c.h>
  97 #include <linux/i2c-smbus.h>
  98 #include <linux/acpi.h>
  99 #include <linux/io.h>
 100 #include <linux/dmi.h>
 101 #include <linux/slab.h>
 102 #include <linux/wait.h>
 103 #include <linux/err.h>
 104 #include <linux/platform_device.h>
 105 #include <linux/platform_data/itco_wdt.h>
 106 #include <linux/pm_runtime.h>
 107
 108 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 109 #include <linux/gpio.h>
 110 #include <linux/platform_data/i2c-mux-gpio.h>
 111 #endif
 112
 113 /* I801 SMBus address offsets */
 114 #define SMBHSTSTS(p)    (0 + (p)->smba)
 115 #define SMBHSTCNT(p)    (2 + (p)->smba)
 116 #define SMBHSTCMD(p)    (3 + (p)->smba)
 117 #define SMBHSTADD(p)    (4 + (p)->smba)
 118 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 119 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 120 #define SMBBLKDAT(p)    (7 + (p)->smba)
 121 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 122 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 123 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 124 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 125 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 126 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 127
 128 /* PCI Address Constants */
 129 #define SMBBAR          4
 130 #define SMBPCICTL       0x004
 131 #define SMBPCISTS       0x006
 132 #define SMBHSTCFG       0x040
 133 #define TCOBASE         0x050
 134 #define TCOCTL          0x054
 135
 136 #define ACPIBASE                0x040
 137 #define ACPIBASE_SMI_OFF        0x030
 138 #define ACPICTRL                0x044
 139 #define ACPICTRL_EN             0x080
 140
 141 #define SBREG_BAR               0x10
 142 #define SBREG_SMBCTRL           0xc6000c
 143 #define SBREG_SMBCTRL_DNV       0xcf000c
 144
 145 /* Host status bits for SMBPCISTS */
 146 #define SMBPCISTS_INTS          BIT(3)
 147
 148 /* Control bits for SMBPCICTL */
 149 #define SMBPCICTL_INTDIS        BIT(10)
 150
 151 /* Host configuration bits for SMBHSTCFG */
 152 #define SMBHSTCFG_HST_EN        BIT(0)
 153 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 154 #define SMBHSTCFG_I2C_EN        BIT(2)
 155 #define SMBHSTCFG_SPD_WD        BIT(4)
 156
 157 /* TCO configuration bits for TCOCTL */
 158 #define TCOCTL_EN               BIT(8)
 159
 160 /* Auxiliary status register bits, ICH4+ only */
 161 #define SMBAUXSTS_CRCE          BIT(0)
 162 #define SMBAUXSTS_STCO          BIT(1)
 163
 164 /* Auxiliary control register bits, ICH4+ only */
 165 #define SMBAUXCTL_CRC           BIT(0)
 166 #define SMBAUXCTL_E32B          BIT(1)
 167
 168 /* Other settings */
 169 #define MAX_RETRIES             400
 170
 171 /* I801 command constants */
 172 #define I801_QUICK              0x00
 173 #define I801_BYTE               0x04
 174 #define I801_BYTE_DATA          0x08
 175 #define I801_WORD_DATA          0x0C
 176 #define I801_PROC_CALL          0x10    /* unimplemented */
 177 #define I801_BLOCK_DATA         0x14
 178 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 179
 180 /* I801 Host Control register bits */
 181 #define SMBHSTCNT_INTREN        BIT(0)
 182 #define SMBHSTCNT_KILL          BIT(1)
 183 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 184 #define SMBHSTCNT_START         BIT(6)
 185 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 186
 187 /* I801 Hosts Status register bits */
 188 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 189 #define SMBHSTSTS_INUSE_STS     BIT(6)
 190 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 191 #define SMBHSTSTS_FAILED        BIT(4)
 192 #define SMBHSTSTS_BUS_ERR       BIT(3)
 193 #define SMBHSTSTS_DEV_ERR       BIT(2)
 194 #define SMBHSTSTS_INTR          BIT(1)
 195 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 196
 197 /* Host Notify Status register bits */
 198 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 199
 200 /* Host Notify Command register bits */
 201 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 202
 203 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 204                                  SMBHSTSTS_DEV_ERR)
 205
 206 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 207                                  STATUS_ERROR_FLAGS)
 208
 209 /* Older devices have their ID defined in <linux/pci_ids.h> */
 210 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 211 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 212 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 213 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 215 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 219 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 220 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 221 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 222 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 223 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 224 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 225 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 226 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 227 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 228 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 229 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 230 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 231 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 232 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 233 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 234 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 235 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 236 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 237 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 238 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 239 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 240 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 241 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 242 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 243
 244 struct i801_mux_config {
 245         char *gpio_chip;
 246         unsigned values[3];
 247         int n_values;
 248         unsigned classes[3];
 249         unsigned gpios[2];              /* Relative to gpio_chip->base */
 250         int n_gpios;
 251 };
 252
 253 struct i801_priv {
 254         struct i2c_adapter adapter;
 255         unsigned long smba;
 256         unsigned char original_hstcfg;
 257         unsigned char original_slvcmd;
 258         struct pci_dev *pci_dev;
 259         unsigned int features;
 260
 261         /* isr processing */
 262         wait_queue_head_t waitq;
 263         u8 status;
 264
 265         /* Command state used by isr for byte-by-byte block transactions */
 266         u8 cmd;
 267         bool is_read;
 268         int count;
 269         int len;
 270         u8 *data;
 271
 272 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 273         const struct i801_mux_config *mux_drvdata;
 274         struct platform_device *mux_pdev;
 275 #endif
 276         struct platform_device *tco_pdev;
 277
 278         /*
 279          * If set to true the host controller registers are reserved for
 280          * ACPI AML use. Protected by acpi_lock.
 281          */
 282         bool acpi_reserved;
 283         struct mutex acpi_lock;
 284 };
 285
 286 #define FEATURE_SMBUS_PEC       BIT(0)
 287 #define FEATURE_BLOCK_BUFFER    BIT(1)
 288 #define FEATURE_BLOCK_PROC      BIT(2)
 289 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 290 #define FEATURE_IRQ             BIT(4)
 291 #define FEATURE_HOST_NOTIFY     BIT(5)
 292 /* Not really a feature, but it's convenient to handle it as such */
 293 #define FEATURE_IDF             BIT(15)
 294 #define FEATURE_TCO             BIT(16)
 295
 296 static const char *i801_feature_names[] = {
 297         "SMBus PEC",
 298         "Block buffer",
 299         "Block process call",
 300         "I2C block read",
 301         "Interrupt",
 302         "SMBus Host Notify",
 303 };
 304
 305 static unsigned int disable_features;
 306 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 307 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 308         "\t\t  0x01  disable SMBus PEC\n"
 309         "\t\t  0x02  disable the block buffer\n"
 310         "\t\t  0x08  disable the I2C block read functionality\n"
 311         "\t\t  0x10  don't use interrupts\n"
 312         "\t\t  0x20  disable SMBus Host Notify ");
 313
 314 /* Make sure the SMBus host is ready to start transmitting.
 315    Return 0 if it is, -EBUSY if it is not. */
 316 static int i801_check_pre(struct i801_priv *priv)
 317 {
 318         int status;
 319
 320         status = inb_p(SMBHSTSTS(priv));
 321         if (status & SMBHSTSTS_HOST_BUSY) {
 322                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 323                 return -EBUSY;
 324         }
 325
 326         status &= STATUS_FLAGS;
 327         if (status) {
 328                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 329                         status);
 330                 outb_p(status, SMBHSTSTS(priv));
 331                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 332                 if (status) {
 333                         dev_err(&priv->pci_dev->dev,
 334                                 "Failed clearing status flags (%02x)\n",
 335                                 status);
 336                         return -EBUSY;
 337                 }
 338         }
 339
 340         /*
 341          * Clear CRC status if needed.
 342          * During normal operation, i801_check_post() takes care
 343          * of it after every operation.  We do it here only in case
 344          * the hardware was already in this state when the driver
 345          * started.
 346          */
 347         if (priv->features & FEATURE_SMBUS_PEC) {
 348                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 349                 if (status) {
 350                         dev_dbg(&priv->pci_dev->dev,
 351                                 "Clearing aux status flags (%02x)\n", status);
 352                         outb_p(status, SMBAUXSTS(priv));
 353                         status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 354                         if (status) {
 355                                 dev_err(&priv->pci_dev->dev,
 356                                         "Failed clearing aux status flags (%02x)\n",
 357                                         status);
 358                                 return -EBUSY;
 359                         }
 360                 }
 361         }
 362
 363         return 0;
 364 }
 365
 366 /*
 367  * Convert the status register to an error code, and clear it.
 368  * Note that status only contains the bits we want to clear, not the
 369  * actual register value.
 370  */
 371 static int i801_check_post(struct i801_priv *priv, int status)
 372 {
 373         int result = 0;
 374
 375         /*
 376          * If the SMBus is still busy, we give up
 377          * Note: This timeout condition only happens when using polling
 378          * transactions.  For interrupt operation, NAK/timeout is indicated by
 379          * DEV_ERR.
 380          */
 381         if (unlikely(status < 0)) {
 382                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 383                 /* try to stop the current command */
 384                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 385                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 386                        SMBHSTCNT(priv));
 387                 usleep_range(1000, 2000);
 388                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 389                        SMBHSTCNT(priv));
 390
 391                 /* Check if it worked */
 392                 status = inb_p(SMBHSTSTS(priv));
 393                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 394                     !(status & SMBHSTSTS_FAILED))
 395                         dev_err(&priv->pci_dev->dev,
 396                                 "Failed terminating the transaction\n");
 397                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 398                 return -ETIMEDOUT;
 399         }
 400
 401         if (status & SMBHSTSTS_FAILED) {
 402                 result = -EIO;
 403                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 404         }
 405         if (status & SMBHSTSTS_DEV_ERR) {
 406                 /*
 407                  * This may be a PEC error, check and clear it.
 408                  *
 409                  * AUXSTS is handled differently from HSTSTS.
 410                  * For HSTSTS, i801_isr() or i801_wait_intr()
 411                  * has already cleared the error bits in hardware,
 412                  * and we are passed a copy of the original value
 413                  * in "status".
 414                  * For AUXSTS, the hardware register is left
 415                  * for us to handle here.
 416                  * This is asymmetric, slightly iffy, but safe,
 417                  * since all this code is serialized and the CRCE
 418                  * bit is harmless as long as it's cleared before
 419                  * the next operation.
 420                  */
 421                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 422                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 423                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 424                         result = -EBADMSG;
 425                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 426                 } else {
 427                         result = -ENXIO;
 428                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 429                 }
 430         }
 431         if (status & SMBHSTSTS_BUS_ERR) {
 432                 result = -EAGAIN;
 433                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 434         }
 435
 436         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 437         outb_p(status, SMBHSTSTS(priv));
 438
 439         return result;
 440 }
 441
 442 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 443 static int i801_wait_intr(struct i801_priv *priv)
 444 {
 445         int timeout = 0;
 446         int status;
 447
 448         /* We will always wait for a fraction of a second! */
 449         do {
 450                 usleep_range(250, 500);
 451                 status = inb_p(SMBHSTSTS(priv));
 452         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 453                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 454                  (timeout++ < MAX_RETRIES));
 455
 456         if (timeout > MAX_RETRIES) {
 457                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 458                 return -ETIMEDOUT;
 459         }
 460         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 461 }
 462
 463 /* Wait for either BYTE_DONE or an error flag being set */
 464 static int i801_wait_byte_done(struct i801_priv *priv)
 465 {
 466         int timeout = 0;
 467         int status;
 468
 469         /* We will always wait for a fraction of a second! */
 470         do {
 471                 usleep_range(250, 500);
 472                 status = inb_p(SMBHSTSTS(priv));
 473         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 474                  (timeout++ < MAX_RETRIES));
 475
 476         if (timeout > MAX_RETRIES) {
 477                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 478                 return -ETIMEDOUT;
 479         }
 480         return status & STATUS_ERROR_FLAGS;
 481 }
 482
 483 static int i801_transaction(struct i801_priv *priv, int xact)
 484 {
 485         int status;
 486         int result;
 487         const struct i2c_adapter *adap = &priv->adapter;
 488
 489         result = i801_check_pre(priv);
 490         if (result < 0)
 491                 return result;
 492
 493         if (priv->features & FEATURE_IRQ) {
 494                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 495                        SMBHSTCNT(priv));
 496                 result = wait_event_timeout(priv->waitq,
 497                                             (status = priv->status),
 498                                             adap->timeout);
 499                 if (!result) {
 500                         status = -ETIMEDOUT;
 501                         dev_warn(&priv->pci_dev->dev,
 502                                  "Timeout waiting for interrupt!\n");
 503                 }
 504                 priv->status = 0;
 505                 return i801_check_post(priv, status);
 506         }
 507
 508         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 509          * SMBSCMD are passed in xact */
 510         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 511
 512         status = i801_wait_intr(priv);
 513         return i801_check_post(priv, status);
 514 }
 515
 516 static int i801_block_transaction_by_block(struct i801_priv *priv,
 517                                            union i2c_smbus_data *data,
 518                                            char read_write, int hwpec)
 519 {
 520         int i, len;
 521         int status;
 522
 523         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 524
 525         /* Use 32-byte buffer to process this transaction */
 526         if (read_write == I2C_SMBUS_WRITE) {
 527                 len = data->block[0];
 528                 outb_p(len, SMBHSTDAT0(priv));
 529                 for (i = 0; i < len; i++)
 530                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 531         }
 532
 533         status = i801_transaction(priv, I801_BLOCK_DATA |
 534                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 535         if (status)
 536                 return status;
 537
 538         if (read_write == I2C_SMBUS_READ) {
 539                 len = inb_p(SMBHSTDAT0(priv));
 540                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 541                         return -EPROTO;
 542
 543                 data->block[0] = len;
 544                 for (i = 0; i < len; i++)
 545                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 546         }
 547         return 0;
 548 }
 549
 550 static void i801_isr_byte_done(struct i801_priv *priv)
 551 {
 552         if (priv->is_read) {
 553                 /* For SMBus block reads, length is received with first byte */
 554                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 555                     (priv->count == 0)) {
 556                         priv->len = inb_p(SMBHSTDAT0(priv));
 557                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 558                                 dev_err(&priv->pci_dev->dev,
 559                                         "Illegal SMBus block read size %d\n",
 560                                         priv->len);
 561                                 /* FIXME: Recover */
 562                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 563                         } else {
 564                                 dev_dbg(&priv->pci_dev->dev,
 565                                         "SMBus block read size is %d\n",
 566                                         priv->len);
 567                         }
 568                         priv->data[-1] = priv->len;
 569                 }
 570
 571                 /* Read next byte */
 572                 if (priv->count < priv->len)
 573                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 574                 else
 575                         dev_dbg(&priv->pci_dev->dev,
 576                                 "Discarding extra byte on block read\n");
 577
 578                 /* Set LAST_BYTE for last byte of read transaction */
 579                 if (priv->count == priv->len - 1)
 580                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 581                                SMBHSTCNT(priv));
 582         } else if (priv->count < priv->len - 1) {
 583                 /* Write next byte, except for IRQ after last byte */
 584                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 585         }
 586
 587         /* Clear BYTE_DONE to continue with next byte */
 588         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 589 }
 590
 591 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 592 {
 593         unsigned short addr;
 594
 595         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 596
 597         /*
 598          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 599          * always returns 0. Our current implementation doesn't provide
 600          * data, so we just ignore it.
 601          */
 602         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 603
 604         /* clear Host Notify bit and return */
 605         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 606         return IRQ_HANDLED;
 607 }
 608
 609 /*
 610  * There are three kinds of interrupts:
 611  *
 612  * 1) i801 signals transaction completion with one of these interrupts:
 613  *      INTR - Success
 614  *      DEV_ERR - Invalid command, NAK or communication timeout
 615  *      BUS_ERR - SMI# transaction collision
 616  *      FAILED - transaction was canceled due to a KILL request
 617  *    When any of these occur, update ->status and wake up the waitq.
 618  *    ->status must be cleared before kicking off the next transaction.
 619  *
 620  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 621  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 622  *
 623  * 3) Host Notify interrupts
 624  */
 625 static irqreturn_t i801_isr(int irq, void *dev_id)
 626 {
 627         struct i801_priv *priv = dev_id;
 628         u16 pcists;
 629         u8 status;
 630
 631         /* Confirm this is our interrupt */
 632         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 633         if (!(pcists & SMBPCISTS_INTS))
 634                 return IRQ_NONE;
 635
 636         if (priv->features & FEATURE_HOST_NOTIFY) {
 637                 status = inb_p(SMBSLVSTS(priv));
 638                 if (status & SMBSLVSTS_HST_NTFY_STS)
 639                         return i801_host_notify_isr(priv);
 640         }
 641
 642         status = inb_p(SMBHSTSTS(priv));
 643         if (status & SMBHSTSTS_BYTE_DONE)
 644                 i801_isr_byte_done(priv);
 645
 646         /*
 647          * Clear irq sources and report transaction result.
 648          * ->status must be cleared before the next transaction is started.
 649          */
 650         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 651         if (status) {
 652                 outb_p(status, SMBHSTSTS(priv));
 653                 priv->status = status;
 654                 wake_up(&priv->waitq);
 655         }
 656
 657         return IRQ_HANDLED;
 658 }
 659
 660 /*
 661  * For "byte-by-byte" block transactions:
 662  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 663  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 664  */
 665 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 666                                                union i2c_smbus_data *data,
 667                                                char read_write, int command,
 668                                                int hwpec)
 669 {
 670         int i, len;
 671         int smbcmd;
 672         int status;
 673         int result;
 674         const struct i2c_adapter *adap = &priv->adapter;
 675
 676         result = i801_check_pre(priv);
 677         if (result < 0)
 678                 return result;
 679
 680         len = data->block[0];
 681
 682         if (read_write == I2C_SMBUS_WRITE) {
 683                 outb_p(len, SMBHSTDAT0(priv));
 684                 outb_p(data->block[1], SMBBLKDAT(priv));
 685         }
 686
 687         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 688             read_write == I2C_SMBUS_READ)
 689                 smbcmd = I801_I2C_BLOCK_DATA;
 690         else
 691                 smbcmd = I801_BLOCK_DATA;
 692
 693         if (priv->features & FEATURE_IRQ) {
 694                 priv->is_read = (read_write == I2C_SMBUS_READ);
 695                 if (len == 1 && priv->is_read)
 696                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 697                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 698                 priv->len = len;
 699                 priv->count = 0;
 700                 priv->data = &data->block[1];
 701
 702                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 703                 result = wait_event_timeout(priv->waitq,
 704                                             (status = priv->status),
 705                                             adap->timeout);
 706                 if (!result) {
 707                         status = -ETIMEDOUT;
 708                         dev_warn(&priv->pci_dev->dev,
 709                                  "Timeout waiting for interrupt!\n");
 710                 }
 711                 priv->status = 0;
 712                 return i801_check_post(priv, status);
 713         }
 714
 715         for (i = 1; i <= len; i++) {
 716                 if (i == len && read_write == I2C_SMBUS_READ)
 717                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 718                 outb_p(smbcmd, SMBHSTCNT(priv));
 719
 720                 if (i == 1)
 721                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 722                                SMBHSTCNT(priv));
 723
 724                 status = i801_wait_byte_done(priv);
 725                 if (status)
 726                         goto exit;
 727
 728                 if (i == 1 && read_write == I2C_SMBUS_READ
 729                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 730                         len = inb_p(SMBHSTDAT0(priv));
 731                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 732                                 dev_err(&priv->pci_dev->dev,
 733                                         "Illegal SMBus block read size %d\n",
 734                                         len);
 735                                 /* Recover */
 736                                 while (inb_p(SMBHSTSTS(priv)) &
 737                                        SMBHSTSTS_HOST_BUSY)
 738                                         outb_p(SMBHSTSTS_BYTE_DONE,
 739                                                SMBHSTSTS(priv));
 740                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 741                                 return -EPROTO;
 742                         }
 743                         data->block[0] = len;
 744                 }
 745
 746                 /* Retrieve/store value in SMBBLKDAT */
 747                 if (read_write == I2C_SMBUS_READ)
 748                         data->block[i] = inb_p(SMBBLKDAT(priv));
 749                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 750                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 751
 752                 /* signals SMBBLKDAT ready */
 753                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 754         }
 755
 756         status = i801_wait_intr(priv);
 757 exit:
 758         return i801_check_post(priv, status);
 759 }
 760
 761 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 762 {
 763         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 764         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 765                 return -EIO;
 766         return 0;
 767 }
 768
 769 /* Block transaction function */
 770 static int i801_block_transaction(struct i801_priv *priv,
 771                                   union i2c_smbus_data *data, char read_write,
 772                                   int command, int hwpec)
 773 {
 774         int result = 0;
 775         unsigned char hostc;
 776
 777         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 778                 if (read_write == I2C_SMBUS_WRITE) {
 779                         /* set I2C_EN bit in configuration register */
 780                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 781                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 782                                               hostc | SMBHSTCFG_I2C_EN);
 783                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 784                         dev_err(&priv->pci_dev->dev,
 785                                 "I2C block read is unsupported!\n");
 786                         return -EOPNOTSUPP;
 787                 }
 788         }
 789
 790         if (read_write == I2C_SMBUS_WRITE
 791          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 792                 if (data->block[0] < 1)
 793                         data->block[0] = 1;
 794                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 795                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 796         } else {
 797                 data->block[0] = 32;    /* max for SMBus block reads */
 798         }
 799
 800         /* Experience has shown that the block buffer can only be used for
 801            SMBus (not I2C) block transactions, even though the datasheet
 802            doesn't mention this limitation. */
 803         if ((priv->features & FEATURE_BLOCK_BUFFER)
 804          && command != I2C_SMBUS_I2C_BLOCK_DATA
 805          && i801_set_block_buffer_mode(priv) == 0)
 806                 result = i801_block_transaction_by_block(priv, data,
 807                                                          read_write, hwpec);
 808         else
 809                 result = i801_block_transaction_byte_by_byte(priv, data,
 810                                                              read_write,
 811                                                              command, hwpec);
 812
 813         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 814          && read_write == I2C_SMBUS_WRITE) {
 815                 /* restore saved configuration register value */
 816                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 817         }
 818         return result;
 819 }
 820
 821 /* Return negative errno on error. */
 822 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 823                        unsigned short flags, char read_write, u8 command,
 824                        int size, union i2c_smbus_data *data)
 825 {
 826         int hwpec;
 827         int block = 0;
 828         int ret = 0, xact = 0;
 829         struct i801_priv *priv = i2c_get_adapdata(adap);
 830
 831         mutex_lock(&priv->acpi_lock);
 832         if (priv->acpi_reserved) {
 833                 mutex_unlock(&priv->acpi_lock);
 834                 return -EBUSY;
 835         }
 836
 837         pm_runtime_get_sync(&priv->pci_dev->dev);
 838
 839         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 840                 && size != I2C_SMBUS_QUICK
 841                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 842
 843         switch (size) {
 844         case I2C_SMBUS_QUICK:
 845                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 846                        SMBHSTADD(priv));
 847                 xact = I801_QUICK;
 848                 break;
 849         case I2C_SMBUS_BYTE:
 850                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 851                        SMBHSTADD(priv));
 852                 if (read_write == I2C_SMBUS_WRITE)
 853                         outb_p(command, SMBHSTCMD(priv));
 854                 xact = I801_BYTE;
 855                 break;
 856         case I2C_SMBUS_BYTE_DATA:
 857                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 858                        SMBHSTADD(priv));
 859                 outb_p(command, SMBHSTCMD(priv));
 860                 if (read_write == I2C_SMBUS_WRITE)
 861                         outb_p(data->byte, SMBHSTDAT0(priv));
 862                 xact = I801_BYTE_DATA;
 863                 break;
 864         case I2C_SMBUS_WORD_DATA:
 865                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 866                        SMBHSTADD(priv));
 867                 outb_p(command, SMBHSTCMD(priv));
 868                 if (read_write == I2C_SMBUS_WRITE) {
 869                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 870                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 871                 }
 872                 xact = I801_WORD_DATA;
 873                 break;
 874         case I2C_SMBUS_BLOCK_DATA:
 875                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 876                        SMBHSTADD(priv));
 877                 outb_p(command, SMBHSTCMD(priv));
 878                 block = 1;
 879                 break;
 880         case I2C_SMBUS_I2C_BLOCK_DATA:
 881                 /*
 882                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 883                  * bit should be cleared here, even when reading.
 884                  * However if SPD Write Disable is set (Lynx Point and later),
 885                  * the read will fail if we don't set the R/#W bit.
 886                  */
 887                 outb_p(((addr & 0x7f) << 1) |
 888                        ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 889                         (read_write & 0x01) : 0),
 890                        SMBHSTADD(priv));
 891                 if (read_write == I2C_SMBUS_READ) {
 892                         /* NB: page 240 of ICH5 datasheet also shows
 893                          * that DATA1 is the cmd field when reading */
 894                         outb_p(command, SMBHSTDAT1(priv));
 895                 } else
 896                         outb_p(command, SMBHSTCMD(priv));
 897                 block = 1;
 898                 break;
 899         default:
 900                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 901                         size);
 902                 ret = -EOPNOTSUPP;
 903                 goto out;
 904         }
 905
 906         if (hwpec)      /* enable/disable hardware PEC */
 907                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 908         else
 909                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 910                        SMBAUXCTL(priv));
 911
 912         if (block)
 913                 ret = i801_block_transaction(priv, data, read_write, size,
 914                                              hwpec);
 915         else
 916                 ret = i801_transaction(priv, xact);
 917
 918         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 919            time, so we forcibly disable it after every transaction. Turn off
 920            E32B for the same reason. */
 921         if (hwpec || block)
 922                 outb_p(inb_p(SMBAUXCTL(priv)) &
 923                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 924
 925         if (block)
 926                 goto out;
 927         if (ret)
 928                 goto out;
 929         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 930                 goto out;
 931
 932         switch (xact & 0x7f) {
 933         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 934         case I801_BYTE_DATA:
 935                 data->byte = inb_p(SMBHSTDAT0(priv));
 936                 break;
 937         case I801_WORD_DATA:
 938                 data->word = inb_p(SMBHSTDAT0(priv)) +
 939                              (inb_p(SMBHSTDAT1(priv)) << 8);
 940                 break;
 941         }
 942
 943 out:
 944         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 945         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 946         mutex_unlock(&priv->acpi_lock);
 947         return ret;
 948 }
 949
 950
 951 static u32 i801_func(struct i2c_adapter *adapter)
 952 {
 953         struct i801_priv *priv = i2c_get_adapdata(adapter);
 954
 955         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 956                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 957                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 958                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 959                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 960                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 961                ((priv->features & FEATURE_HOST_NOTIFY) ?
 962                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 963 }
 964
 965 static void i801_enable_host_notify(struct i2c_adapter *adapter)
 966 {
 967         struct i801_priv *priv = i2c_get_adapdata(adapter);
 968
 969         if (!(priv->features & FEATURE_HOST_NOTIFY))
 970                 return;
 971
 972         if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
 973                 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
 974                        SMBSLVCMD(priv));
 975
 976         /* clear Host Notify bit to allow a new notification */
 977         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 978 }
 979
 980 static void i801_disable_host_notify(struct i801_priv *priv)
 981 {
 982         if (!(priv->features & FEATURE_HOST_NOTIFY))
 983                 return;
 984
 985         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
 986 }
 987
 988 static const struct i2c_algorithm smbus_algorithm = {
 989         .smbus_xfer     = i801_access,
 990         .functionality  = i801_func,
 991 };
 992
 993 static const struct pci_device_id i801_ids[] = {
 994         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 995         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 996         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 997         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 998         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 999         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1000         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1001         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1002         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1003         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1004         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1005         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1006         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1007         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1008         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1009         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1010         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1011         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1012         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1013         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1014         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1015         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1016         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1017         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1018         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1019         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1020         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1021         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1022         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1023         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1024         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1025         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1026         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1027         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1028         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1029         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1030         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1031         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1032         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1033         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1034         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1035         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1036         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1037         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1038         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1039         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1040         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1041         { 0, }
1042 };
1043
1044 MODULE_DEVICE_TABLE(pci, i801_ids);
1045
1046 #if defined CONFIG_X86 && defined CONFIG_DMI
1047 static unsigned char apanel_addr;
1048
1049 /* Scan the system ROM for the signature "FJKEYINF" */
1050 static __init const void __iomem *bios_signature(const void __iomem *bios)
1051 {
1052         ssize_t offset;
1053         const unsigned char signature[] = "FJKEYINF";
1054
1055         for (offset = 0; offset < 0x10000; offset += 0x10) {
1056                 if (check_signature(bios + offset, signature,
1057                                     sizeof(signature)-1))
1058                         return bios + offset;
1059         }
1060         return NULL;
1061 }
1062
1063 static void __init input_apanel_init(void)
1064 {
1065         void __iomem *bios;
1066         const void __iomem *p;
1067
1068         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1069         p = bios_signature(bios);
1070         if (p) {
1071                 /* just use the first address */
1072                 apanel_addr = readb(p + 8 + 3) >> 1;
1073         }
1074         iounmap(bios);
1075 }
1076
1077 struct dmi_onboard_device_info {
1078         const char *name;
1079         u8 type;
1080         unsigned short i2c_addr;
1081         const char *i2c_type;
1082 };
1083
1084 static const struct dmi_onboard_device_info dmi_devices[] = {
1085         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1086         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1087         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1088 };
1089
1090 static void dmi_check_onboard_device(u8 type, const char *name,
1091                                      struct i2c_adapter *adap)
1092 {
1093         int i;
1094         struct i2c_board_info info;
1095
1096         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1097                 /* & ~0x80, ignore enabled/disabled bit */
1098                 if ((type & ~0x80) != dmi_devices[i].type)
1099                         continue;
1100                 if (strcasecmp(name, dmi_devices[i].name))
1101                         continue;
1102
1103                 memset(&info, 0, sizeof(struct i2c_board_info));
1104                 info.addr = dmi_devices[i].i2c_addr;
1105                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1106                 i2c_new_device(adap, &info);
1107                 break;
1108         }
1109 }
1110
1111 /* We use our own function to check for onboard devices instead of
1112    dmi_find_device() as some buggy BIOS's have the devices we are interested
1113    in marked as disabled */
1114 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1115 {
1116         int i, count;
1117
1118         if (dm->type != 10)
1119                 return;
1120
1121         count = (dm->length - sizeof(struct dmi_header)) / 2;
1122         for (i = 0; i < count; i++) {
1123                 const u8 *d = (char *)(dm + 1) + (i * 2);
1124                 const char *name = ((char *) dm) + dm->length;
1125                 u8 type = d[0];
1126                 u8 s = d[1];
1127
1128                 if (!s)
1129                         continue;
1130                 s--;
1131                 while (s > 0 && name[0]) {
1132                         name += strlen(name) + 1;
1133                         s--;
1134                 }
1135                 if (name[0] == 0) /* Bogus string reference */
1136                         continue;
1137
1138                 dmi_check_onboard_device(type, name, adap);
1139         }
1140 }
1141
1142 /* Register optional slaves */
1143 static void i801_probe_optional_slaves(struct i801_priv *priv)
1144 {
1145         /* Only register slaves on main SMBus channel */
1146         if (priv->features & FEATURE_IDF)
1147                 return;
1148
1149         if (apanel_addr) {
1150                 struct i2c_board_info info;
1151
1152                 memset(&info, 0, sizeof(struct i2c_board_info));
1153                 info.addr = apanel_addr;
1154                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1155                 i2c_new_device(&priv->adapter, &info);
1156         }
1157
1158         if (dmi_name_in_vendors("FUJITSU"))
1159                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1160 }
1161 #else
1162 static void __init input_apanel_init(void) {}
1163 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1164 #endif  /* CONFIG_X86 && CONFIG_DMI */
1165
1166 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1167 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1168         .gpio_chip = "gpio_ich",
1169         .values = { 0x02, 0x03 },
1170         .n_values = 2,
1171         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1172         .gpios = { 52, 53 },
1173         .n_gpios = 2,
1174 };
1175
1176 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1177         .gpio_chip = "gpio_ich",
1178         .values = { 0x02, 0x03, 0x01 },
1179         .n_values = 3,
1180         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1181         .gpios = { 52, 53 },
1182         .n_gpios = 2,
1183 };
1184
1185 static const struct dmi_system_id mux_dmi_table[] = {
1186         {
1187                 .matches = {
1188                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1189                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1190                 },
1191                 .driver_data = &i801_mux_config_asus_z8_d12,
1192         },
1193         {
1194                 .matches = {
1195                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1196                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1197                 },
1198                 .driver_data = &i801_mux_config_asus_z8_d12,
1199         },
1200         {
1201                 .matches = {
1202                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1203                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1204                 },
1205                 .driver_data = &i801_mux_config_asus_z8_d12,
1206         },
1207         {
1208                 .matches = {
1209                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1210                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1211                 },
1212                 .driver_data = &i801_mux_config_asus_z8_d12,
1213         },
1214         {
1215                 .matches = {
1216                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1217                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1218                 },
1219                 .driver_data = &i801_mux_config_asus_z8_d12,
1220         },
1221         {
1222                 .matches = {
1223                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1224                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1225                 },
1226                 .driver_data = &i801_mux_config_asus_z8_d12,
1227         },
1228         {
1229                 .matches = {
1230                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1231                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1232                 },
1233                 .driver_data = &i801_mux_config_asus_z8_d18,
1234         },
1235         {
1236                 .matches = {
1237                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1238                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1239                 },
1240                 .driver_data = &i801_mux_config_asus_z8_d18,
1241         },
1242         {
1243                 .matches = {
1244                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1245                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1246                 },
1247                 .driver_data = &i801_mux_config_asus_z8_d12,
1248         },
1249         { }
1250 };
1251
1252 /* Setup multiplexing if needed */
1253 static int i801_add_mux(struct i801_priv *priv)
1254 {
1255         struct device *dev = &priv->adapter.dev;
1256         const struct i801_mux_config *mux_config;
1257         struct i2c_mux_gpio_platform_data gpio_data;
1258         int err;
1259
1260         if (!priv->mux_drvdata)
1261                 return 0;
1262         mux_config = priv->mux_drvdata;
1263
1264         /* Prepare the platform data */
1265         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1266         gpio_data.parent = priv->adapter.nr;
1267         gpio_data.values = mux_config->values;
1268         gpio_data.n_values = mux_config->n_values;
1269         gpio_data.classes = mux_config->classes;
1270         gpio_data.gpio_chip = mux_config->gpio_chip;
1271         gpio_data.gpios = mux_config->gpios;
1272         gpio_data.n_gpios = mux_config->n_gpios;
1273         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1274
1275         /* Register the mux device */
1276         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1277                                 PLATFORM_DEVID_AUTO, &gpio_data,
1278                                 sizeof(struct i2c_mux_gpio_platform_data));
1279         if (IS_ERR(priv->mux_pdev)) {
1280                 err = PTR_ERR(priv->mux_pdev);
1281                 priv->mux_pdev = NULL;
1282                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1283                 return err;
1284         }
1285
1286         return 0;
1287 }
1288
1289 static void i801_del_mux(struct i801_priv *priv)
1290 {
1291         if (priv->mux_pdev)
1292                 platform_device_unregister(priv->mux_pdev);
1293 }
1294
1295 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1296 {
1297         const struct dmi_system_id *id;
1298         const struct i801_mux_config *mux_config;
1299         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1300         int i;
1301
1302         id = dmi_first_match(mux_dmi_table);
1303         if (id) {
1304                 /* Remove branch classes from trunk */
1305                 mux_config = id->driver_data;
1306                 for (i = 0; i < mux_config->n_values; i++)
1307                         class &= ~mux_config->classes[i];
1308
1309                 /* Remember for later */
1310                 priv->mux_drvdata = mux_config;
1311         }
1312
1313         return class;
1314 }
1315 #else
1316 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1317 static inline void i801_del_mux(struct i801_priv *priv) { }
1318
1319 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1320 {
1321         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1322 }
1323 #endif
1324
1325 static const struct itco_wdt_platform_data tco_platform_data = {
1326         .name = "Intel PCH",
1327         .version = 4,
1328 };
1329
1330 static DEFINE_SPINLOCK(p2sb_spinlock);
1331
1332 static void i801_add_tco(struct i801_priv *priv)
1333 {
1334         struct pci_dev *pci_dev = priv->pci_dev;
1335         struct resource tco_res[3], *res;
1336         struct platform_device *pdev;
1337         unsigned int devfn;
1338         u32 tco_base, tco_ctl;
1339         u32 base_addr, ctrl_val;
1340         u64 base64_addr;
1341         u8 hidden;
1342
1343         if (!(priv->features & FEATURE_TCO))
1344                 return;
1345
1346         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1347         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1348         if (!(tco_ctl & TCOCTL_EN))
1349                 return;
1350
1351         memset(tco_res, 0, sizeof(tco_res));
1352
1353         res = &tco_res[ICH_RES_IO_TCO];
1354         res->start = tco_base & ~1;
1355         res->end = res->start + 32 - 1;
1356         res->flags = IORESOURCE_IO;
1357
1358         /*
1359          * Power Management registers.
1360          */
1361         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1362         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1363
1364         res = &tco_res[ICH_RES_IO_SMI];
1365         res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1366         res->end = res->start + 3;
1367         res->flags = IORESOURCE_IO;
1368
1369         /*
1370          * Enable the ACPI I/O space.
1371          */
1372         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1373         ctrl_val |= ACPICTRL_EN;
1374         pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1375
1376         /*
1377          * We must access the NO_REBOOT bit over the Primary to Sideband
1378          * bridge (P2SB). The BIOS prevents the P2SB device from being
1379          * enumerated by the PCI subsystem, so we need to unhide/hide it
1380          * to lookup the P2SB BAR.
1381          */
1382         spin_lock(&p2sb_spinlock);
1383
1384         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1385
1386         /* Unhide the P2SB device, if it is hidden */
1387         pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1388         if (hidden)
1389                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1390
1391         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1392         base64_addr = base_addr & 0xfffffff0;
1393
1394         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1395         base64_addr |= (u64)base_addr << 32;
1396
1397         /* Hide the P2SB device, if it was hidden before */
1398         if (hidden)
1399                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1400         spin_unlock(&p2sb_spinlock);
1401
1402         res = &tco_res[ICH_RES_MEM_OFF];
1403         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1404                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1405         else
1406                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1407
1408         res->end = res->start + 3;
1409         res->flags = IORESOURCE_MEM;
1410
1411         pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1412                                                  tco_res, 3, &tco_platform_data,
1413                                                  sizeof(tco_platform_data));
1414         if (IS_ERR(pdev)) {
1415                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1416                 return;
1417         }
1418
1419         priv->tco_pdev = pdev;
1420 }
1421
1422 #ifdef CONFIG_ACPI
1423 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1424                                       acpi_physical_address address)
1425 {
1426         return address >= priv->smba &&
1427                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1428 }
1429
1430 static acpi_status
1431 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1432                      u64 *value, void *handler_context, void *region_context)
1433 {
1434         struct i801_priv *priv = handler_context;
1435         struct pci_dev *pdev = priv->pci_dev;
1436         acpi_status status;
1437
1438         /*
1439          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1440          * further access from the driver itself. This device is now owned
1441          * by the system firmware.
1442          */
1443         mutex_lock(&priv->acpi_lock);
1444
1445         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1446                 priv->acpi_reserved = true;
1447
1448                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1449                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1450
1451                 /*
1452                  * BIOS is accessing the host controller so prevent it from
1453                  * suspending automatically from now on.
1454                  */
1455                 pm_runtime_get_sync(&pdev->dev);
1456         }
1457
1458         if ((function & ACPI_IO_MASK) == ACPI_READ)
1459                 status = acpi_os_read_port(address, (u32 *)value, bits);
1460         else
1461                 status = acpi_os_write_port(address, (u32)*value, bits);
1462
1463         mutex_unlock(&priv->acpi_lock);
1464
1465         return status;
1466 }
1467
1468 static int i801_acpi_probe(struct i801_priv *priv)
1469 {
1470         struct acpi_device *adev;
1471         acpi_status status;
1472
1473         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1474         if (adev) {
1475                 status = acpi_install_address_space_handler(adev->handle,
1476                                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1477                                 NULL, priv);
1478                 if (ACPI_SUCCESS(status))
1479                         return 0;
1480         }
1481
1482         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1483 }
1484
1485 static void i801_acpi_remove(struct i801_priv *priv)
1486 {
1487         struct acpi_device *adev;
1488
1489         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1490         if (!adev)
1491                 return;
1492
1493         acpi_remove_address_space_handler(adev->handle,
1494                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1495
1496         mutex_lock(&priv->acpi_lock);
1497         if (priv->acpi_reserved)
1498                 pm_runtime_put(&priv->pci_dev->dev);
1499         mutex_unlock(&priv->acpi_lock);
1500 }
1501 #else
1502 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1503 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1504 #endif
1505
1506 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1507 {
1508         unsigned char temp;
1509         int err, i;
1510         struct i801_priv *priv;
1511
1512         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1513         if (!priv)
1514                 return -ENOMEM;
1515
1516         i2c_set_adapdata(&priv->adapter, priv);
1517         priv->adapter.owner = THIS_MODULE;
1518         priv->adapter.class = i801_get_adapter_class(priv);
1519         priv->adapter.algo = &smbus_algorithm;
1520         priv->adapter.dev.parent = &dev->dev;
1521         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1522         priv->adapter.retries = 3;
1523         mutex_init(&priv->acpi_lock);
1524
1525         priv->pci_dev = dev;
1526         switch (dev->device) {
1527         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1528         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1529         case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1530         case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1531         case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1532         case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1533         case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1534         case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1535         case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1536         case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1537                 priv->features |= FEATURE_I2C_BLOCK_READ;
1538                 priv->features |= FEATURE_IRQ;
1539                 priv->features |= FEATURE_SMBUS_PEC;
1540                 priv->features |= FEATURE_BLOCK_BUFFER;
1541                 /* If we have ACPI based watchdog use that instead */
1542                 if (!acpi_has_watchdog())
1543                         priv->features |= FEATURE_TCO;
1544                 priv->features |= FEATURE_HOST_NOTIFY;
1545                 break;
1546
1547         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1548         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1549         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1550         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1551         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1552         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1553                 priv->features |= FEATURE_IDF;
1554                 /* fall through */
1555         default:
1556                 priv->features |= FEATURE_I2C_BLOCK_READ;
1557                 priv->features |= FEATURE_IRQ;
1558                 /* fall through */
1559         case PCI_DEVICE_ID_INTEL_82801DB_3:
1560                 priv->features |= FEATURE_SMBUS_PEC;
1561                 priv->features |= FEATURE_BLOCK_BUFFER;
1562                 /* fall through */
1563         case PCI_DEVICE_ID_INTEL_82801CA_3:
1564                 priv->features |= FEATURE_HOST_NOTIFY;
1565                 /* fall through */
1566         case PCI_DEVICE_ID_INTEL_82801BA_2:
1567         case PCI_DEVICE_ID_INTEL_82801AB_3:
1568         case PCI_DEVICE_ID_INTEL_82801AA_3:
1569                 break;
1570         }
1571
1572         /* Disable features on user request */
1573         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1574                 if (priv->features & disable_features & (1 << i))
1575                         dev_notice(&dev->dev, "%s disabled by user\n",
1576                                    i801_feature_names[i]);
1577         }
1578         priv->features &= ~disable_features;
1579
1580         err = pcim_enable_device(dev);
1581         if (err) {
1582                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1583                         err);
1584                 return err;
1585         }
1586         pcim_pin_device(dev);
1587
1588         /* Determine the address of the SMBus area */
1589         priv->smba = pci_resource_start(dev, SMBBAR);
1590         if (!priv->smba) {
1591                 dev_err(&dev->dev,
1592                         "SMBus base address uninitialized, upgrade BIOS\n");
1593                 return -ENODEV;
1594         }
1595
1596         if (i801_acpi_probe(priv))
1597                 return -ENODEV;
1598
1599         err = pcim_iomap_regions(dev, 1 << SMBBAR,
1600                                  dev_driver_string(&dev->dev));
1601         if (err) {
1602                 dev_err(&dev->dev,
1603                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1604                         priv->smba,
1605                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1606                 i801_acpi_remove(priv);
1607                 return err;
1608         }
1609
1610         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1611         priv->original_hstcfg = temp;
1612         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1613         if (!(temp & SMBHSTCFG_HST_EN)) {
1614                 dev_info(&dev->dev, "Enabling SMBus device\n");
1615                 temp |= SMBHSTCFG_HST_EN;
1616         }
1617         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1618
1619         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1620                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1621                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1622                 priv->features &= ~FEATURE_IRQ;
1623         }
1624         if (temp & SMBHSTCFG_SPD_WD)
1625                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1626
1627         /* Clear special mode bits */
1628         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1629                 outb_p(inb_p(SMBAUXCTL(priv)) &
1630                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1631
1632         /* Remember original Host Notify setting */
1633         if (priv->features & FEATURE_HOST_NOTIFY)
1634                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1635
1636         /* Default timeout in interrupt mode: 200 ms */
1637         priv->adapter.timeout = HZ / 5;
1638
1639         if (dev->irq == IRQ_NOTCONNECTED)
1640                 priv->features &= ~FEATURE_IRQ;
1641
1642         if (priv->features & FEATURE_IRQ) {
1643                 u16 pcictl, pcists;
1644
1645                 /* Complain if an interrupt is already pending */
1646                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1647                 if (pcists & SMBPCISTS_INTS)
1648                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1649
1650                 /* Check if interrupts have been disabled */
1651                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1652                 if (pcictl & SMBPCICTL_INTDIS) {
1653                         dev_info(&dev->dev, "Interrupts are disabled\n");
1654                         priv->features &= ~FEATURE_IRQ;
1655                 }
1656         }
1657
1658         if (priv->features & FEATURE_IRQ) {
1659                 init_waitqueue_head(&priv->waitq);
1660
1661                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1662                                        IRQF_SHARED,
1663                                        dev_driver_string(&dev->dev), priv);
1664                 if (err) {
1665                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1666                                 dev->irq, err);
1667                         priv->features &= ~FEATURE_IRQ;
1668                 }
1669         }
1670         dev_info(&dev->dev, "SMBus using %s\n",
1671                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1672
1673         i801_add_tco(priv);
1674
1675         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1676                 "SMBus I801 adapter at %04lx", priv->smba);
1677         err = i2c_add_adapter(&priv->adapter);
1678         if (err) {
1679                 i801_acpi_remove(priv);
1680                 return err;
1681         }
1682
1683         i801_enable_host_notify(&priv->adapter);
1684
1685         i801_probe_optional_slaves(priv);
1686         /* We ignore errors - multiplexing is optional */
1687         i801_add_mux(priv);
1688
1689         pci_set_drvdata(dev, priv);
1690
1691         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1692         pm_runtime_use_autosuspend(&dev->dev);
1693         pm_runtime_put_autosuspend(&dev->dev);
1694         pm_runtime_allow(&dev->dev);
1695
1696         return 0;
1697 }
1698
1699 static void i801_remove(struct pci_dev *dev)
1700 {
1701         struct i801_priv *priv = pci_get_drvdata(dev);
1702
1703         pm_runtime_forbid(&dev->dev);
1704         pm_runtime_get_noresume(&dev->dev);
1705
1706         i801_disable_host_notify(priv);
1707         i801_del_mux(priv);
1708         i2c_del_adapter(&priv->adapter);
1709         i801_acpi_remove(priv);
1710         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1711
1712         platform_device_unregister(priv->tco_pdev);
1713
1714         /*
1715          * do not call pci_disable_device(dev) since it can cause hard hangs on
1716          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1717          */
1718 }
1719
1720 static void i801_shutdown(struct pci_dev *dev)
1721 {
1722         struct i801_priv *priv = pci_get_drvdata(dev);
1723
1724         /* Restore config registers to avoid hard hang on some systems */
1725         i801_disable_host_notify(priv);
1726         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1727 }
1728
1729 #ifdef CONFIG_PM_SLEEP
1730 static int i801_suspend(struct device *dev)
1731 {
1732         struct pci_dev *pci_dev = to_pci_dev(dev);
1733         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1734
1735         pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1736         return 0;
1737 }
1738
1739 static int i801_resume(struct device *dev)
1740 {
1741         struct pci_dev *pci_dev = to_pci_dev(dev);
1742         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1743
1744         i801_enable_host_notify(&priv->adapter);
1745
1746         return 0;
1747 }
1748 #endif
1749
1750 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1751
1752 static struct pci_driver i801_driver = {
1753         .name           = "i801_smbus",
1754         .id_table       = i801_ids,
1755         .probe          = i801_probe,
1756         .remove         = i801_remove,
1757         .shutdown       = i801_shutdown,
1758         .driver         = {
1759                 .pm     = &i801_pm_ops,
1760         },
1761 };
1762
1763 static int __init i2c_i801_init(void)
1764 {
1765         if (dmi_name_in_vendors("FUJITSU"))
1766                 input_apanel_init();
1767         return pci_register_driver(&i801_driver);
1768 }
1769
1770 static void __exit i2c_i801_exit(void)
1771 {
1772         pci_unregister_driver(&i801_driver);
1773 }
1774
1775 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1776 MODULE_DESCRIPTION("I801 SMBus driver");
1777 MODULE_LICENSE("GPL");
1778
1779 module_init(i2c_i801_init);
1780 module_exit(i2c_i801_exit);