drivers/i2c/busses/i2c-meson.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * I2C bus driver for Amlogic Meson SoCs
   4  *
   5  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/completion.h>
  11 #include <linux/i2c.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/types.h>
  20
  21 /* Meson I2C register map */
  22 #define REG_CTRL                0x00
  23 #define REG_SLAVE_ADDR          0x04
  24 #define REG_TOK_LIST0           0x08
  25 #define REG_TOK_LIST1           0x0c
  26 #define REG_TOK_WDATA0          0x10
  27 #define REG_TOK_WDATA1          0x14
  28 #define REG_TOK_RDATA0          0x18
  29 #define REG_TOK_RDATA1          0x1c
  30
  31 /* Control register fields */
  32 #define REG_CTRL_START                  BIT(0)
  33 #define REG_CTRL_ACK_IGNORE             BIT(1)
  34 #define REG_CTRL_STATUS                 BIT(2)
  35 #define REG_CTRL_ERROR                  BIT(3)
  36 #define REG_CTRL_CLKDIV_SHIFT           12
  37 #define REG_CTRL_CLKDIV_MASK            GENMASK(21, REG_CTRL_CLKDIV_SHIFT)
  38 #define REG_CTRL_CLKDIVEXT_SHIFT        28
  39 #define REG_CTRL_CLKDIVEXT_MASK         GENMASK(29, REG_CTRL_CLKDIVEXT_SHIFT)
  40
  41 #define REG_SLV_ADDR_MASK               GENMASK(7, 0)
  42 #define REG_SLV_SDA_FILTER_MASK         GENMASK(10, 8)
  43 #define REG_SLV_SCL_FILTER_MASK         GENMASK(13, 11)
  44 #define REG_SLV_SCL_LOW_SHIFT           16
  45 #define REG_SLV_SCL_LOW_MASK            GENMASK(27, REG_SLV_SCL_LOW_SHIFT)
  46 #define REG_SLV_SCL_LOW_EN              BIT(28)
  47
  48 #define I2C_TIMEOUT_MS          500
  49 #define FILTER_DELAY            15
  50
  51 enum {
  52         TOKEN_END = 0,
  53         TOKEN_START,
  54         TOKEN_SLAVE_ADDR_WRITE,
  55         TOKEN_SLAVE_ADDR_READ,
  56         TOKEN_DATA,
  57         TOKEN_DATA_LAST,
  58         TOKEN_STOP,
  59 };
  60
  61 enum {
  62         STATE_IDLE,
  63         STATE_READ,
  64         STATE_WRITE,
  65 };
  66
  67 /**
  68  * struct meson_i2c - Meson I2C device private data
  69  *
  70  * @adap:       I2C adapter instance
  71  * @dev:        Pointer to device structure
  72  * @regs:       Base address of the device memory mapped registers
  73  * @clk:        Pointer to clock structure
  74  * @msg:        Pointer to the current I2C message
  75  * @state:      Current state in the driver state machine
  76  * @last:       Flag set for the last message in the transfer
  77  * @count:      Number of bytes to be sent/received in current transfer
  78  * @pos:        Current position in the send/receive buffer
  79  * @error:      Flag set when an error is received
  80  * @lock:       To avoid race conditions between irq handler and xfer code
  81  * @done:       Completion used to wait for transfer termination
  82  * @tokens:     Sequence of tokens to be written to the device
  83  * @num_tokens: Number of tokens
  84  * @data:       Pointer to the controller's platform data
  85  */
  86 struct meson_i2c {
  87         struct i2c_adapter      adap;
  88         struct device           *dev;
  89         void __iomem            *regs;
  90         struct clk              *clk;
  91
  92         struct i2c_msg          *msg;
  93         int                     state;
  94         bool                    last;
  95         int                     count;
  96         int                     pos;
  97         int                     error;
  98
  99         spinlock_t              lock;
 100         struct completion       done;
 101         u32                     tokens[2];
 102         int                     num_tokens;
 103
 104         const struct meson_i2c_data *data;
 105 };
 106
 107 struct meson_i2c_data {
 108         void (*set_clk_div)(struct meson_i2c *i2c, unsigned int freq);
 109 };
 110
 111 static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
 112                                u32 val)
 113 {
 114         u32 data;
 115
 116         data = readl(i2c->regs + reg);
 117         data &= ~mask;
 118         data |= val & mask;
 119         writel(data, i2c->regs + reg);
 120 }
 121
 122 static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
 123 {
 124         i2c->tokens[0] = 0;
 125         i2c->tokens[1] = 0;
 126         i2c->num_tokens = 0;
 127 }
 128
 129 static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
 130 {
 131         if (i2c->num_tokens < 8)
 132                 i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4);
 133         else
 134                 i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4);
 135
 136         i2c->num_tokens++;
 137 }
 138
 139 static void meson_gxbb_axg_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
 140 {
 141         unsigned long clk_rate = clk_get_rate(i2c->clk);
 142         unsigned int div_h, div_l;
 143
 144         /* According to I2C-BUS Spec 2.1, in FAST-MODE, the minimum LOW period is 1.3uS, and
 145          * minimum HIGH is least 0.6us.
 146          * For 400000 freq, the period is 2.5us. To keep within the specs, give 40% of period to
 147          * HIGH and 60% to LOW. This means HIGH at 1.0us and LOW 1.5us.
 148          * The same applies for Fast-mode plus, where LOW is 0.5us and HIGH is 0.26us.
 149          * Duty = H/(H + L) = 2/5
 150          */
 151         if (freq <= I2C_MAX_STANDARD_MODE_FREQ) {
 152                 div_h = DIV_ROUND_UP(clk_rate, freq);
 153                 div_l = DIV_ROUND_UP(div_h, 4);
 154                 div_h = DIV_ROUND_UP(div_h, 2) - FILTER_DELAY;
 155         } else {
 156                 div_h = DIV_ROUND_UP(clk_rate * 2, freq * 5) - FILTER_DELAY;
 157                 div_l = DIV_ROUND_UP(clk_rate * 3, freq * 5 * 2);
 158         }
 159
 160         /* clock divider has 12 bits */
 161         if (div_h > GENMASK(11, 0)) {
 162                 dev_err(i2c->dev, "requested bus frequency too low\n");
 163                 div_h = GENMASK(11, 0);
 164         }
 165         if (div_l > GENMASK(11, 0)) {
 166                 dev_err(i2c->dev, "requested bus frequency too low\n");
 167                 div_l = GENMASK(11, 0);
 168         }
 169
 170         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
 171                            FIELD_PREP(REG_CTRL_CLKDIV_MASK, div_h & GENMASK(9, 0)));
 172
 173         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
 174                            FIELD_PREP(REG_CTRL_CLKDIVEXT_MASK, div_h >> 10));
 175
 176         /* set SCL low delay */
 177         meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_MASK,
 178                            FIELD_PREP(REG_SLV_SCL_LOW_MASK, div_l));
 179
 180         /* Enable HIGH/LOW mode */
 181         meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_EN, REG_SLV_SCL_LOW_EN);
 182
 183         dev_dbg(i2c->dev, "%s: clk %lu, freq %u, divh %u, divl %u\n", __func__,
 184                 clk_rate, freq, div_h, div_l);
 185 }
 186
 187 static void meson6_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
 188 {
 189         unsigned long clk_rate = clk_get_rate(i2c->clk);
 190         unsigned int div;
 191
 192         div = DIV_ROUND_UP(clk_rate, freq);
 193         div -= FILTER_DELAY;
 194         div = DIV_ROUND_UP(div, 4);
 195
 196         /* clock divider has 12 bits */
 197         if (div > GENMASK(11, 0)) {
 198                 dev_err(i2c->dev, "requested bus frequency too low\n");
 199                 div = GENMASK(11, 0);
 200         }
 201
 202         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
 203                            FIELD_PREP(REG_CTRL_CLKDIV_MASK, div & GENMASK(9, 0)));
 204
 205         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
 206                            FIELD_PREP(REG_CTRL_CLKDIVEXT_MASK, div >> 10));
 207
 208         /* Disable HIGH/LOW mode */
 209         meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_EN, 0);
 210
 211         dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__,
 212                 clk_rate, freq, div);
 213 }
 214
 215 static void meson_i2c_get_data(struct meson_i2c *i2c, char *buf, int len)
 216 {
 217         u32 rdata0, rdata1;
 218         int i;
 219
 220         rdata0 = readl(i2c->regs + REG_TOK_RDATA0);
 221         rdata1 = readl(i2c->regs + REG_TOK_RDATA1);
 222
 223         dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
 224                 rdata0, rdata1, len);
 225
 226         for (i = 0; i < min(4, len); i++)
 227                 *buf++ = (rdata0 >> i * 8) & 0xff;
 228
 229         for (i = 4; i < min(8, len); i++)
 230                 *buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
 231 }
 232
 233 static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len)
 234 {
 235         u32 wdata0 = 0, wdata1 = 0;
 236         int i;
 237
 238         for (i = 0; i < min(4, len); i++)
 239                 wdata0 |= *buf++ << (i * 8);
 240
 241         for (i = 4; i < min(8, len); i++)
 242                 wdata1 |= *buf++ << ((i - 4) * 8);
 243
 244         writel(wdata0, i2c->regs + REG_TOK_WDATA0);
 245         writel(wdata1, i2c->regs + REG_TOK_WDATA1);
 246
 247         dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
 248                 wdata0, wdata1, len);
 249 }
 250
 251 static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
 252 {
 253         bool write = !(i2c->msg->flags & I2C_M_RD);
 254         int i;
 255
 256         i2c->count = min(i2c->msg->len - i2c->pos, 8);
 257
 258         for (i = 0; i < i2c->count - 1; i++)
 259                 meson_i2c_add_token(i2c, TOKEN_DATA);
 260
 261         if (i2c->count) {
 262                 if (write || i2c->pos + i2c->count < i2c->msg->len)
 263                         meson_i2c_add_token(i2c, TOKEN_DATA);
 264                 else
 265                         meson_i2c_add_token(i2c, TOKEN_DATA_LAST);
 266         }
 267
 268         if (write)
 269                 meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
 270
 271         if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len)
 272                 meson_i2c_add_token(i2c, TOKEN_STOP);
 273
 274         writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0);
 275         writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1);
 276 }
 277
 278 static void meson_i2c_transfer_complete(struct meson_i2c *i2c, u32 ctrl)
 279 {
 280         if (ctrl & REG_CTRL_ERROR) {
 281                 /*
 282                  * The bit is set when the IGNORE_NAK bit is cleared
 283                  * and the device didn't respond. In this case, the
 284                  * I2C controller automatically generates a STOP
 285                  * condition.
 286                  */
 287                 dev_dbg(i2c->dev, "error bit set\n");
 288                 i2c->error = -ENXIO;
 289                 i2c->state = STATE_IDLE;
 290         } else {
 291                 if (i2c->state == STATE_READ && i2c->count)
 292                         meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos,
 293                                            i2c->count);
 294
 295                 i2c->pos += i2c->count;
 296
 297                 if (i2c->pos >= i2c->msg->len)
 298                         i2c->state = STATE_IDLE;
 299         }
 300 }
 301
 302 static irqreturn_t meson_i2c_irq(int irqno, void *dev_id)
 303 {
 304         struct meson_i2c *i2c = dev_id;
 305         unsigned int ctrl;
 306
 307         spin_lock(&i2c->lock);
 308
 309         meson_i2c_reset_tokens(i2c);
 310         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
 311         ctrl = readl(i2c->regs + REG_CTRL);
 312
 313         dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n",
 314                 i2c->state, i2c->pos, i2c->count, ctrl);
 315
 316         if (i2c->state == STATE_IDLE) {
 317                 spin_unlock(&i2c->lock);
 318                 return IRQ_NONE;
 319         }
 320
 321         meson_i2c_transfer_complete(i2c, ctrl);
 322
 323         if (i2c->state == STATE_IDLE) {
 324                 complete(&i2c->done);
 325                 goto out;
 326         }
 327
 328         /* Restart the processing */
 329         meson_i2c_prepare_xfer(i2c);
 330         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
 331 out:
 332         spin_unlock(&i2c->lock);
 333
 334         return IRQ_HANDLED;
 335 }
 336
 337 static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
 338 {
 339         int token;
 340
 341         token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ :
 342                 TOKEN_SLAVE_ADDR_WRITE;
 343
 344
 345         meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_ADDR_MASK,
 346                            FIELD_PREP(REG_SLV_ADDR_MASK, msg->addr << 1));
 347
 348         meson_i2c_add_token(i2c, TOKEN_START);
 349         meson_i2c_add_token(i2c, token);
 350 }
 351
 352 static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg,
 353                               int last, bool atomic)
 354 {
 355         unsigned long time_left, flags;
 356         int ret = 0;
 357         u32 ctrl;
 358
 359         i2c->msg = msg;
 360         i2c->last = last;
 361         i2c->pos = 0;
 362         i2c->count = 0;
 363         i2c->error = 0;
 364
 365         meson_i2c_reset_tokens(i2c);
 366
 367         flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0;
 368         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags);
 369
 370         if (!(msg->flags & I2C_M_NOSTART))
 371                 meson_i2c_do_start(i2c, msg);
 372
 373         i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
 374         meson_i2c_prepare_xfer(i2c);
 375
 376         if (!atomic)
 377                 reinit_completion(&i2c->done);
 378
 379         /* Start the transfer */
 380         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
 381
 382         if (atomic) {
 383                 ret = readl_poll_timeout_atomic(i2c->regs + REG_CTRL, ctrl,
 384                                                 !(ctrl & REG_CTRL_STATUS),
 385                                                 10, I2C_TIMEOUT_MS * 1000);
 386         } else {
 387                 time_left = msecs_to_jiffies(I2C_TIMEOUT_MS);
 388                 time_left = wait_for_completion_timeout(&i2c->done, time_left);
 389
 390                 if (!time_left)
 391                         ret = -ETIMEDOUT;
 392         }
 393
 394         /*
 395          * Protect access to i2c struct and registers from interrupt
 396          * handlers triggered by a transfer terminated after the
 397          * timeout period
 398          */
 399         spin_lock_irqsave(&i2c->lock, flags);
 400
 401         if (atomic && !ret)
 402                 meson_i2c_transfer_complete(i2c, ctrl);
 403
 404         /* Abort any active operation */
 405         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
 406
 407         if (ret)
 408                 i2c->state = STATE_IDLE;
 409
 410         if (i2c->error)
 411                 ret = i2c->error;
 412
 413         spin_unlock_irqrestore(&i2c->lock, flags);
 414
 415         return ret;
 416 }
 417
 418 static int meson_i2c_xfer_messages(struct i2c_adapter *adap,
 419                                    struct i2c_msg *msgs, int num, bool atomic)
 420 {
 421         struct meson_i2c *i2c = adap->algo_data;
 422         int i, ret = 0;
 423
 424         for (i = 0; i < num; i++) {
 425                 ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1, atomic);
 426                 if (ret)
 427                         break;
 428         }
 429
 430         return ret ?: i;
 431 }
 432
 433 static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 434                           int num)
 435 {
 436         return meson_i2c_xfer_messages(adap, msgs, num, false);
 437 }
 438
 439 static int meson_i2c_xfer_atomic(struct i2c_adapter *adap,
 440                                  struct i2c_msg *msgs, int num)
 441 {
 442         return meson_i2c_xfer_messages(adap, msgs, num, true);
 443 }
 444
 445 static u32 meson_i2c_func(struct i2c_adapter *adap)
 446 {
 447         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 448 }
 449
 450 static const struct i2c_algorithm meson_i2c_algorithm = {
 451         .master_xfer = meson_i2c_xfer,
 452         .master_xfer_atomic = meson_i2c_xfer_atomic,
 453         .functionality = meson_i2c_func,
 454 };
 455
 456 static int meson_i2c_probe(struct platform_device *pdev)
 457 {
 458         struct device_node *np = pdev->dev.of_node;
 459         struct meson_i2c *i2c;
 460         struct i2c_timings timings;
 461         int irq, ret = 0;
 462
 463         i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL);
 464         if (!i2c)
 465                 return -ENOMEM;
 466
 467         i2c_parse_fw_timings(&pdev->dev, &timings, true);
 468
 469         i2c->dev = &pdev->dev;
 470         platform_set_drvdata(pdev, i2c);
 471
 472         spin_lock_init(&i2c->lock);
 473         init_completion(&i2c->done);
 474
 475         i2c->data = (const struct meson_i2c_data *)
 476                 of_device_get_match_data(&pdev->dev);
 477
 478         i2c->clk = devm_clk_get(&pdev->dev, NULL);
 479         if (IS_ERR(i2c->clk)) {
 480                 dev_err(&pdev->dev, "can't get device clock\n");
 481                 return PTR_ERR(i2c->clk);
 482         }
 483
 484         i2c->regs = devm_platform_ioremap_resource(pdev, 0);
 485         if (IS_ERR(i2c->regs))
 486                 return PTR_ERR(i2c->regs);
 487
 488         irq = platform_get_irq(pdev, 0);
 489         if (irq < 0)
 490                 return irq;
 491
 492         ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c);
 493         if (ret < 0) {
 494                 dev_err(&pdev->dev, "can't request IRQ\n");
 495                 return ret;
 496         }
 497
 498         ret = clk_prepare_enable(i2c->clk);
 499         if (ret < 0) {
 500                 dev_err(&pdev->dev, "can't prepare clock\n");
 501                 return ret;
 502         }
 503
 504         strscpy(i2c->adap.name, "Meson I2C adapter",
 505                 sizeof(i2c->adap.name));
 506         i2c->adap.owner = THIS_MODULE;
 507         i2c->adap.algo = &meson_i2c_algorithm;
 508         i2c->adap.dev.parent = &pdev->dev;
 509         i2c->adap.dev.of_node = np;
 510         i2c->adap.algo_data = i2c;
 511
 512         /*
 513          * A transfer is triggered when START bit changes from 0 to 1.
 514          * Ensure that the bit is set to 0 after probe
 515          */
 516         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
 517
 518         /* Disable filtering */
 519         meson_i2c_set_mask(i2c, REG_SLAVE_ADDR,
 520                            REG_SLV_SDA_FILTER_MASK | REG_SLV_SCL_FILTER_MASK, 0);
 521
 522         if (!i2c->data->set_clk_div) {
 523                 clk_disable_unprepare(i2c->clk);
 524                 return -EINVAL;
 525         }
 526         i2c->data->set_clk_div(i2c, timings.bus_freq_hz);
 527
 528         ret = i2c_add_adapter(&i2c->adap);
 529         if (ret < 0) {
 530                 clk_disable_unprepare(i2c->clk);
 531                 return ret;
 532         }
 533
 534         return 0;
 535 }
 536
 537 static void meson_i2c_remove(struct platform_device *pdev)
 538 {
 539         struct meson_i2c *i2c = platform_get_drvdata(pdev);
 540
 541         i2c_del_adapter(&i2c->adap);
 542         clk_disable_unprepare(i2c->clk);
 543 }
 544
 545 static const struct meson_i2c_data i2c_meson6_data = {
 546         .set_clk_div = meson6_i2c_set_clk_div,
 547 };
 548
 549 static const struct meson_i2c_data i2c_gxbb_data = {
 550         .set_clk_div = meson_gxbb_axg_i2c_set_clk_div,
 551 };
 552
 553 static const struct meson_i2c_data i2c_axg_data = {
 554         .set_clk_div = meson_gxbb_axg_i2c_set_clk_div,
 555 };
 556
 557 static const struct of_device_id meson_i2c_match[] = {
 558         { .compatible = "amlogic,meson6-i2c", .data = &i2c_meson6_data },
 559         { .compatible = "amlogic,meson-gxbb-i2c", .data = &i2c_gxbb_data },
 560         { .compatible = "amlogic,meson-axg-i2c", .data = &i2c_axg_data },
 561         {},
 562 };
 563
 564 MODULE_DEVICE_TABLE(of, meson_i2c_match);
 565
 566 static struct platform_driver meson_i2c_driver = {
 567         .probe   = meson_i2c_probe,
 568         .remove_new = meson_i2c_remove,
 569         .driver  = {
 570                 .name  = "meson-i2c",
 571                 .of_match_table = meson_i2c_match,
 572         },
 573 };
 574
 575 module_platform_driver(meson_i2c_driver);
 576
 577 MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver");
 578 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
 579 MODULE_LICENSE("GPL v2");