drivers/i2c/busses/i2c-mxs.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale MXS I2C bus driver
   4  *
   5  * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
   6  * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
   7  *
   8  * based on a (non-working) driver which was:
   9  *
  10  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  11  */
  12
  13 #include <linux/slab.h>
  14 #include <linux/device.h>
  15 #include <linux/module.h>
  16 #include <linux/i2c.h>
  17 #include <linux/err.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/completion.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/io.h>
  23 #include <linux/stmp_device.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/dmaengine.h>
  28 #include <linux/dma/mxs-dma.h>
  29
  30 #define DRIVER_NAME "mxs-i2c"
  31
  32 #define MXS_I2C_CTRL0           (0x00)
  33 #define MXS_I2C_CTRL0_SET       (0x04)
  34 #define MXS_I2C_CTRL0_CLR       (0x08)
  35
  36 #define MXS_I2C_CTRL0_SFTRST                    0x80000000
  37 #define MXS_I2C_CTRL0_RUN                       0x20000000
  38 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST          0x02000000
  39 #define MXS_I2C_CTRL0_PIO_MODE                  0x01000000
  40 #define MXS_I2C_CTRL0_RETAIN_CLOCK              0x00200000
  41 #define MXS_I2C_CTRL0_POST_SEND_STOP            0x00100000
  42 #define MXS_I2C_CTRL0_PRE_SEND_START            0x00080000
  43 #define MXS_I2C_CTRL0_MASTER_MODE               0x00020000
  44 #define MXS_I2C_CTRL0_DIRECTION                 0x00010000
  45 #define MXS_I2C_CTRL0_XFER_COUNT(v)             ((v) & 0x0000FFFF)
  46
  47 #define MXS_I2C_TIMING0         (0x10)
  48 #define MXS_I2C_TIMING1         (0x20)
  49 #define MXS_I2C_TIMING2         (0x30)
  50
  51 #define MXS_I2C_CTRL1           (0x40)
  52 #define MXS_I2C_CTRL1_SET       (0x44)
  53 #define MXS_I2C_CTRL1_CLR       (0x48)
  54
  55 #define MXS_I2C_CTRL1_CLR_GOT_A_NAK             0x10000000
  56 #define MXS_I2C_CTRL1_BUS_FREE_IRQ              0x80
  57 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ     0x40
  58 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ          0x20
  59 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ    0x10
  60 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ            0x08
  61 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ           0x04
  62 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ            0x02
  63 #define MXS_I2C_CTRL1_SLAVE_IRQ                 0x01
  64
  65 #define MXS_I2C_STAT            (0x50)
  66 #define MXS_I2C_STAT_GOT_A_NAK                  0x10000000
  67 #define MXS_I2C_STAT_BUS_BUSY                   0x00000800
  68 #define MXS_I2C_STAT_CLK_GEN_BUSY               0x00000400
  69
  70 #define MXS_I2C_DATA(i2c)       ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
  71
  72 #define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
  73
  74 #define MXS_I2C_DEBUG0_DMAREQ   0x80000000
  75
  76 #define MXS_I2C_IRQ_MASK        (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
  77                                  MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
  78                                  MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
  79                                  MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
  80                                  MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
  81                                  MXS_I2C_CTRL1_SLAVE_IRQ)
  82
  83
  84 #define MXS_CMD_I2C_SELECT      (MXS_I2C_CTRL0_RETAIN_CLOCK |   \
  85                                  MXS_I2C_CTRL0_PRE_SEND_START | \
  86                                  MXS_I2C_CTRL0_MASTER_MODE |    \
  87                                  MXS_I2C_CTRL0_DIRECTION |      \
  88                                  MXS_I2C_CTRL0_XFER_COUNT(1))
  89
  90 #define MXS_CMD_I2C_WRITE       (MXS_I2C_CTRL0_PRE_SEND_START | \
  91                                  MXS_I2C_CTRL0_MASTER_MODE |    \
  92                                  MXS_I2C_CTRL0_DIRECTION)
  93
  94 #define MXS_CMD_I2C_READ        (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
  95                                  MXS_I2C_CTRL0_MASTER_MODE)
  96
  97 enum mxs_i2c_devtype {
  98         MXS_I2C_UNKNOWN = 0,
  99         MXS_I2C_V1,
 100         MXS_I2C_V2,
 101 };
 102
 103 /**
 104  * struct mxs_i2c_dev - per device, private MXS-I2C data
 105  *
 106  * @dev: driver model device node
 107  * @dev_type: distinguish i.MX23/i.MX28 features
 108  * @regs: IO registers pointer
 109  * @cmd_complete: completion object for transaction wait
 110  * @cmd_err: error code for last transaction
 111  * @adapter: i2c subsystem adapter node
 112  */
 113 struct mxs_i2c_dev {
 114         struct device *dev;
 115         enum mxs_i2c_devtype dev_type;
 116         void __iomem *regs;
 117         struct completion cmd_complete;
 118         int cmd_err;
 119         struct i2c_adapter adapter;
 120
 121         uint32_t timing0;
 122         uint32_t timing1;
 123         uint32_t timing2;
 124
 125         /* DMA support components */
 126         struct dma_chan                 *dmach;
 127         uint32_t                        pio_data[2];
 128         uint32_t                        addr_data;
 129         struct scatterlist              sg_io[2];
 130         bool                            dma_read;
 131 };
 132
 133 static int mxs_i2c_reset(struct mxs_i2c_dev *i2c)
 134 {
 135         int ret = stmp_reset_block(i2c->regs);
 136         if (ret)
 137                 return ret;
 138
 139         /*
 140          * Configure timing for the I2C block. The I2C TIMING2 register has to
 141          * be programmed with this particular magic number. The rest is derived
 142          * from the XTAL speed and requested I2C speed.
 143          *
 144          * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
 145          */
 146         writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
 147         writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
 148         writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2);
 149
 150         writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
 151
 152         return 0;
 153 }
 154
 155 static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
 156 {
 157         if (i2c->dma_read) {
 158                 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 159                 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 160         } else {
 161                 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 162         }
 163 }
 164
 165 static void mxs_i2c_dma_irq_callback(void *param)
 166 {
 167         struct mxs_i2c_dev *i2c = param;
 168
 169         complete(&i2c->cmd_complete);
 170         mxs_i2c_dma_finish(i2c);
 171 }
 172
 173 static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
 174                         struct i2c_msg *msg, u8 *buf, uint32_t flags)
 175 {
 176         struct dma_async_tx_descriptor *desc;
 177         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 178
 179         i2c->addr_data = i2c_8bit_addr_from_msg(msg);
 180
 181         if (msg->flags & I2C_M_RD) {
 182                 i2c->dma_read = true;
 183
 184                 /*
 185                  * SELECT command.
 186                  */
 187
 188                 /* Queue the PIO register write transfer. */
 189                 i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
 190                 desc = dmaengine_prep_slave_sg(i2c->dmach,
 191                                         (struct scatterlist *)&i2c->pio_data[0],
 192                                         1, DMA_TRANS_NONE, 0);
 193                 if (!desc) {
 194                         dev_err(i2c->dev,
 195                                 "Failed to get PIO reg. write descriptor.\n");
 196                         goto select_init_pio_fail;
 197                 }
 198
 199                 /* Queue the DMA data transfer. */
 200                 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
 201                 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 202                 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
 203                                         DMA_MEM_TO_DEV,
 204                                         DMA_PREP_INTERRUPT |
 205                                         MXS_DMA_CTRL_WAIT4END);
 206                 if (!desc) {
 207                         dev_err(i2c->dev,
 208                                 "Failed to get DMA data write descriptor.\n");
 209                         goto select_init_dma_fail;
 210                 }
 211
 212                 /*
 213                  * READ command.
 214                  */
 215
 216                 /* Queue the PIO register write transfer. */
 217                 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
 218                                 MXS_I2C_CTRL0_XFER_COUNT(msg->len);
 219                 desc = dmaengine_prep_slave_sg(i2c->dmach,
 220                                         (struct scatterlist *)&i2c->pio_data[1],
 221                                         1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
 222                 if (!desc) {
 223                         dev_err(i2c->dev,
 224                                 "Failed to get PIO reg. write descriptor.\n");
 225                         goto select_init_dma_fail;
 226                 }
 227
 228                 /* Queue the DMA data transfer. */
 229                 sg_init_one(&i2c->sg_io[1], buf, msg->len);
 230                 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 231                 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
 232                                         DMA_DEV_TO_MEM,
 233                                         DMA_PREP_INTERRUPT |
 234                                         MXS_DMA_CTRL_WAIT4END);
 235                 if (!desc) {
 236                         dev_err(i2c->dev,
 237                                 "Failed to get DMA data write descriptor.\n");
 238                         goto read_init_dma_fail;
 239                 }
 240         } else {
 241                 i2c->dma_read = false;
 242
 243                 /*
 244                  * WRITE command.
 245                  */
 246
 247                 /* Queue the PIO register write transfer. */
 248                 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
 249                                 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
 250                 desc = dmaengine_prep_slave_sg(i2c->dmach,
 251                                         (struct scatterlist *)&i2c->pio_data[0],
 252                                         1, DMA_TRANS_NONE, 0);
 253                 if (!desc) {
 254                         dev_err(i2c->dev,
 255                                 "Failed to get PIO reg. write descriptor.\n");
 256                         goto write_init_pio_fail;
 257                 }
 258
 259                 /* Queue the DMA data transfer. */
 260                 sg_init_table(i2c->sg_io, 2);
 261                 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
 262                 sg_set_buf(&i2c->sg_io[1], buf, msg->len);
 263                 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 264                 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
 265                                         DMA_MEM_TO_DEV,
 266                                         DMA_PREP_INTERRUPT |
 267                                         MXS_DMA_CTRL_WAIT4END);
 268                 if (!desc) {
 269                         dev_err(i2c->dev,
 270                                 "Failed to get DMA data write descriptor.\n");
 271                         goto write_init_dma_fail;
 272                 }
 273         }
 274
 275         /*
 276          * The last descriptor must have this callback,
 277          * to finish the DMA transaction.
 278          */
 279         desc->callback = mxs_i2c_dma_irq_callback;
 280         desc->callback_param = i2c;
 281
 282         /* Start the transfer. */
 283         dmaengine_submit(desc);
 284         dma_async_issue_pending(i2c->dmach);
 285         return 0;
 286
 287 /* Read failpath. */
 288 read_init_dma_fail:
 289         dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 290 select_init_dma_fail:
 291         dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 292 select_init_pio_fail:
 293         dmaengine_terminate_sync(i2c->dmach);
 294         return -EINVAL;
 295
 296 /* Write failpath. */
 297 write_init_dma_fail:
 298         dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 299 write_init_pio_fail:
 300         dmaengine_terminate_sync(i2c->dmach);
 301         return -EINVAL;
 302 }
 303
 304 static int mxs_i2c_pio_wait_xfer_end(struct mxs_i2c_dev *i2c)
 305 {
 306         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 307
 308         while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) {
 309                 if (readl(i2c->regs + MXS_I2C_CTRL1) &
 310                                 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
 311                         return -ENXIO;
 312                 if (time_after(jiffies, timeout))
 313                         return -ETIMEDOUT;
 314                 cond_resched();
 315         }
 316
 317         return 0;
 318 }
 319
 320 static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c)
 321 {
 322         u32 state;
 323
 324         state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;
 325
 326         if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
 327                 i2c->cmd_err = -ENXIO;
 328         else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
 329                           MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
 330                           MXS_I2C_CTRL1_SLAVE_STOP_IRQ |
 331                           MXS_I2C_CTRL1_SLAVE_IRQ))
 332                 i2c->cmd_err = -EIO;
 333
 334         return i2c->cmd_err;
 335 }
 336
 337 static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)
 338 {
 339         u32 reg;
 340
 341         writel(cmd, i2c->regs + MXS_I2C_CTRL0);
 342
 343         /* readback makes sure the write is latched into hardware */
 344         reg = readl(i2c->regs + MXS_I2C_CTRL0);
 345         reg |= MXS_I2C_CTRL0_RUN;
 346         writel(reg, i2c->regs + MXS_I2C_CTRL0);
 347 }
 348
 349 /*
 350  * Start WRITE transaction on the I2C bus. By studying i.MX23 datasheet,
 351  * CTRL0::PIO_MODE bit description clarifies the order in which the registers
 352  * must be written during PIO mode operation. First, the CTRL0 register has
 353  * to be programmed with all the necessary bits but the RUN bit. Then the
 354  * payload has to be written into the DATA register. Finally, the transmission
 355  * is executed by setting the RUN bit in CTRL0.
 356  */
 357 static void mxs_i2c_pio_trigger_write_cmd(struct mxs_i2c_dev *i2c, u32 cmd,
 358                                           u32 data)
 359 {
 360         writel(cmd, i2c->regs + MXS_I2C_CTRL0);
 361
 362         if (i2c->dev_type == MXS_I2C_V1)
 363                 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET);
 364
 365         writel(data, i2c->regs + MXS_I2C_DATA(i2c));
 366         writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET);
 367 }
 368
 369 static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
 370                         struct i2c_msg *msg, uint32_t flags)
 371 {
 372         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 373         uint32_t addr_data = i2c_8bit_addr_from_msg(msg);
 374         uint32_t data = 0;
 375         int i, ret, xlen = 0, xmit = 0;
 376         uint32_t start;
 377
 378         /* Mute IRQs coming from this block. */
 379         writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
 380
 381         /*
 382          * MX23 idea:
 383          * - Enable CTRL0::PIO_MODE (1 << 24)
 384          * - Enable CTRL1::ACK_MODE (1 << 27)
 385          *
 386          * WARNING! The MX23 is broken in some way, even if it claims
 387          * to support PIO, when we try to transfer any amount of data
 388          * that is not aligned to 4 bytes, the DMA engine will have
 389          * bits in DEBUG1::DMA_BYTES_ENABLES still set even after the
 390          * transfer. This in turn will mess up the next transfer as
 391          * the block it emit one byte write onto the bus terminated
 392          * with a NAK+STOP. A possible workaround is to reset the IP
 393          * block after every PIO transmission, which might just work.
 394          *
 395          * NOTE: The CTRL0::PIO_MODE description is important, since
 396          * it outlines how the PIO mode is really supposed to work.
 397          */
 398         if (msg->flags & I2C_M_RD) {
 399                 /*
 400                  * PIO READ transfer:
 401                  *
 402                  * This transfer MUST be limited to 4 bytes maximum. It is not
 403                  * possible to transfer more than four bytes via PIO, since we
 404                  * can not in any way make sure we can read the data from the
 405                  * DATA register fast enough. Besides, the RX FIFO is only four
 406                  * bytes deep, thus we can only really read up to four bytes at
 407                  * time. Finally, there is no bit indicating us that new data
 408                  * arrived at the FIFO and can thus be fetched from the DATA
 409                  * register.
 410                  */
 411                 BUG_ON(msg->len > 4);
 412
 413                 /* SELECT command. */
 414                 mxs_i2c_pio_trigger_write_cmd(i2c, MXS_CMD_I2C_SELECT,
 415                                               addr_data);
 416
 417                 ret = mxs_i2c_pio_wait_xfer_end(i2c);
 418                 if (ret) {
 419                         dev_dbg(i2c->dev,
 420                                 "PIO: Failed to send SELECT command!\n");
 421                         goto cleanup;
 422                 }
 423
 424                 /* READ command. */
 425                 mxs_i2c_pio_trigger_cmd(i2c,
 426                                         MXS_CMD_I2C_READ | flags |
 427                                         MXS_I2C_CTRL0_XFER_COUNT(msg->len));
 428
 429                 ret = mxs_i2c_pio_wait_xfer_end(i2c);
 430                 if (ret) {
 431                         dev_dbg(i2c->dev,
 432                                 "PIO: Failed to send READ command!\n");
 433                         goto cleanup;
 434                 }
 435
 436                 data = readl(i2c->regs + MXS_I2C_DATA(i2c));
 437                 for (i = 0; i < msg->len; i++) {
 438                         msg->buf[i] = data & 0xff;
 439                         data >>= 8;
 440                 }
 441         } else {
 442                 /*
 443                  * PIO WRITE transfer:
 444                  *
 445                  * The code below implements clock stretching to circumvent
 446                  * the possibility of kernel not being able to supply data
 447                  * fast enough. It is possible to transfer arbitrary amount
 448                  * of data using PIO write.
 449                  */
 450
 451                 /*
 452                  * The LSB of data buffer is the first byte blasted across
 453                  * the bus. Higher order bytes follow. Thus the following
 454                  * filling schematic.
 455                  */
 456
 457                 data = addr_data << 24;
 458
 459                 /* Start the transfer with START condition. */
 460                 start = MXS_I2C_CTRL0_PRE_SEND_START;
 461
 462                 /* If the transfer is long, use clock stretching. */
 463                 if (msg->len > 3)
 464                         start |= MXS_I2C_CTRL0_RETAIN_CLOCK;
 465
 466                 for (i = 0; i < msg->len; i++) {
 467                         data >>= 8;
 468                         data |= (msg->buf[i] << 24);
 469
 470                         xmit = 0;
 471
 472                         /* This is the last transfer of the message. */
 473                         if (i + 1 == msg->len) {
 474                                 /* Add optional STOP flag. */
 475                                 start |= flags;
 476                                 /* Remove RETAIN_CLOCK bit. */
 477                                 start &= ~MXS_I2C_CTRL0_RETAIN_CLOCK;
 478                                 xmit = 1;
 479                         }
 480
 481                         /* Four bytes are ready in the "data" variable. */
 482                         if ((i & 3) == 2)
 483                                 xmit = 1;
 484
 485                         /* Nothing interesting happened, continue stuffing. */
 486                         if (!xmit)
 487                                 continue;
 488
 489                         /*
 490                          * Compute the size of the transfer and shift the
 491                          * data accordingly.
 492                          *
 493                          * i = (4k + 0) .... xlen = 2
 494                          * i = (4k + 1) .... xlen = 3
 495                          * i = (4k + 2) .... xlen = 4
 496                          * i = (4k + 3) .... xlen = 1
 497                          */
 498
 499                         if ((i % 4) == 3)
 500                                 xlen = 1;
 501                         else
 502                                 xlen = (i % 4) + 2;
 503
 504                         data >>= (4 - xlen) * 8;
 505
 506                         dev_dbg(i2c->dev,
 507                                 "PIO: len=%i pos=%i total=%i [W%s%s%s]\n",
 508                                 xlen, i, msg->len,
 509                                 start & MXS_I2C_CTRL0_PRE_SEND_START ? "S" : "",
 510                                 start & MXS_I2C_CTRL0_POST_SEND_STOP ? "E" : "",
 511                                 start & MXS_I2C_CTRL0_RETAIN_CLOCK ? "C" : "");
 512
 513                         writel(MXS_I2C_DEBUG0_DMAREQ,
 514                                i2c->regs + MXS_I2C_DEBUG0_CLR(i2c));
 515
 516                         mxs_i2c_pio_trigger_write_cmd(i2c,
 517                                 start | MXS_I2C_CTRL0_MASTER_MODE |
 518                                 MXS_I2C_CTRL0_DIRECTION |
 519                                 MXS_I2C_CTRL0_XFER_COUNT(xlen), data);
 520
 521                         /* The START condition is sent only once. */
 522                         start &= ~MXS_I2C_CTRL0_PRE_SEND_START;
 523
 524                         /* Wait for the end of the transfer. */
 525                         ret = mxs_i2c_pio_wait_xfer_end(i2c);
 526                         if (ret) {
 527                                 dev_dbg(i2c->dev,
 528                                         "PIO: Failed to finish WRITE cmd!\n");
 529                                 break;
 530                         }
 531
 532                         /* Check NAK here. */
 533                         ret = readl(i2c->regs + MXS_I2C_STAT) &
 534                                     MXS_I2C_STAT_GOT_A_NAK;
 535                         if (ret) {
 536                                 ret = -ENXIO;
 537                                 goto cleanup;
 538                         }
 539                 }
 540         }
 541
 542         /* make sure we capture any occurred error into cmd_err */
 543         ret = mxs_i2c_pio_check_error_state(i2c);
 544
 545 cleanup:
 546         /* Clear any dangling IRQs and re-enable interrupts. */
 547         writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
 548         writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
 549
 550         /* Clear the PIO_MODE on i.MX23 */
 551         if (i2c->dev_type == MXS_I2C_V1)
 552                 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR);
 553
 554         return ret;
 555 }
 556
 557 /*
 558  * Low level master read/write transaction.
 559  */
 560 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
 561                                 int stop)
 562 {
 563         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 564         int ret;
 565         int flags;
 566         u8 *dma_buf;
 567         int use_pio = 0;
 568         unsigned long time_left;
 569
 570         flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
 571
 572         dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 573                 msg->addr, msg->len, msg->flags, stop);
 574
 575         /*
 576          * The MX28 I2C IP block can only do PIO READ for transfer of to up
 577          * 4 bytes of length. The write transfer is not limited as it can use
 578          * clock stretching to avoid FIFO underruns.
 579          */
 580         if ((msg->flags & I2C_M_RD) && (msg->len <= 4))
 581                 use_pio = 1;
 582         if (!(msg->flags & I2C_M_RD) && (msg->len < 7))
 583                 use_pio = 1;
 584
 585         i2c->cmd_err = 0;
 586         if (use_pio) {
 587                 ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
 588                 /* No need to reset the block if NAK was received. */
 589                 if (ret && (ret != -ENXIO))
 590                         mxs_i2c_reset(i2c);
 591         } else {
 592                 dma_buf = i2c_get_dma_safe_msg_buf(msg, 1);
 593                 if (!dma_buf)
 594                         return -ENOMEM;
 595
 596                 reinit_completion(&i2c->cmd_complete);
 597                 ret = mxs_i2c_dma_setup_xfer(adap, msg, dma_buf, flags);
 598                 if (ret) {
 599                         i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
 600                         return ret;
 601                 }
 602
 603                 time_left = wait_for_completion_timeout(&i2c->cmd_complete,
 604                                                 msecs_to_jiffies(1000));
 605                 i2c_put_dma_safe_msg_buf(dma_buf, msg, true);
 606                 if (!time_left)
 607                         goto timeout;
 608
 609                 ret = i2c->cmd_err;
 610         }
 611
 612         if (ret == -ENXIO) {
 613                 /*
 614                  * If the transfer fails with a NAK from the slave the
 615                  * controller halts until it gets told to return to idle state.
 616                  */
 617                 writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,
 618                        i2c->regs + MXS_I2C_CTRL1_SET);
 619         }
 620
 621         /*
 622          * WARNING!
 623          * The i.MX23 is strange. After each and every operation, it's I2C IP
 624          * block must be reset, otherwise the IP block will misbehave. This can
 625          * be observed on the bus by the block sending out one single byte onto
 626          * the bus. In case such an error happens, bit 27 will be set in the
 627          * DEBUG0 register. This bit is not documented in the i.MX23 datasheet
 628          * and is marked as "TBD" instead. To reset this bit to a correct state,
 629          * reset the whole block. Since the block reset does not take long, do
 630          * reset the block after every transfer to play safe.
 631          */
 632         if (i2c->dev_type == MXS_I2C_V1)
 633                 mxs_i2c_reset(i2c);
 634
 635         dev_dbg(i2c->dev, "Done with err=%d\n", ret);
 636
 637         return ret;
 638
 639 timeout:
 640         dev_dbg(i2c->dev, "Timeout!\n");
 641         mxs_i2c_dma_finish(i2c);
 642         ret = mxs_i2c_reset(i2c);
 643         if (ret)
 644                 return ret;
 645
 646         return -ETIMEDOUT;
 647 }
 648
 649 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 650                         int num)
 651 {
 652         int i;
 653         int err;
 654
 655         for (i = 0; i < num; i++) {
 656                 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
 657                 if (err)
 658                         return err;
 659         }
 660
 661         return num;
 662 }
 663
 664 static u32 mxs_i2c_func(struct i2c_adapter *adap)
 665 {
 666         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 667 }
 668
 669 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
 670 {
 671         struct mxs_i2c_dev *i2c = dev_id;
 672         u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
 673
 674         if (!stat)
 675                 return IRQ_NONE;
 676
 677         if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
 678                 i2c->cmd_err = -ENXIO;
 679         else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
 680                     MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
 681                     MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
 682                 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
 683                 i2c->cmd_err = -EIO;
 684
 685         writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
 686
 687         return IRQ_HANDLED;
 688 }
 689
 690 static const struct i2c_algorithm mxs_i2c_algo = {
 691         .master_xfer = mxs_i2c_xfer,
 692         .functionality = mxs_i2c_func,
 693 };
 694
 695 static const struct i2c_adapter_quirks mxs_i2c_quirks = {
 696         .flags = I2C_AQ_NO_ZERO_LEN,
 697 };
 698
 699 static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed)
 700 {
 701         /* The I2C block clock runs at 24MHz */
 702         const uint32_t clk = 24000000;
 703         uint32_t divider;
 704         uint16_t high_count, low_count, rcv_count, xmit_count;
 705         uint32_t bus_free, leadin;
 706         struct device *dev = i2c->dev;
 707
 708         divider = DIV_ROUND_UP(clk, speed);
 709
 710         if (divider < 25) {
 711                 /*
 712                  * limit the divider, so that min(low_count, high_count)
 713                  * is >= 1
 714                  */
 715                 divider = 25;
 716                 dev_warn(dev,
 717                         "Speed too high (%u.%03u kHz), using %u.%03u kHz\n",
 718                         speed / 1000, speed % 1000,
 719                         clk / divider / 1000, clk / divider % 1000);
 720         } else if (divider > 1897) {
 721                 /*
 722                  * limit the divider, so that max(low_count, high_count)
 723                  * cannot exceed 1023
 724                  */
 725                 divider = 1897;
 726                 dev_warn(dev,
 727                         "Speed too low (%u.%03u kHz), using %u.%03u kHz\n",
 728                         speed / 1000, speed % 1000,
 729                         clk / divider / 1000, clk / divider % 1000);
 730         }
 731
 732         /*
 733          * The I2C spec specifies the following timing data:
 734          *                          standard mode  fast mode Bitfield name
 735          * tLOW (SCL LOW period)     4700 ns        1300 ns
 736          * tHIGH (SCL HIGH period)   4000 ns         600 ns
 737          * tSU;DAT (data setup time)  250 ns         100 ns
 738          * tHD;STA (START hold time) 4000 ns         600 ns
 739          * tBUF (bus free time)      4700 ns        1300 ns
 740          *
 741          * The hardware (of the i.MX28 at least) seems to add 2 additional
 742          * clock cycles to the low_count and 7 cycles to the high_count.
 743          * This is compensated for by subtracting the respective constants
 744          * from the values written to the timing registers.
 745          */
 746         if (speed > I2C_MAX_STANDARD_MODE_FREQ) {
 747                 /* fast mode */
 748                 low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6));
 749                 high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6));
 750                 leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000);
 751                 bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000);
 752         } else {
 753                 /* normal mode */
 754                 low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40));
 755                 high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40));
 756                 leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
 757                 bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
 758         }
 759         rcv_count = high_count * 3 / 8;
 760         xmit_count = low_count * 3 / 8;
 761
 762         dev_dbg(dev,
 763                 "speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n",
 764                 speed, clk / divider, divider, low_count, high_count,
 765                 xmit_count, rcv_count, leadin, bus_free);
 766
 767         low_count -= 2;
 768         high_count -= 7;
 769         i2c->timing0 = (high_count << 16) | rcv_count;
 770         i2c->timing1 = (low_count << 16) | xmit_count;
 771         i2c->timing2 = (bus_free << 16 | leadin);
 772 }
 773
 774 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
 775 {
 776         uint32_t speed;
 777         struct device *dev = i2c->dev;
 778         struct device_node *node = dev->of_node;
 779         int ret;
 780
 781         ret = of_property_read_u32(node, "clock-frequency", &speed);
 782         if (ret) {
 783                 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
 784                 speed = I2C_MAX_STANDARD_MODE_FREQ;
 785         }
 786
 787         mxs_i2c_derive_timing(i2c, speed);
 788
 789         return 0;
 790 }
 791
 792 static const struct of_device_id mxs_i2c_dt_ids[] = {
 793         { .compatible = "fsl,imx23-i2c", .data = (void *)MXS_I2C_V1, },
 794         { .compatible = "fsl,imx28-i2c", .data = (void *)MXS_I2C_V2, },
 795         { /* sentinel */ }
 796 };
 797 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
 798
 799 static int mxs_i2c_probe(struct platform_device *pdev)
 800 {
 801         struct device *dev = &pdev->dev;
 802         struct mxs_i2c_dev *i2c;
 803         struct i2c_adapter *adap;
 804         int err, irq;
 805
 806         i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
 807         if (!i2c)
 808                 return -ENOMEM;
 809
 810         i2c->dev_type = (uintptr_t)of_device_get_match_data(&pdev->dev);
 811
 812         i2c->regs = devm_platform_ioremap_resource(pdev, 0);
 813         if (IS_ERR(i2c->regs))
 814                 return PTR_ERR(i2c->regs);
 815
 816         irq = platform_get_irq(pdev, 0);
 817         if (irq < 0)
 818                 return irq;
 819
 820         err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
 821         if (err)
 822                 return err;
 823
 824         i2c->dev = dev;
 825
 826         init_completion(&i2c->cmd_complete);
 827
 828         if (dev->of_node) {
 829                 err = mxs_i2c_get_ofdata(i2c);
 830                 if (err)
 831                         return err;
 832         }
 833
 834         /* Setup the DMA */
 835         i2c->dmach = dma_request_chan(dev, "rx-tx");
 836         if (IS_ERR(i2c->dmach)) {
 837                 return dev_err_probe(dev, PTR_ERR(i2c->dmach),
 838                                      "Failed to request dma\n");
 839         }
 840
 841         platform_set_drvdata(pdev, i2c);
 842
 843         /* Do reset to enforce correct startup after pinmuxing */
 844         err = mxs_i2c_reset(i2c);
 845         if (err)
 846                 return err;
 847
 848         adap = &i2c->adapter;
 849         strscpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
 850         adap->owner = THIS_MODULE;
 851         adap->algo = &mxs_i2c_algo;
 852         adap->quirks = &mxs_i2c_quirks;
 853         adap->dev.parent = dev;
 854         adap->nr = pdev->id;
 855         adap->dev.of_node = pdev->dev.of_node;
 856         i2c_set_adapdata(adap, i2c);
 857         err = i2c_add_numbered_adapter(adap);
 858         if (err) {
 859                 writel(MXS_I2C_CTRL0_SFTRST,
 860                                 i2c->regs + MXS_I2C_CTRL0_SET);
 861                 return err;
 862         }
 863
 864         return 0;
 865 }
 866
 867 static void mxs_i2c_remove(struct platform_device *pdev)
 868 {
 869         struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
 870
 871         i2c_del_adapter(&i2c->adapter);
 872
 873         if (i2c->dmach)
 874                 dma_release_channel(i2c->dmach);
 875
 876         writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
 877 }
 878
 879 static struct platform_driver mxs_i2c_driver = {
 880         .driver = {
 881                    .name = DRIVER_NAME,
 882                    .of_match_table = mxs_i2c_dt_ids,
 883                    },
 884         .probe = mxs_i2c_probe,
 885         .remove_new = mxs_i2c_remove,
 886 };
 887
 888 static int __init mxs_i2c_init(void)
 889 {
 890         return platform_driver_register(&mxs_i2c_driver);
 891 }
 892 subsys_initcall(mxs_i2c_init);
 893
 894 static void __exit mxs_i2c_exit(void)
 895 {
 896         platform_driver_unregister(&mxs_i2c_driver);
 897 }
 898 module_exit(mxs_i2c_exit);
 899
 900 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
 901 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
 902 MODULE_DESCRIPTION("MXS I2C Bus Driver");
 903 MODULE_LICENSE("GPL");
 904 MODULE_ALIAS("platform:" DRIVER_NAME);