drivers/idle/intel_idle.c

   1 /*
   2  * intel_idle.c - native hardware idle loop for modern Intel processors
   3  *
   4  * Copyright (c) 2010, Intel Corporation.
   5  * Len Brown <len.brown@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 /*
  22  * intel_idle is a cpuidle driver that loads on specific Intel processors
  23  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  24  * make Linux more efficient on these processors, as intel_idle knows
  25  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  26  */
  27
  28 /*
  29  * Design Assumptions
  30  *
  31  * All CPUs have same idle states as boot CPU
  32  *
  33  * Chipset BM_STS (bus master status) bit is a NOP
  34  *      for preventing entry into deep C-stats
  35  */
  36
  37 /*
  38  * Known limitations
  39  *
  40  * The driver currently initializes for_each_online_cpu() upon modprobe.
  41  * It it unaware of subsequent processors hot-added to the system.
  42  * This means that if you boot with maxcpus=n and later online
  43  * processors above n, those processors will use C1 only.
  44  *
  45  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  46  * to avoid complications with the lapic timer workaround.
  47  * Have not seen issues with suspend, but may need same workaround here.
  48  *
  49  * There is currently no kernel-based automatic probing/loading mechanism
  50  * if the driver is built as a module.
  51  */
  52
  53 /* un-comment DEBUG to enable pr_debug() statements */
  54 #define DEBUG
  55
  56 #include <linux/kernel.h>
  57 #include <linux/cpuidle.h>
  58 #include <linux/clockchips.h>
  59 #include <trace/events/power.h>
  60 #include <linux/sched.h>
  61 #include <linux/notifier.h>
  62 #include <linux/cpu.h>
  63 #include <linux/module.h>
  64 #include <asm/cpu_device_id.h>
  65 #include <asm/mwait.h>
  66 #include <asm/msr.h>
  67
  68 #define INTEL_IDLE_VERSION "0.4"
  69 #define PREFIX "intel_idle: "
  70
  71 static struct cpuidle_driver intel_idle_driver = {
  72         .name = "intel_idle",
  73         .owner = THIS_MODULE,
  74 };
  75 /* intel_idle.max_cstate=0 disables driver */
  76 static int max_cstate = CPUIDLE_STATE_MAX - 1;
  77
  78 static unsigned int mwait_substates;
  79
  80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
  81 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
  82 static unsigned int lapic_timer_reliable_states = (1 << 1);      /* Default to only C1 */
  83
  84 struct idle_cpu {
  85         struct cpuidle_state *state_table;
  86
  87         /*
  88          * Hardware C-state auto-demotion may not always be optimal.
  89          * Indicate which enable bits to clear here.
  90          */
  91         unsigned long auto_demotion_disable_flags;
  92         bool disable_promotion_to_c1e;
  93 };
  94
  95 static const struct idle_cpu *icpu;
  96 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  97 static int intel_idle(struct cpuidle_device *dev,
  98                         struct cpuidle_driver *drv, int index);
  99 static int intel_idle_cpu_init(int cpu);
 100
 101 static struct cpuidle_state *cpuidle_state_table;
 102
 103 /*
 104  * Set this flag for states where the HW flushes the TLB for us
 105  * and so we don't need cross-calls to keep it consistent.
 106  * If this flag is set, SW flushes the TLB, so even if the
 107  * HW doesn't do the flushing, this flag is safe to use.
 108  */
 109 #define CPUIDLE_FLAG_TLB_FLUSHED        0x10000
 110
 111 /*
 112  * MWAIT takes an 8-bit "hint" in EAX "suggesting"
 113  * the C-state (top nibble) and sub-state (bottom nibble)
 114  * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
 115  *
 116  * We store the hint at the top of our "flags" for each state.
 117  */
 118 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
 119 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
 120
 121 /*
 122  * States are indexed by the cstate number,
 123  * which is also the index into the MWAIT hint array.
 124  * Thus C0 is a dummy.
 125  */
 126 static struct cpuidle_state nehalem_cstates[CPUIDLE_STATE_MAX] = {
 127         {
 128                 .name = "C1-NHM",
 129                 .desc = "MWAIT 0x00",
 130                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 131                 .exit_latency = 3,
 132                 .target_residency = 6,
 133                 .enter = &intel_idle },
 134         {
 135                 .name = "C1E-NHM",
 136                 .desc = "MWAIT 0x01",
 137                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 138                 .exit_latency = 10,
 139                 .target_residency = 20,
 140                 .enter = &intel_idle },
 141         {
 142                 .name = "C3-NHM",
 143                 .desc = "MWAIT 0x10",
 144                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 145                 .exit_latency = 20,
 146                 .target_residency = 80,
 147                 .enter = &intel_idle },
 148         {
 149                 .name = "C6-NHM",
 150                 .desc = "MWAIT 0x20",
 151                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 152                 .exit_latency = 200,
 153                 .target_residency = 800,
 154                 .enter = &intel_idle },
 155         {
 156                 .enter = NULL }
 157 };
 158
 159 static struct cpuidle_state snb_cstates[CPUIDLE_STATE_MAX] = {
 160         {
 161                 .name = "C1-SNB",
 162                 .desc = "MWAIT 0x00",
 163                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 164                 .exit_latency = 2,
 165                 .target_residency = 2,
 166                 .enter = &intel_idle },
 167         {
 168                 .name = "C1E-SNB",
 169                 .desc = "MWAIT 0x01",
 170                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 171                 .exit_latency = 10,
 172                 .target_residency = 20,
 173                 .enter = &intel_idle },
 174         {
 175                 .name = "C3-SNB",
 176                 .desc = "MWAIT 0x10",
 177                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 178                 .exit_latency = 80,
 179                 .target_residency = 211,
 180                 .enter = &intel_idle },
 181         {
 182                 .name = "C6-SNB",
 183                 .desc = "MWAIT 0x20",
 184                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 185                 .exit_latency = 104,
 186                 .target_residency = 345,
 187                 .enter = &intel_idle },
 188         {
 189                 .name = "C7-SNB",
 190                 .desc = "MWAIT 0x30",
 191                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 192                 .exit_latency = 109,
 193                 .target_residency = 345,
 194                 .enter = &intel_idle },
 195         {
 196                 .enter = NULL }
 197 };
 198
 199 static struct cpuidle_state ivb_cstates[CPUIDLE_STATE_MAX] = {
 200         {
 201                 .name = "C1-IVB",
 202                 .desc = "MWAIT 0x00",
 203                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 204                 .exit_latency = 1,
 205                 .target_residency = 1,
 206                 .enter = &intel_idle },
 207         {
 208                 .name = "C1E-IVB",
 209                 .desc = "MWAIT 0x01",
 210                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 211                 .exit_latency = 10,
 212                 .target_residency = 20,
 213                 .enter = &intel_idle },
 214         {
 215                 .name = "C3-IVB",
 216                 .desc = "MWAIT 0x10",
 217                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 218                 .exit_latency = 59,
 219                 .target_residency = 156,
 220                 .enter = &intel_idle },
 221         {
 222                 .name = "C6-IVB",
 223                 .desc = "MWAIT 0x20",
 224                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 225                 .exit_latency = 80,
 226                 .target_residency = 300,
 227                 .enter = &intel_idle },
 228         {
 229                 .name = "C7-IVB",
 230                 .desc = "MWAIT 0x30",
 231                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 232                 .exit_latency = 87,
 233                 .target_residency = 300,
 234                 .enter = &intel_idle },
 235         {
 236                 .enter = NULL }
 237 };
 238
 239 static struct cpuidle_state hsw_cstates[CPUIDLE_STATE_MAX] = {
 240         {
 241                 .name = "C1-HSW",
 242                 .desc = "MWAIT 0x00",
 243                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 244                 .exit_latency = 2,
 245                 .target_residency = 2,
 246                 .enter = &intel_idle },
 247         {
 248                 .name = "C1E-HSW",
 249                 .desc = "MWAIT 0x01",
 250                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 251                 .exit_latency = 10,
 252                 .target_residency = 20,
 253                 .enter = &intel_idle },
 254         {
 255                 .name = "C3-HSW",
 256                 .desc = "MWAIT 0x10",
 257                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 258                 .exit_latency = 33,
 259                 .target_residency = 100,
 260                 .enter = &intel_idle },
 261         {
 262                 .name = "C6-HSW",
 263                 .desc = "MWAIT 0x20",
 264                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 265                 .exit_latency = 133,
 266                 .target_residency = 400,
 267                 .enter = &intel_idle },
 268         {
 269                 .name = "C7s-HSW",
 270                 .desc = "MWAIT 0x32",
 271                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 272                 .exit_latency = 166,
 273                 .target_residency = 500,
 274                 .enter = &intel_idle },
 275         {
 276                 .enter = NULL }
 277 };
 278
 279 static struct cpuidle_state atom_cstates[CPUIDLE_STATE_MAX] = {
 280         {
 281                 .name = "C1E-ATM",
 282                 .desc = "MWAIT 0x00",
 283                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 284                 .exit_latency = 10,
 285                 .target_residency = 20,
 286                 .enter = &intel_idle },
 287         {
 288                 .name = "C2-ATM",
 289                 .desc = "MWAIT 0x10",
 290                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID,
 291                 .exit_latency = 20,
 292                 .target_residency = 80,
 293                 .enter = &intel_idle },
 294         {
 295                 .name = "C4-ATM",
 296                 .desc = "MWAIT 0x30",
 297                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 298                 .exit_latency = 100,
 299                 .target_residency = 400,
 300                 .enter = &intel_idle },
 301         {
 302                 .name = "C6-ATM",
 303                 .desc = "MWAIT 0x52",
 304                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 305                 .exit_latency = 140,
 306                 .target_residency = 560,
 307                 .enter = &intel_idle },
 308         {
 309                 .enter = NULL }
 310 };
 311
 312 /**
 313  * intel_idle
 314  * @dev: cpuidle_device
 315  * @drv: cpuidle driver
 316  * @index: index of cpuidle state
 317  *
 318  * Must be called under local_irq_disable().
 319  */
 320 static int intel_idle(struct cpuidle_device *dev,
 321                 struct cpuidle_driver *drv, int index)
 322 {
 323         unsigned long ecx = 1; /* break on interrupt flag */
 324         struct cpuidle_state *state = &drv->states[index];
 325         unsigned long eax = flg2MWAIT(state->flags);
 326         unsigned int cstate;
 327         int cpu = smp_processor_id();
 328
 329         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 330
 331         /*
 332          * leave_mm() to avoid costly and often unnecessary wakeups
 333          * for flushing the user TLB's associated with the active mm.
 334          */
 335         if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
 336                 leave_mm(cpu);
 337
 338         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 339                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 340
 341         if (!need_resched()) {
 342
 343                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 344                 smp_mb();
 345                 if (!need_resched())
 346                         __mwait(eax, ecx);
 347         }
 348
 349         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 350                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 351
 352         return index;
 353 }
 354
 355 static void __setup_broadcast_timer(void *arg)
 356 {
 357         unsigned long reason = (unsigned long)arg;
 358         int cpu = smp_processor_id();
 359
 360         reason = reason ?
 361                 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
 362
 363         clockevents_notify(reason, &cpu);
 364 }
 365
 366 static int cpu_hotplug_notify(struct notifier_block *n,
 367                               unsigned long action, void *hcpu)
 368 {
 369         int hotcpu = (unsigned long)hcpu;
 370         struct cpuidle_device *dev;
 371
 372         switch (action & 0xf) {
 373         case CPU_ONLINE:
 374
 375                 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 376                         smp_call_function_single(hotcpu, __setup_broadcast_timer,
 377                                                  (void *)true, 1);
 378
 379                 /*
 380                  * Some systems can hotplug a cpu at runtime after
 381                  * the kernel has booted, we have to initialize the
 382                  * driver in this case
 383                  */
 384                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
 385                 if (!dev->registered)
 386                         intel_idle_cpu_init(hotcpu);
 387
 388                 break;
 389         }
 390         return NOTIFY_OK;
 391 }
 392
 393 static struct notifier_block cpu_hotplug_notifier = {
 394         .notifier_call = cpu_hotplug_notify,
 395 };
 396
 397 static void auto_demotion_disable(void *dummy)
 398 {
 399         unsigned long long msr_bits;
 400
 401         rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 402         msr_bits &= ~(icpu->auto_demotion_disable_flags);
 403         wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 404 }
 405 static void c1e_promotion_disable(void *dummy)
 406 {
 407         unsigned long long msr_bits;
 408
 409         rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
 410         msr_bits &= ~0x2;
 411         wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
 412 }
 413
 414 static const struct idle_cpu idle_cpu_nehalem = {
 415         .state_table = nehalem_cstates,
 416         .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
 417         .disable_promotion_to_c1e = true,
 418 };
 419
 420 static const struct idle_cpu idle_cpu_atom = {
 421         .state_table = atom_cstates,
 422 };
 423
 424 static const struct idle_cpu idle_cpu_lincroft = {
 425         .state_table = atom_cstates,
 426         .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
 427 };
 428
 429 static const struct idle_cpu idle_cpu_snb = {
 430         .state_table = snb_cstates,
 431         .disable_promotion_to_c1e = true,
 432 };
 433
 434 static const struct idle_cpu idle_cpu_ivb = {
 435         .state_table = ivb_cstates,
 436         .disable_promotion_to_c1e = true,
 437 };
 438
 439 static const struct idle_cpu idle_cpu_hsw = {
 440         .state_table = hsw_cstates,
 441         .disable_promotion_to_c1e = true,
 442 };
 443
 444 #define ICPU(model, cpu) \
 445         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
 446
 447 static const struct x86_cpu_id intel_idle_ids[] = {
 448         ICPU(0x1a, idle_cpu_nehalem),
 449         ICPU(0x1e, idle_cpu_nehalem),
 450         ICPU(0x1f, idle_cpu_nehalem),
 451         ICPU(0x25, idle_cpu_nehalem),
 452         ICPU(0x2c, idle_cpu_nehalem),
 453         ICPU(0x2e, idle_cpu_nehalem),
 454         ICPU(0x1c, idle_cpu_atom),
 455         ICPU(0x26, idle_cpu_lincroft),
 456         ICPU(0x2f, idle_cpu_nehalem),
 457         ICPU(0x2a, idle_cpu_snb),
 458         ICPU(0x2d, idle_cpu_snb),
 459         ICPU(0x3a, idle_cpu_ivb),
 460         ICPU(0x3e, idle_cpu_ivb),
 461         ICPU(0x3c, idle_cpu_hsw),
 462         ICPU(0x3f, idle_cpu_hsw),
 463         ICPU(0x45, idle_cpu_hsw),
 464         {}
 465 };
 466 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
 467
 468 /*
 469  * intel_idle_probe()
 470  */
 471 static int intel_idle_probe(void)
 472 {
 473         unsigned int eax, ebx, ecx;
 474         const struct x86_cpu_id *id;
 475
 476         if (max_cstate == 0) {
 477                 pr_debug(PREFIX "disabled\n");
 478                 return -EPERM;
 479         }
 480
 481         id = x86_match_cpu(intel_idle_ids);
 482         if (!id) {
 483                 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 484                     boot_cpu_data.x86 == 6)
 485                         pr_debug(PREFIX "does not run on family %d model %d\n",
 486                                 boot_cpu_data.x86, boot_cpu_data.x86_model);
 487                 return -ENODEV;
 488         }
 489
 490         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
 491                 return -ENODEV;
 492
 493         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
 494
 495         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 496             !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
 497             !mwait_substates)
 498                         return -ENODEV;
 499
 500         pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
 501
 502         icpu = (const struct idle_cpu *)id->driver_data;
 503         cpuidle_state_table = icpu->state_table;
 504
 505         if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
 506                 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 507         else
 508                 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
 509
 510         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
 511                 " model 0x%X\n", boot_cpu_data.x86_model);
 512
 513         pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
 514                 lapic_timer_reliable_states);
 515         return 0;
 516 }
 517
 518 /*
 519  * intel_idle_cpuidle_devices_uninit()
 520  * unregister, free cpuidle_devices
 521  */
 522 static void intel_idle_cpuidle_devices_uninit(void)
 523 {
 524         int i;
 525         struct cpuidle_device *dev;
 526
 527         for_each_online_cpu(i) {
 528                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 529                 cpuidle_unregister_device(dev);
 530         }
 531
 532         free_percpu(intel_idle_cpuidle_devices);
 533         return;
 534 }
 535 /*
 536  * intel_idle_cpuidle_driver_init()
 537  * allocate, initialize cpuidle_states
 538  */
 539 static int intel_idle_cpuidle_driver_init(void)
 540 {
 541         int cstate;
 542         struct cpuidle_driver *drv = &intel_idle_driver;
 543
 544         drv->state_count = 1;
 545
 546         for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
 547                 int num_substates, mwait_hint, mwait_cstate, mwait_substate;
 548
 549                 if (cpuidle_state_table[cstate].enter == NULL)
 550                         break;
 551
 552                 if (cstate + 1 > max_cstate) {
 553                         printk(PREFIX "max_cstate %d reached\n",
 554                                 max_cstate);
 555                         break;
 556                 }
 557
 558                 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
 559                 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
 560                 mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint);
 561
 562                 /* does the state exist in CPUID.MWAIT? */
 563                 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
 564                                         & MWAIT_SUBSTATE_MASK;
 565
 566                 /* if sub-state in table is not enumerated by CPUID */
 567                 if ((mwait_substate + 1) > num_substates)
 568                         continue;
 569
 570                 if (((mwait_cstate + 1) > 2) &&
 571                         !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 572                         mark_tsc_unstable("TSC halts in idle"
 573                                         " states deeper than C2");
 574
 575                 drv->states[drv->state_count] = /* structure copy */
 576                         cpuidle_state_table[cstate];
 577
 578                 drv->state_count += 1;
 579         }
 580
 581         if (icpu->auto_demotion_disable_flags)
 582                 on_each_cpu(auto_demotion_disable, NULL, 1);
 583
 584         if (icpu->disable_promotion_to_c1e)     /* each-cpu is redundant */
 585                 on_each_cpu(c1e_promotion_disable, NULL, 1);
 586
 587         return 0;
 588 }
 589
 590
 591 /*
 592  * intel_idle_cpu_init()
 593  * allocate, initialize, register cpuidle_devices
 594  * @cpu: cpu/core to initialize
 595  */
 596 static int intel_idle_cpu_init(int cpu)
 597 {
 598         int cstate;
 599         struct cpuidle_device *dev;
 600
 601         dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
 602
 603         dev->state_count = 1;
 604
 605         for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
 606                 int num_substates, mwait_hint, mwait_cstate, mwait_substate;
 607
 608                 if (cpuidle_state_table[cstate].enter == NULL)
 609                         continue;
 610
 611                 if (cstate + 1 > max_cstate) {
 612                         printk(PREFIX "max_cstate %d reached\n", max_cstate);
 613                         break;
 614                 }
 615
 616                 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
 617                 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
 618                 mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint);
 619
 620                 /* does the state exist in CPUID.MWAIT? */
 621                 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
 622                                         & MWAIT_SUBSTATE_MASK;
 623
 624                 /* if sub-state in table is not enumerated by CPUID */
 625                 if ((mwait_substate + 1) > num_substates)
 626                         continue;
 627
 628                 dev->state_count += 1;
 629         }
 630
 631         dev->cpu = cpu;
 632
 633         if (cpuidle_register_device(dev)) {
 634                 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
 635                 intel_idle_cpuidle_devices_uninit();
 636                 return -EIO;
 637         }
 638
 639         if (icpu->auto_demotion_disable_flags)
 640                 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
 641
 642         return 0;
 643 }
 644
 645 static int __init intel_idle_init(void)
 646 {
 647         int retval, i;
 648
 649         /* Do not load intel_idle at all for now if idle= is passed */
 650         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
 651                 return -ENODEV;
 652
 653         retval = intel_idle_probe();
 654         if (retval)
 655                 return retval;
 656
 657         intel_idle_cpuidle_driver_init();
 658         retval = cpuidle_register_driver(&intel_idle_driver);
 659         if (retval) {
 660                 struct cpuidle_driver *drv = cpuidle_get_driver();
 661                 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
 662                         drv ? drv->name : "none");
 663                 return retval;
 664         }
 665
 666         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
 667         if (intel_idle_cpuidle_devices == NULL)
 668                 return -ENOMEM;
 669
 670         for_each_online_cpu(i) {
 671                 retval = intel_idle_cpu_init(i);
 672                 if (retval) {
 673                         cpuidle_unregister_driver(&intel_idle_driver);
 674                         return retval;
 675                 }
 676         }
 677         register_cpu_notifier(&cpu_hotplug_notifier);
 678
 679         return 0;
 680 }
 681
 682 static void __exit intel_idle_exit(void)
 683 {
 684         intel_idle_cpuidle_devices_uninit();
 685         cpuidle_unregister_driver(&intel_idle_driver);
 686
 687
 688         if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 689                 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
 690         unregister_cpu_notifier(&cpu_hotplug_notifier);
 691
 692         return;
 693 }
 694
 695 module_init(intel_idle_init);
 696 module_exit(intel_idle_exit);
 697
 698 module_param(max_cstate, int, 0444);
 699
 700 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
 701 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
 702 MODULE_LICENSE("GPL");