drivers/iio/adc/ad7124.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AD7124 SPI ADC driver
   4  *
   5  * Copyright 2018 Analog Devices Inc.
   6  */
   7 #include <linux/bitfield.h>
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/err.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/spi/spi.h>
  16
  17 #include <linux/iio/iio.h>
  18 #include <linux/iio/adc/ad_sigma_delta.h>
  19 #include <linux/iio/sysfs.h>
  20
  21 /* AD7124 registers */
  22 #define AD7124_COMMS                    0x00
  23 #define AD7124_STATUS                   0x00
  24 #define AD7124_ADC_CONTROL              0x01
  25 #define AD7124_DATA                     0x02
  26 #define AD7124_IO_CONTROL_1             0x03
  27 #define AD7124_IO_CONTROL_2             0x04
  28 #define AD7124_ID                       0x05
  29 #define AD7124_ERROR                    0x06
  30 #define AD7124_ERROR_EN         0x07
  31 #define AD7124_MCLK_COUNT               0x08
  32 #define AD7124_CHANNEL(x)               (0x09 + (x))
  33 #define AD7124_CONFIG(x)                (0x19 + (x))
  34 #define AD7124_FILTER(x)                (0x21 + (x))
  35 #define AD7124_OFFSET(x)                (0x29 + (x))
  36 #define AD7124_GAIN(x)                  (0x31 + (x))
  37
  38 /* AD7124_STATUS */
  39 #define AD7124_STATUS_POR_FLAG_MSK      BIT(4)
  40
  41 /* AD7124_ADC_CONTROL */
  42 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
  43 #define AD7124_ADC_CTRL_PWR(x)          FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
  44 #define AD7124_ADC_CTRL_MODE_MSK        GENMASK(5, 2)
  45 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
  46
  47 /* AD7124_CHANNEL_X */
  48 #define AD7124_CHANNEL_EN_MSK           BIT(15)
  49 #define AD7124_CHANNEL_EN(x)            FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
  50 #define AD7124_CHANNEL_SETUP_MSK        GENMASK(14, 12)
  51 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
  52 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
  53 #define AD7124_CHANNEL_AINP(x)          FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
  54 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
  55 #define AD7124_CHANNEL_AINM(x)          FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
  56
  57 /* AD7124_CONFIG_X */
  58 #define AD7124_CONFIG_BIPOLAR_MSK       BIT(11)
  59 #define AD7124_CONFIG_BIPOLAR(x)        FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
  60 #define AD7124_CONFIG_REF_SEL_MSK       GENMASK(4, 3)
  61 #define AD7124_CONFIG_REF_SEL(x)        FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
  62 #define AD7124_CONFIG_PGA_MSK           GENMASK(2, 0)
  63 #define AD7124_CONFIG_PGA(x)            FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
  64
  65 /* AD7124_FILTER_X */
  66 #define AD7124_FILTER_FS_MSK            GENMASK(10, 0)
  67 #define AD7124_FILTER_FS(x)             FIELD_PREP(AD7124_FILTER_FS_MSK, x)
  68
  69 enum ad7124_ids {
  70         ID_AD7124_4,
  71         ID_AD7124_8,
  72 };
  73
  74 enum ad7124_ref_sel {
  75         AD7124_REFIN1,
  76         AD7124_REFIN2,
  77         AD7124_INT_REF,
  78         AD7124_AVDD_REF,
  79 };
  80
  81 enum ad7124_power_mode {
  82         AD7124_LOW_POWER,
  83         AD7124_MID_POWER,
  84         AD7124_FULL_POWER,
  85 };
  86
  87 static const unsigned int ad7124_gain[8] = {
  88         1, 2, 4, 8, 16, 32, 64, 128
  89 };
  90
  91 static const int ad7124_master_clk_freq_hz[3] = {
  92         [AD7124_LOW_POWER] = 76800,
  93         [AD7124_MID_POWER] = 153600,
  94         [AD7124_FULL_POWER] = 614400,
  95 };
  96
  97 static const char * const ad7124_ref_names[] = {
  98         [AD7124_REFIN1] = "refin1",
  99         [AD7124_REFIN2] = "refin2",
 100         [AD7124_INT_REF] = "int",
 101         [AD7124_AVDD_REF] = "avdd",
 102 };
 103
 104 struct ad7124_chip_info {
 105         unsigned int num_inputs;
 106 };
 107
 108 struct ad7124_channel_config {
 109         enum ad7124_ref_sel refsel;
 110         bool bipolar;
 111         unsigned int ain;
 112         unsigned int vref_mv;
 113         unsigned int pga_bits;
 114         unsigned int odr;
 115 };
 116
 117 struct ad7124_state {
 118         const struct ad7124_chip_info *chip_info;
 119         struct ad_sigma_delta sd;
 120         struct ad7124_channel_config channel_config[4];
 121         struct regulator *vref[4];
 122         struct clk *mclk;
 123         unsigned int adc_control;
 124         unsigned int num_channels;
 125 };
 126
 127 static const struct iio_chan_spec ad7124_channel_template = {
 128         .type = IIO_VOLTAGE,
 129         .indexed = 1,
 130         .differential = 1,
 131         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 132                 BIT(IIO_CHAN_INFO_SCALE) |
 133                 BIT(IIO_CHAN_INFO_OFFSET) |
 134                 BIT(IIO_CHAN_INFO_SAMP_FREQ),
 135         .scan_type = {
 136                 .sign = 'u',
 137                 .realbits = 24,
 138                 .storagebits = 32,
 139                 .shift = 8,
 140                 .endianness = IIO_BE,
 141         },
 142 };
 143
 144 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
 145         [ID_AD7124_4] = {
 146                 .num_inputs = 8,
 147         },
 148         [ID_AD7124_8] = {
 149                 .num_inputs = 16,
 150         },
 151 };
 152
 153 static int ad7124_find_closest_match(const int *array,
 154                                      unsigned int size, int val)
 155 {
 156         int i, idx;
 157         unsigned int diff_new, diff_old;
 158
 159         diff_old = U32_MAX;
 160         idx = 0;
 161
 162         for (i = 0; i < size; i++) {
 163                 diff_new = abs(val - array[i]);
 164                 if (diff_new < diff_old) {
 165                         diff_old = diff_new;
 166                         idx = i;
 167                 }
 168         }
 169
 170         return idx;
 171 }
 172
 173 static int ad7124_spi_write_mask(struct ad7124_state *st,
 174                                  unsigned int addr,
 175                                  unsigned long mask,
 176                                  unsigned int val,
 177                                  unsigned int bytes)
 178 {
 179         unsigned int readval;
 180         int ret;
 181
 182         ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
 183         if (ret < 0)
 184                 return ret;
 185
 186         readval &= ~mask;
 187         readval |= val;
 188
 189         return ad_sd_write_reg(&st->sd, addr, bytes, readval);
 190 }
 191
 192 static int ad7124_set_mode(struct ad_sigma_delta *sd,
 193                            enum ad_sigma_delta_mode mode)
 194 {
 195         struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
 196
 197         st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
 198         st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
 199
 200         return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
 201 }
 202
 203 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
 204 {
 205         struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
 206         unsigned int val;
 207
 208         val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |
 209               AD7124_CHANNEL_SETUP(channel);
 210
 211         return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);
 212 }
 213
 214 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
 215         .set_channel = ad7124_set_channel,
 216         .set_mode = ad7124_set_mode,
 217         .has_registers = true,
 218         .addr_shift = 0,
 219         .read_mask = BIT(6),
 220         .data_reg = AD7124_DATA,
 221 };
 222
 223 static int ad7124_set_channel_odr(struct ad7124_state *st,
 224                                   unsigned int channel,
 225                                   unsigned int odr)
 226 {
 227         unsigned int fclk, odr_sel_bits;
 228         int ret;
 229
 230         fclk = clk_get_rate(st->mclk);
 231         /*
 232          * FS[10:0] = fCLK / (fADC x 32) where:
 233          * fADC is the output data rate
 234          * fCLK is the master clock frequency
 235          * FS[10:0] are the bits in the filter register
 236          * FS[10:0] can have a value from 1 to 2047
 237          */
 238         odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
 239         if (odr_sel_bits < 1)
 240                 odr_sel_bits = 1;
 241         else if (odr_sel_bits > 2047)
 242                 odr_sel_bits = 2047;
 243
 244         ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
 245                                     AD7124_FILTER_FS_MSK,
 246                                     AD7124_FILTER_FS(odr_sel_bits), 3);
 247         if (ret < 0)
 248                 return ret;
 249         /* fADC = fCLK / (FS[10:0] x 32) */
 250         st->channel_config[channel].odr =
 251                 DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
 252
 253         return 0;
 254 }
 255
 256 static int ad7124_set_channel_gain(struct ad7124_state *st,
 257                                    unsigned int channel,
 258                                    unsigned int gain)
 259 {
 260         unsigned int res;
 261         int ret;
 262
 263         res = ad7124_find_closest_match(ad7124_gain,
 264                                         ARRAY_SIZE(ad7124_gain), gain);
 265         ret = ad7124_spi_write_mask(st, AD7124_CONFIG(channel),
 266                                     AD7124_CONFIG_PGA_MSK,
 267                                     AD7124_CONFIG_PGA(res), 2);
 268         if (ret < 0)
 269                 return ret;
 270
 271         st->channel_config[channel].pga_bits = res;
 272
 273         return 0;
 274 }
 275
 276 static int ad7124_read_raw(struct iio_dev *indio_dev,
 277                            struct iio_chan_spec const *chan,
 278                            int *val, int *val2, long info)
 279 {
 280         struct ad7124_state *st = iio_priv(indio_dev);
 281         int idx, ret;
 282
 283         switch (info) {
 284         case IIO_CHAN_INFO_RAW:
 285                 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
 286                 if (ret < 0)
 287                         return ret;
 288
 289                 /* After the conversion is performed, disable the channel */
 290                 ret = ad_sd_write_reg(&st->sd,
 291                                       AD7124_CHANNEL(chan->address), 2,
 292                                       st->channel_config[chan->address].ain |
 293                                       AD7124_CHANNEL_EN(0));
 294                 if (ret < 0)
 295                         return ret;
 296
 297                 return IIO_VAL_INT;
 298         case IIO_CHAN_INFO_SCALE:
 299                 idx = st->channel_config[chan->address].pga_bits;
 300                 *val = st->channel_config[chan->address].vref_mv;
 301                 if (st->channel_config[chan->address].bipolar)
 302                         *val2 = chan->scan_type.realbits - 1 + idx;
 303                 else
 304                         *val2 = chan->scan_type.realbits + idx;
 305
 306                 return IIO_VAL_FRACTIONAL_LOG2;
 307         case IIO_CHAN_INFO_OFFSET:
 308                 if (st->channel_config[chan->address].bipolar)
 309                         *val = -(1 << (chan->scan_type.realbits - 1));
 310                 else
 311                         *val = 0;
 312
 313                 return IIO_VAL_INT;
 314         case IIO_CHAN_INFO_SAMP_FREQ:
 315                 *val = st->channel_config[chan->address].odr;
 316
 317                 return IIO_VAL_INT;
 318         default:
 319                 return -EINVAL;
 320         }
 321 }
 322
 323 static int ad7124_write_raw(struct iio_dev *indio_dev,
 324                             struct iio_chan_spec const *chan,
 325                             int val, int val2, long info)
 326 {
 327         struct ad7124_state *st = iio_priv(indio_dev);
 328         unsigned int res, gain, full_scale, vref;
 329
 330         switch (info) {
 331         case IIO_CHAN_INFO_SAMP_FREQ:
 332                 if (val2 != 0)
 333                         return -EINVAL;
 334
 335                 return ad7124_set_channel_odr(st, chan->address, val);
 336         case IIO_CHAN_INFO_SCALE:
 337                 if (val != 0)
 338                         return -EINVAL;
 339
 340                 if (st->channel_config[chan->address].bipolar)
 341                         full_scale = 1 << (chan->scan_type.realbits - 1);
 342                 else
 343                         full_scale = 1 << chan->scan_type.realbits;
 344
 345                 vref = st->channel_config[chan->address].vref_mv * 1000000LL;
 346                 res = DIV_ROUND_CLOSEST(vref, full_scale);
 347                 gain = DIV_ROUND_CLOSEST(res, val2);
 348
 349                 return ad7124_set_channel_gain(st, chan->address, gain);
 350         default:
 351                 return -EINVAL;
 352         }
 353 }
 354
 355 static IIO_CONST_ATTR(in_voltage_scale_available,
 356         "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
 357
 358 static struct attribute *ad7124_attributes[] = {
 359         &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
 360         NULL,
 361 };
 362
 363 static const struct attribute_group ad7124_attrs_group = {
 364         .attrs = ad7124_attributes,
 365 };
 366
 367 static const struct iio_info ad7124_info = {
 368         .read_raw = ad7124_read_raw,
 369         .write_raw = ad7124_write_raw,
 370         .validate_trigger = ad_sd_validate_trigger,
 371         .attrs = &ad7124_attrs_group,
 372 };
 373
 374 static int ad7124_soft_reset(struct ad7124_state *st)
 375 {
 376         unsigned int readval, timeout;
 377         int ret;
 378
 379         ret = ad_sd_reset(&st->sd, 64);
 380         if (ret < 0)
 381                 return ret;
 382
 383         timeout = 100;
 384         do {
 385                 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
 386                 if (ret < 0)
 387                         return ret;
 388
 389                 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
 390                         return 0;
 391
 392                 /* The AD7124 requires typically 2ms to power up and settle */
 393                 usleep_range(100, 2000);
 394         } while (--timeout);
 395
 396         dev_err(&st->sd.spi->dev, "Soft reset failed\n");
 397
 398         return -EIO;
 399 }
 400
 401 static int ad7124_init_channel_vref(struct ad7124_state *st,
 402                                     unsigned int channel_number)
 403 {
 404         unsigned int refsel = st->channel_config[channel_number].refsel;
 405
 406         switch (refsel) {
 407         case AD7124_REFIN1:
 408         case AD7124_REFIN2:
 409         case AD7124_AVDD_REF:
 410                 if (IS_ERR(st->vref[refsel])) {
 411                         dev_err(&st->sd.spi->dev,
 412                                 "Error, trying to use external voltage reference without a %s regulator.\n",
 413                                 ad7124_ref_names[refsel]);
 414                                 return PTR_ERR(st->vref[refsel]);
 415                 }
 416                 st->channel_config[channel_number].vref_mv =
 417                         regulator_get_voltage(st->vref[refsel]);
 418                 /* Conversion from uV to mV */
 419                 st->channel_config[channel_number].vref_mv /= 1000;
 420                 break;
 421         case AD7124_INT_REF:
 422                 st->channel_config[channel_number].vref_mv = 2500;
 423                 break;
 424         default:
 425                 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
 426                 return -EINVAL;
 427         }
 428
 429         return 0;
 430 }
 431
 432 static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
 433                                           struct device_node *np)
 434 {
 435         struct ad7124_state *st = iio_priv(indio_dev);
 436         struct device_node *child;
 437         struct iio_chan_spec *chan;
 438         unsigned int ain[2], channel = 0, tmp;
 439         int ret;
 440
 441         st->num_channels = of_get_available_child_count(np);
 442         if (!st->num_channels) {
 443                 dev_err(indio_dev->dev.parent, "no channel children\n");
 444                 return -ENODEV;
 445         }
 446
 447         chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
 448                             sizeof(*chan), GFP_KERNEL);
 449         if (!chan)
 450                 return -ENOMEM;
 451
 452         indio_dev->channels = chan;
 453         indio_dev->num_channels = st->num_channels;
 454
 455         for_each_available_child_of_node(np, child) {
 456                 ret = of_property_read_u32(child, "reg", &channel);
 457                 if (ret)
 458                         goto err;
 459
 460                 ret = of_property_read_u32_array(child, "diff-channels",
 461                                                  ain, 2);
 462                 if (ret)
 463                         goto err;
 464
 465                 if (ain[0] >= st->chip_info->num_inputs ||
 466                     ain[1] >= st->chip_info->num_inputs) {
 467                         dev_err(indio_dev->dev.parent,
 468                                 "Input pin number out of range.\n");
 469                         ret = -EINVAL;
 470                         goto err;
 471                 }
 472                 st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
 473                                                   AD7124_CHANNEL_AINM(ain[1]);
 474                 st->channel_config[channel].bipolar =
 475                         of_property_read_bool(child, "bipolar");
 476
 477                 ret = of_property_read_u32(child, "adi,reference-select", &tmp);
 478                 if (ret)
 479                         st->channel_config[channel].refsel = AD7124_INT_REF;
 480                 else
 481                         st->channel_config[channel].refsel = tmp;
 482
 483                 *chan = ad7124_channel_template;
 484                 chan->address = channel;
 485                 chan->scan_index = channel;
 486                 chan->channel = ain[0];
 487                 chan->channel2 = ain[1];
 488
 489                 chan++;
 490         }
 491
 492         return 0;
 493 err:
 494         of_node_put(child);
 495
 496         return ret;
 497 }
 498
 499 static int ad7124_setup(struct ad7124_state *st)
 500 {
 501         unsigned int val, fclk, power_mode;
 502         int i, ret;
 503
 504         fclk = clk_get_rate(st->mclk);
 505         if (!fclk)
 506                 return -EINVAL;
 507
 508         /* The power mode changes the master clock frequency */
 509         power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
 510                                         ARRAY_SIZE(ad7124_master_clk_freq_hz),
 511                                         fclk);
 512         if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
 513                 ret = clk_set_rate(st->mclk, fclk);
 514                 if (ret)
 515                         return ret;
 516         }
 517
 518         /* Set the power mode */
 519         st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
 520         st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
 521         ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
 522         if (ret < 0)
 523                 return ret;
 524
 525         for (i = 0; i < st->num_channels; i++) {
 526                 val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);
 527                 ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);
 528                 if (ret < 0)
 529                         return ret;
 530
 531                 ret = ad7124_init_channel_vref(st, i);
 532                 if (ret < 0)
 533                         return ret;
 534
 535                 val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |
 536                       AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel);
 537                 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);
 538                 if (ret < 0)
 539                         return ret;
 540                 /*
 541                  * 9.38 SPS is the minimum output data rate supported
 542                  * regardless of the selected power mode. Round it up to 10 and
 543                  * set all the enabled channels to this default value.
 544                  */
 545                 ret = ad7124_set_channel_odr(st, i, 10);
 546         }
 547
 548         return ret;
 549 }
 550
 551 static int ad7124_probe(struct spi_device *spi)
 552 {
 553         const struct spi_device_id *id;
 554         struct ad7124_state *st;
 555         struct iio_dev *indio_dev;
 556         int i, ret;
 557
 558         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 559         if (!indio_dev)
 560                 return -ENOMEM;
 561
 562         st = iio_priv(indio_dev);
 563
 564         id = spi_get_device_id(spi);
 565         st->chip_info = &ad7124_chip_info_tbl[id->driver_data];
 566
 567         ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
 568
 569         spi_set_drvdata(spi, indio_dev);
 570
 571         indio_dev->dev.parent = &spi->dev;
 572         indio_dev->name = spi_get_device_id(spi)->name;
 573         indio_dev->modes = INDIO_DIRECT_MODE;
 574         indio_dev->info = &ad7124_info;
 575
 576         ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
 577         if (ret < 0)
 578                 return ret;
 579
 580         for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
 581                 if (i == AD7124_INT_REF)
 582                         continue;
 583
 584                 st->vref[i] = devm_regulator_get_optional(&spi->dev,
 585                                                 ad7124_ref_names[i]);
 586                 if (PTR_ERR(st->vref[i]) == -ENODEV)
 587                         continue;
 588                 else if (IS_ERR(st->vref[i]))
 589                         return PTR_ERR(st->vref[i]);
 590
 591                 ret = regulator_enable(st->vref[i]);
 592                 if (ret)
 593                         return ret;
 594         }
 595
 596         st->mclk = devm_clk_get(&spi->dev, "mclk");
 597         if (IS_ERR(st->mclk)) {
 598                 ret = PTR_ERR(st->mclk);
 599                 goto error_regulator_disable;
 600         }
 601
 602         ret = clk_prepare_enable(st->mclk);
 603         if (ret < 0)
 604                 goto error_regulator_disable;
 605
 606         ret = ad7124_soft_reset(st);
 607         if (ret < 0)
 608                 goto error_clk_disable_unprepare;
 609
 610         ret = ad7124_setup(st);
 611         if (ret < 0)
 612                 goto error_clk_disable_unprepare;
 613
 614         ret = ad_sd_setup_buffer_and_trigger(indio_dev);
 615         if (ret < 0)
 616                 goto error_clk_disable_unprepare;
 617
 618         ret = iio_device_register(indio_dev);
 619         if (ret < 0) {
 620                 dev_err(&spi->dev, "Failed to register iio device\n");
 621                 goto error_remove_trigger;
 622         }
 623
 624         return 0;
 625
 626 error_remove_trigger:
 627         ad_sd_cleanup_buffer_and_trigger(indio_dev);
 628 error_clk_disable_unprepare:
 629         clk_disable_unprepare(st->mclk);
 630 error_regulator_disable:
 631         for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
 632                 if (!IS_ERR_OR_NULL(st->vref[i]))
 633                         regulator_disable(st->vref[i]);
 634         }
 635
 636         return ret;
 637 }
 638
 639 static int ad7124_remove(struct spi_device *spi)
 640 {
 641         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 642         struct ad7124_state *st = iio_priv(indio_dev);
 643         int i;
 644
 645         iio_device_unregister(indio_dev);
 646         ad_sd_cleanup_buffer_and_trigger(indio_dev);
 647         clk_disable_unprepare(st->mclk);
 648
 649         for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
 650                 if (!IS_ERR_OR_NULL(st->vref[i]))
 651                         regulator_disable(st->vref[i]);
 652         }
 653
 654         return 0;
 655 }
 656
 657 static const struct spi_device_id ad7124_id_table[] = {
 658         { "ad7124-4", ID_AD7124_4 },
 659         { "ad7124-8", ID_AD7124_8 },
 660         {}
 661 };
 662 MODULE_DEVICE_TABLE(spi, ad7124_id_table);
 663
 664 static const struct of_device_id ad7124_of_match[] = {
 665         { .compatible = "adi,ad7124-4" },
 666         { .compatible = "adi,ad7124-8" },
 667         { },
 668 };
 669 MODULE_DEVICE_TABLE(of, ad7124_of_match);
 670
 671 static struct spi_driver ad71124_driver = {
 672         .driver = {
 673                 .name = "ad7124",
 674                 .of_match_table = ad7124_of_match,
 675         },
 676         .probe = ad7124_probe,
 677         .remove = ad7124_remove,
 678         .id_table = ad7124_id_table,
 679 };
 680 module_spi_driver(ad71124_driver);
 681
 682 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
 683 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
 684 MODULE_LICENSE("GPL");