2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #ifndef __IW_CXGB4_H__
32 #define __IW_CXGB4_H__
34 #include <linux/mutex.h>
35 #include <linux/list.h>
36 #include <linux/spinlock.h>
37 #include <linux/idr.h>
38 #include <linux/completion.h>
39 #include <linux/netdevice.h>
40 #include <linux/sched.h>
41 #include <linux/pci.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/inet.h>
44 #include <linux/wait.h>
45 #include <linux/kref.h>
46 #include <linux/timer.h>
49 #include <asm/byteorder.h>
51 #include <net/net_namespace.h>
53 #include <rdma/ib_verbs.h>
54 #include <rdma/iw_cm.h>
57 #include "cxgb4_uld.h"
61 #define DRV_NAME "iw_cxgb4"
62 #define MOD DRV_NAME ":"
64 extern int c4iw_debug;
65 #define PDBG(fmt, args...) \
68 printk(MOD fmt, ## args); \
73 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
74 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
76 static inline void *cplhdr(struct sk_buff *skb)
81 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
82 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
84 struct c4iw_id_table {
86 u32 start; /* logical minimal id */
87 u32 last; /* hint for find */
93 struct c4iw_resource {
94 struct c4iw_id_table tpt_table;
95 struct c4iw_id_table qid_table;
96 struct c4iw_id_table pdid_table;
99 struct c4iw_qid_list {
100 struct list_head entry;
104 struct c4iw_dev_ucontext {
105 struct list_head qpids;
106 struct list_head cqids;
110 enum c4iw_rdev_flags {
111 T4_FATAL_ERROR = (1<<0),
123 struct c4iw_stat qid;
125 struct c4iw_stat stag;
126 struct c4iw_stat pbl;
127 struct c4iw_stat rqt;
128 struct c4iw_stat ocqp;
132 u64 db_state_transitions;
136 struct c4iw_resource resource;
137 unsigned long qpshift;
139 unsigned long cqshift;
141 struct c4iw_dev_ucontext uctx;
142 struct gen_pool *pbl_pool;
143 struct gen_pool *rqt_pool;
144 struct gen_pool *ocqp_pool;
146 struct cxgb4_lld_info lldi;
147 unsigned long oc_mw_pa;
148 void __iomem *oc_mw_kva;
149 struct c4iw_stats stats;
152 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
154 return rdev->flags & T4_FATAL_ERROR;
157 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
159 return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
162 #define C4IW_WR_TO (10*HZ)
164 struct c4iw_wr_wait {
165 struct completion completion;
169 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
172 init_completion(&wr_waitp->completion);
175 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
178 complete(&wr_waitp->completion);
181 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
182 struct c4iw_wr_wait *wr_waitp,
186 unsigned to = C4IW_WR_TO;
190 ret = wait_for_completion_timeout(&wr_waitp->completion, to);
192 printk(KERN_ERR MOD "%s - Device %s not responding - "
193 "tid %u qpid %u\n", func,
194 pci_name(rdev->lldi.pdev), hwtid, qpid);
195 if (c4iw_fatal_error(rdev)) {
196 wr_waitp->ret = -EIO;
203 PDBG("%s: FW reply %d tid %u qpid %u\n",
204 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
205 return wr_waitp->ret;
215 struct ib_device ibdev;
216 struct c4iw_rdev rdev;
217 u32 device_cap_flags;
222 struct mutex db_mutex;
223 struct dentry *debugfs_root;
224 enum db_state db_state;
228 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
230 return container_of(ibdev, struct c4iw_dev, ibdev);
233 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
235 return container_of(rdev, struct c4iw_dev, rdev);
238 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
240 return idr_find(&rhp->cqidr, cqid);
243 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
245 return idr_find(&rhp->qpidr, qpid);
248 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
250 return idr_find(&rhp->mmidr, mmid);
253 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
254 void *handle, u32 id, int lock)
260 if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC))
263 spin_lock_irq(&rhp->lock);
264 ret = idr_get_new_above(idr, handle, id, &newid);
265 BUG_ON(!ret && newid != id);
267 spin_unlock_irq(&rhp->lock);
268 } while (ret == -EAGAIN);
273 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
274 void *handle, u32 id)
276 return _insert_handle(rhp, idr, handle, id, 1);
279 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
280 void *handle, u32 id)
282 return _insert_handle(rhp, idr, handle, id, 0);
285 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
289 spin_lock_irq(&rhp->lock);
292 spin_unlock_irq(&rhp->lock);
295 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
297 _remove_handle(rhp, idr, id, 1);
300 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
301 struct idr *idr, u32 id)
303 _remove_handle(rhp, idr, id, 0);
309 struct c4iw_dev *rhp;
312 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
314 return container_of(ibpd, struct c4iw_pd, ibpd);
317 struct tpt_attributes {
320 enum fw_ri_mem_perms perms;
329 u32 remote_invaliate_disable:1;
331 u32 mw_bind_enable:1;
337 struct ib_umem *umem;
338 struct c4iw_dev *rhp;
340 struct tpt_attributes attr;
343 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
345 return container_of(ibmr, struct c4iw_mr, ibmr);
350 struct c4iw_dev *rhp;
352 struct tpt_attributes attr;
355 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
357 return container_of(ibmw, struct c4iw_mw, ibmw);
360 struct c4iw_fr_page_list {
361 struct ib_fast_reg_page_list ibpl;
362 DEFINE_DMA_UNMAP_ADDR(mapping);
364 struct c4iw_dev *dev;
368 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
369 struct ib_fast_reg_page_list *ibpl)
371 return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
376 struct c4iw_dev *rhp;
379 spinlock_t comp_handler_lock;
381 wait_queue_head_t wait;
384 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
386 return container_of(ibcq, struct c4iw_cq, ibcq);
389 struct c4iw_mpa_attributes {
391 u8 recv_marker_enabled;
392 u8 xmit_marker_enabled;
394 u8 enhanced_rdma_conn;
399 struct c4iw_qp_attributes {
405 u32 sq_max_sges_rdma_write;
409 u8 enable_rdma_write;
411 u8 enable_mmid0_fastreg;
416 char terminate_buffer[52];
417 u32 terminate_msg_len;
418 u8 is_terminate_local;
419 struct c4iw_mpa_attributes mpa_attr;
420 struct c4iw_ep *llp_stream_handle;
429 struct c4iw_dev *rhp;
431 struct c4iw_qp_attributes attr;
436 wait_queue_head_t wait;
437 struct timer_list timer;
440 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
442 return container_of(ibqp, struct c4iw_qp, ibqp);
445 struct c4iw_ucontext {
446 struct ib_ucontext ibucontext;
447 struct c4iw_dev_ucontext uctx;
449 spinlock_t mmap_lock;
450 struct list_head mmaps;
453 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
455 return container_of(c, struct c4iw_ucontext, ibucontext);
458 struct c4iw_mm_entry {
459 struct list_head entry;
465 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
466 u32 key, unsigned len)
468 struct list_head *pos, *nxt;
469 struct c4iw_mm_entry *mm;
471 spin_lock(&ucontext->mmap_lock);
472 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
474 mm = list_entry(pos, struct c4iw_mm_entry, entry);
475 if (mm->key == key && mm->len == len) {
476 list_del_init(&mm->entry);
477 spin_unlock(&ucontext->mmap_lock);
478 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
479 key, (unsigned long long) mm->addr, mm->len);
483 spin_unlock(&ucontext->mmap_lock);
487 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
488 struct c4iw_mm_entry *mm)
490 spin_lock(&ucontext->mmap_lock);
491 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
492 mm->key, (unsigned long long) mm->addr, mm->len);
493 list_add_tail(&mm->entry, &ucontext->mmaps);
494 spin_unlock(&ucontext->mmap_lock);
497 enum c4iw_qp_attr_mask {
498 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
499 C4IW_QP_ATTR_SQ_DB = 1<<1,
500 C4IW_QP_ATTR_RQ_DB = 1<<2,
501 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
502 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
503 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
504 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
505 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
506 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
507 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
508 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
509 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
510 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
511 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
512 C4IW_QP_ATTR_MAX_ORD |
513 C4IW_QP_ATTR_MAX_IRD |
514 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
515 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
516 C4IW_QP_ATTR_MPA_ATTR |
517 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
520 int c4iw_modify_qp(struct c4iw_dev *rhp,
522 enum c4iw_qp_attr_mask mask,
523 struct c4iw_qp_attributes *attrs,
530 C4IW_QP_STATE_TERMINATE,
531 C4IW_QP_STATE_CLOSING,
535 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
540 return C4IW_QP_STATE_IDLE;
542 return C4IW_QP_STATE_RTS;
544 return C4IW_QP_STATE_CLOSING;
546 return C4IW_QP_STATE_TERMINATE;
548 return C4IW_QP_STATE_ERROR;
554 static inline int to_ib_qp_state(int c4iw_qp_state)
556 switch (c4iw_qp_state) {
557 case C4IW_QP_STATE_IDLE:
559 case C4IW_QP_STATE_RTS:
561 case C4IW_QP_STATE_CLOSING:
563 case C4IW_QP_STATE_TERMINATE:
565 case C4IW_QP_STATE_ERROR:
571 static inline u32 c4iw_ib_to_tpt_access(int a)
573 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
574 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
575 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
576 FW_RI_MEM_ACCESS_LOCAL_READ;
579 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
581 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
582 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
585 enum c4iw_mmid_state {
586 C4IW_STAG_STATE_VALID,
587 C4IW_STAG_STATE_INVALID
590 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
592 #define MPA_KEY_REQ "MPA ID Req Frame"
593 #define MPA_KEY_REP "MPA ID Rep Frame"
595 #define MPA_MAX_PRIVATE_DATA 256
596 #define MPA_ENHANCED_RDMA_CONN 0x10
597 #define MPA_REJECT 0x20
599 #define MPA_MARKERS 0x80
600 #define MPA_FLAGS_MASK 0xE0
602 #define MPA_V2_PEER2PEER_MODEL 0x8000
603 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
604 #define MPA_V2_RDMA_WRITE_RTR 0x8000
605 #define MPA_V2_RDMA_READ_RTR 0x4000
606 #define MPA_V2_IRD_ORD_MASK 0x3FFF
608 #define c4iw_put_ep(ep) { \
609 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \
610 ep, atomic_read(&((ep)->kref.refcount))); \
611 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
612 kref_put(&((ep)->kref), _c4iw_free_ep); \
615 #define c4iw_get_ep(ep) { \
616 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
617 ep, atomic_read(&((ep)->kref.refcount))); \
618 kref_get(&((ep)->kref)); \
620 void _c4iw_free_ep(struct kref *kref);
626 __be16 private_data_size;
630 struct mpa_v2_conn_params {
635 struct terminate_message {
642 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
644 enum c4iw_layers_types {
648 RDMAP_LOCAL_CATA = 0x00,
649 RDMAP_REMOTE_PROT = 0x01,
650 RDMAP_REMOTE_OP = 0x02,
651 DDP_LOCAL_CATA = 0x00,
652 DDP_TAGGED_ERR = 0x01,
653 DDP_UNTAGGED_ERR = 0x02,
657 enum c4iw_rdma_ecodes {
658 RDMAP_INV_STAG = 0x00,
659 RDMAP_BASE_BOUNDS = 0x01,
660 RDMAP_ACC_VIOL = 0x02,
661 RDMAP_STAG_NOT_ASSOC = 0x03,
662 RDMAP_TO_WRAP = 0x04,
663 RDMAP_INV_VERS = 0x05,
664 RDMAP_INV_OPCODE = 0x06,
665 RDMAP_STREAM_CATA = 0x07,
666 RDMAP_GLOBAL_CATA = 0x08,
667 RDMAP_CANT_INV_STAG = 0x09,
668 RDMAP_UNSPECIFIED = 0xff
671 enum c4iw_ddp_ecodes {
672 DDPT_INV_STAG = 0x00,
673 DDPT_BASE_BOUNDS = 0x01,
674 DDPT_STAG_NOT_ASSOC = 0x02,
676 DDPT_INV_VERS = 0x04,
678 DDPU_INV_MSN_NOBUF = 0x02,
679 DDPU_INV_MSN_RANGE = 0x03,
681 DDPU_MSG_TOOBIG = 0x05,
685 enum c4iw_mpa_ecodes {
687 MPA_MARKER_ERR = 0x03,
688 MPA_LOCAL_CATA = 0x05,
689 MPA_INSUFF_IRD = 0x06,
690 MPA_NOMATCH_RTR = 0x07,
709 PEER_ABORT_IN_PROGRESS = 0,
710 ABORT_REQ_IN_PROGRESS = 1,
711 RELEASE_RESOURCES = 2,
715 struct c4iw_ep_common {
716 struct iw_cm_id *cm_id;
718 struct c4iw_dev *dev;
719 enum c4iw_ep_state state;
722 struct sockaddr_in local_addr;
723 struct sockaddr_in remote_addr;
724 struct c4iw_wr_wait wr_wait;
728 struct c4iw_listen_ep {
729 struct c4iw_ep_common com;
735 struct c4iw_ep_common com;
736 struct c4iw_ep *parent_ep;
737 struct timer_list timer;
738 struct list_head entry;
743 struct l2t_entry *l2t;
744 struct dst_entry *dst;
745 struct sk_buff *mpa_skb;
746 struct c4iw_mpa_attributes mpa_attr;
747 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
748 unsigned int mpa_pkt_len;
761 u8 retry_with_mpa_v1;
762 u8 tried_with_mpa_v1;
765 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
767 return cm_id->provider_data;
770 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
772 return cm_id->provider_data;
775 static inline int compute_wscale(int win)
779 while (wscale < 14 && (65535<<wscale) < win)
784 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
785 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
786 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
787 u32 reserved, u32 flags);
788 void c4iw_id_table_free(struct c4iw_id_table *alloc);
790 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
792 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
793 struct l2t_entry *l2t);
794 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
795 struct c4iw_dev_ucontext *uctx);
796 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
797 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
798 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
799 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
800 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
801 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
802 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
803 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
804 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
805 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
806 void c4iw_destroy_resource(struct c4iw_resource *rscp);
807 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
808 int c4iw_register_device(struct c4iw_dev *dev);
809 void c4iw_unregister_device(struct c4iw_dev *dev);
810 int __init c4iw_cm_init(void);
811 void __exit c4iw_cm_term(void);
812 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
813 struct c4iw_dev_ucontext *uctx);
814 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
815 struct c4iw_dev_ucontext *uctx);
816 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
817 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
818 struct ib_send_wr **bad_wr);
819 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
820 struct ib_recv_wr **bad_wr);
821 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
822 struct ib_mw_bind *mw_bind);
823 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
824 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
825 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
826 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
827 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
828 void c4iw_qp_add_ref(struct ib_qp *qp);
829 void c4iw_qp_rem_ref(struct ib_qp *qp);
830 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
831 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
832 struct ib_device *device,
834 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
835 int c4iw_dealloc_mw(struct ib_mw *mw);
836 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd);
837 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
838 u64 length, u64 virt, int acc,
839 struct ib_udata *udata);
840 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
841 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
842 struct ib_phys_buf *buffer_list,
846 int c4iw_reregister_phys_mem(struct ib_mr *mr,
849 struct ib_phys_buf *buffer_list,
851 int acc, u64 *iova_start);
852 int c4iw_dereg_mr(struct ib_mr *ib_mr);
853 int c4iw_destroy_cq(struct ib_cq *ib_cq);
854 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
856 struct ib_ucontext *ib_context,
857 struct ib_udata *udata);
858 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
859 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
860 int c4iw_destroy_qp(struct ib_qp *ib_qp);
861 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
862 struct ib_qp_init_attr *attrs,
863 struct ib_udata *udata);
864 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
865 int attr_mask, struct ib_udata *udata);
866 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
867 int attr_mask, struct ib_qp_init_attr *init_attr);
868 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
869 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
870 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
871 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
872 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
873 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
874 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
875 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
876 void c4iw_flush_hw_cq(struct t4_cq *cq);
877 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
878 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
879 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
880 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
881 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
882 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
883 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
884 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
885 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
886 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
887 struct c4iw_dev_ucontext *uctx);
888 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
889 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
890 struct c4iw_dev_ucontext *uctx);
891 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
893 extern struct cxgb4_client t4c_client;
894 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
895 extern int c4iw_max_read_depth;
896 extern int db_fc_threshold;