drivers/infiniband/hw/hns/hns_roce_hw_v2.c

   1 /*
   2  * Copyright (c) 2016-2017 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/acpi.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/kernel.h>
  37 #include <linux/types.h>
  38 #include <net/addrconf.h>
  39 #include <rdma/ib_addr.h>
  40 #include <rdma/ib_cache.h>
  41 #include <rdma/ib_umem.h>
  42 #include <rdma/uverbs_ioctl.h>
  43
  44 #include "hnae3.h"
  45 #include "hns_roce_common.h"
  46 #include "hns_roce_device.h"
  47 #include "hns_roce_cmd.h"
  48 #include "hns_roce_hem.h"
  49 #include "hns_roce_hw_v2.h"
  50
  51 enum {
  52         CMD_RST_PRC_OTHERS,
  53         CMD_RST_PRC_SUCCESS,
  54         CMD_RST_PRC_EBUSY,
  55 };
  56
  57 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
  58                                    struct ib_sge *sg)
  59 {
  60         dseg->lkey = cpu_to_le32(sg->lkey);
  61         dseg->addr = cpu_to_le64(sg->addr);
  62         dseg->len  = cpu_to_le32(sg->length);
  63 }
  64
  65 /*
  66  * mapped-value = 1 + real-value
  67  * The hns wr opcode real value is start from 0, In order to distinguish between
  68  * initialized and uninitialized map values, we plus 1 to the actual value when
  69  * defining the mapping, so that the validity can be identified by checking the
  70  * mapped value is greater than 0.
  71  */
  72 #define HR_OPC_MAP(ib_key, hr_key) \
  73                 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
  74
  75 static const u32 hns_roce_op_code[] = {
  76         HR_OPC_MAP(RDMA_WRITE,                  RDMA_WRITE),
  77         HR_OPC_MAP(RDMA_WRITE_WITH_IMM,         RDMA_WRITE_WITH_IMM),
  78         HR_OPC_MAP(SEND,                        SEND),
  79         HR_OPC_MAP(SEND_WITH_IMM,               SEND_WITH_IMM),
  80         HR_OPC_MAP(RDMA_READ,                   RDMA_READ),
  81         HR_OPC_MAP(ATOMIC_CMP_AND_SWP,          ATOM_CMP_AND_SWAP),
  82         HR_OPC_MAP(ATOMIC_FETCH_AND_ADD,        ATOM_FETCH_AND_ADD),
  83         HR_OPC_MAP(SEND_WITH_INV,               SEND_WITH_INV),
  84         HR_OPC_MAP(LOCAL_INV,                   LOCAL_INV),
  85         HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP,   ATOM_MSK_CMP_AND_SWAP),
  86         HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
  87         HR_OPC_MAP(REG_MR,                      FAST_REG_PMR),
  88 };
  89
  90 static u32 to_hr_opcode(u32 ib_opcode)
  91 {
  92         if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
  93                 return HNS_ROCE_V2_WQE_OP_MASK;
  94
  95         return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
  96                                              HNS_ROCE_V2_WQE_OP_MASK;
  97 }
  98
  99 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 100                          const struct ib_reg_wr *wr)
 101 {
 102         struct hns_roce_wqe_frmr_seg *fseg =
 103                 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
 104         struct hns_roce_mr *mr = to_hr_mr(wr->mr);
 105         u64 pbl_ba;
 106
 107         /* use ib_access_flags */
 108         hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND);
 109         hr_reg_write_bool(fseg, FRMR_ATOMIC,
 110                           wr->access & IB_ACCESS_REMOTE_ATOMIC);
 111         hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ);
 112         hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE);
 113         hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE);
 114
 115         /* Data structure reuse may lead to confusion */
 116         pbl_ba = mr->pbl_mtr.hem_cfg.root_ba;
 117         rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba));
 118         rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba));
 119
 120         rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
 121         rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
 122         rc_sq_wqe->rkey = cpu_to_le32(wr->key);
 123         rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
 124
 125         hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages);
 126         hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ,
 127                      to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
 128         hr_reg_clear(fseg, FRMR_BLK_MODE);
 129 }
 130
 131 static void set_atomic_seg(const struct ib_send_wr *wr,
 132                            struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 133                            unsigned int valid_num_sge)
 134 {
 135         struct hns_roce_v2_wqe_data_seg *dseg =
 136                 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
 137         struct hns_roce_wqe_atomic_seg *aseg =
 138                 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg);
 139
 140         set_data_seg_v2(dseg, wr->sg_list);
 141
 142         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
 143                 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
 144                 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
 145         } else {
 146                 aseg->fetchadd_swap_data =
 147                         cpu_to_le64(atomic_wr(wr)->compare_add);
 148                 aseg->cmp_data = 0;
 149         }
 150
 151         roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
 152                        V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
 153 }
 154
 155 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp,
 156                                  const struct ib_send_wr *wr,
 157                                  unsigned int *sge_idx, u32 msg_len)
 158 {
 159         struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev;
 160         unsigned int dseg_len = sizeof(struct hns_roce_v2_wqe_data_seg);
 161         unsigned int ext_sge_sz = qp->sq.max_gs * dseg_len;
 162         unsigned int left_len_in_pg;
 163         unsigned int idx = *sge_idx;
 164         unsigned int i = 0;
 165         unsigned int len;
 166         void *addr;
 167         void *dseg;
 168
 169         if (msg_len > ext_sge_sz) {
 170                 ibdev_err(ibdev,
 171                           "no enough extended sge space for inline data.\n");
 172                 return -EINVAL;
 173         }
 174
 175         dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
 176         left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg;
 177         len = wr->sg_list[0].length;
 178         addr = (void *)(unsigned long)(wr->sg_list[0].addr);
 179
 180         /* When copying data to extended sge space, the left length in page may
 181          * not long enough for current user's sge. So the data should be
 182          * splited into several parts, one in the first page, and the others in
 183          * the subsequent pages.
 184          */
 185         while (1) {
 186                 if (len <= left_len_in_pg) {
 187                         memcpy(dseg, addr, len);
 188
 189                         idx += len / dseg_len;
 190
 191                         i++;
 192                         if (i >= wr->num_sge)
 193                                 break;
 194
 195                         left_len_in_pg -= len;
 196                         len = wr->sg_list[i].length;
 197                         addr = (void *)(unsigned long)(wr->sg_list[i].addr);
 198                         dseg += len;
 199                 } else {
 200                         memcpy(dseg, addr, left_len_in_pg);
 201
 202                         len -= left_len_in_pg;
 203                         addr += left_len_in_pg;
 204                         idx += left_len_in_pg / dseg_len;
 205                         dseg = hns_roce_get_extend_sge(qp,
 206                                                 idx & (qp->sge.sge_cnt - 1));
 207                         left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT;
 208                 }
 209         }
 210
 211         *sge_idx = idx;
 212
 213         return 0;
 214 }
 215
 216 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge,
 217                            unsigned int *sge_ind, unsigned int cnt)
 218 {
 219         struct hns_roce_v2_wqe_data_seg *dseg;
 220         unsigned int idx = *sge_ind;
 221
 222         while (cnt > 0) {
 223                 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
 224                 if (likely(sge->length)) {
 225                         set_data_seg_v2(dseg, sge);
 226                         idx++;
 227                         cnt--;
 228                 }
 229                 sge++;
 230         }
 231
 232         *sge_ind = idx;
 233 }
 234
 235 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len)
 236 {
 237         struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
 238         int mtu = ib_mtu_enum_to_int(qp->path_mtu);
 239
 240         if (len > qp->max_inline_data || len > mtu) {
 241                 ibdev_err(&hr_dev->ib_dev,
 242                           "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n",
 243                           len, qp->max_inline_data, mtu);
 244                 return false;
 245         }
 246
 247         return true;
 248 }
 249
 250 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
 251                       struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 252                       unsigned int *sge_idx)
 253 {
 254         struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
 255         u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len);
 256         struct ib_device *ibdev = &hr_dev->ib_dev;
 257         unsigned int curr_idx = *sge_idx;
 258         void *dseg = rc_sq_wqe;
 259         unsigned int i;
 260         int ret;
 261
 262         if (unlikely(wr->opcode == IB_WR_RDMA_READ)) {
 263                 ibdev_err(ibdev, "invalid inline parameters!\n");
 264                 return -EINVAL;
 265         }
 266
 267         if (!check_inl_data_len(qp, msg_len))
 268                 return -EINVAL;
 269
 270         dseg += sizeof(struct hns_roce_v2_rc_send_wqe);
 271
 272         roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, 1);
 273
 274         if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) {
 275                 roce_set_bit(rc_sq_wqe->byte_20,
 276                              V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S, 0);
 277
 278                 for (i = 0; i < wr->num_sge; i++) {
 279                         memcpy(dseg, ((void *)wr->sg_list[i].addr),
 280                                wr->sg_list[i].length);
 281                         dseg += wr->sg_list[i].length;
 282                 }
 283         } else {
 284                 roce_set_bit(rc_sq_wqe->byte_20,
 285                              V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S, 1);
 286
 287                 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len);
 288                 if (ret)
 289                         return ret;
 290
 291                 roce_set_field(rc_sq_wqe->byte_16,
 292                                V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
 293                                V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S,
 294                                curr_idx - *sge_idx);
 295         }
 296
 297         *sge_idx = curr_idx;
 298
 299         return 0;
 300 }
 301
 302 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 303                              struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 304                              unsigned int *sge_ind,
 305                              unsigned int valid_num_sge)
 306 {
 307         struct hns_roce_v2_wqe_data_seg *dseg =
 308                 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
 309         struct hns_roce_qp *qp = to_hr_qp(ibqp);
 310         int j = 0;
 311         int i;
 312
 313         roce_set_field(rc_sq_wqe->byte_20,
 314                        V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
 315                        V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
 316                        (*sge_ind) & (qp->sge.sge_cnt - 1));
 317
 318         if (wr->send_flags & IB_SEND_INLINE)
 319                 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind);
 320
 321         if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) {
 322                 for (i = 0; i < wr->num_sge; i++) {
 323                         if (likely(wr->sg_list[i].length)) {
 324                                 set_data_seg_v2(dseg, wr->sg_list + i);
 325                                 dseg++;
 326                         }
 327                 }
 328         } else {
 329                 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) {
 330                         if (likely(wr->sg_list[i].length)) {
 331                                 set_data_seg_v2(dseg, wr->sg_list + i);
 332                                 dseg++;
 333                                 j++;
 334                         }
 335                 }
 336
 337                 set_extend_sge(qp, wr->sg_list + i, sge_ind,
 338                                valid_num_sge - HNS_ROCE_SGE_IN_WQE);
 339         }
 340
 341         roce_set_field(rc_sq_wqe->byte_16,
 342                        V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
 343                        V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
 344
 345         return 0;
 346 }
 347
 348 static int check_send_valid(struct hns_roce_dev *hr_dev,
 349                             struct hns_roce_qp *hr_qp)
 350 {
 351         struct ib_device *ibdev = &hr_dev->ib_dev;
 352         struct ib_qp *ibqp = &hr_qp->ibqp;
 353
 354         if (unlikely(ibqp->qp_type != IB_QPT_RC &&
 355                      ibqp->qp_type != IB_QPT_GSI &&
 356                      ibqp->qp_type != IB_QPT_UD)) {
 357                 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n",
 358                           ibqp->qp_type);
 359                 return -EOPNOTSUPP;
 360         } else if (unlikely(hr_qp->state == IB_QPS_RESET ||
 361                    hr_qp->state == IB_QPS_INIT ||
 362                    hr_qp->state == IB_QPS_RTR)) {
 363                 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n",
 364                           hr_qp->state);
 365                 return -EINVAL;
 366         } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) {
 367                 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n",
 368                           hr_dev->state);
 369                 return -EIO;
 370         }
 371
 372         return 0;
 373 }
 374
 375 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr,
 376                                     unsigned int *sge_len)
 377 {
 378         unsigned int valid_num = 0;
 379         unsigned int len = 0;
 380         int i;
 381
 382         for (i = 0; i < wr->num_sge; i++) {
 383                 if (likely(wr->sg_list[i].length)) {
 384                         len += wr->sg_list[i].length;
 385                         valid_num++;
 386                 }
 387         }
 388
 389         *sge_len = len;
 390         return valid_num;
 391 }
 392
 393 static __le32 get_immtdata(const struct ib_send_wr *wr)
 394 {
 395         switch (wr->opcode) {
 396         case IB_WR_SEND_WITH_IMM:
 397         case IB_WR_RDMA_WRITE_WITH_IMM:
 398                 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
 399         default:
 400                 return 0;
 401         }
 402 }
 403
 404 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
 405                          const struct ib_send_wr *wr)
 406 {
 407         u32 ib_op = wr->opcode;
 408
 409         if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM)
 410                 return -EINVAL;
 411
 412         ud_sq_wqe->immtdata = get_immtdata(wr);
 413
 414         roce_set_field(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
 415                        V2_UD_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op));
 416
 417         return 0;
 418 }
 419
 420 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
 421                       struct hns_roce_ah *ah)
 422 {
 423         struct ib_device *ib_dev = ah->ibah.device;
 424         struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 425
 426         roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
 427                        V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, ah->av.udp_sport);
 428
 429         roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
 430                        V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit);
 431         roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
 432                        V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass);
 433         roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
 434                        V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel);
 435
 436         if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL))
 437                 return -EINVAL;
 438
 439         roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M,
 440                        V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl);
 441
 442         ud_sq_wqe->sgid_index = ah->av.gid_index;
 443
 444         memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN);
 445         memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2);
 446
 447         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
 448                 return 0;
 449
 450         roce_set_bit(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S,
 451                      ah->av.vlan_en);
 452         roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_VLAN_M,
 453                        V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id);
 454
 455         return 0;
 456 }
 457
 458 static inline int set_ud_wqe(struct hns_roce_qp *qp,
 459                              const struct ib_send_wr *wr,
 460                              void *wqe, unsigned int *sge_idx,
 461                              unsigned int owner_bit)
 462 {
 463         struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
 464         struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
 465         unsigned int curr_idx = *sge_idx;
 466         unsigned int valid_num_sge;
 467         u32 msg_len = 0;
 468         int ret;
 469
 470         valid_num_sge = calc_wr_sge_num(wr, &msg_len);
 471
 472         ret = set_ud_opcode(ud_sq_wqe, wr);
 473         if (WARN_ON(ret))
 474                 return ret;
 475
 476         ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
 477
 478         roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S,
 479                      !!(wr->send_flags & IB_SEND_SIGNALED));
 480
 481         roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S,
 482                      !!(wr->send_flags & IB_SEND_SOLICITED));
 483
 484         roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M,
 485                        V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn);
 486
 487         roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
 488                        V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
 489
 490         roce_set_field(ud_sq_wqe->byte_20,
 491                        V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
 492                        V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
 493                        curr_idx & (qp->sge.sge_cnt - 1));
 494
 495         ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
 496                           qp->qkey : ud_wr(wr)->remote_qkey);
 497         roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M,
 498                        V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn);
 499
 500         ret = fill_ud_av(ud_sq_wqe, ah);
 501         if (ret)
 502                 return ret;
 503
 504         qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl;
 505
 506         set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge);
 507
 508         /*
 509          * The pipeline can sequentially post all valid WQEs into WQ buffer,
 510          * including new WQEs waiting for the doorbell to update the PI again.
 511          * Therefore, the owner bit of WQE MUST be updated after all fields
 512          * and extSGEs have been written into DDR instead of cache.
 513          */
 514         if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
 515                 dma_wmb();
 516
 517         *sge_idx = curr_idx;
 518         roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S,
 519                      owner_bit);
 520
 521         return 0;
 522 }
 523
 524 static int set_rc_opcode(struct hns_roce_dev *hr_dev,
 525                          struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
 526                          const struct ib_send_wr *wr)
 527 {
 528         u32 ib_op = wr->opcode;
 529         int ret = 0;
 530
 531         rc_sq_wqe->immtdata = get_immtdata(wr);
 532
 533         switch (ib_op) {
 534         case IB_WR_RDMA_READ:
 535         case IB_WR_RDMA_WRITE:
 536         case IB_WR_RDMA_WRITE_WITH_IMM:
 537                 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
 538                 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
 539                 break;
 540         case IB_WR_SEND:
 541         case IB_WR_SEND_WITH_IMM:
 542                 break;
 543         case IB_WR_ATOMIC_CMP_AND_SWP:
 544         case IB_WR_ATOMIC_FETCH_AND_ADD:
 545                 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
 546                 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
 547                 break;
 548         case IB_WR_REG_MR:
 549                 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
 550                         set_frmr_seg(rc_sq_wqe, reg_wr(wr));
 551                 else
 552                         ret = -EOPNOTSUPP;
 553                 break;
 554         case IB_WR_LOCAL_INV:
 555                 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1);
 556                 fallthrough;
 557         case IB_WR_SEND_WITH_INV:
 558                 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
 559                 break;
 560         default:
 561                 ret = -EINVAL;
 562         }
 563
 564         if (unlikely(ret))
 565                 return ret;
 566
 567         roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
 568                        V2_RC_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op));
 569
 570         return ret;
 571 }
 572 static inline int set_rc_wqe(struct hns_roce_qp *qp,
 573                              const struct ib_send_wr *wr,
 574                              void *wqe, unsigned int *sge_idx,
 575                              unsigned int owner_bit)
 576 {
 577         struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
 578         struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
 579         unsigned int curr_idx = *sge_idx;
 580         unsigned int valid_num_sge;
 581         u32 msg_len = 0;
 582         int ret;
 583
 584         valid_num_sge = calc_wr_sge_num(wr, &msg_len);
 585
 586         rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
 587
 588         ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr);
 589         if (WARN_ON(ret))
 590                 return ret;
 591
 592         roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S,
 593                      (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
 594
 595         roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S,
 596                      (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
 597
 598         roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S,
 599                      (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
 600
 601         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
 602             wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
 603                 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge);
 604         else if (wr->opcode != IB_WR_REG_MR)
 605                 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
 606                                         &curr_idx, valid_num_sge);
 607
 608         /*
 609          * The pipeline can sequentially post all valid WQEs into WQ buffer,
 610          * including new WQEs waiting for the doorbell to update the PI again.
 611          * Therefore, the owner bit of WQE MUST be updated after all fields
 612          * and extSGEs have been written into DDR instead of cache.
 613          */
 614         if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
 615                 dma_wmb();
 616
 617         *sge_idx = curr_idx;
 618         roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S,
 619                      owner_bit);
 620
 621         return ret;
 622 }
 623
 624 static inline void update_sq_db(struct hns_roce_dev *hr_dev,
 625                                 struct hns_roce_qp *qp)
 626 {
 627         /*
 628          * Hip08 hardware cannot flush the WQEs in SQ if the QP state
 629          * gets into errored mode. Hence, as a workaround to this
 630          * hardware limitation, driver needs to assist in flushing. But
 631          * the flushing operation uses mailbox to convey the QP state to
 632          * the hardware and which can sleep due to the mutex protection
 633          * around the mailbox calls. Hence, use the deferred flush for
 634          * now.
 635          */
 636         if (unlikely(qp->state == IB_QPS_ERR)) {
 637                 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
 638                         init_flush_work(hr_dev, qp);
 639         } else {
 640                 struct hns_roce_v2_db sq_db = {};
 641
 642                 hr_reg_write(&sq_db, DB_TAG, qp->doorbell_qpn);
 643                 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB);
 644                 hr_reg_write(&sq_db, DB_PI, qp->sq.head);
 645                 hr_reg_write(&sq_db, DB_SL, qp->sl);
 646
 647                 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg);
 648         }
 649 }
 650
 651 static inline void update_rq_db(struct hns_roce_dev *hr_dev,
 652                                 struct hns_roce_qp *qp)
 653 {
 654         /*
 655          * Hip08 hardware cannot flush the WQEs in RQ if the QP state
 656          * gets into errored mode. Hence, as a workaround to this
 657          * hardware limitation, driver needs to assist in flushing. But
 658          * the flushing operation uses mailbox to convey the QP state to
 659          * the hardware and which can sleep due to the mutex protection
 660          * around the mailbox calls. Hence, use the deferred flush for
 661          * now.
 662          */
 663         if (unlikely(qp->state == IB_QPS_ERR)) {
 664                 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
 665                         init_flush_work(hr_dev, qp);
 666         } else {
 667                 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) {
 668                         *qp->rdb.db_record =
 669                                         qp->rq.head & V2_DB_PRODUCER_IDX_M;
 670                 } else {
 671                         struct hns_roce_v2_db rq_db = {};
 672
 673                         hr_reg_write(&rq_db, DB_TAG, qp->qpn);
 674                         hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB);
 675                         hr_reg_write(&rq_db, DB_PI, qp->rq.head);
 676
 677                         hns_roce_write64(hr_dev, (__le32 *)&rq_db,
 678                                          qp->rq.db_reg);
 679                 }
 680         }
 681 }
 682
 683 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val,
 684                               u64 __iomem *dest)
 685 {
 686 #define HNS_ROCE_WRITE_TIMES 8
 687         struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
 688         struct hnae3_handle *handle = priv->handle;
 689         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
 690         int i;
 691
 692         if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
 693                 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++)
 694                         writeq_relaxed(*(val + i), dest + i);
 695 }
 696
 697 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
 698                        void *wqe)
 699 {
 700         struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
 701
 702         /* All kinds of DirectWQE have the same header field layout */
 703         roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FLAG_S, 1);
 704         roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M,
 705                        V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S, qp->sl);
 706         roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M,
 707                        V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S, qp->sl >> 2);
 708         roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M,
 709                        V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S, qp->sq.head);
 710
 711         hns_roce_write512(hr_dev, wqe, qp->sq.db_reg);
 712 }
 713
 714 static int hns_roce_v2_post_send(struct ib_qp *ibqp,
 715                                  const struct ib_send_wr *wr,
 716                                  const struct ib_send_wr **bad_wr)
 717 {
 718         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 719         struct ib_device *ibdev = &hr_dev->ib_dev;
 720         struct hns_roce_qp *qp = to_hr_qp(ibqp);
 721         unsigned long flags = 0;
 722         unsigned int owner_bit;
 723         unsigned int sge_idx;
 724         unsigned int wqe_idx;
 725         void *wqe = NULL;
 726         u32 nreq;
 727         int ret;
 728
 729         spin_lock_irqsave(&qp->sq.lock, flags);
 730
 731         ret = check_send_valid(hr_dev, qp);
 732         if (unlikely(ret)) {
 733                 *bad_wr = wr;
 734                 nreq = 0;
 735                 goto out;
 736         }
 737
 738         sge_idx = qp->next_sge;
 739
 740         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 741                 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
 742                         ret = -ENOMEM;
 743                         *bad_wr = wr;
 744                         goto out;
 745                 }
 746
 747                 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
 748
 749                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
 750                         ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n",
 751                                   wr->num_sge, qp->sq.max_gs);
 752                         ret = -EINVAL;
 753                         *bad_wr = wr;
 754                         goto out;
 755                 }
 756
 757                 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
 758                 qp->sq.wrid[wqe_idx] = wr->wr_id;
 759                 owner_bit =
 760                        ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
 761
 762                 /* Corresponding to the QP type, wqe process separately */
 763                 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
 764                         ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
 765                 else if (ibqp->qp_type == IB_QPT_RC)
 766                         ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
 767
 768                 if (unlikely(ret)) {
 769                         *bad_wr = wr;
 770                         goto out;
 771                 }
 772         }
 773
 774 out:
 775         if (likely(nreq)) {
 776                 qp->sq.head += nreq;
 777                 qp->next_sge = sge_idx;
 778
 779                 if (nreq == 1 && (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE))
 780                         write_dwqe(hr_dev, qp, wqe);
 781                 else
 782                         update_sq_db(hr_dev, qp);
 783         }
 784
 785         spin_unlock_irqrestore(&qp->sq.lock, flags);
 786
 787         return ret;
 788 }
 789
 790 static int check_recv_valid(struct hns_roce_dev *hr_dev,
 791                             struct hns_roce_qp *hr_qp)
 792 {
 793         struct ib_device *ibdev = &hr_dev->ib_dev;
 794         struct ib_qp *ibqp = &hr_qp->ibqp;
 795
 796         if (unlikely(ibqp->qp_type != IB_QPT_RC &&
 797                      ibqp->qp_type != IB_QPT_GSI &&
 798                      ibqp->qp_type != IB_QPT_UD)) {
 799                 ibdev_err(ibdev, "unsupported qp type, qp_type = %d.\n",
 800                           ibqp->qp_type);
 801                 return -EOPNOTSUPP;
 802         }
 803
 804         if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
 805                 return -EIO;
 806
 807         if (hr_qp->state == IB_QPS_RESET)
 808                 return -EINVAL;
 809
 810         return 0;
 811 }
 812
 813 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe,
 814                                  u32 max_sge, bool rsv)
 815 {
 816         struct hns_roce_v2_wqe_data_seg *dseg = wqe;
 817         u32 i, cnt;
 818
 819         for (i = 0, cnt = 0; i < wr->num_sge; i++) {
 820                 /* Skip zero-length sge */
 821                 if (!wr->sg_list[i].length)
 822                         continue;
 823                 set_data_seg_v2(dseg + cnt, wr->sg_list + i);
 824                 cnt++;
 825         }
 826
 827         /* Fill a reserved sge to make hw stop reading remaining segments */
 828         if (rsv) {
 829                 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
 830                 dseg[cnt].addr = 0;
 831                 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);
 832         } else {
 833                 /* Clear remaining segments to make ROCEE ignore sges */
 834                 if (cnt < max_sge)
 835                         memset(dseg + cnt, 0,
 836                                (max_sge - cnt) * HNS_ROCE_SGE_SIZE);
 837         }
 838 }
 839
 840 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr,
 841                         u32 wqe_idx, u32 max_sge)
 842 {
 843         struct hns_roce_rinl_sge *sge_list;
 844         void *wqe = NULL;
 845         u32 i;
 846
 847         wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
 848         fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge);
 849
 850         /* rq support inline data */
 851         if (hr_qp->rq_inl_buf.wqe_cnt) {
 852                 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list;
 853                 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = (u32)wr->num_sge;
 854                 for (i = 0; i < wr->num_sge; i++) {
 855                         sge_list[i].addr = (void *)(u64)wr->sg_list[i].addr;
 856                         sge_list[i].len = wr->sg_list[i].length;
 857                 }
 858         }
 859 }
 860
 861 static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
 862                                  const struct ib_recv_wr *wr,
 863                                  const struct ib_recv_wr **bad_wr)
 864 {
 865         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 866         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
 867         struct ib_device *ibdev = &hr_dev->ib_dev;
 868         u32 wqe_idx, nreq, max_sge;
 869         unsigned long flags;
 870         int ret;
 871
 872         spin_lock_irqsave(&hr_qp->rq.lock, flags);
 873
 874         ret = check_recv_valid(hr_dev, hr_qp);
 875         if (unlikely(ret)) {
 876                 *bad_wr = wr;
 877                 nreq = 0;
 878                 goto out;
 879         }
 880
 881         max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
 882         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 883                 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq,
 884                                                   hr_qp->ibqp.recv_cq))) {
 885                         ret = -ENOMEM;
 886                         *bad_wr = wr;
 887                         goto out;
 888                 }
 889
 890                 if (unlikely(wr->num_sge > max_sge)) {
 891                         ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n",
 892                                   wr->num_sge, max_sge);
 893                         ret = -EINVAL;
 894                         *bad_wr = wr;
 895                         goto out;
 896                 }
 897
 898                 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
 899                 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge);
 900                 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
 901         }
 902
 903 out:
 904         if (likely(nreq)) {
 905                 hr_qp->rq.head += nreq;
 906
 907                 update_rq_db(hr_dev, hr_qp);
 908         }
 909         spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
 910
 911         return ret;
 912 }
 913
 914 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n)
 915 {
 916         return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
 917 }
 918
 919 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n)
 920 {
 921         return hns_roce_buf_offset(idx_que->mtr.kmem,
 922                                    n << idx_que->entry_shift);
 923 }
 924
 925 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index)
 926 {
 927         /* always called with interrupts disabled. */
 928         spin_lock(&srq->lock);
 929
 930         bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
 931         srq->idx_que.tail++;
 932
 933         spin_unlock(&srq->lock);
 934 }
 935
 936 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq)
 937 {
 938         struct hns_roce_idx_que *idx_que = &srq->idx_que;
 939
 940         return idx_que->head - idx_que->tail >= srq->wqe_cnt;
 941 }
 942
 943 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge,
 944                                 const struct ib_recv_wr *wr)
 945 {
 946         struct ib_device *ib_dev = srq->ibsrq.device;
 947
 948         if (unlikely(wr->num_sge > max_sge)) {
 949                 ibdev_err(ib_dev,
 950                           "failed to check sge, wr->num_sge = %d, max_sge = %u.\n",
 951                           wr->num_sge, max_sge);
 952                 return -EINVAL;
 953         }
 954
 955         if (unlikely(hns_roce_srqwq_overflow(srq))) {
 956                 ibdev_err(ib_dev,
 957                           "failed to check srqwq status, srqwq is full.\n");
 958                 return -ENOMEM;
 959         }
 960
 961         return 0;
 962 }
 963
 964 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx)
 965 {
 966         struct hns_roce_idx_que *idx_que = &srq->idx_que;
 967         u32 pos;
 968
 969         pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt);
 970         if (unlikely(pos == srq->wqe_cnt))
 971                 return -ENOSPC;
 972
 973         bitmap_set(idx_que->bitmap, pos, 1);
 974         *wqe_idx = pos;
 975         return 0;
 976 }
 977
 978 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx)
 979 {
 980         struct hns_roce_idx_que *idx_que = &srq->idx_que;
 981         unsigned int head;
 982         __le32 *buf;
 983
 984         head = idx_que->head & (srq->wqe_cnt - 1);
 985
 986         buf = get_idx_buf(idx_que, head);
 987         *buf = cpu_to_le32(wqe_idx);
 988
 989         idx_que->head++;
 990 }
 991
 992 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq)
 993 {
 994         hr_reg_write(db, DB_TAG, srq->srqn);
 995         hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB);
 996         hr_reg_write(db, DB_PI, srq->idx_que.head);
 997 }
 998
 999 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
1000                                      const struct ib_recv_wr *wr,
1001                                      const struct ib_recv_wr **bad_wr)
1002 {
1003         struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
1004         struct hns_roce_srq *srq = to_hr_srq(ibsrq);
1005         struct hns_roce_v2_db srq_db;
1006         unsigned long flags;
1007         int ret = 0;
1008         u32 max_sge;
1009         u32 wqe_idx;
1010         void *wqe;
1011         u32 nreq;
1012
1013         spin_lock_irqsave(&srq->lock, flags);
1014
1015         max_sge = srq->max_gs - srq->rsv_sge;
1016         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1017                 ret = check_post_srq_valid(srq, max_sge, wr);
1018                 if (ret) {
1019                         *bad_wr = wr;
1020                         break;
1021                 }
1022
1023                 ret = get_srq_wqe_idx(srq, &wqe_idx);
1024                 if (unlikely(ret)) {
1025                         *bad_wr = wr;
1026                         break;
1027                 }
1028
1029                 wqe = get_srq_wqe_buf(srq, wqe_idx);
1030                 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge);
1031                 fill_wqe_idx(srq, wqe_idx);
1032                 srq->wrid[wqe_idx] = wr->wr_id;
1033         }
1034
1035         if (likely(nreq)) {
1036                 update_srq_db(&srq_db, srq);
1037
1038                 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg);
1039         }
1040
1041         spin_unlock_irqrestore(&srq->lock, flags);
1042
1043         return ret;
1044 }
1045
1046 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
1047                                       unsigned long instance_stage,
1048                                       unsigned long reset_stage)
1049 {
1050         /* When hardware reset has been completed once or more, we should stop
1051          * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
1052          * function, we should exit with error. If now at HNAE3_INIT_CLIENT
1053          * stage of soft reset process, we should exit with error, and then
1054          * HNAE3_INIT_CLIENT related process can rollback the operation like
1055          * notifing hardware to free resources, HNAE3_INIT_CLIENT related
1056          * process will exit with error to notify NIC driver to reschedule soft
1057          * reset process once again.
1058          */
1059         hr_dev->is_reset = true;
1060         hr_dev->dis_db = true;
1061
1062         if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
1063             instance_stage == HNS_ROCE_STATE_INIT)
1064                 return CMD_RST_PRC_EBUSY;
1065
1066         return CMD_RST_PRC_SUCCESS;
1067 }
1068
1069 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
1070                                         unsigned long instance_stage,
1071                                         unsigned long reset_stage)
1072 {
1073         struct hns_roce_v2_priv *priv = hr_dev->priv;
1074         struct hnae3_handle *handle = priv->handle;
1075         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1076
1077         /* When hardware reset is detected, we should stop sending mailbox&cmq&
1078          * doorbell to hardware. If now in .init_instance() function, we should
1079          * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
1080          * process, we should exit with error, and then HNAE3_INIT_CLIENT
1081          * related process can rollback the operation like notifing hardware to
1082          * free resources, HNAE3_INIT_CLIENT related process will exit with
1083          * error to notify NIC driver to reschedule soft reset process once
1084          * again.
1085          */
1086         hr_dev->dis_db = true;
1087         if (!ops->get_hw_reset_stat(handle))
1088                 hr_dev->is_reset = true;
1089
1090         if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
1091             instance_stage == HNS_ROCE_STATE_INIT)
1092                 return CMD_RST_PRC_EBUSY;
1093
1094         return CMD_RST_PRC_SUCCESS;
1095 }
1096
1097 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
1098 {
1099         struct hns_roce_v2_priv *priv = hr_dev->priv;
1100         struct hnae3_handle *handle = priv->handle;
1101         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1102
1103         /* When software reset is detected at .init_instance() function, we
1104          * should stop sending mailbox&cmq&doorbell to hardware, and exit
1105          * with error.
1106          */
1107         hr_dev->dis_db = true;
1108         if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
1109                 hr_dev->is_reset = true;
1110
1111         return CMD_RST_PRC_EBUSY;
1112 }
1113
1114 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev,
1115                                     struct hnae3_handle *handle)
1116 {
1117         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1118         unsigned long instance_stage; /* the current instance stage */
1119         unsigned long reset_stage; /* the current reset stage */
1120         unsigned long reset_cnt;
1121         bool sw_resetting;
1122         bool hw_resetting;
1123
1124         /* Get information about reset from NIC driver or RoCE driver itself,
1125          * the meaning of the following variables from NIC driver are described
1126          * as below:
1127          * reset_cnt -- The count value of completed hardware reset.
1128          * hw_resetting -- Whether hardware device is resetting now.
1129          * sw_resetting -- Whether NIC's software reset process is running now.
1130          */
1131         instance_stage = handle->rinfo.instance_state;
1132         reset_stage = handle->rinfo.reset_state;
1133         reset_cnt = ops->ae_dev_reset_cnt(handle);
1134         if (reset_cnt != hr_dev->reset_cnt)
1135                 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
1136                                                   reset_stage);
1137
1138         hw_resetting = ops->get_cmdq_stat(handle);
1139         if (hw_resetting)
1140                 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
1141                                                     reset_stage);
1142
1143         sw_resetting = ops->ae_dev_resetting(handle);
1144         if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
1145                 return hns_roce_v2_cmd_sw_resetting(hr_dev);
1146
1147         return CMD_RST_PRC_OTHERS;
1148 }
1149
1150 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev)
1151 {
1152         struct hns_roce_v2_priv *priv = hr_dev->priv;
1153         struct hnae3_handle *handle = priv->handle;
1154         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1155
1156         if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle))
1157                 return true;
1158
1159         if (ops->get_hw_reset_stat(handle))
1160                 return true;
1161
1162         if (ops->ae_dev_resetting(handle))
1163                 return true;
1164
1165         return false;
1166 }
1167
1168 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy)
1169 {
1170         struct hns_roce_v2_priv *priv = hr_dev->priv;
1171         u32 status;
1172
1173         if (hr_dev->is_reset)
1174                 status = CMD_RST_PRC_SUCCESS;
1175         else
1176                 status = check_aedev_reset_status(hr_dev, priv->handle);
1177
1178         *busy = (status == CMD_RST_PRC_EBUSY);
1179
1180         return status == CMD_RST_PRC_OTHERS;
1181 }
1182
1183 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
1184                                    struct hns_roce_v2_cmq_ring *ring)
1185 {
1186         int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
1187
1188         ring->desc = kzalloc(size, GFP_KERNEL);
1189         if (!ring->desc)
1190                 return -ENOMEM;
1191
1192         ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
1193                                              DMA_BIDIRECTIONAL);
1194         if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
1195                 ring->desc_dma_addr = 0;
1196                 kfree(ring->desc);
1197                 ring->desc = NULL;
1198
1199                 return -ENOMEM;
1200         }
1201
1202         return 0;
1203 }
1204
1205 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
1206                                    struct hns_roce_v2_cmq_ring *ring)
1207 {
1208         dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
1209                          ring->desc_num * sizeof(struct hns_roce_cmq_desc),
1210                          DMA_BIDIRECTIONAL);
1211
1212         ring->desc_dma_addr = 0;
1213         kfree(ring->desc);
1214 }
1215
1216 static int init_csq(struct hns_roce_dev *hr_dev,
1217                     struct hns_roce_v2_cmq_ring *csq)
1218 {
1219         dma_addr_t dma;
1220         int ret;
1221
1222         csq->desc_num = CMD_CSQ_DESC_NUM;
1223         spin_lock_init(&csq->lock);
1224         csq->flag = TYPE_CSQ;
1225         csq->head = 0;
1226
1227         ret = hns_roce_alloc_cmq_desc(hr_dev, csq);
1228         if (ret)
1229                 return ret;
1230
1231         dma = csq->desc_dma_addr;
1232         roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma));
1233         roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma));
1234         roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
1235                    (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1236
1237         /* Make sure to write CI first and then PI */
1238         roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
1239         roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
1240
1241         return 0;
1242 }
1243
1244 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
1245 {
1246         struct hns_roce_v2_priv *priv = hr_dev->priv;
1247         int ret;
1248
1249         priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1250
1251         ret = init_csq(hr_dev, &priv->cmq.csq);
1252         if (ret)
1253                 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret);
1254
1255         return ret;
1256 }
1257
1258 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
1259 {
1260         struct hns_roce_v2_priv *priv = hr_dev->priv;
1261
1262         hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1263 }
1264
1265 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
1266                                           enum hns_roce_opcode_type opcode,
1267                                           bool is_read)
1268 {
1269         memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
1270         desc->opcode = cpu_to_le16(opcode);
1271         desc->flag =
1272                 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
1273         if (is_read)
1274                 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
1275         else
1276                 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1277 }
1278
1279 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
1280 {
1281         u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1282         struct hns_roce_v2_priv *priv = hr_dev->priv;
1283
1284         return tail == priv->cmq.csq.head;
1285 }
1286
1287 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1288                                struct hns_roce_cmq_desc *desc, int num)
1289 {
1290         struct hns_roce_v2_priv *priv = hr_dev->priv;
1291         struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1292         u32 timeout = 0;
1293         u16 desc_ret;
1294         u32 tail;
1295         int ret;
1296         int i;
1297
1298         spin_lock_bh(&csq->lock);
1299
1300         tail = csq->head;
1301
1302         for (i = 0; i < num; i++) {
1303                 csq->desc[csq->head++] = desc[i];
1304                 if (csq->head == csq->desc_num)
1305                         csq->head = 0;
1306         }
1307
1308         /* Write to hardware */
1309         roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head);
1310
1311         /* If the command is sync, wait for the firmware to write back,
1312          * if multi descriptors to be sent, use the first one to check
1313          */
1314         if (le16_to_cpu(desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
1315                 do {
1316                         if (hns_roce_cmq_csq_done(hr_dev))
1317                                 break;
1318                         udelay(1);
1319                 } while (++timeout < priv->cmq.tx_timeout);
1320         }
1321
1322         if (hns_roce_cmq_csq_done(hr_dev)) {
1323                 for (ret = 0, i = 0; i < num; i++) {
1324                         /* check the result of hardware write back */
1325                         desc[i] = csq->desc[tail++];
1326                         if (tail == csq->desc_num)
1327                                 tail = 0;
1328
1329                         desc_ret = le16_to_cpu(desc[i].retval);
1330                         if (likely(desc_ret == CMD_EXEC_SUCCESS))
1331                                 continue;
1332
1333                         dev_err_ratelimited(hr_dev->dev,
1334                                             "Cmdq IO error, opcode = %x, return = %x\n",
1335                                             desc->opcode, desc_ret);
1336                         ret = -EIO;
1337                 }
1338         } else {
1339                 /* FW/HW reset or incorrect number of desc */
1340                 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1341                 dev_warn(hr_dev->dev, "CMDQ move tail from %d to %d\n",
1342                          csq->head, tail);
1343                 csq->head = tail;
1344
1345                 ret = -EAGAIN;
1346         }
1347
1348         spin_unlock_bh(&csq->lock);
1349
1350         return ret;
1351 }
1352
1353 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1354                              struct hns_roce_cmq_desc *desc, int num)
1355 {
1356         bool busy;
1357         int ret;
1358
1359         if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1360                 return busy ? -EBUSY : 0;
1361
1362         ret = __hns_roce_cmq_send(hr_dev, desc, num);
1363         if (ret) {
1364                 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1365                         return busy ? -EBUSY : 0;
1366         }
1367
1368         return ret;
1369 }
1370
1371 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,
1372                                dma_addr_t base_addr, u16 op)
1373 {
1374         struct hns_roce_cmd_mailbox *mbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1375         int ret;
1376
1377         if (IS_ERR(mbox))
1378                 return PTR_ERR(mbox);
1379
1380         ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, obj, 0, op,
1381                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
1382         hns_roce_free_cmd_mailbox(hr_dev, mbox);
1383         return ret;
1384 }
1385
1386 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
1387 {
1388         struct hns_roce_query_version *resp;
1389         struct hns_roce_cmq_desc desc;
1390         int ret;
1391
1392         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1393         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1394         if (ret)
1395                 return ret;
1396
1397         resp = (struct hns_roce_query_version *)desc.data;
1398         hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
1399         hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1400
1401         return 0;
1402 }
1403
1404 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev,
1405                                         struct hnae3_handle *handle)
1406 {
1407         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1408         unsigned long end;
1409
1410         hr_dev->dis_db = true;
1411
1412         dev_warn(hr_dev->dev,
1413                  "Func clear is pending, device in resetting state.\n");
1414         end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1415         while (end) {
1416                 if (!ops->get_hw_reset_stat(handle)) {
1417                         hr_dev->is_reset = true;
1418                         dev_info(hr_dev->dev,
1419                                  "Func clear success after reset.\n");
1420                         return;
1421                 }
1422                 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1423                 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1424         }
1425
1426         dev_warn(hr_dev->dev, "Func clear failed.\n");
1427 }
1428
1429 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev,
1430                                         struct hnae3_handle *handle)
1431 {
1432         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1433         unsigned long end;
1434
1435         hr_dev->dis_db = true;
1436
1437         dev_warn(hr_dev->dev,
1438                  "Func clear is pending, device in resetting state.\n");
1439         end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1440         while (end) {
1441                 if (ops->ae_dev_reset_cnt(handle) !=
1442                     hr_dev->reset_cnt) {
1443                         hr_dev->is_reset = true;
1444                         dev_info(hr_dev->dev,
1445                                  "Func clear success after sw reset\n");
1446                         return;
1447                 }
1448                 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1449                 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1450         }
1451
1452         dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n");
1453 }
1454
1455 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval,
1456                                        int flag)
1457 {
1458         struct hns_roce_v2_priv *priv = hr_dev->priv;
1459         struct hnae3_handle *handle = priv->handle;
1460         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1461
1462         if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) {
1463                 hr_dev->dis_db = true;
1464                 hr_dev->is_reset = true;
1465                 dev_info(hr_dev->dev, "Func clear success after reset.\n");
1466                 return;
1467         }
1468
1469         if (ops->get_hw_reset_stat(handle)) {
1470                 func_clr_hw_resetting_state(hr_dev, handle);
1471                 return;
1472         }
1473
1474         if (ops->ae_dev_resetting(handle) &&
1475             handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) {
1476                 func_clr_sw_resetting_state(hr_dev, handle);
1477                 return;
1478         }
1479
1480         if (retval && !flag)
1481                 dev_warn(hr_dev->dev,
1482                          "Func clear read failed, ret = %d.\n", retval);
1483
1484         dev_warn(hr_dev->dev, "Func clear failed.\n");
1485 }
1486
1487 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id)
1488 {
1489         bool fclr_write_fail_flag = false;
1490         struct hns_roce_func_clear *resp;
1491         struct hns_roce_cmq_desc desc;
1492         unsigned long end;
1493         int ret = 0;
1494
1495         if (check_device_is_in_reset(hr_dev))
1496                 goto out;
1497
1498         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1499         resp = (struct hns_roce_func_clear *)desc.data;
1500         resp->rst_funcid_en = cpu_to_le32(vf_id);
1501
1502         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1503         if (ret) {
1504                 fclr_write_fail_flag = true;
1505                 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n",
1506                          ret);
1507                 goto out;
1508         }
1509
1510         msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1511         end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1512         while (end) {
1513                 if (check_device_is_in_reset(hr_dev))
1514                         goto out;
1515                 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1516                 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1517
1518                 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1519                                               true);
1520
1521                 resp->rst_funcid_en = cpu_to_le32(vf_id);
1522                 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1523                 if (ret)
1524                         continue;
1525
1526                 if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) {
1527                         if (vf_id == 0)
1528                                 hr_dev->is_reset = true;
1529                         return;
1530                 }
1531         }
1532
1533 out:
1534         hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag);
1535 }
1536
1537 static void hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id)
1538 {
1539         enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1540         struct hns_roce_cmq_desc desc[2];
1541         struct hns_roce_cmq_req *req_a;
1542
1543         req_a = (struct hns_roce_cmq_req *)desc[0].data;
1544         hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1545         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1546         hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1547         hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id);
1548         hns_roce_cmq_send(hr_dev, desc, 2);
1549 }
1550
1551 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1552 {
1553         int i;
1554
1555         for (i = hr_dev->func_num - 1; i >= 0; i--) {
1556                 __hns_roce_function_clear(hr_dev, i);
1557                 if (i != 0)
1558                         hns_roce_free_vf_resource(hr_dev, i);
1559         }
1560 }
1561
1562 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev)
1563 {
1564         struct hns_roce_cmq_desc desc;
1565         int ret;
1566
1567         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO,
1568                                       false);
1569         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1570         if (ret)
1571                 ibdev_err(&hr_dev->ib_dev,
1572                           "failed to clear extended doorbell info, ret = %d.\n",
1573                           ret);
1574
1575         return ret;
1576 }
1577
1578 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1579 {
1580         struct hns_roce_query_fw_info *resp;
1581         struct hns_roce_cmq_desc desc;
1582         int ret;
1583
1584         hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1585         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1586         if (ret)
1587                 return ret;
1588
1589         resp = (struct hns_roce_query_fw_info *)desc.data;
1590         hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
1591
1592         return 0;
1593 }
1594
1595 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev)
1596 {
1597         struct hns_roce_cmq_desc desc;
1598         int ret;
1599
1600         if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09) {
1601                 hr_dev->func_num = 1;
1602                 return 0;
1603         }
1604
1605         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO,
1606                                       true);
1607         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1608         if (ret) {
1609                 hr_dev->func_num = 1;
1610                 return ret;
1611         }
1612
1613         hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num);
1614         hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id);
1615
1616         return 0;
1617 }
1618
1619 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1620 {
1621         struct hns_roce_cmq_desc desc;
1622         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1623
1624         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1625                                       false);
1626
1627         hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, 0x3e8);
1628         hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT);
1629
1630         return hns_roce_cmq_send(hr_dev, &desc, 1);
1631 }
1632
1633 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1634 {
1635         struct hns_roce_cmq_desc desc[2];
1636         struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1637         struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1638         struct hns_roce_caps *caps = &hr_dev->caps;
1639         enum hns_roce_opcode_type opcode;
1640         u32 func_num;
1641         int ret;
1642
1643         if (is_vf) {
1644                 opcode = HNS_ROCE_OPC_QUERY_VF_RES;
1645                 func_num = 1;
1646         } else {
1647                 opcode = HNS_ROCE_OPC_QUERY_PF_RES;
1648                 func_num = hr_dev->func_num;
1649         }
1650
1651         hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true);
1652         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1653         hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true);
1654
1655         ret = hns_roce_cmq_send(hr_dev, desc, 2);
1656         if (ret)
1657                 return ret;
1658
1659         caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num;
1660         caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num;
1661         caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num;
1662         caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num;
1663         caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num;
1664         caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num;
1665         caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num;
1666         caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num;
1667
1668         if (is_vf) {
1669                 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num;
1670                 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) /
1671                                                func_num;
1672         } else {
1673                 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num;
1674                 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) /
1675                                                func_num;
1676         }
1677
1678         return 0;
1679 }
1680
1681 static int load_ext_cfg_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1682 {
1683         struct hns_roce_cmq_desc desc;
1684         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1685         struct hns_roce_caps *caps = &hr_dev->caps;
1686         u32 func_num, qp_num;
1687         int ret;
1688
1689         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, true);
1690         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1691         if (ret)
1692                 return ret;
1693
1694         func_num = is_vf ? 1 : max_t(u32, 1, hr_dev->func_num);
1695         qp_num = hr_reg_read(req, EXT_CFG_QP_PI_NUM) / func_num;
1696         caps->num_pi_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM);
1697
1698         qp_num = hr_reg_read(req, EXT_CFG_QP_NUM) / func_num;
1699         caps->num_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM);
1700
1701         return 0;
1702 }
1703
1704 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev)
1705 {
1706         struct hns_roce_cmq_desc desc;
1707         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1708         struct hns_roce_caps *caps = &hr_dev->caps;
1709         int ret;
1710
1711         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1712                                       true);
1713
1714         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1715         if (ret)
1716                 return ret;
1717
1718         caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM);
1719         caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM);
1720
1721         return 0;
1722 }
1723
1724 static int query_func_resource_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1725 {
1726         struct device *dev = hr_dev->dev;
1727         int ret;
1728
1729         ret = load_func_res_caps(hr_dev, is_vf);
1730         if (ret) {
1731                 dev_err(dev, "failed to load res caps, ret = %d (%s).\n", ret,
1732                         is_vf ? "vf" : "pf");
1733                 return ret;
1734         }
1735
1736         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1737                 ret = load_ext_cfg_caps(hr_dev, is_vf);
1738                 if (ret)
1739                         dev_err(dev, "failed to load ext cfg, ret = %d (%s).\n",
1740                                 ret, is_vf ? "vf" : "pf");
1741         }
1742
1743         return ret;
1744 }
1745
1746 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1747 {
1748         struct device *dev = hr_dev->dev;
1749         int ret;
1750
1751         ret = query_func_resource_caps(hr_dev, false);
1752         if (ret)
1753                 return ret;
1754
1755         ret = load_pf_timer_res_caps(hr_dev);
1756         if (ret)
1757                 dev_err(dev, "failed to load pf timer resource, ret = %d.\n",
1758                         ret);
1759
1760         return ret;
1761 }
1762
1763 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev)
1764 {
1765         return query_func_resource_caps(hr_dev, true);
1766 }
1767
1768 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev,
1769                                           u32 vf_id)
1770 {
1771         struct hns_roce_vf_switch *swt;
1772         struct hns_roce_cmq_desc desc;
1773         int ret;
1774
1775         swt = (struct hns_roce_vf_switch *)desc.data;
1776         hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
1777         swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
1778         roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M,
1779                        VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id);
1780         ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1781         if (ret)
1782                 return ret;
1783
1784         desc.flag =
1785                 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
1786         desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1787         roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1);
1788         roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0);
1789         roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1);
1790
1791         return hns_roce_cmq_send(hr_dev, &desc, 1);
1792 }
1793
1794 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev)
1795 {
1796         u32 vf_id;
1797         int ret;
1798
1799         for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) {
1800                 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id);
1801                 if (ret)
1802                         return ret;
1803         }
1804         return 0;
1805 }
1806
1807 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id)
1808 {
1809         struct hns_roce_cmq_desc desc[2];
1810         struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1811         struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1812         enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1813         struct hns_roce_caps *caps = &hr_dev->caps;
1814
1815         hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1816         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1817         hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1818
1819         hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id);
1820
1821         hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num);
1822         hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num);
1823         hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num);
1824         hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num);
1825         hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num);
1826         hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num);
1827         hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num);
1828         hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num);
1829         hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num);
1830         hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num);
1831         hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num);
1832         hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num);
1833         hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num);
1834         hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num);
1835
1836         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1837                 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num);
1838                 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX,
1839                              vf_id * caps->gmv_bt_num);
1840         } else {
1841                 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num);
1842                 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX,
1843                              vf_id * caps->sgid_bt_num);
1844                 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num);
1845                 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX,
1846                              vf_id * caps->smac_bt_num);
1847         }
1848
1849         return hns_roce_cmq_send(hr_dev, desc, 2);
1850 }
1851
1852 static int config_vf_ext_resource(struct hns_roce_dev *hr_dev, u32 vf_id)
1853 {
1854         struct hns_roce_cmq_desc desc;
1855         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1856         struct hns_roce_caps *caps = &hr_dev->caps;
1857
1858         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, false);
1859
1860         hr_reg_write(req, EXT_CFG_VF_ID, vf_id);
1861
1862         hr_reg_write(req, EXT_CFG_QP_PI_NUM, caps->num_pi_qps);
1863         hr_reg_write(req, EXT_CFG_QP_PI_IDX, vf_id * caps->num_pi_qps);
1864         hr_reg_write(req, EXT_CFG_QP_NUM, caps->num_qps);
1865         hr_reg_write(req, EXT_CFG_QP_IDX, vf_id * caps->num_qps);
1866
1867         return hns_roce_cmq_send(hr_dev, &desc, 1);
1868 }
1869
1870 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1871 {
1872         u32 func_num = max_t(u32, 1, hr_dev->func_num);
1873         u32 vf_id;
1874         int ret;
1875
1876         for (vf_id = 0; vf_id < func_num; vf_id++) {
1877                 ret = config_vf_hem_resource(hr_dev, vf_id);
1878                 if (ret) {
1879                         dev_err(hr_dev->dev,
1880                                 "failed to config vf-%u hem res, ret = %d.\n",
1881                                 vf_id, ret);
1882                         return ret;
1883                 }
1884
1885                 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1886                         ret = config_vf_ext_resource(hr_dev, vf_id);
1887                         if (ret) {
1888                                 dev_err(hr_dev->dev,
1889                                         "failed to config vf-%u ext res, ret = %d.\n",
1890                                         vf_id, ret);
1891                                 return ret;
1892                         }
1893                 }
1894         }
1895
1896         return 0;
1897 }
1898
1899 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1900 {
1901         struct hns_roce_cmq_desc desc;
1902         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1903         struct hns_roce_caps *caps = &hr_dev->caps;
1904
1905         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1906
1907         hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ,
1908                      caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET);
1909         hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ,
1910                      caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET);
1911         hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM,
1912                      to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps));
1913
1914         hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ,
1915                      caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET);
1916         hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ,
1917                      caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET);
1918         hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM,
1919                      to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs));
1920
1921         hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ,
1922                      caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET);
1923         hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ,
1924                      caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET);
1925         hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM,
1926                      to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs));
1927
1928         hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ,
1929                      caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET);
1930         hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ,
1931                      caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET);
1932         hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM,
1933                      to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts));
1934
1935         hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ,
1936                      caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1937         hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ,
1938                      caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1939         hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM,
1940                      to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps));
1941
1942         return hns_roce_cmq_send(hr_dev, &desc, 1);
1943 }
1944
1945 /* Use default caps when hns_roce_query_pf_caps() failed or init VF profile */
1946 static void set_default_caps(struct hns_roce_dev *hr_dev)
1947 {
1948         struct hns_roce_caps *caps = &hr_dev->caps;
1949
1950         caps->num_qps           = HNS_ROCE_V2_MAX_QP_NUM;
1951         caps->max_wqes          = HNS_ROCE_V2_MAX_WQE_NUM;
1952         caps->num_cqs           = HNS_ROCE_V2_MAX_CQ_NUM;
1953         caps->num_srqs          = HNS_ROCE_V2_MAX_SRQ_NUM;
1954         caps->min_cqes          = HNS_ROCE_MIN_CQE_NUM;
1955         caps->max_cqes          = HNS_ROCE_V2_MAX_CQE_NUM;
1956         caps->max_sq_sg         = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
1957         caps->max_extend_sg     = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM;
1958         caps->max_rq_sg         = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1959
1960         caps->num_uars          = HNS_ROCE_V2_UAR_NUM;
1961         caps->phy_num_uars      = HNS_ROCE_V2_PHY_UAR_NUM;
1962         caps->num_aeq_vectors   = HNS_ROCE_V2_AEQE_VEC_NUM;
1963         caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
1964         caps->num_comp_vectors  = 0;
1965
1966         caps->num_mtpts         = HNS_ROCE_V2_MAX_MTPT_NUM;
1967         caps->num_pds           = HNS_ROCE_V2_MAX_PD_NUM;
1968         caps->num_qpc_timer     = HNS_ROCE_V2_MAX_QPC_TIMER_NUM;
1969         caps->num_cqc_timer     = HNS_ROCE_V2_MAX_CQC_TIMER_NUM;
1970
1971         caps->max_qp_init_rdma  = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1972         caps->max_qp_dest_rdma  = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1973         caps->max_sq_desc_sz    = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1974         caps->max_rq_desc_sz    = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1975         caps->max_srq_desc_sz   = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
1976         caps->irrl_entry_sz     = HNS_ROCE_V2_IRRL_ENTRY_SZ;
1977         caps->trrl_entry_sz     = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ;
1978         caps->cqc_entry_sz      = HNS_ROCE_V2_CQC_ENTRY_SZ;
1979         caps->srqc_entry_sz     = HNS_ROCE_V2_SRQC_ENTRY_SZ;
1980         caps->mtpt_entry_sz     = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1981         caps->idx_entry_sz      = HNS_ROCE_V2_IDX_ENTRY_SZ;
1982         caps->page_size_cap     = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1983         caps->reserved_lkey     = 0;
1984         caps->reserved_pds      = 0;
1985         caps->reserved_mrws     = 1;
1986         caps->reserved_uars     = 0;
1987         caps->reserved_cqs      = 0;
1988         caps->reserved_srqs     = 0;
1989         caps->reserved_qps      = HNS_ROCE_V2_RSV_QPS;
1990
1991         caps->qpc_hop_num       = HNS_ROCE_CONTEXT_HOP_NUM;
1992         caps->srqc_hop_num      = HNS_ROCE_CONTEXT_HOP_NUM;
1993         caps->cqc_hop_num       = HNS_ROCE_CONTEXT_HOP_NUM;
1994         caps->mpt_hop_num       = HNS_ROCE_CONTEXT_HOP_NUM;
1995         caps->sccc_hop_num      = HNS_ROCE_SCCC_HOP_NUM;
1996
1997         caps->mtt_hop_num       = HNS_ROCE_MTT_HOP_NUM;
1998         caps->wqe_sq_hop_num    = HNS_ROCE_SQWQE_HOP_NUM;
1999         caps->wqe_sge_hop_num   = HNS_ROCE_EXT_SGE_HOP_NUM;
2000         caps->wqe_rq_hop_num    = HNS_ROCE_RQWQE_HOP_NUM;
2001         caps->cqe_hop_num       = HNS_ROCE_CQE_HOP_NUM;
2002         caps->srqwqe_hop_num    = HNS_ROCE_SRQWQE_HOP_NUM;
2003         caps->idx_hop_num       = HNS_ROCE_IDX_HOP_NUM;
2004         caps->chunk_sz          = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
2005
2006         caps->flags             = HNS_ROCE_CAP_FLAG_REREG_MR |
2007                                   HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
2008                                   HNS_ROCE_CAP_FLAG_CQ_RECORD_DB |
2009                                   HNS_ROCE_CAP_FLAG_QP_RECORD_DB;
2010
2011         caps->pkey_table_len[0] = 1;
2012         caps->ceqe_depth        = HNS_ROCE_V2_COMP_EQE_NUM;
2013         caps->aeqe_depth        = HNS_ROCE_V2_ASYNC_EQE_NUM;
2014         caps->local_ca_ack_delay = 0;
2015         caps->max_mtu = IB_MTU_4096;
2016
2017         caps->max_srq_wrs       = HNS_ROCE_V2_MAX_SRQ_WR;
2018         caps->max_srq_sges      = HNS_ROCE_V2_MAX_SRQ_SGE;
2019
2020         caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW |
2021                        HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR |
2022                        HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL | HNS_ROCE_CAP_FLAG_XRC;
2023
2024         caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
2025
2026         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2027                 caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE;
2028         } else {
2029                 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
2030
2031                 /* The following configuration are only valid for HIP08 */
2032                 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ;
2033                 caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ;
2034                 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE;
2035         }
2036 }
2037
2038 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num,
2039                        u32 *buf_page_size, u32 *bt_page_size, u32 hem_type)
2040 {
2041         u64 obj_per_chunk;
2042         u64 bt_chunk_size = PAGE_SIZE;
2043         u64 buf_chunk_size = PAGE_SIZE;
2044         u64 obj_per_chunk_default = buf_chunk_size / obj_size;
2045
2046         *buf_page_size = 0;
2047         *bt_page_size = 0;
2048
2049         switch (hop_num) {
2050         case 3:
2051                 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2052                                 (bt_chunk_size / BA_BYTE_LEN) *
2053                                 (bt_chunk_size / BA_BYTE_LEN) *
2054                                  obj_per_chunk_default;
2055                 break;
2056         case 2:
2057                 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2058                                 (bt_chunk_size / BA_BYTE_LEN) *
2059                                  obj_per_chunk_default;
2060                 break;
2061         case 1:
2062                 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2063                                 obj_per_chunk_default;
2064                 break;
2065         case HNS_ROCE_HOP_NUM_0:
2066                 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
2067                 break;
2068         default:
2069                 pr_err("table %u not support hop_num = %u!\n", hem_type,
2070                        hop_num);
2071                 return;
2072         }
2073
2074         if (hem_type >= HEM_TYPE_MTT)
2075                 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
2076         else
2077                 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
2078 }
2079
2080 static void set_hem_page_size(struct hns_roce_dev *hr_dev)
2081 {
2082         struct hns_roce_caps *caps = &hr_dev->caps;
2083
2084         /* EQ */
2085         caps->eqe_ba_pg_sz = 0;
2086         caps->eqe_buf_pg_sz = 0;
2087
2088         /* Link Table */
2089         caps->llm_buf_pg_sz = 0;
2090
2091         /* MR */
2092         caps->mpt_ba_pg_sz = 0;
2093         caps->mpt_buf_pg_sz = 0;
2094         caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
2095         caps->pbl_buf_pg_sz = 0;
2096         calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
2097                    caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
2098                    HEM_TYPE_MTPT);
2099
2100         /* QP */
2101         caps->qpc_ba_pg_sz = 0;
2102         caps->qpc_buf_pg_sz = 0;
2103         caps->qpc_timer_ba_pg_sz = 0;
2104         caps->qpc_timer_buf_pg_sz = 0;
2105         caps->sccc_ba_pg_sz = 0;
2106         caps->sccc_buf_pg_sz = 0;
2107         caps->mtt_ba_pg_sz = 0;
2108         caps->mtt_buf_pg_sz = 0;
2109         calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
2110                    caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
2111                    HEM_TYPE_QPC);
2112
2113         if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
2114                 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num,
2115                            caps->sccc_bt_num, &caps->sccc_buf_pg_sz,
2116                            &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC);
2117
2118         /* CQ */
2119         caps->cqc_ba_pg_sz = 0;
2120         caps->cqc_buf_pg_sz = 0;
2121         caps->cqc_timer_ba_pg_sz = 0;
2122         caps->cqc_timer_buf_pg_sz = 0;
2123         caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
2124         caps->cqe_buf_pg_sz = 0;
2125         calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
2126                    caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
2127                    HEM_TYPE_CQC);
2128         calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num,
2129                    1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
2130
2131         /* SRQ */
2132         if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) {
2133                 caps->srqc_ba_pg_sz = 0;
2134                 caps->srqc_buf_pg_sz = 0;
2135                 caps->srqwqe_ba_pg_sz = 0;
2136                 caps->srqwqe_buf_pg_sz = 0;
2137                 caps->idx_ba_pg_sz = 0;
2138                 caps->idx_buf_pg_sz = 0;
2139                 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz,
2140                            caps->srqc_hop_num, caps->srqc_bt_num,
2141                            &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz,
2142                            HEM_TYPE_SRQC);
2143                 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
2144                            caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
2145                            &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
2146                 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz,
2147                            caps->idx_hop_num, 1, &caps->idx_buf_pg_sz,
2148                            &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
2149         }
2150
2151         /* GMV */
2152         caps->gmv_ba_pg_sz = 0;
2153         caps->gmv_buf_pg_sz = 0;
2154 }
2155
2156 /* Apply all loaded caps before setting to hardware */
2157 static void apply_func_caps(struct hns_roce_dev *hr_dev)
2158 {
2159         struct hns_roce_caps *caps = &hr_dev->caps;
2160         struct hns_roce_v2_priv *priv = hr_dev->priv;
2161
2162         /* The following configurations don't need to be got from firmware. */
2163         caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
2164         caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
2165         caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
2166
2167         caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
2168         caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
2169         caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2170         caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2171
2172         caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM;
2173         caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM;
2174
2175         caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
2176         caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
2177         caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
2178
2179         if (!caps->num_comp_vectors)
2180                 caps->num_comp_vectors = min_t(u32, caps->eqc_bt_num - 1,
2181                                   (u32)priv->handle->rinfo.num_vectors - 2);
2182
2183         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2184                 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
2185                 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
2186
2187                 /* The following configurations will be overwritten */
2188                 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
2189                 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
2190                 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ;
2191
2192                 /* The following configurations are not got from firmware */
2193                 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ;
2194
2195                 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0;
2196                 caps->gid_table_len[0] = caps->gmv_bt_num *
2197                                         (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz);
2198
2199                 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE /
2200                                                           caps->gmv_entry_sz);
2201         } else {
2202                 u32 func_num = max_t(u32, 1, hr_dev->func_num);
2203
2204                 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
2205                 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
2206                 caps->gid_table_len[0] /= func_num;
2207         }
2208
2209         if (hr_dev->is_vf) {
2210                 caps->default_aeq_arm_st = 0x3;
2211                 caps->default_ceq_arm_st = 0x3;
2212                 caps->default_ceq_max_cnt = 0x1;
2213                 caps->default_ceq_period = 0x10;
2214                 caps->default_aeq_max_cnt = 0x1;
2215                 caps->default_aeq_period = 0x10;
2216         }
2217
2218         set_hem_page_size(hr_dev);
2219 }
2220
2221 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
2222 {
2223         struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
2224         struct hns_roce_caps *caps = &hr_dev->caps;
2225         struct hns_roce_query_pf_caps_a *resp_a;
2226         struct hns_roce_query_pf_caps_b *resp_b;
2227         struct hns_roce_query_pf_caps_c *resp_c;
2228         struct hns_roce_query_pf_caps_d *resp_d;
2229         struct hns_roce_query_pf_caps_e *resp_e;
2230         int ctx_hop_num;
2231         int pbl_hop_num;
2232         int ret;
2233         int i;
2234
2235         for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
2236                 hns_roce_cmq_setup_basic_desc(&desc[i],
2237                                               HNS_ROCE_OPC_QUERY_PF_CAPS_NUM,
2238                                               true);
2239                 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))
2240                         desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2241                 else
2242                         desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2243         }
2244
2245         ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM);
2246         if (ret)
2247                 return ret;
2248
2249         resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
2250         resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
2251         resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
2252         resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
2253         resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
2254
2255         caps->local_ca_ack_delay     = resp_a->local_ca_ack_delay;
2256         caps->max_sq_sg              = le16_to_cpu(resp_a->max_sq_sg);
2257         caps->max_sq_inline          = le16_to_cpu(resp_a->max_sq_inline);
2258         caps->max_rq_sg              = le16_to_cpu(resp_a->max_rq_sg);
2259         caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg);
2260         caps->max_extend_sg          = le32_to_cpu(resp_a->max_extend_sg);
2261         caps->num_qpc_timer          = le16_to_cpu(resp_a->num_qpc_timer);
2262         caps->num_cqc_timer          = le16_to_cpu(resp_a->num_cqc_timer);
2263         caps->max_srq_sges           = le16_to_cpu(resp_a->max_srq_sges);
2264         caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges);
2265         caps->num_aeq_vectors        = resp_a->num_aeq_vectors;
2266         caps->num_other_vectors      = resp_a->num_other_vectors;
2267         caps->max_sq_desc_sz         = resp_a->max_sq_desc_sz;
2268         caps->max_rq_desc_sz         = resp_a->max_rq_desc_sz;
2269         caps->max_srq_desc_sz        = resp_a->max_srq_desc_sz;
2270         caps->cqe_sz                 = resp_a->cqe_sz;
2271
2272         caps->mtpt_entry_sz          = resp_b->mtpt_entry_sz;
2273         caps->irrl_entry_sz          = resp_b->irrl_entry_sz;
2274         caps->trrl_entry_sz          = resp_b->trrl_entry_sz;
2275         caps->cqc_entry_sz           = resp_b->cqc_entry_sz;
2276         caps->srqc_entry_sz          = resp_b->srqc_entry_sz;
2277         caps->idx_entry_sz           = resp_b->idx_entry_sz;
2278         caps->sccc_sz                = resp_b->sccc_sz;
2279         caps->max_mtu                = resp_b->max_mtu;
2280         caps->qpc_sz                 = le16_to_cpu(resp_b->qpc_sz);
2281         caps->min_cqes               = resp_b->min_cqes;
2282         caps->min_wqes               = resp_b->min_wqes;
2283         caps->page_size_cap          = le32_to_cpu(resp_b->page_size_cap);
2284         caps->pkey_table_len[0]      = resp_b->pkey_table_len;
2285         caps->phy_num_uars           = resp_b->phy_num_uars;
2286         ctx_hop_num                  = resp_b->ctx_hop_num;
2287         pbl_hop_num                  = resp_b->pbl_hop_num;
2288
2289         caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds,
2290                                             V2_QUERY_PF_CAPS_C_NUM_PDS_M,
2291                                             V2_QUERY_PF_CAPS_C_NUM_PDS_S);
2292         caps->flags = roce_get_field(resp_c->cap_flags_num_pds,
2293                                      V2_QUERY_PF_CAPS_C_CAP_FLAGS_M,
2294                                      V2_QUERY_PF_CAPS_C_CAP_FLAGS_S);
2295         caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<
2296                        HNS_ROCE_CAP_FLAGS_EX_SHIFT;
2297
2298         caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs,
2299                                             V2_QUERY_PF_CAPS_C_NUM_CQS_M,
2300                                             V2_QUERY_PF_CAPS_C_NUM_CQS_S);
2301         caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs,
2302                                                 V2_QUERY_PF_CAPS_C_MAX_GID_M,
2303                                                 V2_QUERY_PF_CAPS_C_MAX_GID_S);
2304
2305         caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth,
2306                                              V2_QUERY_PF_CAPS_C_CQ_DEPTH_M,
2307                                              V2_QUERY_PF_CAPS_C_CQ_DEPTH_S);
2308         caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws,
2309                                               V2_QUERY_PF_CAPS_C_NUM_MRWS_M,
2310                                               V2_QUERY_PF_CAPS_C_NUM_MRWS_S);
2311         caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps,
2312                                             V2_QUERY_PF_CAPS_C_NUM_QPS_M,
2313                                             V2_QUERY_PF_CAPS_C_NUM_QPS_S);
2314         caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps,
2315                                                 V2_QUERY_PF_CAPS_C_MAX_ORD_M,
2316                                                 V2_QUERY_PF_CAPS_C_MAX_ORD_S);
2317         caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
2318         caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
2319         caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs,
2320                                              V2_QUERY_PF_CAPS_D_NUM_SRQS_M,
2321                                              V2_QUERY_PF_CAPS_D_NUM_SRQS_S);
2322         caps->cong_type = roce_get_field(resp_d->wq_hop_num_max_srqs,
2323                                          V2_QUERY_PF_CAPS_D_CONG_TYPE_M,
2324                                          V2_QUERY_PF_CAPS_D_CONG_TYPE_S);
2325         caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
2326
2327         caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth,
2328                                                V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M,
2329                                                V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S);
2330         caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth,
2331                                                 V2_QUERY_PF_CAPS_D_NUM_CEQS_M,
2332                                                 V2_QUERY_PF_CAPS_D_NUM_CEQS_S);
2333
2334         caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth,
2335                                                V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M,
2336                                                V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S);
2337         caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,
2338                                             V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M,
2339                                             V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S);
2340         caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,
2341                                             V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M,
2342                                             V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S);
2343         caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds,
2344                                             V2_QUERY_PF_CAPS_D_RSV_PDS_M,
2345                                             V2_QUERY_PF_CAPS_D_RSV_PDS_S);
2346         caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds,
2347                                              V2_QUERY_PF_CAPS_D_NUM_UARS_M,
2348                                              V2_QUERY_PF_CAPS_D_NUM_UARS_S);
2349         caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps,
2350                                             V2_QUERY_PF_CAPS_D_RSV_QPS_M,
2351                                             V2_QUERY_PF_CAPS_D_RSV_QPS_S);
2352         caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps,
2353                                              V2_QUERY_PF_CAPS_D_RSV_UARS_M,
2354                                              V2_QUERY_PF_CAPS_D_RSV_UARS_S);
2355         caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws,
2356                                              V2_QUERY_PF_CAPS_E_RSV_MRWS_M,
2357                                              V2_QUERY_PF_CAPS_E_RSV_MRWS_S);
2358         caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws,
2359                                          V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M,
2360                                          V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S);
2361         caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs,
2362                                             V2_QUERY_PF_CAPS_E_RSV_CQS_M,
2363                                             V2_QUERY_PF_CAPS_E_RSV_CQS_S);
2364         caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs,
2365                                              V2_QUERY_PF_CAPS_E_RSV_SRQS_M,
2366                                              V2_QUERY_PF_CAPS_E_RSV_SRQS_S);
2367         caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey,
2368                                              V2_QUERY_PF_CAPS_E_RSV_LKEYS_M,
2369                                              V2_QUERY_PF_CAPS_E_RSV_LKEYS_S);
2370         caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
2371         caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
2372         caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
2373         caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
2374
2375         caps->qpc_hop_num = ctx_hop_num;
2376         caps->sccc_hop_num = ctx_hop_num;
2377         caps->srqc_hop_num = ctx_hop_num;
2378         caps->cqc_hop_num = ctx_hop_num;
2379         caps->mpt_hop_num = ctx_hop_num;
2380         caps->mtt_hop_num = pbl_hop_num;
2381         caps->cqe_hop_num = pbl_hop_num;
2382         caps->srqwqe_hop_num = pbl_hop_num;
2383         caps->idx_hop_num = pbl_hop_num;
2384         caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
2385                                           V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M,
2386                                           V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S);
2387         caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
2388                                           V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M,
2389                                           V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S);
2390         caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
2391                                           V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M,
2392                                           V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S);
2393
2394         return 0;
2395 }
2396
2397 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val)
2398 {
2399         struct hns_roce_cmq_desc desc;
2400         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
2401
2402         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,
2403                                       false);
2404
2405         hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type);
2406         hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val);
2407
2408         return hns_roce_cmq_send(hr_dev, &desc, 1);
2409 }
2410
2411 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)
2412 {
2413         struct hns_roce_caps *caps = &hr_dev->caps;
2414         int ret;
2415
2416         if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09)
2417                 return 0;
2418
2419         ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE,
2420                                     caps->qpc_sz);
2421         if (ret) {
2422                 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret);
2423                 return ret;
2424         }
2425
2426         ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE,
2427                                     caps->sccc_sz);
2428         if (ret)
2429                 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret);
2430
2431         return ret;
2432 }
2433
2434 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev)
2435 {
2436         struct device *dev = hr_dev->dev;
2437         int ret;
2438
2439         hr_dev->func_num = 1;
2440
2441         set_default_caps(hr_dev);
2442
2443         ret = hns_roce_query_vf_resource(hr_dev);
2444         if (ret) {
2445                 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret);
2446                 return ret;
2447         }
2448
2449         apply_func_caps(hr_dev);
2450
2451         ret = hns_roce_v2_set_bt(hr_dev);
2452         if (ret)
2453                 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret);
2454
2455         return ret;
2456 }
2457
2458 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev)
2459 {
2460         struct device *dev = hr_dev->dev;
2461         int ret;
2462
2463         ret = hns_roce_query_func_info(hr_dev);
2464         if (ret) {
2465                 dev_err(dev, "failed to query func info, ret = %d.\n", ret);
2466                 return ret;
2467         }
2468
2469         ret = hns_roce_config_global_param(hr_dev);
2470         if (ret) {
2471                 dev_err(dev, "failed to config global param, ret = %d.\n", ret);
2472                 return ret;
2473         }
2474
2475         ret = hns_roce_set_vf_switch_param(hr_dev);
2476         if (ret) {
2477                 dev_err(dev, "failed to set switch param, ret = %d.\n", ret);
2478                 return ret;
2479         }
2480
2481         ret = hns_roce_query_pf_caps(hr_dev);
2482         if (ret)
2483                 set_default_caps(hr_dev);
2484
2485         ret = hns_roce_query_pf_resource(hr_dev);
2486         if (ret) {
2487                 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret);
2488                 return ret;
2489         }
2490
2491         apply_func_caps(hr_dev);
2492
2493         ret = hns_roce_alloc_vf_resource(hr_dev);
2494         if (ret) {
2495                 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret);
2496                 return ret;
2497         }
2498
2499         ret = hns_roce_v2_set_bt(hr_dev);
2500         if (ret) {
2501                 dev_err(dev, "failed to config BA table, ret = %d.\n", ret);
2502                 return ret;
2503         }
2504
2505         /* Configure the size of QPC, SCCC, etc. */
2506         return hns_roce_config_entry_size(hr_dev);
2507 }
2508
2509 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
2510 {
2511         struct device *dev = hr_dev->dev;
2512         int ret;
2513
2514         ret = hns_roce_cmq_query_hw_info(hr_dev);
2515         if (ret) {
2516                 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret);
2517                 return ret;
2518         }
2519
2520         ret = hns_roce_query_fw_ver(hr_dev);
2521         if (ret) {
2522                 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret);
2523                 return ret;
2524         }
2525
2526         hr_dev->vendor_part_id = hr_dev->pci_dev->device;
2527         hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
2528
2529         if (hr_dev->is_vf)
2530                 return hns_roce_v2_vf_profile(hr_dev);
2531         else
2532                 return hns_roce_v2_pf_profile(hr_dev);
2533 }
2534
2535 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf)
2536 {
2537         u32 i, next_ptr, page_num;
2538         __le64 *entry = cfg_buf;
2539         dma_addr_t addr;
2540         u64 val;
2541
2542         page_num = data_buf->npages;
2543         for (i = 0; i < page_num; i++) {
2544                 addr = hns_roce_buf_page(data_buf, i);
2545                 if (i == (page_num - 1))
2546                         next_ptr = 0;
2547                 else
2548                         next_ptr = i + 1;
2549
2550                 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr);
2551                 entry[i] = cpu_to_le64(val);
2552         }
2553 }
2554
2555 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev,
2556                              struct hns_roce_link_table *table)
2557 {
2558         struct hns_roce_cmq_desc desc[2];
2559         struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
2560         struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
2561         struct hns_roce_buf *buf = table->buf;
2562         enum hns_roce_opcode_type opcode;
2563         dma_addr_t addr;
2564
2565         opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2566         hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
2567         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2568         hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
2569
2570         hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map));
2571         hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map));
2572         hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages);
2573         hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift));
2574         hr_reg_enable(r_a, CFG_LLM_A_INIT_EN);
2575
2576         addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0));
2577         hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr));
2578         hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr));
2579         hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1);
2580         hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0);
2581
2582         addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1));
2583         hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr));
2584         hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr));
2585         hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1);
2586
2587         return hns_roce_cmq_send(hr_dev, desc, 2);
2588 }
2589
2590 static struct hns_roce_link_table *
2591 alloc_link_table_buf(struct hns_roce_dev *hr_dev)
2592 {
2593         struct hns_roce_v2_priv *priv = hr_dev->priv;
2594         struct hns_roce_link_table *link_tbl;
2595         u32 pg_shift, size, min_size;
2596
2597         link_tbl = &priv->ext_llm;
2598         pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT;
2599         size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;
2600         min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift;
2601
2602         /* Alloc data table */
2603         size = max(size, min_size);
2604         link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0);
2605         if (IS_ERR(link_tbl->buf))
2606                 return ERR_PTR(-ENOMEM);
2607
2608         /* Alloc config table */
2609         size = link_tbl->buf->npages * sizeof(u64);
2610         link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size,
2611                                                  &link_tbl->table.map,
2612                                                  GFP_KERNEL);
2613         if (!link_tbl->table.buf) {
2614                 hns_roce_buf_free(hr_dev, link_tbl->buf);
2615                 return ERR_PTR(-ENOMEM);
2616         }
2617
2618         return link_tbl;
2619 }
2620
2621 static void free_link_table_buf(struct hns_roce_dev *hr_dev,
2622                                 struct hns_roce_link_table *tbl)
2623 {
2624         if (tbl->buf) {
2625                 u32 size = tbl->buf->npages * sizeof(u64);
2626
2627                 dma_free_coherent(hr_dev->dev, size, tbl->table.buf,
2628                                   tbl->table.map);
2629         }
2630
2631         hns_roce_buf_free(hr_dev, tbl->buf);
2632 }
2633
2634 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev)
2635 {
2636         struct hns_roce_link_table *link_tbl;
2637         int ret;
2638
2639         link_tbl = alloc_link_table_buf(hr_dev);
2640         if (IS_ERR(link_tbl))
2641                 return -ENOMEM;
2642
2643         if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) {
2644                 ret = -EINVAL;
2645                 goto err_alloc;
2646         }
2647
2648         config_llm_table(link_tbl->buf, link_tbl->table.buf);
2649         ret = set_llm_cfg_to_hw(hr_dev, link_tbl);
2650         if (ret)
2651                 goto err_alloc;
2652
2653         return 0;
2654
2655 err_alloc:
2656         free_link_table_buf(hr_dev, link_tbl);
2657         return ret;
2658 }
2659
2660 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev)
2661 {
2662         struct hns_roce_v2_priv *priv = hr_dev->priv;
2663
2664         free_link_table_buf(hr_dev, &priv->ext_llm);
2665 }
2666
2667 static void free_dip_list(struct hns_roce_dev *hr_dev)
2668 {
2669         struct hns_roce_dip *hr_dip;
2670         struct hns_roce_dip *tmp;
2671         unsigned long flags;
2672
2673         spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
2674
2675         list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) {
2676                 list_del(&hr_dip->node);
2677                 kfree(hr_dip);
2678         }
2679
2680         spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
2681 }
2682
2683 static int get_hem_table(struct hns_roce_dev *hr_dev)
2684 {
2685         unsigned int qpc_count;
2686         unsigned int cqc_count;
2687         unsigned int gmv_count;
2688         int ret;
2689         int i;
2690
2691         /* Alloc memory for source address table buffer space chunk */
2692         for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num;
2693              gmv_count++) {
2694                 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count);
2695                 if (ret)
2696                         goto err_gmv_failed;
2697         }
2698
2699         if (hr_dev->is_vf)
2700                 return 0;
2701
2702         /* Alloc memory for QPC Timer buffer space chunk */
2703         for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2704              qpc_count++) {
2705                 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2706                                          qpc_count);
2707                 if (ret) {
2708                         dev_err(hr_dev->dev, "QPC Timer get failed\n");
2709                         goto err_qpc_timer_failed;
2710                 }
2711         }
2712
2713         /* Alloc memory for CQC Timer buffer space chunk */
2714         for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2715              cqc_count++) {
2716                 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2717                                          cqc_count);
2718                 if (ret) {
2719                         dev_err(hr_dev->dev, "CQC Timer get failed\n");
2720                         goto err_cqc_timer_failed;
2721                 }
2722         }
2723
2724         return 0;
2725
2726 err_cqc_timer_failed:
2727         for (i = 0; i < cqc_count; i++)
2728                 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2729
2730 err_qpc_timer_failed:
2731         for (i = 0; i < qpc_count; i++)
2732                 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2733
2734 err_gmv_failed:
2735         for (i = 0; i < gmv_count; i++)
2736                 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2737
2738         return ret;
2739 }
2740
2741 static void put_hem_table(struct hns_roce_dev *hr_dev)
2742 {
2743         int i;
2744
2745         for (i = 0; i < hr_dev->caps.gmv_entry_num; i++)
2746                 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2747
2748         if (hr_dev->is_vf)
2749                 return;
2750
2751         for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++)
2752                 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2753
2754         for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++)
2755                 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2756 }
2757
2758 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2759 {
2760         int ret;
2761
2762         /* The hns ROCEE requires the extdb info to be cleared before using */
2763         ret = hns_roce_clear_extdb_list_info(hr_dev);
2764         if (ret)
2765                 return ret;
2766
2767         ret = get_hem_table(hr_dev);
2768         if (ret)
2769                 return ret;
2770
2771         if (hr_dev->is_vf)
2772                 return 0;
2773
2774         ret = hns_roce_init_link_table(hr_dev);
2775         if (ret) {
2776                 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret);
2777                 goto err_llm_init_failed;
2778         }
2779
2780         return 0;
2781
2782 err_llm_init_failed:
2783         put_hem_table(hr_dev);
2784
2785         return ret;
2786 }
2787
2788 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
2789 {
2790         hns_roce_function_clear(hr_dev);
2791
2792         if (!hr_dev->is_vf)
2793                 hns_roce_free_link_table(hr_dev);
2794
2795         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09)
2796                 free_dip_list(hr_dev);
2797 }
2798
2799 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param,
2800                               u64 out_param, u32 in_modifier, u8 op_modifier,
2801                               u16 op, u16 token, int event)
2802 {
2803         struct hns_roce_cmq_desc desc;
2804         struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
2805
2806         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
2807
2808         mb->in_param_l = cpu_to_le32(in_param);
2809         mb->in_param_h = cpu_to_le32(in_param >> 32);
2810         mb->out_param_l = cpu_to_le32(out_param);
2811         mb->out_param_h = cpu_to_le32(out_param >> 32);
2812         mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op);
2813         mb->token_event_en = cpu_to_le32(event << 16 | token);
2814
2815         return hns_roce_cmq_send(hr_dev, &desc, 1);
2816 }
2817
2818 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout,
2819                                  u8 *complete_status)
2820 {
2821         struct hns_roce_mbox_status *mb_st;
2822         struct hns_roce_cmq_desc desc;
2823         unsigned long end;
2824         int ret = -EBUSY;
2825         u32 status;
2826         bool busy;
2827
2828         mb_st = (struct hns_roce_mbox_status *)desc.data;
2829         end = msecs_to_jiffies(timeout) + jiffies;
2830         while (v2_chk_mbox_is_avail(hr_dev, &busy)) {
2831                 status = 0;
2832                 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST,
2833                                               true);
2834                 ret = __hns_roce_cmq_send(hr_dev, &desc, 1);
2835                 if (!ret) {
2836                         status = le32_to_cpu(mb_st->mb_status_hw_run);
2837                         /* No pending message exists in ROCEE mbox. */
2838                         if (!(status & MB_ST_HW_RUN_M))
2839                                 break;
2840                 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
2841                         break;
2842                 }
2843
2844                 if (time_after(jiffies, end)) {
2845                         dev_err_ratelimited(hr_dev->dev,
2846                                             "failed to wait mbox status 0x%x\n",
2847                                             status);
2848                         return -ETIMEDOUT;
2849                 }
2850
2851                 cond_resched();
2852                 ret = -EBUSY;
2853         }
2854
2855         if (!ret) {
2856                 *complete_status = (u8)(status & MB_ST_COMPLETE_M);
2857         } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
2858                 /* Ignore all errors if the mbox is unavailable. */
2859                 ret = 0;
2860                 *complete_status = MB_ST_COMPLETE_M;
2861         }
2862
2863         return ret;
2864 }
2865
2866 static int v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
2867                         u64 out_param, u32 in_modifier, u8 op_modifier,
2868                         u16 op, u16 token, int event)
2869 {
2870         u8 status = 0;
2871         int ret;
2872
2873         /* Waiting for the mbox to be idle */
2874         ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS,
2875                                     &status);
2876         if (unlikely(ret)) {
2877                 dev_err_ratelimited(hr_dev->dev,
2878                                     "failed to check post mbox status = 0x%x, ret = %d.\n",
2879                                     status, ret);
2880                 return ret;
2881         }
2882
2883         /* Post new message to mbox */
2884         ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier,
2885                                  op_modifier, op, token, event);
2886         if (ret)
2887                 dev_err_ratelimited(hr_dev->dev,
2888                                     "failed to post mailbox, ret = %d.\n", ret);
2889
2890         return ret;
2891 }
2892
2893 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev, unsigned int timeout)
2894 {
2895         u8 status = 0;
2896         int ret;
2897
2898         ret = v2_wait_mbox_complete(hr_dev, timeout, &status);
2899         if (!ret) {
2900                 if (status != MB_ST_COMPLETE_SUCC)
2901                         return -EBUSY;
2902         } else {
2903                 dev_err_ratelimited(hr_dev->dev,
2904                                     "failed to check mbox status = 0x%x, ret = %d.\n",
2905                                     status, ret);
2906         }
2907
2908         return ret;
2909 }
2910
2911 static void copy_gid(void *dest, const union ib_gid *gid)
2912 {
2913 #define GID_SIZE 4
2914         const union ib_gid *src = gid;
2915         __le32 (*p)[GID_SIZE] = dest;
2916         int i;
2917
2918         if (!gid)
2919                 src = &zgid;
2920
2921         for (i = 0; i < GID_SIZE; i++)
2922                 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]);
2923 }
2924
2925 static int config_sgid_table(struct hns_roce_dev *hr_dev,
2926                              int gid_index, const union ib_gid *gid,
2927                              enum hns_roce_sgid_type sgid_type)
2928 {
2929         struct hns_roce_cmq_desc desc;
2930         struct hns_roce_cfg_sgid_tb *sgid_tb =
2931                                     (struct hns_roce_cfg_sgid_tb *)desc.data;
2932
2933         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
2934
2935         roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M,
2936                        CFG_SGID_TB_TABLE_IDX_S, gid_index);
2937         roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M,
2938                        CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);
2939
2940         copy_gid(&sgid_tb->vf_sgid_l, gid);
2941
2942         return hns_roce_cmq_send(hr_dev, &desc, 1);
2943 }
2944
2945 static int config_gmv_table(struct hns_roce_dev *hr_dev,
2946                             int gid_index, const union ib_gid *gid,
2947                             enum hns_roce_sgid_type sgid_type,
2948                             const struct ib_gid_attr *attr)
2949 {
2950         struct hns_roce_cmq_desc desc[2];
2951         struct hns_roce_cfg_gmv_tb_a *tb_a =
2952                                 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data;
2953         struct hns_roce_cfg_gmv_tb_b *tb_b =
2954                                 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data;
2955
2956         u16 vlan_id = VLAN_CFI_MASK;
2957         u8 mac[ETH_ALEN] = {};
2958         int ret;
2959
2960         if (gid) {
2961                 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac);
2962                 if (ret)
2963                         return ret;
2964         }
2965
2966         hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false);
2967         desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2968
2969         hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false);
2970
2971         copy_gid(&tb_a->vf_sgid_l, gid);
2972
2973         roce_set_field(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_SGID_TYPE_M,
2974                        CFG_GMV_TB_VF_SGID_TYPE_S, sgid_type);
2975         roce_set_bit(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_VLAN_EN_S,
2976                      vlan_id < VLAN_CFI_MASK);
2977         roce_set_field(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_VLAN_ID_M,
2978                        CFG_GMV_TB_VF_VLAN_ID_S, vlan_id);
2979
2980         tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac);
2981         roce_set_field(tb_b->vf_smac_h, CFG_GMV_TB_SMAC_H_M,
2982                        CFG_GMV_TB_SMAC_H_S, *(u16 *)&mac[4]);
2983
2984         roce_set_field(tb_b->table_idx_rsv, CFG_GMV_TB_SGID_IDX_M,
2985                        CFG_GMV_TB_SGID_IDX_S, gid_index);
2986
2987         return hns_roce_cmq_send(hr_dev, desc, 2);
2988 }
2989
2990 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u32 port,
2991                                int gid_index, const union ib_gid *gid,
2992                                const struct ib_gid_attr *attr)
2993 {
2994         enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
2995         int ret;
2996
2997         if (gid) {
2998                 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
2999                         if (ipv6_addr_v4mapped((void *)gid))
3000                                 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
3001                         else
3002                                 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
3003                 } else if (attr->gid_type == IB_GID_TYPE_ROCE) {
3004                         sgid_type = GID_TYPE_FLAG_ROCE_V1;
3005                 }
3006         }
3007
3008         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
3009                 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr);
3010         else
3011                 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type);
3012
3013         if (ret)
3014                 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n",
3015                           ret);
3016
3017         return ret;
3018 }
3019
3020 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
3021                                u8 *addr)
3022 {
3023         struct hns_roce_cmq_desc desc;
3024         struct hns_roce_cfg_smac_tb *smac_tb =
3025                                     (struct hns_roce_cfg_smac_tb *)desc.data;
3026         u16 reg_smac_h;
3027         u32 reg_smac_l;
3028
3029         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
3030
3031         reg_smac_l = *(u32 *)(&addr[0]);
3032         reg_smac_h = *(u16 *)(&addr[4]);
3033
3034         roce_set_field(smac_tb->tb_idx_rsv, CFG_SMAC_TB_IDX_M,
3035                        CFG_SMAC_TB_IDX_S, phy_port);
3036         roce_set_field(smac_tb->vf_smac_h_rsv, CFG_SMAC_TB_VF_SMAC_H_M,
3037                        CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);
3038         smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
3039
3040         return hns_roce_cmq_send(hr_dev, &desc, 1);
3041 }
3042
3043 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
3044                         struct hns_roce_v2_mpt_entry *mpt_entry,
3045                         struct hns_roce_mr *mr)
3046 {
3047         u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 };
3048         struct ib_device *ibdev = &hr_dev->ib_dev;
3049         dma_addr_t pbl_ba;
3050         int i, count;
3051
3052         count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
3053                                   ARRAY_SIZE(pages), &pbl_ba);
3054         if (count < 1) {
3055                 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n",
3056                           count);
3057                 return -ENOBUFS;
3058         }
3059
3060         /* Aligned to the hardware address access unit */
3061         for (i = 0; i < count; i++)
3062                 pages[i] >>= 6;
3063
3064         mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3065         mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3);
3066         roce_set_field(mpt_entry->byte_48_mode_ba,
3067                        V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S,
3068                        upper_32_bits(pbl_ba >> 3));
3069
3070         mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
3071         roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
3072                        V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0]));
3073
3074         mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
3075         roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
3076                        V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
3077         roce_set_field(mpt_entry->byte_64_buf_pa1,
3078                        V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
3079                        V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
3080                        to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3081
3082         return 0;
3083 }
3084
3085 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
3086                                   void *mb_buf, struct hns_roce_mr *mr,
3087                                   unsigned long mtpt_idx)
3088 {
3089         struct hns_roce_v2_mpt_entry *mpt_entry;
3090         int ret;
3091
3092         mpt_entry = mb_buf;
3093         memset(mpt_entry, 0, sizeof(*mpt_entry));
3094
3095         hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3096         hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3097         hr_reg_enable(mpt_entry, MPT_L_INV_EN);
3098
3099         hr_reg_write_bool(mpt_entry, MPT_BIND_EN,
3100                           mr->access & IB_ACCESS_MW_BIND);
3101         hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN,
3102                           mr->access & IB_ACCESS_REMOTE_ATOMIC);
3103         hr_reg_write_bool(mpt_entry, MPT_RR_EN,
3104                           mr->access & IB_ACCESS_REMOTE_READ);
3105         hr_reg_write_bool(mpt_entry, MPT_RW_EN,
3106                           mr->access & IB_ACCESS_REMOTE_WRITE);
3107         hr_reg_write_bool(mpt_entry, MPT_LW_EN,
3108                           mr->access & IB_ACCESS_LOCAL_WRITE);
3109
3110         mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3111         mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3112         mpt_entry->lkey = cpu_to_le32(mr->key);
3113         mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3114         mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3115
3116         if (mr->type != MR_TYPE_MR)
3117                 hr_reg_enable(mpt_entry, MPT_PA);
3118
3119         if (mr->type == MR_TYPE_DMA)
3120                 return 0;
3121
3122         if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0)
3123                 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num);
3124
3125         hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3126                      to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3127         hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD);
3128
3129         ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
3130
3131         return ret;
3132 }
3133
3134 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
3135                                         struct hns_roce_mr *mr, int flags,
3136                                         void *mb_buf)
3137 {
3138         struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
3139         u32 mr_access_flags = mr->access;
3140         int ret = 0;
3141
3142         roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
3143                        V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
3144
3145         roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
3146                        V2_MPT_BYTE_4_PD_S, mr->pd);
3147
3148         if (flags & IB_MR_REREG_ACCESS) {
3149                 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
3150                              V2_MPT_BYTE_8_BIND_EN_S,
3151                              (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
3152                 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
3153                              V2_MPT_BYTE_8_ATOMIC_EN_S,
3154                              mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3155                 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
3156                              mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
3157                 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
3158                              mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
3159                 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
3160                              mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
3161         }
3162
3163         if (flags & IB_MR_REREG_TRANS) {
3164                 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3165                 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3166                 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3167                 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3168
3169                 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
3170         }
3171
3172         return ret;
3173 }
3174
3175 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev,
3176                                        void *mb_buf, struct hns_roce_mr *mr)
3177 {
3178         struct ib_device *ibdev = &hr_dev->ib_dev;
3179         struct hns_roce_v2_mpt_entry *mpt_entry;
3180         dma_addr_t pbl_ba = 0;
3181
3182         mpt_entry = mb_buf;
3183         memset(mpt_entry, 0, sizeof(*mpt_entry));
3184
3185         if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) {
3186                 ibdev_err(ibdev, "failed to find frmr mtr.\n");
3187                 return -ENOBUFS;
3188         }
3189
3190         roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
3191                        V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
3192         roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
3193                        V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1);
3194         roce_set_field(mpt_entry->byte_4_pd_hop_st,
3195                        V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
3196                        V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
3197                        to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3198         roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
3199                        V2_MPT_BYTE_4_PD_S, mr->pd);
3200
3201         roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1);
3202         roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
3203         roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
3204
3205         roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1);
3206         roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
3207         roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0);
3208         roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
3209
3210         mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3211
3212         mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3));
3213         roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
3214                        V2_MPT_BYTE_48_PBL_BA_H_S,
3215                        upper_32_bits(pbl_ba >> 3));
3216
3217         roce_set_field(mpt_entry->byte_64_buf_pa1,
3218                        V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
3219                        V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
3220                        to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3221
3222         return 0;
3223 }
3224
3225 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
3226 {
3227         struct hns_roce_v2_mpt_entry *mpt_entry;
3228
3229         mpt_entry = mb_buf;
3230         memset(mpt_entry, 0, sizeof(*mpt_entry));
3231
3232         roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
3233                        V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
3234         roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
3235                        V2_MPT_BYTE_4_PD_S, mw->pdn);
3236         roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
3237                        V2_MPT_BYTE_4_PBL_HOP_NUM_S,
3238                        mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
3239                                                                mw->pbl_hop_num);
3240         roce_set_field(mpt_entry->byte_4_pd_hop_st,
3241                        V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
3242                        V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
3243                        mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3244
3245         roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
3246         roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
3247         roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1);
3248
3249         roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
3250         roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1);
3251         roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
3252         roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S,
3253                      mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
3254
3255         roce_set_field(mpt_entry->byte_64_buf_pa1,
3256                        V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
3257                        V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
3258                        mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3259
3260         mpt_entry->lkey = cpu_to_le32(mw->rkey);
3261
3262         return 0;
3263 }
3264
3265 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
3266 {
3267         return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
3268 }
3269
3270 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n)
3271 {
3272         struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
3273
3274         /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
3275         return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe :
3276                                                                          NULL;
3277 }
3278
3279 static inline void update_cq_db(struct hns_roce_dev *hr_dev,
3280                                 struct hns_roce_cq *hr_cq)
3281 {
3282         if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) {
3283                 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M;
3284         } else {
3285                 struct hns_roce_v2_db cq_db = {};
3286
3287                 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3288                 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB);
3289                 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3290                 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1);
3291
3292                 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3293         }
3294 }
3295
3296 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3297                                    struct hns_roce_srq *srq)
3298 {
3299         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3300         struct hns_roce_v2_cqe *cqe, *dest;
3301         u32 prod_index;
3302         int nfreed = 0;
3303         int wqe_index;
3304         u8 owner_bit;
3305
3306         for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
3307              ++prod_index) {
3308                 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
3309                         break;
3310         }
3311
3312         /*
3313          * Now backwards through the CQ, removing CQ entries
3314          * that match our QP by overwriting them with next entries.
3315          */
3316         while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
3317                 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
3318                 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) {
3319                         if (srq && hr_reg_read(cqe, CQE_S_R)) {
3320                                 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX);
3321                                 hns_roce_free_srq_wqe(srq, wqe_index);
3322                         }
3323                         ++nfreed;
3324                 } else if (nfreed) {
3325                         dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
3326                                           hr_cq->ib_cq.cqe);
3327                         owner_bit = hr_reg_read(dest, CQE_OWNER);
3328                         memcpy(dest, cqe, sizeof(*cqe));
3329                         hr_reg_write(dest, CQE_OWNER, owner_bit);
3330                 }
3331         }
3332
3333         if (nfreed) {
3334                 hr_cq->cons_index += nfreed;
3335                 update_cq_db(hr_dev, hr_cq);
3336         }
3337 }
3338
3339 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3340                                  struct hns_roce_srq *srq)
3341 {
3342         spin_lock_irq(&hr_cq->lock);
3343         __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
3344         spin_unlock_irq(&hr_cq->lock);
3345 }
3346
3347 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
3348                                   struct hns_roce_cq *hr_cq, void *mb_buf,
3349                                   u64 *mtts, dma_addr_t dma_handle)
3350 {
3351         struct hns_roce_v2_cq_context *cq_context;
3352
3353         cq_context = mb_buf;
3354         memset(cq_context, 0, sizeof(*cq_context));
3355
3356         hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID);
3357         hr_reg_write(cq_context, CQC_ARM_ST, REG_NXT_CEQE);
3358         hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth));
3359         hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector);
3360         hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn);
3361
3362         if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE)
3363                 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B);
3364
3365         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
3366                 hr_reg_enable(cq_context, CQC_STASH);
3367
3368         hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L,
3369                      to_hr_hw_page_addr(mtts[0]));
3370         hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H,
3371                      upper_32_bits(to_hr_hw_page_addr(mtts[0])));
3372         hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num ==
3373                      HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
3374         hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L,
3375                      to_hr_hw_page_addr(mtts[1]));
3376         hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H,
3377                      upper_32_bits(to_hr_hw_page_addr(mtts[1])));
3378         hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ,
3379                      to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
3380         hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ,
3381                      to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
3382         hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3);
3383         hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3)));
3384         hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN,
3385                           hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB);
3386         hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L,
3387                      ((u32)hr_cq->db.dma) >> 1);
3388         hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H,
3389                      hr_cq->db.dma >> 32);
3390         hr_reg_write(cq_context, CQC_CQ_MAX_CNT,
3391                      HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
3392         hr_reg_write(cq_context, CQC_CQ_PERIOD,
3393                      HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
3394 }
3395
3396 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
3397                                      enum ib_cq_notify_flags flags)
3398 {
3399         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3400         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3401         struct hns_roce_v2_db cq_db = {};
3402         u32 notify_flag;
3403
3404         /*
3405          * flags = 0, then notify_flag : next
3406          * flags = 1, then notify flag : solocited
3407          */
3408         notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
3409                       V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
3410
3411         hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3412         hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY);
3413         hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3414         hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn);
3415         hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag);
3416
3417         hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3418
3419         return 0;
3420 }
3421
3422 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
3423                                         struct hns_roce_qp *qp,
3424                                         struct ib_wc *wc)
3425 {
3426         struct hns_roce_rinl_sge *sge_list;
3427         u32 wr_num, wr_cnt, sge_num;
3428         u32 sge_cnt, data_len, size;
3429         void *wqe_buf;
3430
3431         wr_num = hr_reg_read(cqe, CQE_WQE_IDX);
3432         wr_cnt = wr_num & (qp->rq.wqe_cnt - 1);
3433
3434         sge_list = qp->rq_inl_buf.wqe_list[wr_cnt].sg_list;
3435         sge_num = qp->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
3436         wqe_buf = hns_roce_get_recv_wqe(qp, wr_cnt);
3437         data_len = wc->byte_len;
3438
3439         for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
3440                 size = min(sge_list[sge_cnt].len, data_len);
3441                 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
3442
3443                 data_len -= size;
3444                 wqe_buf += size;
3445         }
3446
3447         if (unlikely(data_len)) {
3448                 wc->status = IB_WC_LOC_LEN_ERR;
3449                 return -EAGAIN;
3450         }
3451
3452         return 0;
3453 }
3454
3455 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
3456                    int num_entries, struct ib_wc *wc)
3457 {
3458         unsigned int left;
3459         int npolled = 0;
3460
3461         left = wq->head - wq->tail;
3462         if (left == 0)
3463                 return 0;
3464
3465         left = min_t(unsigned int, (unsigned int)num_entries, left);
3466         while (npolled < left) {
3467                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3468                 wc->status = IB_WC_WR_FLUSH_ERR;
3469                 wc->vendor_err = 0;
3470                 wc->qp = &hr_qp->ibqp;
3471
3472                 wq->tail++;
3473                 wc++;
3474                 npolled++;
3475         }
3476
3477         return npolled;
3478 }
3479
3480 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
3481                                   struct ib_wc *wc)
3482 {
3483         struct hns_roce_qp *hr_qp;
3484         int npolled = 0;
3485
3486         list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
3487                 npolled += sw_comp(hr_qp, &hr_qp->sq,
3488                                    num_entries - npolled, wc + npolled);
3489                 if (npolled >= num_entries)
3490                         goto out;
3491         }
3492
3493         list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
3494                 npolled += sw_comp(hr_qp, &hr_qp->rq,
3495                                    num_entries - npolled, wc + npolled);
3496                 if (npolled >= num_entries)
3497                         goto out;
3498         }
3499
3500 out:
3501         return npolled;
3502 }
3503
3504 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
3505                            struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe,
3506                            struct ib_wc *wc)
3507 {
3508         static const struct {
3509                 u32 cqe_status;
3510                 enum ib_wc_status wc_status;
3511         } map[] = {
3512                 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS },
3513                 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR },
3514                 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR },
3515                 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR },
3516                 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR },
3517                 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR },
3518                 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR },
3519                 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR },
3520                 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR },
3521                 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR },
3522                 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR },
3523                 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR,
3524                   IB_WC_RETRY_EXC_ERR },
3525                 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR },
3526                 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR },
3527                 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR}
3528         };
3529
3530         u32 cqe_status = hr_reg_read(cqe, CQE_STATUS);
3531         int i;
3532
3533         wc->status = IB_WC_GENERAL_ERR;
3534         for (i = 0; i < ARRAY_SIZE(map); i++)
3535                 if (cqe_status == map[i].cqe_status) {
3536                         wc->status = map[i].wc_status;
3537                         break;
3538                 }
3539
3540         if (likely(wc->status == IB_WC_SUCCESS ||
3541                    wc->status == IB_WC_WR_FLUSH_ERR))
3542                 return;
3543
3544         ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status);
3545         print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe,
3546                        cq->cqe_size, false);
3547
3548         /*
3549          * For hns ROCEE, GENERAL_ERR is an error type that is not defined in
3550          * the standard protocol, the driver must ignore it and needn't to set
3551          * the QP to an error state.
3552          */
3553         if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR)
3554                 return;
3555
3556         /*
3557          * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state gets
3558          * into errored mode. Hence, as a workaround to this hardware
3559          * limitation, driver needs to assist in flushing. But the flushing
3560          * operation uses mailbox to convey the QP state to the hardware and
3561          * which can sleep due to the mutex protection around the mailbox calls.
3562          * Hence, use the deferred flush for now. Once wc error detected, the
3563          * flushing operation is needed.
3564          */
3565         if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
3566                 init_flush_work(hr_dev, qp);
3567 }
3568
3569 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe,
3570                       struct hns_roce_qp **cur_qp)
3571 {
3572         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3573         struct hns_roce_qp *hr_qp = *cur_qp;
3574         u32 qpn;
3575
3576         qpn = hr_reg_read(cqe, CQE_LCL_QPN);
3577
3578         if (!hr_qp || qpn != hr_qp->qpn) {
3579                 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3580                 if (unlikely(!hr_qp)) {
3581                         ibdev_err(&hr_dev->ib_dev,
3582                                   "CQ %06lx with entry for unknown QPN %06x\n",
3583                                   hr_cq->cqn, qpn);
3584                         return -EINVAL;
3585                 }
3586                 *cur_qp = hr_qp;
3587         }
3588
3589         return 0;
3590 }
3591
3592 /*
3593  * mapped-value = 1 + real-value
3594  * The ib wc opcode's real value is start from 0, In order to distinguish
3595  * between initialized and uninitialized map values, we plus 1 to the actual
3596  * value when defining the mapping, so that the validity can be identified by
3597  * checking whether the mapped value is greater than 0.
3598  */
3599 #define HR_WC_OP_MAP(hr_key, ib_key) \
3600                 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key
3601
3602 static const u32 wc_send_op_map[] = {
3603         HR_WC_OP_MAP(SEND,                      SEND),
3604         HR_WC_OP_MAP(SEND_WITH_INV,             SEND),
3605         HR_WC_OP_MAP(SEND_WITH_IMM,             SEND),
3606         HR_WC_OP_MAP(RDMA_READ,                 RDMA_READ),
3607         HR_WC_OP_MAP(RDMA_WRITE,                RDMA_WRITE),
3608         HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM,       RDMA_WRITE),
3609         HR_WC_OP_MAP(LOCAL_INV,                 LOCAL_INV),
3610         HR_WC_OP_MAP(ATOM_CMP_AND_SWAP,         COMP_SWAP),
3611         HR_WC_OP_MAP(ATOM_FETCH_AND_ADD,        FETCH_ADD),
3612         HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP,     MASKED_COMP_SWAP),
3613         HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD,    MASKED_FETCH_ADD),
3614         HR_WC_OP_MAP(FAST_REG_PMR,              REG_MR),
3615         HR_WC_OP_MAP(BIND_MW,                   REG_MR),
3616 };
3617
3618 static int to_ib_wc_send_op(u32 hr_opcode)
3619 {
3620         if (hr_opcode >= ARRAY_SIZE(wc_send_op_map))
3621                 return -EINVAL;
3622
3623         return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 :
3624                                            -EINVAL;
3625 }
3626
3627 static const u32 wc_recv_op_map[] = {
3628         HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM,               WITH_IMM),
3629         HR_WC_OP_MAP(SEND,                              RECV),
3630         HR_WC_OP_MAP(SEND_WITH_IMM,                     WITH_IMM),
3631         HR_WC_OP_MAP(SEND_WITH_INV,                     RECV),
3632 };
3633
3634 static int to_ib_wc_recv_op(u32 hr_opcode)
3635 {
3636         if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map))
3637                 return -EINVAL;
3638
3639         return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 :
3640                                            -EINVAL;
3641 }
3642
3643 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3644 {
3645         u32 hr_opcode;
3646         int ib_opcode;
3647
3648         wc->wc_flags = 0;
3649
3650         hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3651         switch (hr_opcode) {
3652         case HNS_ROCE_V2_WQE_OP_RDMA_READ:
3653                 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3654                 break;
3655         case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
3656         case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
3657                 wc->wc_flags |= IB_WC_WITH_IMM;
3658                 break;
3659         case HNS_ROCE_V2_WQE_OP_LOCAL_INV:
3660                 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3661                 break;
3662         case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
3663         case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
3664         case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
3665         case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
3666                 wc->byte_len  = 8;
3667                 break;
3668         default:
3669                 break;
3670         }
3671
3672         ib_opcode = to_ib_wc_send_op(hr_opcode);
3673         if (ib_opcode < 0)
3674                 wc->status = IB_WC_GENERAL_ERR;
3675         else
3676                 wc->opcode = ib_opcode;
3677 }
3678
3679 static inline bool is_rq_inl_enabled(struct ib_wc *wc, u32 hr_opcode,
3680                                      struct hns_roce_v2_cqe *cqe)
3681 {
3682         return wc->qp->qp_type != IB_QPT_UD && wc->qp->qp_type != IB_QPT_GSI &&
3683                (hr_opcode == HNS_ROCE_V2_OPCODE_SEND ||
3684                 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
3685                 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
3686                hr_reg_read(cqe, CQE_RQ_INLINE);
3687 }
3688
3689 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3690 {
3691         struct hns_roce_qp *qp = to_hr_qp(wc->qp);
3692         u32 hr_opcode;
3693         int ib_opcode;
3694         int ret;
3695
3696         wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3697
3698         hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3699         switch (hr_opcode) {
3700         case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3701         case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3702                 wc->wc_flags = IB_WC_WITH_IMM;
3703                 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata));
3704                 break;
3705         case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3706                 wc->wc_flags = IB_WC_WITH_INVALIDATE;
3707                 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
3708                 break;
3709         default:
3710                 wc->wc_flags = 0;
3711         }
3712
3713         ib_opcode = to_ib_wc_recv_op(hr_opcode);
3714         if (ib_opcode < 0)
3715                 wc->status = IB_WC_GENERAL_ERR;
3716         else
3717                 wc->opcode = ib_opcode;
3718
3719         if (is_rq_inl_enabled(wc, hr_opcode, cqe)) {
3720                 ret = hns_roce_handle_recv_inl_wqe(cqe, qp, wc);
3721                 if (unlikely(ret))
3722                         return ret;
3723         }
3724
3725         wc->sl = hr_reg_read(cqe, CQE_SL);
3726         wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN);
3727         wc->slid = 0;
3728         wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0;
3729         wc->port_num = hr_reg_read(cqe, CQE_PORTN);
3730         wc->pkey_index = 0;
3731
3732         if (hr_reg_read(cqe, CQE_VID_VLD)) {
3733                 wc->vlan_id = hr_reg_read(cqe, CQE_VID);
3734                 wc->wc_flags |= IB_WC_WITH_VLAN;
3735         } else {
3736                 wc->vlan_id = 0xffff;
3737         }
3738
3739         wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE);
3740
3741         return 0;
3742 }
3743
3744 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
3745                                 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
3746 {
3747         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3748         struct hns_roce_qp *qp = *cur_qp;
3749         struct hns_roce_srq *srq = NULL;
3750         struct hns_roce_v2_cqe *cqe;
3751         struct hns_roce_wq *wq;
3752         int is_send;
3753         u16 wqe_idx;
3754         int ret;
3755
3756         cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
3757         if (!cqe)
3758                 return -EAGAIN;
3759
3760         ++hr_cq->cons_index;
3761         /* Memory barrier */
3762         rmb();
3763
3764         ret = get_cur_qp(hr_cq, cqe, &qp);
3765         if (ret)
3766                 return ret;
3767
3768         wc->qp = &qp->ibqp;
3769         wc->vendor_err = 0;
3770
3771         wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
3772
3773         is_send = !hr_reg_read(cqe, CQE_S_R);
3774         if (is_send) {
3775                 wq = &qp->sq;
3776
3777                 /* If sg_signal_bit is set, tail pointer will be updated to
3778                  * the WQE corresponding to the current CQE.
3779                  */
3780                 if (qp->sq_signal_bits)
3781                         wq->tail += (wqe_idx - (u16)wq->tail) &
3782                                     (wq->wqe_cnt - 1);
3783
3784                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3785                 ++wq->tail;
3786
3787                 fill_send_wc(wc, cqe);
3788         } else {
3789                 if (qp->ibqp.srq) {
3790                         srq = to_hr_srq(qp->ibqp.srq);
3791                         wc->wr_id = srq->wrid[wqe_idx];
3792                         hns_roce_free_srq_wqe(srq, wqe_idx);
3793                 } else {
3794                         wq = &qp->rq;
3795                         wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3796                         ++wq->tail;
3797                 }
3798
3799                 ret = fill_recv_wc(wc, cqe);
3800         }
3801
3802         get_cqe_status(hr_dev, qp, hr_cq, cqe, wc);
3803         if (unlikely(wc->status != IB_WC_SUCCESS))
3804                 return 0;
3805
3806         return ret;
3807 }
3808
3809 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3810                                struct ib_wc *wc)
3811 {
3812         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3813         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3814         struct hns_roce_qp *cur_qp = NULL;
3815         unsigned long flags;
3816         int npolled;
3817
3818         spin_lock_irqsave(&hr_cq->lock, flags);
3819
3820         /*
3821          * When the device starts to reset, the state is RST_DOWN. At this time,
3822          * there may still be some valid CQEs in the hardware that are not
3823          * polled. Therefore, it is not allowed to switch to the software mode
3824          * immediately. When the state changes to UNINIT, CQE no longer exists
3825          * in the hardware, and then switch to software mode.
3826          */
3827         if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
3828                 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
3829                 goto out;
3830         }
3831
3832         for (npolled = 0; npolled < num_entries; ++npolled) {
3833                 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
3834                         break;
3835         }
3836
3837         if (npolled)
3838                 update_cq_db(hr_dev, hr_cq);
3839
3840 out:
3841         spin_unlock_irqrestore(&hr_cq->lock, flags);
3842
3843         return npolled;
3844 }
3845
3846 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
3847                               int step_idx, u16 *mbox_op)
3848 {
3849         u16 op;
3850
3851         switch (type) {
3852         case HEM_TYPE_QPC:
3853                 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
3854                 break;
3855         case HEM_TYPE_MTPT:
3856                 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
3857                 break;
3858         case HEM_TYPE_CQC:
3859                 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
3860                 break;
3861         case HEM_TYPE_SRQC:
3862                 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
3863                 break;
3864         case HEM_TYPE_SCCC:
3865                 op = HNS_ROCE_CMD_WRITE_SCCC_BT0;
3866                 break;
3867         case HEM_TYPE_QPC_TIMER:
3868                 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
3869                 break;
3870         case HEM_TYPE_CQC_TIMER:
3871                 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
3872                 break;
3873         default:
3874                 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type);
3875                 return -EINVAL;
3876         }
3877
3878         *mbox_op = op + step_idx;
3879
3880         return 0;
3881 }
3882
3883 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,
3884                                dma_addr_t base_addr)
3885 {
3886         struct hns_roce_cmq_desc desc;
3887         struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
3888         u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz);
3889         u64 addr = to_hr_hw_page_addr(base_addr);
3890
3891         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
3892
3893         hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr));
3894         hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr));
3895         hr_reg_write(req, CFG_GMV_BT_IDX, idx);
3896
3897         return hns_roce_cmq_send(hr_dev, &desc, 1);
3898 }
3899
3900 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj,
3901                          dma_addr_t base_addr, u32 hem_type, int step_idx)
3902 {
3903         int ret;
3904         u16 op;
3905
3906         if (unlikely(hem_type == HEM_TYPE_GMV))
3907                 return config_gmv_ba_to_hw(hr_dev, obj, base_addr);
3908
3909         if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx))
3910                 return 0;
3911
3912         ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &op);
3913         if (ret < 0)
3914                 return ret;
3915
3916         return config_hem_ba_to_hw(hr_dev, obj, base_addr, op);
3917 }
3918
3919 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
3920                                struct hns_roce_hem_table *table, int obj,
3921                                int step_idx)
3922 {
3923         struct hns_roce_hem_iter iter;
3924         struct hns_roce_hem_mhop mhop;
3925         struct hns_roce_hem *hem;
3926         unsigned long mhop_obj = obj;
3927         int i, j, k;
3928         int ret = 0;
3929         u64 hem_idx = 0;
3930         u64 l1_idx = 0;
3931         u64 bt_ba = 0;
3932         u32 chunk_ba_num;
3933         u32 hop_num;
3934
3935         if (!hns_roce_check_whether_mhop(hr_dev, table->type))
3936                 return 0;
3937
3938         hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
3939         i = mhop.l0_idx;
3940         j = mhop.l1_idx;
3941         k = mhop.l2_idx;
3942         hop_num = mhop.hop_num;
3943         chunk_ba_num = mhop.bt_chunk_size / 8;
3944
3945         if (hop_num == 2) {
3946                 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
3947                           k;
3948                 l1_idx = i * chunk_ba_num + j;
3949         } else if (hop_num == 1) {
3950                 hem_idx = i * chunk_ba_num + j;
3951         } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
3952                 hem_idx = i;
3953         }
3954
3955         if (table->type == HEM_TYPE_SCCC)
3956                 obj = mhop.l0_idx;
3957
3958         if (check_whether_last_step(hop_num, step_idx)) {
3959                 hem = table->hem[hem_idx];
3960                 for (hns_roce_hem_first(hem, &iter);
3961                      !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
3962                         bt_ba = hns_roce_hem_addr(&iter);
3963                         ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type,
3964                                             step_idx);
3965                 }
3966         } else {
3967                 if (step_idx == 0)
3968                         bt_ba = table->bt_l0_dma_addr[i];
3969                 else if (step_idx == 1 && hop_num == 2)
3970                         bt_ba = table->bt_l1_dma_addr[l1_idx];
3971
3972                 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx);
3973         }
3974
3975         return ret;
3976 }
3977
3978 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
3979                                  struct hns_roce_hem_table *table, int obj,
3980                                  int step_idx)
3981 {
3982         struct device *dev = hr_dev->dev;
3983         struct hns_roce_cmd_mailbox *mailbox;
3984         int ret;
3985         u16 op = 0xff;
3986
3987         if (!hns_roce_check_whether_mhop(hr_dev, table->type))
3988                 return 0;
3989
3990         switch (table->type) {
3991         case HEM_TYPE_QPC:
3992                 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
3993                 break;
3994         case HEM_TYPE_MTPT:
3995                 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
3996                 break;
3997         case HEM_TYPE_CQC:
3998                 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
3999                 break;
4000         case HEM_TYPE_SRQC:
4001                 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
4002                 break;
4003         case HEM_TYPE_SCCC:
4004         case HEM_TYPE_QPC_TIMER:
4005         case HEM_TYPE_CQC_TIMER:
4006         case HEM_TYPE_GMV:
4007                 return 0;
4008         default:
4009                 dev_warn(dev, "table %u not to be destroyed by mailbox!\n",
4010                          table->type);
4011                 return 0;
4012         }
4013
4014         op += step_idx;
4015
4016         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4017         if (IS_ERR(mailbox))
4018                 return PTR_ERR(mailbox);
4019
4020         /* configure the tag and op */
4021         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
4022                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
4023
4024         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4025         return ret;
4026 }
4027
4028 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
4029                                  struct hns_roce_v2_qp_context *context,
4030                                  struct hns_roce_v2_qp_context *qpc_mask,
4031                                  struct hns_roce_qp *hr_qp)
4032 {
4033         struct hns_roce_cmd_mailbox *mailbox;
4034         int qpc_size;
4035         int ret;
4036
4037         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4038         if (IS_ERR(mailbox))
4039                 return PTR_ERR(mailbox);
4040
4041         /* The qpc size of HIP08 is only 256B, which is half of HIP09 */
4042         qpc_size = hr_dev->caps.qpc_sz;
4043         memcpy(mailbox->buf, context, qpc_size);
4044         memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
4045
4046         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
4047                                 HNS_ROCE_CMD_MODIFY_QPC,
4048                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
4049
4050         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4051
4052         return ret;
4053 }
4054
4055 static void set_access_flags(struct hns_roce_qp *hr_qp,
4056                              struct hns_roce_v2_qp_context *context,
4057                              struct hns_roce_v2_qp_context *qpc_mask,
4058                              const struct ib_qp_attr *attr, int attr_mask)
4059 {
4060         u8 dest_rd_atomic;
4061         u32 access_flags;
4062
4063         dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
4064                          attr->max_dest_rd_atomic : hr_qp->resp_depth;
4065
4066         access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
4067                        attr->qp_access_flags : hr_qp->atomic_rd_en;
4068
4069         if (!dest_rd_atomic)
4070                 access_flags &= IB_ACCESS_REMOTE_WRITE;
4071
4072         hr_reg_write_bool(context, QPC_RRE,
4073                           access_flags & IB_ACCESS_REMOTE_READ);
4074         hr_reg_clear(qpc_mask, QPC_RRE);
4075
4076         hr_reg_write_bool(context, QPC_RWE,
4077                           access_flags & IB_ACCESS_REMOTE_WRITE);
4078         hr_reg_clear(qpc_mask, QPC_RWE);
4079
4080         hr_reg_write_bool(context, QPC_ATE,
4081                           access_flags & IB_ACCESS_REMOTE_ATOMIC);
4082         hr_reg_clear(qpc_mask, QPC_ATE);
4083         hr_reg_write_bool(context, QPC_EXT_ATE,
4084                           access_flags & IB_ACCESS_REMOTE_ATOMIC);
4085         hr_reg_clear(qpc_mask, QPC_EXT_ATE);
4086 }
4087
4088 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
4089                             struct hns_roce_v2_qp_context *context,
4090                             struct hns_roce_v2_qp_context *qpc_mask)
4091 {
4092         hr_reg_write(context, QPC_SGE_SHIFT,
4093                      to_hr_hem_entries_shift(hr_qp->sge.sge_cnt,
4094                                              hr_qp->sge.sge_shift));
4095
4096         hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt));
4097
4098         hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt));
4099 }
4100
4101 static inline int get_cqn(struct ib_cq *ib_cq)
4102 {
4103         return ib_cq ? to_hr_cq(ib_cq)->cqn : 0;
4104 }
4105
4106 static inline int get_pdn(struct ib_pd *ib_pd)
4107 {
4108         return ib_pd ? to_hr_pd(ib_pd)->pdn : 0;
4109 }
4110
4111 static void modify_qp_reset_to_init(struct ib_qp *ibqp,
4112                                     const struct ib_qp_attr *attr,
4113                                     int attr_mask,
4114                                     struct hns_roce_v2_qp_context *context,
4115                                     struct hns_roce_v2_qp_context *qpc_mask)
4116 {
4117         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4118         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4119
4120         /*
4121          * In v2 engine, software pass context and context mask to hardware
4122          * when modifying qp. If software need modify some fields in context,
4123          * we should set all bits of the relevant fields in context mask to
4124          * 0 at the same time, else set them to 0x1.
4125          */
4126         hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4127
4128         hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4129
4130         hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs));
4131
4132         set_qpc_wqe_cnt(hr_qp, context, qpc_mask);
4133
4134         /* No VLAN need to set 0xFFF */
4135         hr_reg_write(context, QPC_VLAN_ID, 0xfff);
4136
4137         if (ibqp->qp_type == IB_QPT_XRC_TGT) {
4138                 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn);
4139
4140                 hr_reg_enable(context, QPC_XRC_QP_TYPE);
4141         }
4142
4143         if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
4144                 hr_reg_enable(context, QPC_RQ_RECORD_EN);
4145
4146         hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L,
4147                      lower_32_bits(hr_qp->rdb.dma) >> 1);
4148         hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H,
4149                      upper_32_bits(hr_qp->rdb.dma));
4150
4151         if (ibqp->qp_type != IB_QPT_UD && ibqp->qp_type != IB_QPT_GSI)
4152                 hr_reg_write_bool(context, QPC_RQIE,
4153                              hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE);
4154
4155         hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4156
4157         if (ibqp->srq) {
4158                 hr_reg_enable(context, QPC_SRQ_EN);
4159                 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4160         }
4161
4162         hr_reg_enable(context, QPC_FRE);
4163
4164         hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4165
4166         if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ)
4167                 return;
4168
4169         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
4170                 hr_reg_enable(&context->ext, QPCEX_STASH);
4171 }
4172
4173 static void modify_qp_init_to_init(struct ib_qp *ibqp,
4174                                    const struct ib_qp_attr *attr, int attr_mask,
4175                                    struct hns_roce_v2_qp_context *context,
4176                                    struct hns_roce_v2_qp_context *qpc_mask)
4177 {
4178         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4179
4180         /*
4181          * In v2 engine, software pass context and context mask to hardware
4182          * when modifying qp. If software need modify some fields in context,
4183          * we should set all bits of the relevant fields in context mask to
4184          * 0 at the same time, else set them to 0x1.
4185          */
4186         hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4187         hr_reg_clear(qpc_mask, QPC_TST);
4188
4189         hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4190         hr_reg_clear(qpc_mask, QPC_PD);
4191
4192         hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4193         hr_reg_clear(qpc_mask, QPC_RX_CQN);
4194
4195         hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4196         hr_reg_clear(qpc_mask, QPC_TX_CQN);
4197
4198         if (ibqp->srq) {
4199                 hr_reg_enable(context, QPC_SRQ_EN);
4200                 hr_reg_clear(qpc_mask, QPC_SRQ_EN);
4201                 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4202                 hr_reg_clear(qpc_mask, QPC_SRQN);
4203         }
4204
4205         if (attr_mask & IB_QP_DEST_QPN) {
4206                 hr_reg_write(context, QPC_DQPN, hr_qp->qpn);
4207                 hr_reg_clear(qpc_mask, QPC_DQPN);
4208         }
4209 }
4210
4211 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev,
4212                             struct hns_roce_qp *hr_qp,
4213                             struct hns_roce_v2_qp_context *context,
4214                             struct hns_roce_v2_qp_context *qpc_mask)
4215 {
4216         u64 mtts[MTT_MIN_COUNT] = { 0 };
4217         u64 wqe_sge_ba;
4218         int count;
4219
4220         /* Search qp buf's mtts */
4221         count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts,
4222                                   MTT_MIN_COUNT, &wqe_sge_ba);
4223         if (hr_qp->rq.wqe_cnt && count < 1) {
4224                 ibdev_err(&hr_dev->ib_dev,
4225                           "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn);
4226                 return -EINVAL;
4227         }
4228
4229         context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
4230         qpc_mask->wqe_sge_ba = 0;
4231
4232         /*
4233          * In v2 engine, software pass context and context mask to hardware
4234          * when modifying qp. If software need modify some fields in context,
4235          * we should set all bits of the relevant fields in context mask to
4236          * 0 at the same time, else set them to 0x1.
4237          */
4238         hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3));
4239         hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H);
4240
4241         hr_reg_write(context, QPC_SQ_HOP_NUM,
4242                      to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num,
4243                                       hr_qp->sq.wqe_cnt));
4244         hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM);
4245
4246         hr_reg_write(context, QPC_SGE_HOP_NUM,
4247                      to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num,
4248                                       hr_qp->sge.sge_cnt));
4249         hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM);
4250
4251         hr_reg_write(context, QPC_RQ_HOP_NUM,
4252                      to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num,
4253                                       hr_qp->rq.wqe_cnt));
4254
4255         hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM);
4256
4257         hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ,
4258                      to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
4259         hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ);
4260
4261         hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ,
4262                      to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
4263         hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ);
4264
4265         context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
4266         qpc_mask->rq_cur_blk_addr = 0;
4267
4268         hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H,
4269                      upper_32_bits(to_hr_hw_page_addr(mtts[0])));
4270         hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H);
4271
4272         context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
4273         qpc_mask->rq_nxt_blk_addr = 0;
4274
4275         hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H,
4276                      upper_32_bits(to_hr_hw_page_addr(mtts[1])));
4277         hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H);
4278
4279         return 0;
4280 }
4281
4282 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev,
4283                             struct hns_roce_qp *hr_qp,
4284                             struct hns_roce_v2_qp_context *context,
4285                             struct hns_roce_v2_qp_context *qpc_mask)
4286 {
4287         struct ib_device *ibdev = &hr_dev->ib_dev;
4288         u64 sge_cur_blk = 0;
4289         u64 sq_cur_blk = 0;
4290         int count;
4291
4292         /* search qp buf's mtts */
4293         count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL);
4294         if (count < 1) {
4295                 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n",
4296                           hr_qp->qpn);
4297                 return -EINVAL;
4298         }
4299         if (hr_qp->sge.sge_cnt > 0) {
4300                 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
4301                                           hr_qp->sge.offset,
4302                                           &sge_cur_blk, 1, NULL);
4303                 if (count < 1) {
4304                         ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n",
4305                                   hr_qp->qpn);
4306                         return -EINVAL;
4307                 }
4308         }
4309
4310         /*
4311          * In v2 engine, software pass context and context mask to hardware
4312          * when modifying qp. If software need modify some fields in context,
4313          * we should set all bits of the relevant fields in context mask to
4314          * 0 at the same time, else set them to 0x1.
4315          */
4316         hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L,
4317                      lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4318         hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H,
4319                      upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4320         hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L);
4321         hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H);
4322
4323         hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L,
4324                      lower_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4325         hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H,
4326                      upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4327         hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L);
4328         hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H);
4329
4330         hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L,
4331                      lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4332         hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H,
4333                      upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4334         hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L);
4335         hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H);
4336
4337         return 0;
4338 }
4339
4340 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp,
4341                                   const struct ib_qp_attr *attr)
4342 {
4343         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
4344                 return IB_MTU_4096;
4345
4346         return attr->path_mtu;
4347 }
4348
4349 static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
4350                                  const struct ib_qp_attr *attr, int attr_mask,
4351                                  struct hns_roce_v2_qp_context *context,
4352                                  struct hns_roce_v2_qp_context *qpc_mask)
4353 {
4354         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4355         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4356         struct ib_device *ibdev = &hr_dev->ib_dev;
4357         dma_addr_t trrl_ba;
4358         dma_addr_t irrl_ba;
4359         enum ib_mtu ib_mtu;
4360         u8 lp_pktn_ini;
4361         u64 *mtts;
4362         u8 *dmac;
4363         u8 *smac;
4364         u32 port;
4365         int mtu;
4366         int ret;
4367
4368         ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask);
4369         if (ret) {
4370                 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret);
4371                 return ret;
4372         }
4373
4374         /* Search IRRL's mtts */
4375         mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
4376                                    hr_qp->qpn, &irrl_ba);
4377         if (!mtts) {
4378                 ibdev_err(ibdev, "failed to find qp irrl_table.\n");
4379                 return -EINVAL;
4380         }
4381
4382         /* Search TRRL's mtts */
4383         mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
4384                                    hr_qp->qpn, &trrl_ba);
4385         if (!mtts) {
4386                 ibdev_err(ibdev, "failed to find qp trrl_table.\n");
4387                 return -EINVAL;
4388         }
4389
4390         if (attr_mask & IB_QP_ALT_PATH) {
4391                 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n",
4392                           attr_mask);
4393                 return -EINVAL;
4394         }
4395
4396         hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4);
4397         hr_reg_clear(qpc_mask, QPC_TRRL_BA_L);
4398         context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4));
4399         qpc_mask->trrl_ba = 0;
4400         hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4));
4401         hr_reg_clear(qpc_mask, QPC_TRRL_BA_H);
4402
4403         context->irrl_ba = cpu_to_le32(irrl_ba >> 6);
4404         qpc_mask->irrl_ba = 0;
4405         hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6));
4406         hr_reg_clear(qpc_mask, QPC_IRRL_BA_H);
4407
4408         hr_reg_enable(context, QPC_RMT_E2E);
4409         hr_reg_clear(qpc_mask, QPC_RMT_E2E);
4410
4411         hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits);
4412         hr_reg_clear(qpc_mask, QPC_SIG_TYPE);
4413
4414         port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
4415
4416         smac = (u8 *)hr_dev->dev_addr[port];
4417         dmac = (u8 *)attr->ah_attr.roce.dmac;
4418         /* when dmac equals smac or loop_idc is 1, it should loopback */
4419         if (ether_addr_equal_unaligned(dmac, smac) ||
4420             hr_dev->loop_idc == 0x1) {
4421                 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc);
4422                 hr_reg_clear(qpc_mask, QPC_LBI);
4423         }
4424
4425         if (attr_mask & IB_QP_DEST_QPN) {
4426                 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num);
4427                 hr_reg_clear(qpc_mask, QPC_DQPN);
4428         }
4429
4430         memcpy(&(context->dmac), dmac, sizeof(u32));
4431         hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4])));
4432         qpc_mask->dmac = 0;
4433         hr_reg_clear(qpc_mask, QPC_DMAC_H);
4434
4435         ib_mtu = get_mtu(ibqp, attr);
4436         hr_qp->path_mtu = ib_mtu;
4437
4438         mtu = ib_mtu_enum_to_int(ib_mtu);
4439         if (WARN_ON(mtu < 0))
4440                 return -EINVAL;
4441
4442         if (attr_mask & IB_QP_PATH_MTU) {
4443                 hr_reg_write(context, QPC_MTU, ib_mtu);
4444                 hr_reg_clear(qpc_mask, QPC_MTU);
4445         }
4446
4447 #define MAX_LP_MSG_LEN 65536
4448         /* MTU * (2 ^ LP_PKTN_INI) shouldn't be bigger than 64KB */
4449         lp_pktn_ini = ilog2(MAX_LP_MSG_LEN / mtu);
4450
4451         hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini);
4452         hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI);
4453
4454         /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */
4455         hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini);
4456         hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ);
4457
4458         hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR);
4459         hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN);
4460         hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE);
4461
4462         context->rq_rnr_timer = 0;
4463         qpc_mask->rq_rnr_timer = 0;
4464
4465         hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX);
4466         hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX);
4467
4468         /* rocee send 2^lp_sgen_ini segs every time */
4469         hr_reg_write(context, QPC_LP_SGEN_INI, 3);
4470         hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI);
4471
4472         return 0;
4473 }
4474
4475 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
4476                                 const struct ib_qp_attr *attr, int attr_mask,
4477                                 struct hns_roce_v2_qp_context *context,
4478                                 struct hns_roce_v2_qp_context *qpc_mask)
4479 {
4480         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4481         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4482         struct ib_device *ibdev = &hr_dev->ib_dev;
4483         int ret;
4484
4485         /* Not support alternate path and path migration */
4486         if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
4487                 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
4488                 return -EINVAL;
4489         }
4490
4491         ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask);
4492         if (ret) {
4493                 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret);
4494                 return ret;
4495         }
4496
4497         /*
4498          * Set some fields in context to zero, Because the default values
4499          * of all fields in context are zero, we need not set them to 0 again.
4500          * but we should set the relevant fields of context mask to 0.
4501          */
4502         hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX);
4503
4504         hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN);
4505
4506         hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE);
4507         hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD);
4508         hr_reg_clear(qpc_mask, QPC_IRRL_PSN);
4509
4510         hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL);
4511
4512         hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN);
4513
4514         hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG);
4515
4516         hr_reg_clear(qpc_mask, QPC_CHECK_FLG);
4517
4518         hr_reg_write(context, QPC_LSN, 0x100);
4519         hr_reg_clear(qpc_mask, QPC_LSN);
4520
4521         hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD);
4522
4523         return 0;
4524 }
4525
4526 static inline u16 get_udp_sport(u32 fl, u32 lqpn, u32 rqpn)
4527 {
4528         if (!fl)
4529                 fl = rdma_calc_flow_label(lqpn, rqpn);
4530
4531         return rdma_flow_label_to_udp_sport(fl);
4532 }
4533
4534 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4535                            u32 *dip_idx)
4536 {
4537         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4538         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4539         struct hns_roce_dip *hr_dip;
4540         unsigned long flags;
4541         int ret = 0;
4542
4543         spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
4544
4545         list_for_each_entry(hr_dip, &hr_dev->dip_list, node) {
4546                 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16))
4547                         goto out;
4548         }
4549
4550         /* If no dgid is found, a new dip and a mapping between dgid and
4551          * dip_idx will be created.
4552          */
4553         hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC);
4554         if (!hr_dip) {
4555                 ret = -ENOMEM;
4556                 goto out;
4557         }
4558
4559         memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4560         hr_dip->dip_idx = *dip_idx = ibqp->qp_num;
4561         list_add_tail(&hr_dip->node, &hr_dev->dip_list);
4562
4563 out:
4564         spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
4565         return ret;
4566 }
4567
4568 enum {
4569         CONG_DCQCN,
4570         CONG_WINDOW,
4571 };
4572
4573 enum {
4574         UNSUPPORT_CONG_LEVEL,
4575         SUPPORT_CONG_LEVEL,
4576 };
4577
4578 enum {
4579         CONG_LDCP,
4580         CONG_HC3,
4581 };
4582
4583 enum {
4584         DIP_INVALID,
4585         DIP_VALID,
4586 };
4587
4588 static int check_cong_type(struct ib_qp *ibqp,
4589                            struct hns_roce_congestion_algorithm *cong_alg)
4590 {
4591         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4592
4593         /* different congestion types match different configurations */
4594         switch (hr_dev->caps.cong_type) {
4595         case CONG_TYPE_DCQCN:
4596                 cong_alg->alg_sel = CONG_DCQCN;
4597                 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4598                 cong_alg->dip_vld = DIP_INVALID;
4599                 break;
4600         case CONG_TYPE_LDCP:
4601                 cong_alg->alg_sel = CONG_WINDOW;
4602                 cong_alg->alg_sub_sel = CONG_LDCP;
4603                 cong_alg->dip_vld = DIP_INVALID;
4604                 break;
4605         case CONG_TYPE_HC3:
4606                 cong_alg->alg_sel = CONG_WINDOW;
4607                 cong_alg->alg_sub_sel = CONG_HC3;
4608                 cong_alg->dip_vld = DIP_INVALID;
4609                 break;
4610         case CONG_TYPE_DIP:
4611                 cong_alg->alg_sel = CONG_DCQCN;
4612                 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4613                 cong_alg->dip_vld = DIP_VALID;
4614                 break;
4615         default:
4616                 ibdev_err(&hr_dev->ib_dev,
4617                           "error type(%u) for congestion selection.\n",
4618                           hr_dev->caps.cong_type);
4619                 return -EINVAL;
4620         }
4621
4622         return 0;
4623 }
4624
4625 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4626                            struct hns_roce_v2_qp_context *context,
4627                            struct hns_roce_v2_qp_context *qpc_mask)
4628 {
4629         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4630         struct hns_roce_congestion_algorithm cong_field;
4631         struct ib_device *ibdev = ibqp->device;
4632         struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
4633         u32 dip_idx = 0;
4634         int ret;
4635
4636         if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ||
4637             grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE)
4638                 return 0;
4639
4640         ret = check_cong_type(ibqp, &cong_field);
4641         if (ret)
4642                 return ret;
4643
4644         hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id +
4645                      hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE);
4646         hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID);
4647         hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel);
4648         hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL);
4649         hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL,
4650                      cong_field.alg_sub_sel);
4651         hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL);
4652         hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld);
4653         hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD);
4654
4655         /* if dip is disabled, there is no need to set dip idx */
4656         if (cong_field.dip_vld == 0)
4657                 return 0;
4658
4659         ret = get_dip_ctx_idx(ibqp, attr, &dip_idx);
4660         if (ret) {
4661                 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret);
4662                 return ret;
4663         }
4664
4665         hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx);
4666         hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0);
4667
4668         return 0;
4669 }
4670
4671 static int hns_roce_v2_set_path(struct ib_qp *ibqp,
4672                                 const struct ib_qp_attr *attr,
4673                                 int attr_mask,
4674                                 struct hns_roce_v2_qp_context *context,
4675                                 struct hns_roce_v2_qp_context *qpc_mask)
4676 {
4677         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4678         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4679         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4680         struct ib_device *ibdev = &hr_dev->ib_dev;
4681         const struct ib_gid_attr *gid_attr = NULL;
4682         int is_roce_protocol;
4683         u16 vlan_id = 0xffff;
4684         bool is_udp = false;
4685         u8 ib_port;
4686         u8 hr_port;
4687         int ret;
4688
4689         ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4690         hr_port = ib_port - 1;
4691         is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4692                            rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4693
4694         if (is_roce_protocol) {
4695                 gid_attr = attr->ah_attr.grh.sgid_attr;
4696                 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
4697                 if (ret)
4698                         return ret;
4699
4700                 if (gid_attr)
4701                         is_udp = (gid_attr->gid_type ==
4702                                  IB_GID_TYPE_ROCE_UDP_ENCAP);
4703         }
4704
4705         /* Only HIP08 needs to set the vlan_en bits in QPC */
4706         if (vlan_id < VLAN_N_VID &&
4707             hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
4708                 hr_reg_enable(qpc_mask, QPC_RQ_VLAN_EN);
4709                 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN);
4710                 hr_reg_enable(qpc_mask, QPC_SQ_VLAN_EN);
4711                 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN);
4712         }
4713
4714         hr_reg_write(context, QPC_VLAN_ID, vlan_id);
4715         hr_reg_clear(qpc_mask, QPC_VLAN_ID);
4716
4717         if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
4718                 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
4719                           grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
4720                 return -EINVAL;
4721         }
4722
4723         if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
4724                 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
4725                 return -EINVAL;
4726         }
4727
4728         hr_reg_write(context, QPC_UDPSPN,
4729                      is_udp ? get_udp_sport(grh->flow_label, ibqp->qp_num,
4730                                             attr->dest_qp_num) : 0);
4731
4732         hr_reg_clear(qpc_mask, QPC_UDPSPN);
4733
4734         hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index);
4735
4736         hr_reg_clear(qpc_mask, QPC_GMV_IDX);
4737
4738         hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit);
4739         hr_reg_clear(qpc_mask, QPC_HOPLIMIT);
4740
4741         ret = fill_cong_field(ibqp, attr, context, qpc_mask);
4742         if (ret)
4743                 return ret;
4744
4745         hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh));
4746         hr_reg_clear(qpc_mask, QPC_TC);
4747
4748         hr_reg_write(context, QPC_FL, grh->flow_label);
4749         hr_reg_clear(qpc_mask, QPC_FL);
4750         memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4751         memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4752
4753         hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
4754         if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) {
4755                 ibdev_err(ibdev,
4756                           "failed to fill QPC, sl (%d) shouldn't be larger than %d.\n",
4757                           hr_qp->sl, MAX_SERVICE_LEVEL);
4758                 return -EINVAL;
4759         }
4760
4761         hr_reg_write(context, QPC_SL, hr_qp->sl);
4762         hr_reg_clear(qpc_mask, QPC_SL);
4763
4764         return 0;
4765 }
4766
4767 static bool check_qp_state(enum ib_qp_state cur_state,
4768                            enum ib_qp_state new_state)
4769 {
4770         static const bool sm[][IB_QPS_ERR + 1] = {
4771                 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
4772                                    [IB_QPS_INIT] = true },
4773                 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
4774                                   [IB_QPS_INIT] = true,
4775                                   [IB_QPS_RTR] = true,
4776                                   [IB_QPS_ERR] = true },
4777                 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
4778                                  [IB_QPS_RTS] = true,
4779                                  [IB_QPS_ERR] = true },
4780                 [IB_QPS_RTS] = { [IB_QPS_RESET] = true,
4781                                  [IB_QPS_RTS] = true,
4782                                  [IB_QPS_ERR] = true },
4783                 [IB_QPS_SQD] = {},
4784                 [IB_QPS_SQE] = {},
4785                 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }
4786         };
4787
4788         return sm[cur_state][new_state];
4789 }
4790
4791 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
4792                                       const struct ib_qp_attr *attr,
4793                                       int attr_mask,
4794                                       enum ib_qp_state cur_state,
4795                                       enum ib_qp_state new_state,
4796                                       struct hns_roce_v2_qp_context *context,
4797                                       struct hns_roce_v2_qp_context *qpc_mask)
4798 {
4799         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4800         int ret = 0;
4801
4802         if (!check_qp_state(cur_state, new_state)) {
4803                 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n");
4804                 return -EINVAL;
4805         }
4806
4807         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4808                 memset(qpc_mask, 0, hr_dev->caps.qpc_sz);
4809                 modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
4810                                         qpc_mask);
4811         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4812                 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
4813                                        qpc_mask);
4814         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4815                 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
4816                                             qpc_mask);
4817         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4818                 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
4819                                            qpc_mask);
4820         }
4821
4822         return ret;
4823 }
4824
4825 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
4826                                       const struct ib_qp_attr *attr,
4827                                       int attr_mask,
4828                                       struct hns_roce_v2_qp_context *context,
4829                                       struct hns_roce_v2_qp_context *qpc_mask)
4830 {
4831         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4832         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4833         int ret = 0;
4834
4835         if (attr_mask & IB_QP_AV) {
4836                 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
4837                                            qpc_mask);
4838                 if (ret)
4839                         return ret;
4840         }
4841
4842         if (attr_mask & IB_QP_TIMEOUT) {
4843                 if (attr->timeout < 31) {
4844                         hr_reg_write(context, QPC_AT, attr->timeout);
4845                         hr_reg_clear(qpc_mask, QPC_AT);
4846                 } else {
4847                         ibdev_warn(&hr_dev->ib_dev,
4848                                    "Local ACK timeout shall be 0 to 30.\n");
4849                 }
4850         }
4851
4852         if (attr_mask & IB_QP_RETRY_CNT) {
4853                 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt);
4854                 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT);
4855
4856                 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt);
4857                 hr_reg_clear(qpc_mask, QPC_RETRY_CNT);
4858         }
4859
4860         if (attr_mask & IB_QP_RNR_RETRY) {
4861                 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry);
4862                 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT);
4863
4864                 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry);
4865                 hr_reg_clear(qpc_mask, QPC_RNR_CNT);
4866         }
4867
4868         if (attr_mask & IB_QP_SQ_PSN) {
4869                 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn);
4870                 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN);
4871
4872                 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn);
4873                 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN);
4874
4875                 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn);
4876                 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L);
4877
4878                 hr_reg_write(context, QPC_RETRY_MSG_PSN_H,
4879                              attr->sq_psn >> RETRY_MSG_PSN_SHIFT);
4880                 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H);
4881
4882                 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn);
4883                 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN);
4884
4885                 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn);
4886                 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN);
4887         }
4888
4889         if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
4890              attr->max_dest_rd_atomic) {
4891                 hr_reg_write(context, QPC_RR_MAX,
4892                              fls(attr->max_dest_rd_atomic - 1));
4893                 hr_reg_clear(qpc_mask, QPC_RR_MAX);
4894         }
4895
4896         if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
4897                 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1));
4898                 hr_reg_clear(qpc_mask, QPC_SR_MAX);
4899         }
4900
4901         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
4902                 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
4903
4904         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
4905                 hr_reg_write(context, QPC_MIN_RNR_TIME, attr->min_rnr_timer);
4906                 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME);
4907         }
4908
4909         if (attr_mask & IB_QP_RQ_PSN) {
4910                 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn);
4911                 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN);
4912
4913                 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1);
4914                 hr_reg_clear(qpc_mask, QPC_RAQ_PSN);
4915         }
4916
4917         if (attr_mask & IB_QP_QKEY) {
4918                 context->qkey_xrcd = cpu_to_le32(attr->qkey);
4919                 qpc_mask->qkey_xrcd = 0;
4920                 hr_qp->qkey = attr->qkey;
4921         }
4922
4923         return ret;
4924 }
4925
4926 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
4927                                           const struct ib_qp_attr *attr,
4928                                           int attr_mask)
4929 {
4930         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4931         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4932
4933         if (attr_mask & IB_QP_ACCESS_FLAGS)
4934                 hr_qp->atomic_rd_en = attr->qp_access_flags;
4935
4936         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
4937                 hr_qp->resp_depth = attr->max_dest_rd_atomic;
4938         if (attr_mask & IB_QP_PORT) {
4939                 hr_qp->port = attr->port_num - 1;
4940                 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
4941         }
4942 }
4943
4944 static void clear_qp(struct hns_roce_qp *hr_qp)
4945 {
4946         struct ib_qp *ibqp = &hr_qp->ibqp;
4947
4948         if (ibqp->send_cq)
4949                 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
4950                                      hr_qp->qpn, NULL);
4951
4952         if (ibqp->recv_cq  && ibqp->recv_cq != ibqp->send_cq)
4953                 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq),
4954                                      hr_qp->qpn, ibqp->srq ?
4955                                      to_hr_srq(ibqp->srq) : NULL);
4956
4957         if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
4958                 *hr_qp->rdb.db_record = 0;
4959
4960         hr_qp->rq.head = 0;
4961         hr_qp->rq.tail = 0;
4962         hr_qp->sq.head = 0;
4963         hr_qp->sq.tail = 0;
4964         hr_qp->next_sge = 0;
4965 }
4966
4967 static void v2_set_flushed_fields(struct ib_qp *ibqp,
4968                                   struct hns_roce_v2_qp_context *context,
4969                                   struct hns_roce_v2_qp_context *qpc_mask)
4970 {
4971         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4972         unsigned long sq_flag = 0;
4973         unsigned long rq_flag = 0;
4974
4975         if (ibqp->qp_type == IB_QPT_XRC_TGT)
4976                 return;
4977
4978         spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
4979         hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head);
4980         hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX);
4981         hr_qp->state = IB_QPS_ERR;
4982         spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
4983
4984         if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */
4985                 return;
4986
4987         spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
4988         hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head);
4989         hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX);
4990         spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
4991 }
4992
4993 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
4994                                  const struct ib_qp_attr *attr,
4995                                  int attr_mask, enum ib_qp_state cur_state,
4996                                  enum ib_qp_state new_state)
4997 {
4998         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4999         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5000         struct hns_roce_v2_qp_context ctx[2];
5001         struct hns_roce_v2_qp_context *context = ctx;
5002         struct hns_roce_v2_qp_context *qpc_mask = ctx + 1;
5003         struct ib_device *ibdev = &hr_dev->ib_dev;
5004         int ret;
5005
5006         if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
5007                 return -EOPNOTSUPP;
5008
5009         /*
5010          * In v2 engine, software pass context and context mask to hardware
5011          * when modifying qp. If software need modify some fields in context,
5012          * we should set all bits of the relevant fields in context mask to
5013          * 0 at the same time, else set them to 0x1.
5014          */
5015         memset(context, 0, hr_dev->caps.qpc_sz);
5016         memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz);
5017
5018         ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
5019                                          new_state, context, qpc_mask);
5020         if (ret)
5021                 goto out;
5022
5023         /* When QP state is err, SQ and RQ WQE should be flushed */
5024         if (new_state == IB_QPS_ERR)
5025                 v2_set_flushed_fields(ibqp, context, qpc_mask);
5026
5027         /* Configure the optional fields */
5028         ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
5029                                          qpc_mask);
5030         if (ret)
5031                 goto out;
5032
5033         hr_reg_write_bool(context, QPC_INV_CREDIT,
5034                           to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC ||
5035                           ibqp->srq);
5036         hr_reg_clear(qpc_mask, QPC_INV_CREDIT);
5037
5038         /* Every status migrate must change state */
5039         hr_reg_write(context, QPC_QP_ST, new_state);
5040         hr_reg_clear(qpc_mask, QPC_QP_ST);
5041
5042         /* SW pass context to HW */
5043         ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp);
5044         if (ret) {
5045                 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret);
5046                 goto out;
5047         }
5048
5049         hr_qp->state = new_state;
5050
5051         hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
5052
5053         if (new_state == IB_QPS_RESET && !ibqp->uobject)
5054                 clear_qp(hr_qp);
5055
5056 out:
5057         return ret;
5058 }
5059
5060 static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
5061 {
5062         static const enum ib_qp_state map[] = {
5063                 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
5064                 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
5065                 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
5066                 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
5067                 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
5068                 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
5069                 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
5070                 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
5071         };
5072
5073         return (state < ARRAY_SIZE(map)) ? map[state] : -1;
5074 }
5075
5076 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
5077                                  struct hns_roce_qp *hr_qp,
5078                                  struct hns_roce_v2_qp_context *hr_context)
5079 {
5080         struct hns_roce_cmd_mailbox *mailbox;
5081         int ret;
5082
5083         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5084         if (IS_ERR(mailbox))
5085                 return PTR_ERR(mailbox);
5086
5087         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
5088                                 HNS_ROCE_CMD_QUERY_QPC,
5089                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
5090         if (ret)
5091                 goto out;
5092
5093         memcpy(hr_context, mailbox->buf, hr_dev->caps.qpc_sz);
5094
5095 out:
5096         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5097         return ret;
5098 }
5099
5100 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5101                                 int qp_attr_mask,
5102                                 struct ib_qp_init_attr *qp_init_attr)
5103 {
5104         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5105         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5106         struct hns_roce_v2_qp_context context = {};
5107         struct ib_device *ibdev = &hr_dev->ib_dev;
5108         int tmp_qp_state;
5109         int state;
5110         int ret;
5111
5112         memset(qp_attr, 0, sizeof(*qp_attr));
5113         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5114
5115         mutex_lock(&hr_qp->mutex);
5116
5117         if (hr_qp->state == IB_QPS_RESET) {
5118                 qp_attr->qp_state = IB_QPS_RESET;
5119                 ret = 0;
5120                 goto done;
5121         }
5122
5123         ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context);
5124         if (ret) {
5125                 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret);
5126                 ret = -EINVAL;
5127                 goto out;
5128         }
5129
5130         state = hr_reg_read(&context, QPC_QP_ST);
5131         tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
5132         if (tmp_qp_state == -1) {
5133                 ibdev_err(ibdev, "Illegal ib_qp_state\n");
5134                 ret = -EINVAL;
5135                 goto out;
5136         }
5137         hr_qp->state = (u8)tmp_qp_state;
5138         qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
5139         qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU);
5140         qp_attr->path_mig_state = IB_MIG_ARMED;
5141         qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
5142         if (hr_qp->ibqp.qp_type == IB_QPT_UD)
5143                 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd);
5144
5145         qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN);
5146         qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN);
5147         qp_attr->dest_qp_num = (u8)hr_reg_read(&context, QPC_DQPN);
5148         qp_attr->qp_access_flags =
5149                 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) |
5150                 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) |
5151                 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S);
5152
5153         if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
5154             hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5155             hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) {
5156                 struct ib_global_route *grh =
5157                         rdma_ah_retrieve_grh(&qp_attr->ah_attr);
5158
5159                 rdma_ah_set_sl(&qp_attr->ah_attr,
5160                                hr_reg_read(&context, QPC_SL));
5161                 grh->flow_label = hr_reg_read(&context, QPC_FL);
5162                 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX);
5163                 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT);
5164                 grh->traffic_class = hr_reg_read(&context, QPC_TC);
5165
5166                 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
5167         }
5168
5169         qp_attr->port_num = hr_qp->port + 1;
5170         qp_attr->sq_draining = 0;
5171         qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX);
5172         qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX);
5173
5174         qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME);
5175         qp_attr->timeout = (u8)hr_reg_read(&context, QPC_AT);
5176         qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT);
5177         qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT);
5178
5179 done:
5180         qp_attr->cur_qp_state = qp_attr->qp_state;
5181         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
5182         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
5183         qp_attr->cap.max_inline_data = hr_qp->max_inline_data;
5184
5185         if (!ibqp->uobject) {
5186                 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
5187                 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
5188         } else {
5189                 qp_attr->cap.max_send_wr = 0;
5190                 qp_attr->cap.max_send_sge = 0;
5191         }
5192
5193         qp_init_attr->cap = qp_attr->cap;
5194         qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits;
5195
5196 out:
5197         mutex_unlock(&hr_qp->mutex);
5198         return ret;
5199 }
5200
5201 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp)
5202 {
5203         return ((hr_qp->ibqp.qp_type == IB_QPT_RC ||
5204                  hr_qp->ibqp.qp_type == IB_QPT_UD ||
5205                  hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5206                  hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
5207                 hr_qp->state != IB_QPS_RESET);
5208 }
5209
5210 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
5211                                          struct hns_roce_qp *hr_qp,
5212                                          struct ib_udata *udata)
5213 {
5214         struct ib_device *ibdev = &hr_dev->ib_dev;
5215         struct hns_roce_cq *send_cq, *recv_cq;
5216         unsigned long flags;
5217         int ret = 0;
5218
5219         if (modify_qp_is_ok(hr_qp)) {
5220                 /* Modify qp to reset before destroying qp */
5221                 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
5222                                             hr_qp->state, IB_QPS_RESET);
5223                 if (ret)
5224                         ibdev_err(ibdev,
5225                                   "failed to modify QP to RST, ret = %d.\n",
5226                                   ret);
5227         }
5228
5229         send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
5230         recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
5231
5232         spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
5233         hns_roce_lock_cqs(send_cq, recv_cq);
5234
5235         if (!udata) {
5236                 if (recv_cq)
5237                         __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
5238                                                (hr_qp->ibqp.srq ?
5239                                                 to_hr_srq(hr_qp->ibqp.srq) :
5240                                                 NULL));
5241
5242                 if (send_cq && send_cq != recv_cq)
5243                         __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
5244
5245         }
5246
5247         hns_roce_qp_remove(hr_dev, hr_qp);
5248
5249         hns_roce_unlock_cqs(send_cq, recv_cq);
5250         spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
5251
5252         return ret;
5253 }
5254
5255 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
5256 {
5257         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5258         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5259         int ret;
5260
5261         ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
5262         if (ret)
5263                 ibdev_err(&hr_dev->ib_dev,
5264                           "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n",
5265                           hr_qp->qpn, ret);
5266
5267         hns_roce_qp_destroy(hr_dev, hr_qp, udata);
5268
5269         return 0;
5270 }
5271
5272 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
5273                                             struct hns_roce_qp *hr_qp)
5274 {
5275         struct ib_device *ibdev = &hr_dev->ib_dev;
5276         struct hns_roce_sccc_clr_done *resp;
5277         struct hns_roce_sccc_clr *clr;
5278         struct hns_roce_cmq_desc desc;
5279         int ret, i;
5280
5281         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
5282                 return 0;
5283
5284         mutex_lock(&hr_dev->qp_table.scc_mutex);
5285
5286         /* set scc ctx clear done flag */
5287         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
5288         ret =  hns_roce_cmq_send(hr_dev, &desc, 1);
5289         if (ret) {
5290                 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret);
5291                 goto out;
5292         }
5293
5294         /* clear scc context */
5295         hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
5296         clr = (struct hns_roce_sccc_clr *)desc.data;
5297         clr->qpn = cpu_to_le32(hr_qp->qpn);
5298         ret =  hns_roce_cmq_send(hr_dev, &desc, 1);
5299         if (ret) {
5300                 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret);
5301                 goto out;
5302         }
5303
5304         /* query scc context clear is done or not */
5305         resp = (struct hns_roce_sccc_clr_done *)desc.data;
5306         for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
5307                 hns_roce_cmq_setup_basic_desc(&desc,
5308                                               HNS_ROCE_OPC_QUERY_SCCC, true);
5309                 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5310                 if (ret) {
5311                         ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
5312                                   ret);
5313                         goto out;
5314                 }
5315
5316                 if (resp->clr_done)
5317                         goto out;
5318
5319                 msleep(20);
5320         }
5321
5322         ibdev_err(ibdev, "Query SCC clr done flag overtime.\n");
5323         ret = -ETIMEDOUT;
5324
5325 out:
5326         mutex_unlock(&hr_dev->qp_table.scc_mutex);
5327         return ret;
5328 }
5329
5330 #define DMA_IDX_SHIFT 3
5331 #define DMA_WQE_SHIFT 3
5332
5333 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq,
5334                                               struct hns_roce_srq_context *ctx)
5335 {
5336         struct hns_roce_idx_que *idx_que = &srq->idx_que;
5337         struct ib_device *ibdev = srq->ibsrq.device;
5338         struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5339         u64 mtts_idx[MTT_MIN_COUNT] = {};
5340         dma_addr_t dma_handle_idx = 0;
5341         int ret;
5342
5343         /* Get physical address of idx que buf */
5344         ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx,
5345                                 ARRAY_SIZE(mtts_idx), &dma_handle_idx);
5346         if (ret < 1) {
5347                 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n",
5348                           ret);
5349                 return -ENOBUFS;
5350         }
5351
5352         hr_reg_write(ctx, SRQC_IDX_HOP_NUM,
5353                      to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt));
5354
5355         hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT);
5356         hr_reg_write(ctx, SRQC_IDX_BT_BA_H,
5357                      upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT));
5358
5359         hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ,
5360                      to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift));
5361         hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ,
5362                      to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift));
5363
5364         hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L,
5365                      to_hr_hw_page_addr(mtts_idx[0]));
5366         hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H,
5367                      upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
5368
5369         hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L,
5370                      to_hr_hw_page_addr(mtts_idx[1]));
5371         hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H,
5372                      upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
5373
5374         return 0;
5375 }
5376
5377 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf)
5378 {
5379         struct ib_device *ibdev = srq->ibsrq.device;
5380         struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5381         struct hns_roce_srq_context *ctx = mb_buf;
5382         u64 mtts_wqe[MTT_MIN_COUNT] = {};
5383         dma_addr_t dma_handle_wqe = 0;
5384         int ret;
5385
5386         memset(ctx, 0, sizeof(*ctx));
5387
5388         /* Get the physical address of srq buf */
5389         ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe,
5390                                 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe);
5391         if (ret < 1) {
5392                 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n",
5393                           ret);
5394                 return -ENOBUFS;
5395         }
5396
5397         hr_reg_write(ctx, SRQC_SRQ_ST, 1);
5398         hr_reg_write_bool(ctx, SRQC_SRQ_TYPE,
5399                           srq->ibsrq.srq_type == IB_SRQT_XRC);
5400         hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn);
5401         hr_reg_write(ctx, SRQC_SRQN, srq->srqn);
5402         hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn);
5403         hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn);
5404         hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt));
5405         hr_reg_write(ctx, SRQC_RQWS,
5406                      srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1));
5407
5408         hr_reg_write(ctx, SRQC_WQE_HOP_NUM,
5409                      to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num,
5410                                       srq->wqe_cnt));
5411
5412         hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT);
5413         hr_reg_write(ctx, SRQC_WQE_BT_BA_H,
5414                      upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT));
5415
5416         hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ,
5417                      to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
5418         hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ,
5419                      to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
5420
5421         return hns_roce_v2_write_srqc_index_queue(srq, ctx);
5422 }
5423
5424 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5425                                   struct ib_srq_attr *srq_attr,
5426                                   enum ib_srq_attr_mask srq_attr_mask,
5427                                   struct ib_udata *udata)
5428 {
5429         struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5430         struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5431         struct hns_roce_srq_context *srq_context;
5432         struct hns_roce_srq_context *srqc_mask;
5433         struct hns_roce_cmd_mailbox *mailbox;
5434         int ret;
5435
5436         /* Resizing SRQs is not supported yet */
5437         if (srq_attr_mask & IB_SRQ_MAX_WR)
5438                 return -EINVAL;
5439
5440         if (srq_attr_mask & IB_SRQ_LIMIT) {
5441                 if (srq_attr->srq_limit > srq->wqe_cnt)
5442                         return -EINVAL;
5443
5444                 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5445                 if (IS_ERR(mailbox))
5446                         return PTR_ERR(mailbox);
5447
5448                 srq_context = mailbox->buf;
5449                 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5450
5451                 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5452
5453                 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit);
5454                 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL);
5455
5456                 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0,
5457                                         HNS_ROCE_CMD_MODIFY_SRQC,
5458                                         HNS_ROCE_CMD_TIMEOUT_MSECS);
5459                 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5460                 if (ret) {
5461                         ibdev_err(&hr_dev->ib_dev,
5462                                   "failed to handle cmd of modifying SRQ, ret = %d.\n",
5463                                   ret);
5464                         return ret;
5465                 }
5466         }
5467
5468         return 0;
5469 }
5470
5471 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
5472 {
5473         struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5474         struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5475         struct hns_roce_srq_context *srq_context;
5476         struct hns_roce_cmd_mailbox *mailbox;
5477         int ret;
5478
5479         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5480         if (IS_ERR(mailbox))
5481                 return PTR_ERR(mailbox);
5482
5483         srq_context = mailbox->buf;
5484         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0,
5485                                 HNS_ROCE_CMD_QUERY_SRQC,
5486                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
5487         if (ret) {
5488                 ibdev_err(&hr_dev->ib_dev,
5489                           "failed to process cmd of querying SRQ, ret = %d.\n",
5490                           ret);
5491                 goto out;
5492         }
5493
5494         attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL);
5495         attr->max_wr = srq->wqe_cnt;
5496         attr->max_sge = srq->max_gs - srq->rsv_sge;
5497
5498 out:
5499         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5500         return ret;
5501 }
5502
5503 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
5504 {
5505         struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
5506         struct hns_roce_v2_cq_context *cq_context;
5507         struct hns_roce_cq *hr_cq = to_hr_cq(cq);
5508         struct hns_roce_v2_cq_context *cqc_mask;
5509         struct hns_roce_cmd_mailbox *mailbox;
5510         int ret;
5511
5512         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5513         if (IS_ERR(mailbox))
5514                 return PTR_ERR(mailbox);
5515
5516         cq_context = mailbox->buf;
5517         cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
5518
5519         memset(cqc_mask, 0xff, sizeof(*cqc_mask));
5520
5521         hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count);
5522         hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT);
5523         hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period);
5524         hr_reg_clear(cqc_mask, CQC_CQ_PERIOD);
5525
5526         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
5527                                 HNS_ROCE_CMD_MODIFY_CQC,
5528                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
5529         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5530         if (ret)
5531                 ibdev_err(&hr_dev->ib_dev,
5532                           "failed to process cmd when modifying CQ, ret = %d.\n",
5533                           ret);
5534
5535         return ret;
5536 }
5537
5538 static void hns_roce_irq_work_handle(struct work_struct *work)
5539 {
5540         struct hns_roce_work *irq_work =
5541                                 container_of(work, struct hns_roce_work, work);
5542         struct ib_device *ibdev = &irq_work->hr_dev->ib_dev;
5543
5544         switch (irq_work->event_type) {
5545         case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5546                 ibdev_info(ibdev, "Path migrated succeeded.\n");
5547                 break;
5548         case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5549                 ibdev_warn(ibdev, "Path migration failed.\n");
5550                 break;
5551         case HNS_ROCE_EVENT_TYPE_COMM_EST:
5552                 break;
5553         case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5554                 ibdev_warn(ibdev, "Send queue drained.\n");
5555                 break;
5556         case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5557                 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n",
5558                           irq_work->queue_num, irq_work->sub_type);
5559                 break;
5560         case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5561                 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n",
5562                           irq_work->queue_num);
5563                 break;
5564         case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5565                 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n",
5566                           irq_work->queue_num, irq_work->sub_type);
5567                 break;
5568         case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5569                 ibdev_warn(ibdev, "SRQ limit reach.\n");
5570                 break;
5571         case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5572                 ibdev_warn(ibdev, "SRQ last wqe reach.\n");
5573                 break;
5574         case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5575                 ibdev_err(ibdev, "SRQ catas error.\n");
5576                 break;
5577         case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5578                 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num);
5579                 break;
5580         case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5581                 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num);
5582                 break;
5583         case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5584                 ibdev_warn(ibdev, "DB overflow.\n");
5585                 break;
5586         case HNS_ROCE_EVENT_TYPE_FLR:
5587                 ibdev_warn(ibdev, "Function level reset.\n");
5588                 break;
5589         case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5590                 ibdev_err(ibdev, "xrc domain violation error.\n");
5591                 break;
5592         case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5593                 ibdev_err(ibdev, "invalid xrceth error.\n");
5594                 break;
5595         default:
5596                 break;
5597         }
5598
5599         kfree(irq_work);
5600 }
5601
5602 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
5603                                       struct hns_roce_eq *eq, u32 queue_num)
5604 {
5605         struct hns_roce_work *irq_work;
5606
5607         irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
5608         if (!irq_work)
5609                 return;
5610
5611         INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle);
5612         irq_work->hr_dev = hr_dev;
5613         irq_work->event_type = eq->event_type;
5614         irq_work->sub_type = eq->sub_type;
5615         irq_work->queue_num = queue_num;
5616         queue_work(hr_dev->irq_workq, &(irq_work->work));
5617 }
5618
5619 static void update_eq_db(struct hns_roce_eq *eq)
5620 {
5621         struct hns_roce_dev *hr_dev = eq->hr_dev;
5622         struct hns_roce_v2_db eq_db = {};
5623
5624         if (eq->type_flag == HNS_ROCE_AEQ) {
5625                 hr_reg_write(&eq_db, EQ_DB_CMD,
5626                              eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5627                              HNS_ROCE_EQ_DB_CMD_AEQ :
5628                              HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
5629         } else {
5630                 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn);
5631
5632                 hr_reg_write(&eq_db, EQ_DB_CMD,
5633                              eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5634                              HNS_ROCE_EQ_DB_CMD_CEQ :
5635                              HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
5636         }
5637
5638         hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index);
5639
5640         hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg);
5641 }
5642
5643 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
5644 {
5645         struct hns_roce_aeqe *aeqe;
5646
5647         aeqe = hns_roce_buf_offset(eq->mtr.kmem,
5648                                    (eq->cons_index & (eq->entries - 1)) *
5649                                    eq->eqe_size);
5650
5651         return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
5652                 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
5653 }
5654
5655 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
5656                                struct hns_roce_eq *eq)
5657 {
5658         struct device *dev = hr_dev->dev;
5659         struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
5660         int aeqe_found = 0;
5661         int event_type;
5662         u32 queue_num;
5663         int sub_type;
5664
5665         while (aeqe) {
5666                 /* Make sure we read AEQ entry after we have checked the
5667                  * ownership bit
5668                  */
5669                 dma_rmb();
5670
5671                 event_type = roce_get_field(aeqe->asyn,
5672                                             HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
5673                                             HNS_ROCE_V2_AEQE_EVENT_TYPE_S);
5674                 sub_type = roce_get_field(aeqe->asyn,
5675                                           HNS_ROCE_V2_AEQE_SUB_TYPE_M,
5676                                           HNS_ROCE_V2_AEQE_SUB_TYPE_S);
5677                 queue_num = roce_get_field(aeqe->event.queue_event.num,
5678                                            HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5679                                            HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
5680
5681                 switch (event_type) {
5682                 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5683                 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5684                 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5685                 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5686                 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5687                 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5688                 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5689                 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5690                 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5691                 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5692                         hns_roce_qp_event(hr_dev, queue_num, event_type);
5693                         break;
5694                 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5695                 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5696                         hns_roce_srq_event(hr_dev, queue_num, event_type);
5697                         break;
5698                 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5699                 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5700                         hns_roce_cq_event(hr_dev, queue_num, event_type);
5701                         break;
5702                 case HNS_ROCE_EVENT_TYPE_MB:
5703                         hns_roce_cmd_event(hr_dev,
5704                                         le16_to_cpu(aeqe->event.cmd.token),
5705                                         aeqe->event.cmd.status,
5706                                         le64_to_cpu(aeqe->event.cmd.out_param));
5707                         break;
5708                 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5709                 case HNS_ROCE_EVENT_TYPE_FLR:
5710                         break;
5711                 default:
5712                         dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",
5713                                 event_type, eq->eqn, eq->cons_index);
5714                         break;
5715                 }
5716
5717                 eq->event_type = event_type;
5718                 eq->sub_type = sub_type;
5719                 ++eq->cons_index;
5720                 aeqe_found = 1;
5721
5722                 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num);
5723
5724                 aeqe = next_aeqe_sw_v2(eq);
5725         }
5726
5727         update_eq_db(eq);
5728         return aeqe_found;
5729 }
5730
5731 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
5732 {
5733         struct hns_roce_ceqe *ceqe;
5734
5735         ceqe = hns_roce_buf_offset(eq->mtr.kmem,
5736                                    (eq->cons_index & (eq->entries - 1)) *
5737                                    eq->eqe_size);
5738
5739         return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
5740                 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
5741 }
5742
5743 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
5744                                struct hns_roce_eq *eq)
5745 {
5746         struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
5747         int ceqe_found = 0;
5748         u32 cqn;
5749
5750         while (ceqe) {
5751                 /* Make sure we read CEQ entry after we have checked the
5752                  * ownership bit
5753                  */
5754                 dma_rmb();
5755
5756                 cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M,
5757                                      HNS_ROCE_V2_CEQE_COMP_CQN_S);
5758
5759                 hns_roce_cq_completion(hr_dev, cqn);
5760
5761                 ++eq->cons_index;
5762                 ceqe_found = 1;
5763
5764                 ceqe = next_ceqe_sw_v2(eq);
5765         }
5766
5767         update_eq_db(eq);
5768
5769         return ceqe_found;
5770 }
5771
5772 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
5773 {
5774         struct hns_roce_eq *eq = eq_ptr;
5775         struct hns_roce_dev *hr_dev = eq->hr_dev;
5776         int int_work;
5777
5778         if (eq->type_flag == HNS_ROCE_CEQ)
5779                 /* Completion event interrupt */
5780                 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
5781         else
5782                 /* Asychronous event interrupt */
5783                 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
5784
5785         return IRQ_RETVAL(int_work);
5786 }
5787
5788 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
5789 {
5790         struct hns_roce_dev *hr_dev = dev_id;
5791         struct device *dev = hr_dev->dev;
5792         int int_work = 0;
5793         u32 int_st;
5794         u32 int_en;
5795
5796         /* Abnormal interrupt */
5797         int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
5798         int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
5799
5800         if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
5801                 struct pci_dev *pdev = hr_dev->pci_dev;
5802                 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5803                 const struct hnae3_ae_ops *ops = ae_dev->ops;
5804
5805                 dev_err(dev, "AEQ overflow!\n");
5806
5807                 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S;
5808                 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5809
5810                 /* Set reset level for reset_event() */
5811                 if (ops->set_default_reset_request)
5812                         ops->set_default_reset_request(ae_dev,
5813                                                        HNAE3_FUNC_RESET);
5814                 if (ops->reset_event)
5815                         ops->reset_event(pdev, NULL);
5816
5817                 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
5818                 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5819
5820                 int_work = 1;
5821         } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_RAS_INT_S)) {
5822                 dev_err(dev, "RAS interrupt!\n");
5823
5824                 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_RAS_INT_S;
5825                 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5826
5827                 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
5828                 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5829
5830                 int_work = 1;
5831         } else {
5832                 dev_err(dev, "There is no abnormal irq found!\n");
5833         }
5834
5835         return IRQ_RETVAL(int_work);
5836 }
5837
5838 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
5839                                         int eq_num, u32 enable_flag)
5840 {
5841         int i;
5842
5843         for (i = 0; i < eq_num; i++)
5844                 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5845                            i * EQ_REG_OFFSET, enable_flag);
5846
5847         roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag);
5848         roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);
5849 }
5850
5851 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
5852 {
5853         struct device *dev = hr_dev->dev;
5854         int ret;
5855
5856         if (eqn < hr_dev->caps.num_comp_vectors)
5857                 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5858                                         0, HNS_ROCE_CMD_DESTROY_CEQC,
5859                                         HNS_ROCE_CMD_TIMEOUT_MSECS);
5860         else
5861                 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5862                                         0, HNS_ROCE_CMD_DESTROY_AEQC,
5863                                         HNS_ROCE_CMD_TIMEOUT_MSECS);
5864         if (ret)
5865                 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
5866 }
5867
5868 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
5869 {
5870         hns_roce_mtr_destroy(hr_dev, &eq->mtr);
5871 }
5872
5873 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
5874 {
5875         eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
5876         eq->cons_index = 0;
5877         eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
5878         eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
5879         eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
5880         eq->shift = ilog2((unsigned int)eq->entries);
5881 }
5882
5883 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
5884                       void *mb_buf)
5885 {
5886         u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
5887         struct hns_roce_eq_context *eqc;
5888         u64 bt_ba = 0;
5889         int count;
5890
5891         eqc = mb_buf;
5892         memset(eqc, 0, sizeof(struct hns_roce_eq_context));
5893
5894         init_eq_config(hr_dev, eq);
5895
5896         /* if not multi-hop, eqe buffer only use one trunk */
5897         count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT,
5898                                   &bt_ba);
5899         if (count < 1) {
5900                 dev_err(hr_dev->dev, "failed to find EQE mtr\n");
5901                 return -ENOBUFS;
5902         }
5903
5904         hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);
5905         hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);
5906         hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);
5907         hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);
5908         hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);
5909         hr_reg_write(eqc, EQC_EQN, eq->eqn);
5910         hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);
5911         hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,
5912                      to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
5913         hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,
5914                      to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
5915         hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);
5916         hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);
5917
5918         hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);
5919         hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);
5920         hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);
5921         hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);
5922         hr_reg_write(eqc, EQC_SHIFT, eq->shift);
5923         hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);
5924         hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);
5925         hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);
5926         hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);
5927         hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);
5928         hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);
5929         hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);
5930         hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE);
5931
5932         return 0;
5933 }
5934
5935 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
5936 {
5937         struct hns_roce_buf_attr buf_attr = {};
5938         int err;
5939
5940         if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
5941                 eq->hop_num = 0;
5942         else
5943                 eq->hop_num = hr_dev->caps.eqe_hop_num;
5944
5945         buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT;
5946         buf_attr.region[0].size = eq->entries * eq->eqe_size;
5947         buf_attr.region[0].hopnum = eq->hop_num;
5948         buf_attr.region_count = 1;
5949
5950         err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
5951                                   hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL,
5952                                   0);
5953         if (err)
5954                 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err);
5955
5956         return err;
5957 }
5958
5959 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
5960                                  struct hns_roce_eq *eq,
5961                                  unsigned int eq_cmd)
5962 {
5963         struct hns_roce_cmd_mailbox *mailbox;
5964         int ret;
5965
5966         /* Allocate mailbox memory */
5967         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5968         if (IS_ERR_OR_NULL(mailbox))
5969                 return -ENOMEM;
5970
5971         ret = alloc_eq_buf(hr_dev, eq);
5972         if (ret)
5973                 goto free_cmd_mbox;
5974
5975         ret = config_eqc(hr_dev, eq, mailbox->buf);
5976         if (ret)
5977                 goto err_cmd_mbox;
5978
5979         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,
5980                                 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
5981         if (ret) {
5982                 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
5983                 goto err_cmd_mbox;
5984         }
5985
5986         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5987
5988         return 0;
5989
5990 err_cmd_mbox:
5991         free_eq_buf(hr_dev, eq);
5992
5993 free_cmd_mbox:
5994         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5995
5996         return ret;
5997 }
5998
5999 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
6000                                   int comp_num, int aeq_num, int other_num)
6001 {
6002         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6003         int i, j;
6004         int ret;
6005
6006         for (i = 0; i < irq_num; i++) {
6007                 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
6008                                                GFP_KERNEL);
6009                 if (!hr_dev->irq_names[i]) {
6010                         ret = -ENOMEM;
6011                         goto err_kzalloc_failed;
6012                 }
6013         }
6014
6015         /* irq contains: abnormal + AEQ + CEQ */
6016         for (j = 0; j < other_num; j++)
6017                 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6018                          "hns-abn-%d", j);
6019
6020         for (j = other_num; j < (other_num + aeq_num); j++)
6021                 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6022                          "hns-aeq-%d", j - other_num);
6023
6024         for (j = (other_num + aeq_num); j < irq_num; j++)
6025                 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6026                          "hns-ceq-%d", j - other_num - aeq_num);
6027
6028         for (j = 0; j < irq_num; j++) {
6029                 if (j < other_num)
6030                         ret = request_irq(hr_dev->irq[j],
6031                                           hns_roce_v2_msix_interrupt_abn,
6032                                           0, hr_dev->irq_names[j], hr_dev);
6033
6034                 else if (j < (other_num + comp_num))
6035                         ret = request_irq(eq_table->eq[j - other_num].irq,
6036                                           hns_roce_v2_msix_interrupt_eq,
6037                                           0, hr_dev->irq_names[j + aeq_num],
6038                                           &eq_table->eq[j - other_num]);
6039                 else
6040                         ret = request_irq(eq_table->eq[j - other_num].irq,
6041                                           hns_roce_v2_msix_interrupt_eq,
6042                                           0, hr_dev->irq_names[j - comp_num],
6043                                           &eq_table->eq[j - other_num]);
6044                 if (ret) {
6045                         dev_err(hr_dev->dev, "Request irq error!\n");
6046                         goto err_request_failed;
6047                 }
6048         }
6049
6050         return 0;
6051
6052 err_request_failed:
6053         for (j -= 1; j >= 0; j--)
6054                 if (j < other_num)
6055                         free_irq(hr_dev->irq[j], hr_dev);
6056                 else
6057                         free_irq(eq_table->eq[j - other_num].irq,
6058                                  &eq_table->eq[j - other_num]);
6059
6060 err_kzalloc_failed:
6061         for (i -= 1; i >= 0; i--)
6062                 kfree(hr_dev->irq_names[i]);
6063
6064         return ret;
6065 }
6066
6067 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
6068 {
6069         int irq_num;
6070         int eq_num;
6071         int i;
6072
6073         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6074         irq_num = eq_num + hr_dev->caps.num_other_vectors;
6075
6076         for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
6077                 free_irq(hr_dev->irq[i], hr_dev);
6078
6079         for (i = 0; i < eq_num; i++)
6080                 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
6081
6082         for (i = 0; i < irq_num; i++)
6083                 kfree(hr_dev->irq_names[i]);
6084 }
6085
6086 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
6087 {
6088         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6089         struct device *dev = hr_dev->dev;
6090         struct hns_roce_eq *eq;
6091         unsigned int eq_cmd;
6092         int irq_num;
6093         int eq_num;
6094         int other_num;
6095         int comp_num;
6096         int aeq_num;
6097         int i;
6098         int ret;
6099
6100         other_num = hr_dev->caps.num_other_vectors;
6101         comp_num = hr_dev->caps.num_comp_vectors;
6102         aeq_num = hr_dev->caps.num_aeq_vectors;
6103
6104         eq_num = comp_num + aeq_num;
6105         irq_num = eq_num + other_num;
6106
6107         eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
6108         if (!eq_table->eq)
6109                 return -ENOMEM;
6110
6111         /* create eq */
6112         for (i = 0; i < eq_num; i++) {
6113                 eq = &eq_table->eq[i];
6114                 eq->hr_dev = hr_dev;
6115                 eq->eqn = i;
6116                 if (i < comp_num) {
6117                         /* CEQ */
6118                         eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
6119                         eq->type_flag = HNS_ROCE_CEQ;
6120                         eq->entries = hr_dev->caps.ceqe_depth;
6121                         eq->eqe_size = hr_dev->caps.ceqe_size;
6122                         eq->irq = hr_dev->irq[i + other_num + aeq_num];
6123                         eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
6124                         eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
6125                 } else {
6126                         /* AEQ */
6127                         eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
6128                         eq->type_flag = HNS_ROCE_AEQ;
6129                         eq->entries = hr_dev->caps.aeqe_depth;
6130                         eq->eqe_size = hr_dev->caps.aeqe_size;
6131                         eq->irq = hr_dev->irq[i - comp_num + other_num];
6132                         eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
6133                         eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
6134                 }
6135
6136                 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
6137                 if (ret) {
6138                         dev_err(dev, "eq create failed.\n");
6139                         goto err_create_eq_fail;
6140                 }
6141         }
6142
6143         /* enable irq */
6144         hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
6145
6146         ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num,
6147                                      aeq_num, other_num);
6148         if (ret) {
6149                 dev_err(dev, "Request irq failed.\n");
6150                 goto err_request_irq_fail;
6151         }
6152
6153         hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
6154         if (!hr_dev->irq_workq) {
6155                 dev_err(dev, "Create irq workqueue failed!\n");
6156                 ret = -ENOMEM;
6157                 goto err_create_wq_fail;
6158         }
6159
6160         return 0;
6161
6162 err_create_wq_fail:
6163         __hns_roce_free_irq(hr_dev);
6164
6165 err_request_irq_fail:
6166         hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
6167
6168 err_create_eq_fail:
6169         for (i -= 1; i >= 0; i--)
6170                 free_eq_buf(hr_dev, &eq_table->eq[i]);
6171         kfree(eq_table->eq);
6172
6173         return ret;
6174 }
6175
6176 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
6177 {
6178         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6179         int eq_num;
6180         int i;
6181
6182         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6183
6184         /* Disable irq */
6185         hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
6186
6187         __hns_roce_free_irq(hr_dev);
6188         destroy_workqueue(hr_dev->irq_workq);
6189
6190         for (i = 0; i < eq_num; i++) {
6191                 hns_roce_v2_destroy_eqc(hr_dev, i);
6192
6193                 free_eq_buf(hr_dev, &eq_table->eq[i]);
6194         }
6195
6196         kfree(eq_table->eq);
6197 }
6198
6199 static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = {
6200         .query_cqc_info = hns_roce_v2_query_cqc_info,
6201 };
6202
6203 static const struct ib_device_ops hns_roce_v2_dev_ops = {
6204         .destroy_qp = hns_roce_v2_destroy_qp,
6205         .modify_cq = hns_roce_v2_modify_cq,
6206         .poll_cq = hns_roce_v2_poll_cq,
6207         .post_recv = hns_roce_v2_post_recv,
6208         .post_send = hns_roce_v2_post_send,
6209         .query_qp = hns_roce_v2_query_qp,
6210         .req_notify_cq = hns_roce_v2_req_notify_cq,
6211 };
6212
6213 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
6214         .modify_srq = hns_roce_v2_modify_srq,
6215         .post_srq_recv = hns_roce_v2_post_srq_recv,
6216         .query_srq = hns_roce_v2_query_srq,
6217 };
6218
6219 static const struct hns_roce_hw hns_roce_hw_v2 = {
6220         .cmq_init = hns_roce_v2_cmq_init,
6221         .cmq_exit = hns_roce_v2_cmq_exit,
6222         .hw_profile = hns_roce_v2_profile,
6223         .hw_init = hns_roce_v2_init,
6224         .hw_exit = hns_roce_v2_exit,
6225         .post_mbox = v2_post_mbox,
6226         .poll_mbox_done = v2_poll_mbox_done,
6227         .chk_mbox_avail = v2_chk_mbox_is_avail,
6228         .set_gid = hns_roce_v2_set_gid,
6229         .set_mac = hns_roce_v2_set_mac,
6230         .write_mtpt = hns_roce_v2_write_mtpt,
6231         .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
6232         .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
6233         .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
6234         .write_cqc = hns_roce_v2_write_cqc,
6235         .set_hem = hns_roce_v2_set_hem,
6236         .clear_hem = hns_roce_v2_clear_hem,
6237         .modify_qp = hns_roce_v2_modify_qp,
6238         .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
6239         .init_eq = hns_roce_v2_init_eq_table,
6240         .cleanup_eq = hns_roce_v2_cleanup_eq_table,
6241         .write_srqc = hns_roce_v2_write_srqc,
6242         .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
6243         .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
6244 };
6245
6246 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
6247         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
6248         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
6249         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
6250         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
6251         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
6252         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
6253         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
6254          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
6255         /* required last entry */
6256         {0, }
6257 };
6258
6259 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
6260
6261 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
6262                                   struct hnae3_handle *handle)
6263 {
6264         struct hns_roce_v2_priv *priv = hr_dev->priv;
6265         const struct pci_device_id *id;
6266         int i;
6267
6268         hr_dev->pci_dev = handle->pdev;
6269         id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
6270         hr_dev->is_vf = id->driver_data;
6271         hr_dev->dev = &handle->pdev->dev;
6272         hr_dev->hw = &hns_roce_hw_v2;
6273         hr_dev->dfx = &hns_roce_dfx_hw_v2;
6274         hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6275         hr_dev->odb_offset = hr_dev->sdb_offset;
6276
6277         /* Get info from NIC driver. */
6278         hr_dev->reg_base = handle->rinfo.roce_io_base;
6279         hr_dev->mem_base = handle->rinfo.roce_mem_base;
6280         hr_dev->caps.num_ports = 1;
6281         hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6282         hr_dev->iboe.phy_port[0] = 0;
6283
6284         addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6285                             hr_dev->iboe.netdevs[0]->dev_addr);
6286
6287         for (i = 0; i < handle->rinfo.num_vectors; i++)
6288                 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6289                                                 i + handle->rinfo.base_vector);
6290
6291         /* cmd issue mode: 0 is poll, 1 is event */
6292         hr_dev->cmd_mod = 1;
6293         hr_dev->loop_idc = 0;
6294
6295         hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6296         priv->handle = handle;
6297 }
6298
6299 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6300 {
6301         struct hns_roce_dev *hr_dev;
6302         int ret;
6303
6304         hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
6305         if (!hr_dev)
6306                 return -ENOMEM;
6307
6308         hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6309         if (!hr_dev->priv) {
6310                 ret = -ENOMEM;
6311                 goto error_failed_kzalloc;
6312         }
6313
6314         hns_roce_hw_v2_get_cfg(hr_dev, handle);
6315
6316         ret = hns_roce_init(hr_dev);
6317         if (ret) {
6318                 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6319                 goto error_failed_get_cfg;
6320         }
6321
6322         handle->priv = hr_dev;
6323
6324         return 0;
6325
6326 error_failed_get_cfg:
6327         kfree(hr_dev->priv);
6328
6329 error_failed_kzalloc:
6330         ib_dealloc_device(&hr_dev->ib_dev);
6331
6332         return ret;
6333 }
6334
6335 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6336                                            bool reset)
6337 {
6338         struct hns_roce_dev *hr_dev = handle->priv;
6339
6340         if (!hr_dev)
6341                 return;
6342
6343         handle->priv = NULL;
6344
6345         hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6346         hns_roce_handle_device_err(hr_dev);
6347
6348         hns_roce_exit(hr_dev);
6349         kfree(hr_dev->priv);
6350         ib_dealloc_device(&hr_dev->ib_dev);
6351 }
6352
6353 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6354 {
6355         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
6356         const struct pci_device_id *id;
6357         struct device *dev = &handle->pdev->dev;
6358         int ret;
6359
6360         handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6361
6362         if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6363                 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6364                 goto reset_chk_err;
6365         }
6366
6367         id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6368         if (!id)
6369                 return 0;
6370
6371         if (id->driver_data && handle->pdev->revision < PCI_REVISION_ID_HIP09)
6372                 return 0;
6373
6374         ret = __hns_roce_hw_v2_init_instance(handle);
6375         if (ret) {
6376                 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6377                 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6378                 if (ops->ae_dev_resetting(handle) ||
6379                     ops->get_hw_reset_stat(handle))
6380                         goto reset_chk_err;
6381                 else
6382                         return ret;
6383         }
6384
6385         handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6386
6387
6388         return 0;
6389
6390 reset_chk_err:
6391         dev_err(dev, "Device is busy in resetting state.\n"
6392                      "please retry later.\n");
6393
6394         return -EBUSY;
6395 }
6396
6397 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6398                                            bool reset)
6399 {
6400         if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6401                 return;
6402
6403         handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6404
6405         __hns_roce_hw_v2_uninit_instance(handle, reset);
6406
6407         handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6408 }
6409 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6410 {
6411         struct hns_roce_dev *hr_dev;
6412
6413         if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6414                 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6415                 return 0;
6416         }
6417
6418         handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6419         clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6420
6421         hr_dev = handle->priv;
6422         if (!hr_dev)
6423                 return 0;
6424
6425         hr_dev->is_reset = true;
6426         hr_dev->active = false;
6427         hr_dev->dis_db = true;
6428
6429         hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
6430
6431         return 0;
6432 }
6433
6434 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6435 {
6436         struct device *dev = &handle->pdev->dev;
6437         int ret;
6438
6439         if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6440                                &handle->rinfo.state)) {
6441                 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6442                 return 0;
6443         }
6444
6445         handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6446
6447         dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6448         ret = __hns_roce_hw_v2_init_instance(handle);
6449         if (ret) {
6450                 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6451                  * callback function, RoCE Engine reinitialize. If RoCE reinit
6452                  * failed, we should inform NIC driver.
6453                  */
6454                 handle->priv = NULL;
6455                 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6456         } else {
6457                 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6458                 dev_info(dev, "Reset done, RoCE client reinit finished.\n");
6459         }
6460
6461         return ret;
6462 }
6463
6464 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6465 {
6466         if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6467                 return 0;
6468
6469         handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6470         dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
6471         msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
6472         __hns_roce_hw_v2_uninit_instance(handle, false);
6473
6474         return 0;
6475 }
6476
6477 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6478                                        enum hnae3_reset_notify_type type)
6479 {
6480         int ret = 0;
6481
6482         switch (type) {
6483         case HNAE3_DOWN_CLIENT:
6484                 ret = hns_roce_hw_v2_reset_notify_down(handle);
6485                 break;
6486         case HNAE3_INIT_CLIENT:
6487                 ret = hns_roce_hw_v2_reset_notify_init(handle);
6488                 break;
6489         case HNAE3_UNINIT_CLIENT:
6490                 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6491                 break;
6492         default:
6493                 break;
6494         }
6495
6496         return ret;
6497 }
6498
6499 static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6500         .init_instance = hns_roce_hw_v2_init_instance,
6501         .uninit_instance = hns_roce_hw_v2_uninit_instance,
6502         .reset_notify = hns_roce_hw_v2_reset_notify,
6503 };
6504
6505 static struct hnae3_client hns_roce_hw_v2_client = {
6506         .name = "hns_roce_hw_v2",
6507         .type = HNAE3_CLIENT_ROCE,
6508         .ops = &hns_roce_hw_v2_ops,
6509 };
6510
6511 static int __init hns_roce_hw_v2_init(void)
6512 {
6513         return hnae3_register_client(&hns_roce_hw_v2_client);
6514 }
6515
6516 static void __exit hns_roce_hw_v2_exit(void)
6517 {
6518         hnae3_unregister_client(&hns_roce_hw_v2_client);
6519 }
6520
6521 module_init(hns_roce_hw_v2_init);
6522 module_exit(hns_roce_hw_v2_exit);
6523
6524 MODULE_LICENSE("Dual BSD/GPL");
6525 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
6526 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
6527 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
6528 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");