1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
3 * Copyright (c) 2018 Hisilicon Limited.
6 #include <rdma/ib_umem.h>
7 #include <rdma/hns-abi.h>
8 #include "hns_roce_device.h"
9 #include "hns_roce_cmd.h"
10 #include "hns_roce_hem.h"
12 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type)
14 struct hns_roce_srq_table *srq_table = &hr_dev->srq_table;
15 struct hns_roce_srq *srq;
17 xa_lock(&srq_table->xa);
18 srq = xa_load(&srq_table->xa, srqn & (hr_dev->caps.num_srqs - 1));
20 atomic_inc(&srq->refcount);
21 xa_unlock(&srq_table->xa);
24 dev_warn(hr_dev->dev, "Async event for bogus SRQ %08x\n", srqn);
28 srq->event(srq, event_type);
30 if (atomic_dec_and_test(&srq->refcount))
33 EXPORT_SYMBOL_GPL(hns_roce_srq_event);
35 static void hns_roce_ib_srq_event(struct hns_roce_srq *srq,
36 enum hns_roce_event event_type)
38 struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device);
39 struct ib_srq *ibsrq = &srq->ibsrq;
40 struct ib_event event;
42 if (ibsrq->event_handler) {
43 event.device = ibsrq->device;
44 event.element.srq = ibsrq;
46 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
47 event.event = IB_EVENT_SRQ_LIMIT_REACHED;
49 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
50 event.event = IB_EVENT_SRQ_ERR;
54 "hns_roce:Unexpected event type 0x%x on SRQ %06lx\n",
55 event_type, srq->srqn);
59 ibsrq->event_handler(&event, ibsrq->srq_context);
63 static int hns_roce_sw2hw_srq(struct hns_roce_dev *dev,
64 struct hns_roce_cmd_mailbox *mailbox,
65 unsigned long srq_num)
67 return hns_roce_cmd_mbox(dev, mailbox->dma, 0, srq_num, 0,
68 HNS_ROCE_CMD_SW2HW_SRQ,
69 HNS_ROCE_CMD_TIMEOUT_MSECS);
72 static int hns_roce_hw2sw_srq(struct hns_roce_dev *dev,
73 struct hns_roce_cmd_mailbox *mailbox,
74 unsigned long srq_num)
76 return hns_roce_cmd_mbox(dev, 0, mailbox ? mailbox->dma : 0, srq_num,
77 mailbox ? 0 : 1, HNS_ROCE_CMD_HW2SW_SRQ,
78 HNS_ROCE_CMD_TIMEOUT_MSECS);
81 int hns_roce_srq_alloc(struct hns_roce_dev *hr_dev, u32 pdn, u32 cqn, u16 xrcd,
82 struct hns_roce_mtt *hr_mtt, u64 db_rec_addr,
83 struct hns_roce_srq *srq)
85 struct hns_roce_srq_table *srq_table = &hr_dev->srq_table;
86 struct hns_roce_cmd_mailbox *mailbox;
87 dma_addr_t dma_handle_wqe;
88 dma_addr_t dma_handle_idx;
93 /* Get the physical address of srq buf */
94 mtts_wqe = hns_roce_table_find(hr_dev,
95 &hr_dev->mr_table.mtt_srqwqe_table,
100 "SRQ alloc.Failed to find srq buf addr.\n");
104 /* Get physical address of idx que buf */
105 mtts_idx = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_idx_table,
106 srq->idx_que.mtt.first_seg,
110 "SRQ alloc.Failed to find idx que buf addr.\n");
114 ret = hns_roce_bitmap_alloc(&srq_table->bitmap, &srq->srqn);
116 dev_err(hr_dev->dev, "SRQ alloc.Failed to alloc index.\n");
120 ret = hns_roce_table_get(hr_dev, &srq_table->table, srq->srqn);
124 ret = xa_err(xa_store(&srq_table->xa, srq->srqn, srq, GFP_KERNEL));
128 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
129 if (IS_ERR(mailbox)) {
130 ret = PTR_ERR(mailbox);
134 hr_dev->hw->write_srqc(hr_dev, srq, pdn, xrcd, cqn, mailbox->buf,
135 mtts_wqe, mtts_idx, dma_handle_wqe,
138 ret = hns_roce_sw2hw_srq(hr_dev, mailbox, srq->srqn);
139 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
143 atomic_set(&srq->refcount, 1);
144 init_completion(&srq->free);
148 xa_erase(&srq_table->xa, srq->srqn);
151 hns_roce_table_put(hr_dev, &srq_table->table, srq->srqn);
154 hns_roce_bitmap_free(&srq_table->bitmap, srq->srqn, BITMAP_NO_RR);
158 void hns_roce_srq_free(struct hns_roce_dev *hr_dev, struct hns_roce_srq *srq)
160 struct hns_roce_srq_table *srq_table = &hr_dev->srq_table;
163 ret = hns_roce_hw2sw_srq(hr_dev, NULL, srq->srqn);
165 dev_err(hr_dev->dev, "HW2SW_SRQ failed (%d) for CQN %06lx\n",
168 xa_erase(&srq_table->xa, srq->srqn);
170 if (atomic_dec_and_test(&srq->refcount))
171 complete(&srq->free);
172 wait_for_completion(&srq->free);
174 hns_roce_table_put(hr_dev, &srq_table->table, srq->srqn);
175 hns_roce_bitmap_free(&srq_table->bitmap, srq->srqn, BITMAP_NO_RR);
178 static int hns_roce_create_idx_que(struct ib_pd *pd, struct hns_roce_srq *srq,
181 struct hns_roce_dev *hr_dev = to_hr_dev(pd->device);
182 struct hns_roce_idx_que *idx_que = &srq->idx_que;
186 bitmap_num = HNS_ROCE_ALOGN_UP(srq->max, 8 * sizeof(u64));
188 idx_que->bitmap = kcalloc(1, bitmap_num / 8, GFP_KERNEL);
189 if (!idx_que->bitmap)
192 bitmap_num = bitmap_num / (8 * sizeof(u64));
194 idx_que->buf_size = srq->idx_que.buf_size;
196 if (hns_roce_buf_alloc(hr_dev, idx_que->buf_size, (1 << page_shift) * 2,
197 &idx_que->idx_buf, page_shift)) {
198 kfree(idx_que->bitmap);
202 for (i = 0; i < bitmap_num; i++)
203 idx_que->bitmap[i] = ~(0UL);
208 struct ib_srq *hns_roce_create_srq(struct ib_pd *pd,
209 struct ib_srq_init_attr *srq_init_attr,
210 struct ib_udata *udata)
212 struct hns_roce_dev *hr_dev = to_hr_dev(pd->device);
213 struct hns_roce_ib_create_srq_resp resp = {};
214 struct hns_roce_srq *srq;
222 /* Check the actual SRQ wqe and SRQ sge num */
223 if (srq_init_attr->attr.max_wr >= hr_dev->caps.max_srq_wrs ||
224 srq_init_attr->attr.max_sge > hr_dev->caps.max_srq_sges)
225 return ERR_PTR(-EINVAL);
227 srq = kzalloc(sizeof(*srq), GFP_KERNEL);
229 return ERR_PTR(-ENOMEM);
231 mutex_init(&srq->mutex);
232 spin_lock_init(&srq->lock);
234 srq->max = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1);
235 srq->max_gs = srq_init_attr->attr.max_sge;
237 srq_desc_size = max(16, 16 * srq->max_gs);
239 srq->wqe_shift = ilog2(srq_desc_size);
241 srq_buf_size = srq->max * srq_desc_size;
243 srq->idx_que.entry_sz = HNS_ROCE_IDX_QUE_ENTRY_SZ;
244 srq->idx_que.buf_size = srq->max * srq->idx_que.entry_sz;
245 srq->mtt.mtt_type = MTT_TYPE_SRQWQE;
246 srq->idx_que.mtt.mtt_type = MTT_TYPE_IDX;
249 struct hns_roce_ib_create_srq ucmd;
251 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
256 srq->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
258 if (IS_ERR(srq->umem)) {
259 ret = PTR_ERR(srq->umem);
263 if (hr_dev->caps.srqwqe_buf_pg_sz) {
264 npages = (ib_umem_page_count(srq->umem) +
265 (1 << hr_dev->caps.srqwqe_buf_pg_sz) - 1) /
266 (1 << hr_dev->caps.srqwqe_buf_pg_sz);
267 page_shift = PAGE_SHIFT + hr_dev->caps.srqwqe_buf_pg_sz;
268 ret = hns_roce_mtt_init(hr_dev, npages,
272 ret = hns_roce_mtt_init(hr_dev,
273 ib_umem_page_count(srq->umem),
274 srq->umem->page_shift,
279 ret = hns_roce_ib_umem_write_mtt(hr_dev, &srq->mtt, srq->umem);
283 /* config index queue BA */
284 srq->idx_que.umem = ib_umem_get(pd->uobject->context,
286 srq->idx_que.buf_size, 0, 0);
287 if (IS_ERR(srq->idx_que.umem)) {
289 "ib_umem_get error for index queue\n");
290 ret = PTR_ERR(srq->idx_que.umem);
294 if (hr_dev->caps.idx_buf_pg_sz) {
295 npages = (ib_umem_page_count(srq->idx_que.umem) +
296 (1 << hr_dev->caps.idx_buf_pg_sz) - 1) /
297 (1 << hr_dev->caps.idx_buf_pg_sz);
298 page_shift = PAGE_SHIFT + hr_dev->caps.idx_buf_pg_sz;
299 ret = hns_roce_mtt_init(hr_dev, npages,
300 page_shift, &srq->idx_que.mtt);
302 ret = hns_roce_mtt_init(hr_dev,
303 ib_umem_page_count(srq->idx_que.umem),
304 srq->idx_que.umem->page_shift,
310 "hns_roce_mtt_init error for idx que\n");
314 ret = hns_roce_ib_umem_write_mtt(hr_dev, &srq->idx_que.mtt,
318 "hns_roce_ib_umem_write_mtt error for idx que\n");
322 page_shift = PAGE_SHIFT + hr_dev->caps.srqwqe_buf_pg_sz;
323 if (hns_roce_buf_alloc(hr_dev, srq_buf_size,
324 (1 << page_shift) * 2,
325 &srq->buf, page_shift)) {
331 srq->tail = srq->max - 1;
333 ret = hns_roce_mtt_init(hr_dev, srq->buf.npages,
334 srq->buf.page_shift, &srq->mtt);
338 ret = hns_roce_buf_write_mtt(hr_dev, &srq->mtt, &srq->buf);
342 page_shift = PAGE_SHIFT + hr_dev->caps.idx_buf_pg_sz;
343 ret = hns_roce_create_idx_que(pd, srq, page_shift);
345 dev_err(hr_dev->dev, "Create idx queue fail(%d)!\n",
350 /* Init mtt table for idx_que */
351 ret = hns_roce_mtt_init(hr_dev, srq->idx_que.idx_buf.npages,
352 srq->idx_que.idx_buf.page_shift,
357 /* Write buffer address into the mtt table */
358 ret = hns_roce_buf_write_mtt(hr_dev, &srq->idx_que.mtt,
359 &srq->idx_que.idx_buf);
363 srq->wrid = kvmalloc_array(srq->max, sizeof(u64), GFP_KERNEL);
370 cqn = ib_srq_has_cq(srq_init_attr->srq_type) ?
371 to_hr_cq(srq_init_attr->ext.cq)->cqn : 0;
373 srq->db_reg_l = hr_dev->reg_base + SRQ_DB_REG;
375 ret = hns_roce_srq_alloc(hr_dev, to_hr_pd(pd)->pdn, cqn, 0,
380 srq->event = hns_roce_ib_srq_event;
381 srq->ibsrq.ext.xrc.srq_num = srq->srqn;
382 resp.srqn = srq->srqn;
385 if (ib_copy_to_udata(udata, &resp,
386 min(udata->outlen, sizeof(resp)))) {
395 hns_roce_srq_free(hr_dev, srq);
401 hns_roce_mtt_cleanup(hr_dev, &srq->idx_que.mtt);
405 ib_umem_release(srq->idx_que.umem);
408 hns_roce_buf_free(hr_dev, srq->idx_que.buf_size,
409 &srq->idx_que.idx_buf);
410 kfree(srq->idx_que.bitmap);
413 hns_roce_mtt_cleanup(hr_dev, &srq->mtt);
417 ib_umem_release(srq->umem);
419 hns_roce_buf_free(hr_dev, srq_buf_size, &srq->buf);
426 int hns_roce_destroy_srq(struct ib_srq *ibsrq)
428 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
429 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
431 hns_roce_srq_free(hr_dev, srq);
432 hns_roce_mtt_cleanup(hr_dev, &srq->mtt);
434 if (ibsrq->uobject) {
435 hns_roce_mtt_cleanup(hr_dev, &srq->idx_que.mtt);
436 ib_umem_release(srq->idx_que.umem);
437 ib_umem_release(srq->umem);
440 hns_roce_buf_free(hr_dev, srq->max << srq->wqe_shift,
449 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev)
451 struct hns_roce_srq_table *srq_table = &hr_dev->srq_table;
453 xa_init(&srq_table->xa);
455 return hns_roce_bitmap_init(&srq_table->bitmap, hr_dev->caps.num_srqs,
456 hr_dev->caps.num_srqs - 1,
457 hr_dev->caps.reserved_srqs, 0);
460 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev)
462 hns_roce_bitmap_cleanup(&hr_dev->srq_table.bitmap);