drivers/infiniband/hw/irdma/hw.c

   1 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
   2 /* Copyright (c) 2015 - 2021 Intel Corporation */
   3 #include "main.h"
   4
   5 static struct irdma_rsrc_limits rsrc_limits_table[] = {
   6         [0] = {
   7                 .qplimit = SZ_128,
   8         },
   9         [1] = {
  10                 .qplimit = SZ_1K,
  11         },
  12         [2] = {
  13                 .qplimit = SZ_2K,
  14         },
  15         [3] = {
  16                 .qplimit = SZ_4K,
  17         },
  18         [4] = {
  19                 .qplimit = SZ_16K,
  20         },
  21         [5] = {
  22                 .qplimit = SZ_64K,
  23         },
  24         [6] = {
  25                 .qplimit = SZ_128K,
  26         },
  27         [7] = {
  28                 .qplimit = SZ_256K,
  29         },
  30 };
  31
  32 /* types of hmc objects */
  33 static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = {
  34         IRDMA_HMC_IW_QP,
  35         IRDMA_HMC_IW_CQ,
  36         IRDMA_HMC_IW_HTE,
  37         IRDMA_HMC_IW_ARP,
  38         IRDMA_HMC_IW_APBVT_ENTRY,
  39         IRDMA_HMC_IW_MR,
  40         IRDMA_HMC_IW_XF,
  41         IRDMA_HMC_IW_XFFL,
  42         IRDMA_HMC_IW_Q1,
  43         IRDMA_HMC_IW_Q1FL,
  44         IRDMA_HMC_IW_PBLE,
  45         IRDMA_HMC_IW_TIMER,
  46         IRDMA_HMC_IW_FSIMC,
  47         IRDMA_HMC_IW_FSIAV,
  48         IRDMA_HMC_IW_RRF,
  49         IRDMA_HMC_IW_RRFFL,
  50         IRDMA_HMC_IW_HDR,
  51         IRDMA_HMC_IW_MD,
  52         IRDMA_HMC_IW_OOISC,
  53         IRDMA_HMC_IW_OOISCFFL,
  54 };
  55
  56 /**
  57  * irdma_iwarp_ce_handler - handle iwarp completions
  58  * @iwcq: iwarp cq receiving event
  59  */
  60 static void irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq)
  61 {
  62         struct irdma_cq *cq = iwcq->back_cq;
  63
  64         if (!cq->user_mode)
  65                 atomic_set(&cq->armed, 0);
  66         if (cq->ibcq.comp_handler)
  67                 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
  68 }
  69
  70 /**
  71  * irdma_puda_ce_handler - handle puda completion events
  72  * @rf: RDMA PCI function
  73  * @cq: puda completion q for event
  74  */
  75 static void irdma_puda_ce_handler(struct irdma_pci_f *rf,
  76                                   struct irdma_sc_cq *cq)
  77 {
  78         struct irdma_sc_dev *dev = &rf->sc_dev;
  79         u32 compl_error;
  80         int status;
  81
  82         do {
  83                 status = irdma_puda_poll_cmpl(dev, cq, &compl_error);
  84                 if (status == -ENOENT)
  85                         break;
  86                 if (status) {
  87                         ibdev_dbg(to_ibdev(dev), "ERR: puda status = %d\n", status);
  88                         break;
  89                 }
  90                 if (compl_error) {
  91                         ibdev_dbg(to_ibdev(dev), "ERR: puda compl_err  =0x%x\n",
  92                                   compl_error);
  93                         break;
  94                 }
  95         } while (1);
  96
  97         irdma_sc_ccq_arm(cq);
  98 }
  99
 100 /**
 101  * irdma_process_ceq - handle ceq for completions
 102  * @rf: RDMA PCI function
 103  * @ceq: ceq having cq for completion
 104  */
 105 static void irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq)
 106 {
 107         struct irdma_sc_dev *dev = &rf->sc_dev;
 108         struct irdma_sc_ceq *sc_ceq;
 109         struct irdma_sc_cq *cq;
 110         unsigned long flags;
 111
 112         sc_ceq = &ceq->sc_ceq;
 113         do {
 114                 spin_lock_irqsave(&ceq->ce_lock, flags);
 115                 cq = irdma_sc_process_ceq(dev, sc_ceq);
 116                 if (!cq) {
 117                         spin_unlock_irqrestore(&ceq->ce_lock, flags);
 118                         break;
 119                 }
 120
 121                 if (cq->cq_type == IRDMA_CQ_TYPE_IWARP)
 122                         irdma_iwarp_ce_handler(cq);
 123
 124                 spin_unlock_irqrestore(&ceq->ce_lock, flags);
 125
 126                 if (cq->cq_type == IRDMA_CQ_TYPE_CQP)
 127                         queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work);
 128                 else if (cq->cq_type == IRDMA_CQ_TYPE_ILQ ||
 129                          cq->cq_type == IRDMA_CQ_TYPE_IEQ)
 130                         irdma_puda_ce_handler(rf, cq);
 131         } while (1);
 132 }
 133
 134 static void irdma_set_flush_fields(struct irdma_sc_qp *qp,
 135                                    struct irdma_aeqe_info *info)
 136 {
 137         qp->sq_flush_code = info->sq;
 138         qp->rq_flush_code = info->rq;
 139         qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 140
 141         switch (info->ae_id) {
 142         case IRDMA_AE_AMP_BOUNDS_VIOLATION:
 143         case IRDMA_AE_AMP_INVALID_STAG:
 144         case IRDMA_AE_AMP_RIGHTS_VIOLATION:
 145         case IRDMA_AE_AMP_UNALLOCATED_STAG:
 146         case IRDMA_AE_AMP_BAD_PD:
 147         case IRDMA_AE_AMP_BAD_QP:
 148         case IRDMA_AE_AMP_BAD_STAG_KEY:
 149         case IRDMA_AE_AMP_BAD_STAG_INDEX:
 150         case IRDMA_AE_AMP_TO_WRAP:
 151         case IRDMA_AE_PRIV_OPERATION_DENIED:
 152                 qp->flush_code = FLUSH_PROT_ERR;
 153                 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
 154                 break;
 155         case IRDMA_AE_UDA_XMIT_BAD_PD:
 156         case IRDMA_AE_WQE_UNEXPECTED_OPCODE:
 157                 qp->flush_code = FLUSH_LOC_QP_OP_ERR;
 158                 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 159                 break;
 160         case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
 161         case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT:
 162         case IRDMA_AE_UDA_L4LEN_INVALID:
 163         case IRDMA_AE_DDP_UBE_INVALID_MO:
 164         case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
 165                 qp->flush_code = FLUSH_LOC_LEN_ERR;
 166                 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 167                 break;
 168         case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
 169         case IRDMA_AE_IB_REMOTE_ACCESS_ERROR:
 170                 qp->flush_code = FLUSH_REM_ACCESS_ERR;
 171                 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
 172                 break;
 173         case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
 174         case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
 175         case IRDMA_AE_ROCE_RSP_LENGTH_ERROR:
 176         case IRDMA_AE_IB_REMOTE_OP_ERROR:
 177                 qp->flush_code = FLUSH_REM_OP_ERR;
 178                 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 179                 break;
 180         case IRDMA_AE_LCE_QP_CATASTROPHIC:
 181                 qp->flush_code = FLUSH_FATAL_ERR;
 182                 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 183                 break;
 184         case IRDMA_AE_IB_RREQ_AND_Q1_FULL:
 185                 qp->flush_code = FLUSH_GENERAL_ERR;
 186                 break;
 187         case IRDMA_AE_LLP_TOO_MANY_RETRIES:
 188                 qp->flush_code = FLUSH_RETRY_EXC_ERR;
 189                 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 190                 break;
 191         case IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS:
 192         case IRDMA_AE_AMP_MWBIND_BIND_DISABLED:
 193         case IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS:
 194         case IRDMA_AE_AMP_MWBIND_VALID_STAG:
 195                 qp->flush_code = FLUSH_MW_BIND_ERR;
 196                 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
 197                 break;
 198         case IRDMA_AE_IB_INVALID_REQUEST:
 199                 qp->flush_code = FLUSH_REM_INV_REQ_ERR;
 200                 qp->event_type = IRDMA_QP_EVENT_REQ_ERR;
 201                 break;
 202         default:
 203                 qp->flush_code = FLUSH_GENERAL_ERR;
 204                 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 205                 break;
 206         }
 207 }
 208
 209 /**
 210  * irdma_process_aeq - handle aeq events
 211  * @rf: RDMA PCI function
 212  */
 213 static void irdma_process_aeq(struct irdma_pci_f *rf)
 214 {
 215         struct irdma_sc_dev *dev = &rf->sc_dev;
 216         struct irdma_aeq *aeq = &rf->aeq;
 217         struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq;
 218         struct irdma_aeqe_info aeinfo;
 219         struct irdma_aeqe_info *info = &aeinfo;
 220         int ret;
 221         struct irdma_qp *iwqp = NULL;
 222         struct irdma_cq *iwcq = NULL;
 223         struct irdma_sc_qp *qp = NULL;
 224         struct irdma_qp_host_ctx_info *ctx_info = NULL;
 225         struct irdma_device *iwdev = rf->iwdev;
 226         unsigned long flags;
 227
 228         u32 aeqcnt = 0;
 229
 230         if (!sc_aeq->size)
 231                 return;
 232
 233         do {
 234                 memset(info, 0, sizeof(*info));
 235                 ret = irdma_sc_get_next_aeqe(sc_aeq, info);
 236                 if (ret)
 237                         break;
 238
 239                 aeqcnt++;
 240                 ibdev_dbg(&iwdev->ibdev,
 241                           "AEQ: ae_id = 0x%x bool qp=%d qp_id = %d tcp_state=%d iwarp_state=%d ae_src=%d\n",
 242                           info->ae_id, info->qp, info->qp_cq_id, info->tcp_state,
 243                           info->iwarp_state, info->ae_src);
 244
 245                 if (info->qp) {
 246                         spin_lock_irqsave(&rf->qptable_lock, flags);
 247                         iwqp = rf->qp_table[info->qp_cq_id];
 248                         if (!iwqp) {
 249                                 spin_unlock_irqrestore(&rf->qptable_lock,
 250                                                        flags);
 251                                 if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) {
 252                                         atomic_dec(&iwdev->vsi.qp_suspend_reqs);
 253                                         wake_up(&iwdev->suspend_wq);
 254                                         continue;
 255                                 }
 256                                 ibdev_dbg(&iwdev->ibdev, "AEQ: qp_id %d is already freed\n",
 257                                           info->qp_cq_id);
 258                                 continue;
 259                         }
 260                         irdma_qp_add_ref(&iwqp->ibqp);
 261                         spin_unlock_irqrestore(&rf->qptable_lock, flags);
 262                         qp = &iwqp->sc_qp;
 263                         spin_lock_irqsave(&iwqp->lock, flags);
 264                         iwqp->hw_tcp_state = info->tcp_state;
 265                         iwqp->hw_iwarp_state = info->iwarp_state;
 266                         if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE)
 267                                 iwqp->last_aeq = info->ae_id;
 268                         spin_unlock_irqrestore(&iwqp->lock, flags);
 269                         ctx_info = &iwqp->ctx_info;
 270                 } else {
 271                         if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR)
 272                                 continue;
 273                 }
 274
 275                 switch (info->ae_id) {
 276                         struct irdma_cm_node *cm_node;
 277                 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED:
 278                         cm_node = iwqp->cm_node;
 279                         if (cm_node->accept_pend) {
 280                                 atomic_dec(&cm_node->listener->pend_accepts_cnt);
 281                                 cm_node->accept_pend = 0;
 282                         }
 283                         iwqp->rts_ae_rcvd = 1;
 284                         wake_up_interruptible(&iwqp->waitq);
 285                         break;
 286                 case IRDMA_AE_LLP_FIN_RECEIVED:
 287                 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE:
 288                         if (qp->term_flags)
 289                                 break;
 290                         if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
 291                                 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT;
 292                                 if (iwqp->hw_tcp_state == IRDMA_TCP_STATE_CLOSE_WAIT &&
 293                                     iwqp->ibqp_state == IB_QPS_RTS) {
 294                                         irdma_next_iw_state(iwqp,
 295                                                             IRDMA_QP_STATE_CLOSING,
 296                                                             0, 0, 0);
 297                                         irdma_cm_disconn(iwqp);
 298                                 }
 299                                 irdma_schedule_cm_timer(iwqp->cm_node,
 300                                                         (struct irdma_puda_buf *)iwqp,
 301                                                         IRDMA_TIMER_TYPE_CLOSE,
 302                                                         1, 0);
 303                         }
 304                         break;
 305                 case IRDMA_AE_LLP_CLOSE_COMPLETE:
 306                         if (qp->term_flags)
 307                                 irdma_terminate_done(qp, 0);
 308                         else
 309                                 irdma_cm_disconn(iwqp);
 310                         break;
 311                 case IRDMA_AE_BAD_CLOSE:
 312                 case IRDMA_AE_RESET_SENT:
 313                         irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0,
 314                                             0);
 315                         irdma_cm_disconn(iwqp);
 316                         break;
 317                 case IRDMA_AE_LLP_CONNECTION_RESET:
 318                         if (atomic_read(&iwqp->close_timer_started))
 319                                 break;
 320                         irdma_cm_disconn(iwqp);
 321                         break;
 322                 case IRDMA_AE_QP_SUSPEND_COMPLETE:
 323                         if (iwqp->iwdev->vsi.tc_change_pending) {
 324                                 atomic_dec(&iwqp->sc_qp.vsi->qp_suspend_reqs);
 325                                 wake_up(&iwqp->iwdev->suspend_wq);
 326                         }
 327                         break;
 328                 case IRDMA_AE_TERMINATE_SENT:
 329                         irdma_terminate_send_fin(qp);
 330                         break;
 331                 case IRDMA_AE_LLP_TERMINATE_RECEIVED:
 332                         irdma_terminate_received(qp, info);
 333                         break;
 334                 case IRDMA_AE_CQ_OPERATION_ERROR:
 335                         ibdev_err(&iwdev->ibdev,
 336                                   "Processing an iWARP related AE for CQ misc = 0x%04X\n",
 337                                   info->ae_id);
 338
 339                         spin_lock_irqsave(&rf->cqtable_lock, flags);
 340                         iwcq = rf->cq_table[info->qp_cq_id];
 341                         if (!iwcq) {
 342                                 spin_unlock_irqrestore(&rf->cqtable_lock,
 343                                                        flags);
 344                                 ibdev_dbg(to_ibdev(dev),
 345                                           "cq_id %d is already freed\n", info->qp_cq_id);
 346                                 continue;
 347                         }
 348                         irdma_cq_add_ref(&iwcq->ibcq);
 349                         spin_unlock_irqrestore(&rf->cqtable_lock, flags);
 350
 351                         if (iwcq->ibcq.event_handler) {
 352                                 struct ib_event ibevent;
 353
 354                                 ibevent.device = iwcq->ibcq.device;
 355                                 ibevent.event = IB_EVENT_CQ_ERR;
 356                                 ibevent.element.cq = &iwcq->ibcq;
 357                                 iwcq->ibcq.event_handler(&ibevent,
 358                                                          iwcq->ibcq.cq_context);
 359                         }
 360                         irdma_cq_rem_ref(&iwcq->ibcq);
 361                         break;
 362                 case IRDMA_AE_RESET_NOT_SENT:
 363                 case IRDMA_AE_LLP_DOUBT_REACHABILITY:
 364                 case IRDMA_AE_RESOURCE_EXHAUSTION:
 365                         break;
 366                 case IRDMA_AE_PRIV_OPERATION_DENIED:
 367                 case IRDMA_AE_STAG_ZERO_INVALID:
 368                 case IRDMA_AE_IB_RREQ_AND_Q1_FULL:
 369                 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION:
 370                 case IRDMA_AE_DDP_UBE_INVALID_MO:
 371                 case IRDMA_AE_DDP_UBE_INVALID_QN:
 372                 case IRDMA_AE_DDP_NO_L_BIT:
 373                 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
 374                 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
 375                 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST:
 376                 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
 377                 case IRDMA_AE_INVALID_ARP_ENTRY:
 378                 case IRDMA_AE_INVALID_TCP_OPTION_RCVD:
 379                 case IRDMA_AE_STALE_ARP_ENTRY:
 380                 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
 381                 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
 382                 case IRDMA_AE_LLP_SYN_RECEIVED:
 383                 case IRDMA_AE_LLP_TOO_MANY_RETRIES:
 384                 case IRDMA_AE_LCE_QP_CATASTROPHIC:
 385                 case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC:
 386                 case IRDMA_AE_LCE_CQ_CATASTROPHIC:
 387                 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
 388                 default:
 389                         ibdev_err(&iwdev->ibdev, "abnormal ae_id = 0x%x bool qp=%d qp_id = %d, ae_src=%d\n",
 390                                   info->ae_id, info->qp, info->qp_cq_id, info->ae_src);
 391                         if (rdma_protocol_roce(&iwdev->ibdev, 1)) {
 392                                 ctx_info->roce_info->err_rq_idx_valid = info->rq;
 393                                 if (info->rq) {
 394                                         ctx_info->roce_info->err_rq_idx = info->wqe_idx;
 395                                         irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va,
 396                                                                 ctx_info);
 397                                 }
 398                                 irdma_set_flush_fields(qp, info);
 399                                 irdma_cm_disconn(iwqp);
 400                                 break;
 401                         }
 402                         ctx_info->iwarp_info->err_rq_idx_valid = info->rq;
 403                         if (info->rq) {
 404                                 ctx_info->iwarp_info->err_rq_idx = info->wqe_idx;
 405                                 ctx_info->tcp_info_valid = false;
 406                                 ctx_info->iwarp_info_valid = true;
 407                                 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va,
 408                                                    ctx_info);
 409                         }
 410                         if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS &&
 411                             iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) {
 412                                 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0);
 413                                 irdma_cm_disconn(iwqp);
 414                         } else {
 415                                 irdma_terminate_connection(qp, info);
 416                         }
 417                         break;
 418                 }
 419                 if (info->qp)
 420                         irdma_qp_rem_ref(&iwqp->ibqp);
 421         } while (1);
 422
 423         if (aeqcnt)
 424                 irdma_sc_repost_aeq_entries(dev, aeqcnt);
 425 }
 426
 427 /**
 428  * irdma_ena_intr - set up device interrupts
 429  * @dev: hardware control device structure
 430  * @msix_id: id of the interrupt to be enabled
 431  */
 432 static void irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id)
 433 {
 434         dev->irq_ops->irdma_en_irq(dev, msix_id);
 435 }
 436
 437 /**
 438  * irdma_dpc - tasklet for aeq and ceq 0
 439  * @t: tasklet_struct ptr
 440  */
 441 static void irdma_dpc(struct tasklet_struct *t)
 442 {
 443         struct irdma_pci_f *rf = from_tasklet(rf, t, dpc_tasklet);
 444
 445         if (rf->msix_shared)
 446                 irdma_process_ceq(rf, rf->ceqlist);
 447         irdma_process_aeq(rf);
 448         irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx);
 449 }
 450
 451 /**
 452  * irdma_ceq_dpc - dpc handler for CEQ
 453  * @t: tasklet_struct ptr
 454  */
 455 static void irdma_ceq_dpc(struct tasklet_struct *t)
 456 {
 457         struct irdma_ceq *iwceq = from_tasklet(iwceq, t, dpc_tasklet);
 458         struct irdma_pci_f *rf = iwceq->rf;
 459
 460         irdma_process_ceq(rf, iwceq);
 461         irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx);
 462 }
 463
 464 /**
 465  * irdma_save_msix_info - copy msix vector information to iwarp device
 466  * @rf: RDMA PCI function
 467  *
 468  * Allocate iwdev msix table and copy the msix info to the table
 469  * Return 0 if successful, otherwise return error
 470  */
 471 static int irdma_save_msix_info(struct irdma_pci_f *rf)
 472 {
 473         struct irdma_qvlist_info *iw_qvlist;
 474         struct irdma_qv_info *iw_qvinfo;
 475         struct msix_entry *pmsix;
 476         u32 ceq_idx;
 477         u32 i;
 478         size_t size;
 479
 480         if (!rf->msix_count)
 481                 return -EINVAL;
 482
 483         size = sizeof(struct irdma_msix_vector) * rf->msix_count;
 484         size += struct_size(iw_qvlist, qv_info, rf->msix_count);
 485         rf->iw_msixtbl = kzalloc(size, GFP_KERNEL);
 486         if (!rf->iw_msixtbl)
 487                 return -ENOMEM;
 488
 489         rf->iw_qvlist = (struct irdma_qvlist_info *)
 490                         (&rf->iw_msixtbl[rf->msix_count]);
 491         iw_qvlist = rf->iw_qvlist;
 492         iw_qvinfo = iw_qvlist->qv_info;
 493         iw_qvlist->num_vectors = rf->msix_count;
 494         if (rf->msix_count <= num_online_cpus())
 495                 rf->msix_shared = true;
 496         else if (rf->msix_count > num_online_cpus() + 1)
 497                 rf->msix_count = num_online_cpus() + 1;
 498
 499         pmsix = rf->msix_entries;
 500         for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) {
 501                 rf->iw_msixtbl[i].idx = pmsix->entry;
 502                 rf->iw_msixtbl[i].irq = pmsix->vector;
 503                 rf->iw_msixtbl[i].cpu_affinity = ceq_idx;
 504                 if (!i) {
 505                         iw_qvinfo->aeq_idx = 0;
 506                         if (rf->msix_shared)
 507                                 iw_qvinfo->ceq_idx = ceq_idx++;
 508                         else
 509                                 iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX;
 510                 } else {
 511                         iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX;
 512                         iw_qvinfo->ceq_idx = ceq_idx++;
 513                 }
 514                 iw_qvinfo->itr_idx = 3;
 515                 iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx;
 516                 pmsix++;
 517         }
 518
 519         return 0;
 520 }
 521
 522 /**
 523  * irdma_irq_handler - interrupt handler for aeq and ceq0
 524  * @irq: Interrupt request number
 525  * @data: RDMA PCI function
 526  */
 527 static irqreturn_t irdma_irq_handler(int irq, void *data)
 528 {
 529         struct irdma_pci_f *rf = data;
 530
 531         tasklet_schedule(&rf->dpc_tasklet);
 532
 533         return IRQ_HANDLED;
 534 }
 535
 536 /**
 537  * irdma_ceq_handler - interrupt handler for ceq
 538  * @irq: interrupt request number
 539  * @data: ceq pointer
 540  */
 541 static irqreturn_t irdma_ceq_handler(int irq, void *data)
 542 {
 543         struct irdma_ceq *iwceq = data;
 544
 545         if (iwceq->irq != irq)
 546                 ibdev_err(to_ibdev(&iwceq->rf->sc_dev), "expected irq = %d received irq = %d\n",
 547                           iwceq->irq, irq);
 548         tasklet_schedule(&iwceq->dpc_tasklet);
 549
 550         return IRQ_HANDLED;
 551 }
 552
 553 /**
 554  * irdma_destroy_irq - destroy device interrupts
 555  * @rf: RDMA PCI function
 556  * @msix_vec: msix vector to disable irq
 557  * @dev_id: parameter to pass to free_irq (used during irq setup)
 558  *
 559  * The function is called when destroying aeq/ceq
 560  */
 561 static void irdma_destroy_irq(struct irdma_pci_f *rf,
 562                               struct irdma_msix_vector *msix_vec, void *dev_id)
 563 {
 564         struct irdma_sc_dev *dev = &rf->sc_dev;
 565
 566         dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx);
 567         irq_update_affinity_hint(msix_vec->irq, NULL);
 568         free_irq(msix_vec->irq, dev_id);
 569 }
 570
 571 /**
 572  * irdma_destroy_cqp  - destroy control qp
 573  * @rf: RDMA PCI function
 574  *
 575  * Issue destroy cqp request and
 576  * free the resources associated with the cqp
 577  */
 578 static void irdma_destroy_cqp(struct irdma_pci_f *rf)
 579 {
 580         struct irdma_sc_dev *dev = &rf->sc_dev;
 581         struct irdma_cqp *cqp = &rf->cqp;
 582         int status = 0;
 583
 584         if (rf->cqp_cmpl_wq)
 585                 destroy_workqueue(rf->cqp_cmpl_wq);
 586
 587         status = irdma_sc_cqp_destroy(dev->cqp);
 588         if (status)
 589                 ibdev_dbg(to_ibdev(dev), "ERR: Destroy CQP failed %d\n", status);
 590
 591         irdma_cleanup_pending_cqp_op(rf);
 592         dma_free_coherent(dev->hw->device, cqp->sq.size, cqp->sq.va,
 593                           cqp->sq.pa);
 594         cqp->sq.va = NULL;
 595         kfree(cqp->scratch_array);
 596         cqp->scratch_array = NULL;
 597         kfree(cqp->cqp_requests);
 598         cqp->cqp_requests = NULL;
 599 }
 600
 601 static void irdma_destroy_virt_aeq(struct irdma_pci_f *rf)
 602 {
 603         struct irdma_aeq *aeq = &rf->aeq;
 604         u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE);
 605         dma_addr_t *pg_arr = (dma_addr_t *)aeq->palloc.level1.addr;
 606
 607         irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt);
 608         irdma_free_pble(rf->pble_rsrc, &aeq->palloc);
 609         vfree(aeq->mem.va);
 610 }
 611
 612 /**
 613  * irdma_destroy_aeq - destroy aeq
 614  * @rf: RDMA PCI function
 615  *
 616  * Issue a destroy aeq request and
 617  * free the resources associated with the aeq
 618  * The function is called during driver unload
 619  */
 620 static void irdma_destroy_aeq(struct irdma_pci_f *rf)
 621 {
 622         struct irdma_sc_dev *dev = &rf->sc_dev;
 623         struct irdma_aeq *aeq = &rf->aeq;
 624         int status = -EBUSY;
 625
 626         if (!rf->msix_shared) {
 627                 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, rf->iw_msixtbl->idx, false);
 628                 irdma_destroy_irq(rf, rf->iw_msixtbl, rf);
 629         }
 630         if (rf->reset)
 631                 goto exit;
 632
 633         aeq->sc_aeq.size = 0;
 634         status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY);
 635         if (status)
 636                 ibdev_dbg(to_ibdev(dev), "ERR: Destroy AEQ failed %d\n", status);
 637
 638 exit:
 639         if (aeq->virtual_map) {
 640                 irdma_destroy_virt_aeq(rf);
 641         } else {
 642                 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va,
 643                                   aeq->mem.pa);
 644                 aeq->mem.va = NULL;
 645         }
 646 }
 647
 648 /**
 649  * irdma_destroy_ceq - destroy ceq
 650  * @rf: RDMA PCI function
 651  * @iwceq: ceq to be destroyed
 652  *
 653  * Issue a destroy ceq request and
 654  * free the resources associated with the ceq
 655  */
 656 static void irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq)
 657 {
 658         struct irdma_sc_dev *dev = &rf->sc_dev;
 659         int status;
 660
 661         if (rf->reset)
 662                 goto exit;
 663
 664         status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1);
 665         if (status) {
 666                 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy command failed %d\n", status);
 667                 goto exit;
 668         }
 669
 670         status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq);
 671         if (status)
 672                 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy completion failed %d\n",
 673                           status);
 674 exit:
 675         dma_free_coherent(dev->hw->device, iwceq->mem.size, iwceq->mem.va,
 676                           iwceq->mem.pa);
 677         iwceq->mem.va = NULL;
 678 }
 679
 680 /**
 681  * irdma_del_ceq_0 - destroy ceq 0
 682  * @rf: RDMA PCI function
 683  *
 684  * Disable the ceq 0 interrupt and destroy the ceq 0
 685  */
 686 static void irdma_del_ceq_0(struct irdma_pci_f *rf)
 687 {
 688         struct irdma_ceq *iwceq = rf->ceqlist;
 689         struct irdma_msix_vector *msix_vec;
 690
 691         if (rf->msix_shared) {
 692                 msix_vec = &rf->iw_msixtbl[0];
 693                 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev,
 694                                                   msix_vec->ceq_id,
 695                                                   msix_vec->idx, false);
 696                 irdma_destroy_irq(rf, msix_vec, rf);
 697         } else {
 698                 msix_vec = &rf->iw_msixtbl[1];
 699                 irdma_destroy_irq(rf, msix_vec, iwceq);
 700         }
 701
 702         irdma_destroy_ceq(rf, iwceq);
 703         rf->sc_dev.ceq_valid = false;
 704         rf->ceqs_count = 0;
 705 }
 706
 707 /**
 708  * irdma_del_ceqs - destroy all ceq's except CEQ 0
 709  * @rf: RDMA PCI function
 710  *
 711  * Go through all of the device ceq's, except 0, and for each
 712  * ceq disable the ceq interrupt and destroy the ceq
 713  */
 714 static void irdma_del_ceqs(struct irdma_pci_f *rf)
 715 {
 716         struct irdma_ceq *iwceq = &rf->ceqlist[1];
 717         struct irdma_msix_vector *msix_vec;
 718         u32 i = 0;
 719
 720         if (rf->msix_shared)
 721                 msix_vec = &rf->iw_msixtbl[1];
 722         else
 723                 msix_vec = &rf->iw_msixtbl[2];
 724
 725         for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) {
 726                 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, msix_vec->ceq_id,
 727                                                   msix_vec->idx, false);
 728                 irdma_destroy_irq(rf, msix_vec, iwceq);
 729                 irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq,
 730                                   IRDMA_OP_CEQ_DESTROY);
 731                 dma_free_coherent(rf->sc_dev.hw->device, iwceq->mem.size,
 732                                   iwceq->mem.va, iwceq->mem.pa);
 733                 iwceq->mem.va = NULL;
 734         }
 735         rf->ceqs_count = 1;
 736 }
 737
 738 /**
 739  * irdma_destroy_ccq - destroy control cq
 740  * @rf: RDMA PCI function
 741  *
 742  * Issue destroy ccq request and
 743  * free the resources associated with the ccq
 744  */
 745 static void irdma_destroy_ccq(struct irdma_pci_f *rf)
 746 {
 747         struct irdma_sc_dev *dev = &rf->sc_dev;
 748         struct irdma_ccq *ccq = &rf->ccq;
 749         int status = 0;
 750
 751         if (!rf->reset)
 752                 status = irdma_sc_ccq_destroy(dev->ccq, 0, true);
 753         if (status)
 754                 ibdev_dbg(to_ibdev(dev), "ERR: CCQ destroy failed %d\n", status);
 755         dma_free_coherent(dev->hw->device, ccq->mem_cq.size, ccq->mem_cq.va,
 756                           ccq->mem_cq.pa);
 757         ccq->mem_cq.va = NULL;
 758 }
 759
 760 /**
 761  * irdma_close_hmc_objects_type - delete hmc objects of a given type
 762  * @dev: iwarp device
 763  * @obj_type: the hmc object type to be deleted
 764  * @hmc_info: host memory info struct
 765  * @privileged: permission to close HMC objects
 766  * @reset: true if called before reset
 767  */
 768 static void irdma_close_hmc_objects_type(struct irdma_sc_dev *dev,
 769                                          enum irdma_hmc_rsrc_type obj_type,
 770                                          struct irdma_hmc_info *hmc_info,
 771                                          bool privileged, bool reset)
 772 {
 773         struct irdma_hmc_del_obj_info info = {};
 774
 775         info.hmc_info = hmc_info;
 776         info.rsrc_type = obj_type;
 777         info.count = hmc_info->hmc_obj[obj_type].cnt;
 778         info.privileged = privileged;
 779         if (irdma_sc_del_hmc_obj(dev, &info, reset))
 780                 ibdev_dbg(to_ibdev(dev), "ERR: del HMC obj of type %d failed\n",
 781                           obj_type);
 782 }
 783
 784 /**
 785  * irdma_del_hmc_objects - remove all device hmc objects
 786  * @dev: iwarp device
 787  * @hmc_info: hmc_info to free
 788  * @privileged: permission to delete HMC objects
 789  * @reset: true if called before reset
 790  * @vers: hardware version
 791  */
 792 static void irdma_del_hmc_objects(struct irdma_sc_dev *dev,
 793                                   struct irdma_hmc_info *hmc_info, bool privileged,
 794                                   bool reset, enum irdma_vers vers)
 795 {
 796         unsigned int i;
 797
 798         for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) {
 799                 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt)
 800                         irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i],
 801                                                      hmc_info, privileged, reset);
 802                 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER)
 803                         break;
 804         }
 805 }
 806
 807 /**
 808  * irdma_create_hmc_obj_type - create hmc object of a given type
 809  * @dev: hardware control device structure
 810  * @info: information for the hmc object to create
 811  */
 812 static int irdma_create_hmc_obj_type(struct irdma_sc_dev *dev,
 813                                      struct irdma_hmc_create_obj_info *info)
 814 {
 815         return irdma_sc_create_hmc_obj(dev, info);
 816 }
 817
 818 /**
 819  * irdma_create_hmc_objs - create all hmc objects for the device
 820  * @rf: RDMA PCI function
 821  * @privileged: permission to create HMC objects
 822  * @vers: HW version
 823  *
 824  * Create the device hmc objects and allocate hmc pages
 825  * Return 0 if successful, otherwise clean up and return error
 826  */
 827 static int irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged,
 828                                  enum irdma_vers vers)
 829 {
 830         struct irdma_sc_dev *dev = &rf->sc_dev;
 831         struct irdma_hmc_create_obj_info info = {};
 832         int i, status = 0;
 833
 834         info.hmc_info = dev->hmc_info;
 835         info.privileged = privileged;
 836         info.entry_type = rf->sd_type;
 837
 838         for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) {
 839                 if (iw_hmc_obj_types[i] == IRDMA_HMC_IW_PBLE)
 840                         continue;
 841                 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) {
 842                         info.rsrc_type = iw_hmc_obj_types[i];
 843                         info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt;
 844                         info.add_sd_cnt = 0;
 845                         status = irdma_create_hmc_obj_type(dev, &info);
 846                         if (status) {
 847                                 ibdev_dbg(to_ibdev(dev),
 848                                           "ERR: create obj type %d status = %d\n",
 849                                           iw_hmc_obj_types[i], status);
 850                                 break;
 851                         }
 852                 }
 853                 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER)
 854                         break;
 855         }
 856
 857         if (!status)
 858                 return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id,
 859                                                            true, true);
 860
 861         while (i) {
 862                 i--;
 863                 /* destroy the hmc objects of a given type */
 864                 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt)
 865                         irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i],
 866                                                      dev->hmc_info, privileged,
 867                                                      false);
 868         }
 869
 870         return status;
 871 }
 872
 873 /**
 874  * irdma_obj_aligned_mem - get aligned memory from device allocated memory
 875  * @rf: RDMA PCI function
 876  * @memptr: points to the memory addresses
 877  * @size: size of memory needed
 878  * @mask: mask for the aligned memory
 879  *
 880  * Get aligned memory of the requested size and
 881  * update the memptr to point to the new aligned memory
 882  * Return 0 if successful, otherwise return no memory error
 883  */
 884 static int irdma_obj_aligned_mem(struct irdma_pci_f *rf,
 885                                  struct irdma_dma_mem *memptr, u32 size,
 886                                  u32 mask)
 887 {
 888         unsigned long va, newva;
 889         unsigned long extra;
 890
 891         va = (unsigned long)rf->obj_next.va;
 892         newva = va;
 893         if (mask)
 894                 newva = ALIGN(va, (unsigned long)mask + 1ULL);
 895         extra = newva - va;
 896         memptr->va = (u8 *)va + extra;
 897         memptr->pa = rf->obj_next.pa + extra;
 898         memptr->size = size;
 899         if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size))
 900                 return -ENOMEM;
 901
 902         rf->obj_next.va = (u8 *)memptr->va + size;
 903         rf->obj_next.pa = memptr->pa + size;
 904
 905         return 0;
 906 }
 907
 908 /**
 909  * irdma_create_cqp - create control qp
 910  * @rf: RDMA PCI function
 911  *
 912  * Return 0, if the cqp and all the resources associated with it
 913  * are successfully created, otherwise return error
 914  */
 915 static int irdma_create_cqp(struct irdma_pci_f *rf)
 916 {
 917         u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048;
 918         struct irdma_dma_mem mem;
 919         struct irdma_sc_dev *dev = &rf->sc_dev;
 920         struct irdma_cqp_init_info cqp_init_info = {};
 921         struct irdma_cqp *cqp = &rf->cqp;
 922         u16 maj_err, min_err;
 923         int i, status;
 924
 925         cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL);
 926         if (!cqp->cqp_requests)
 927                 return -ENOMEM;
 928
 929         cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL);
 930         if (!cqp->scratch_array) {
 931                 status = -ENOMEM;
 932                 goto err_scratch;
 933         }
 934
 935         dev->cqp = &cqp->sc_cqp;
 936         dev->cqp->dev = dev;
 937         cqp->sq.size = ALIGN(sizeof(struct irdma_cqp_sq_wqe) * sqsize,
 938                              IRDMA_CQP_ALIGNMENT);
 939         cqp->sq.va = dma_alloc_coherent(dev->hw->device, cqp->sq.size,
 940                                         &cqp->sq.pa, GFP_KERNEL);
 941         if (!cqp->sq.va) {
 942                 status = -ENOMEM;
 943                 goto err_sq;
 944         }
 945
 946         status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx),
 947                                        IRDMA_HOST_CTX_ALIGNMENT_M);
 948         if (status)
 949                 goto err_ctx;
 950
 951         dev->cqp->host_ctx_pa = mem.pa;
 952         dev->cqp->host_ctx = mem.va;
 953         /* populate the cqp init info */
 954         cqp_init_info.dev = dev;
 955         cqp_init_info.sq_size = sqsize;
 956         cqp_init_info.sq = cqp->sq.va;
 957         cqp_init_info.sq_pa = cqp->sq.pa;
 958         cqp_init_info.host_ctx_pa = mem.pa;
 959         cqp_init_info.host_ctx = mem.va;
 960         cqp_init_info.hmc_profile = rf->rsrc_profile;
 961         cqp_init_info.scratch_array = cqp->scratch_array;
 962         cqp_init_info.protocol_used = rf->protocol_used;
 963
 964         switch (rf->rdma_ver) {
 965         case IRDMA_GEN_1:
 966                 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1;
 967                 break;
 968         case IRDMA_GEN_2:
 969                 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2;
 970                 break;
 971         }
 972         status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info);
 973         if (status) {
 974                 ibdev_dbg(to_ibdev(dev), "ERR: cqp init status %d\n", status);
 975                 goto err_ctx;
 976         }
 977
 978         spin_lock_init(&cqp->req_lock);
 979         spin_lock_init(&cqp->compl_lock);
 980
 981         status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err);
 982         if (status) {
 983                 ibdev_dbg(to_ibdev(dev),
 984                           "ERR: cqp create failed - status %d maj_err %d min_err %d\n",
 985                           status, maj_err, min_err);
 986                 goto err_ctx;
 987         }
 988
 989         INIT_LIST_HEAD(&cqp->cqp_avail_reqs);
 990         INIT_LIST_HEAD(&cqp->cqp_pending_reqs);
 991
 992         /* init the waitqueue of the cqp_requests and add them to the list */
 993         for (i = 0; i < sqsize; i++) {
 994                 init_waitqueue_head(&cqp->cqp_requests[i].waitq);
 995                 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs);
 996         }
 997         init_waitqueue_head(&cqp->remove_wq);
 998         return 0;
 999
1000 err_ctx:
1001         dma_free_coherent(dev->hw->device, cqp->sq.size,
1002                           cqp->sq.va, cqp->sq.pa);
1003         cqp->sq.va = NULL;
1004 err_sq:
1005         kfree(cqp->scratch_array);
1006         cqp->scratch_array = NULL;
1007 err_scratch:
1008         kfree(cqp->cqp_requests);
1009         cqp->cqp_requests = NULL;
1010
1011         return status;
1012 }
1013
1014 /**
1015  * irdma_create_ccq - create control cq
1016  * @rf: RDMA PCI function
1017  *
1018  * Return 0, if the ccq and the resources associated with it
1019  * are successfully created, otherwise return error
1020  */
1021 static int irdma_create_ccq(struct irdma_pci_f *rf)
1022 {
1023         struct irdma_sc_dev *dev = &rf->sc_dev;
1024         struct irdma_ccq_init_info info = {};
1025         struct irdma_ccq *ccq = &rf->ccq;
1026         int status;
1027
1028         dev->ccq = &ccq->sc_cq;
1029         dev->ccq->dev = dev;
1030         info.dev = dev;
1031         ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area);
1032         ccq->mem_cq.size = ALIGN(sizeof(struct irdma_cqe) * IW_CCQ_SIZE,
1033                                  IRDMA_CQ0_ALIGNMENT);
1034         ccq->mem_cq.va = dma_alloc_coherent(dev->hw->device, ccq->mem_cq.size,
1035                                             &ccq->mem_cq.pa, GFP_KERNEL);
1036         if (!ccq->mem_cq.va)
1037                 return -ENOMEM;
1038
1039         status = irdma_obj_aligned_mem(rf, &ccq->shadow_area,
1040                                        ccq->shadow_area.size,
1041                                        IRDMA_SHADOWAREA_M);
1042         if (status)
1043                 goto exit;
1044
1045         ccq->sc_cq.back_cq = ccq;
1046         /* populate the ccq init info */
1047         info.cq_base = ccq->mem_cq.va;
1048         info.cq_pa = ccq->mem_cq.pa;
1049         info.num_elem = IW_CCQ_SIZE;
1050         info.shadow_area = ccq->shadow_area.va;
1051         info.shadow_area_pa = ccq->shadow_area.pa;
1052         info.ceqe_mask = false;
1053         info.ceq_id_valid = true;
1054         info.shadow_read_threshold = 16;
1055         info.vsi = &rf->default_vsi;
1056         status = irdma_sc_ccq_init(dev->ccq, &info);
1057         if (!status)
1058                 status = irdma_sc_ccq_create(dev->ccq, 0, true, true);
1059 exit:
1060         if (status) {
1061                 dma_free_coherent(dev->hw->device, ccq->mem_cq.size,
1062                                   ccq->mem_cq.va, ccq->mem_cq.pa);
1063                 ccq->mem_cq.va = NULL;
1064         }
1065
1066         return status;
1067 }
1068
1069 /**
1070  * irdma_alloc_set_mac - set up a mac address table entry
1071  * @iwdev: irdma device
1072  *
1073  * Allocate a mac ip entry and add it to the hw table Return 0
1074  * if successful, otherwise return error
1075  */
1076 static int irdma_alloc_set_mac(struct irdma_device *iwdev)
1077 {
1078         int status;
1079
1080         status = irdma_alloc_local_mac_entry(iwdev->rf,
1081                                              &iwdev->mac_ip_table_idx);
1082         if (!status) {
1083                 status = irdma_add_local_mac_entry(iwdev->rf,
1084                                                    (const u8 *)iwdev->netdev->dev_addr,
1085                                                    (u8)iwdev->mac_ip_table_idx);
1086                 if (status)
1087                         irdma_del_local_mac_entry(iwdev->rf,
1088                                                   (u8)iwdev->mac_ip_table_idx);
1089         }
1090         return status;
1091 }
1092
1093 /**
1094  * irdma_cfg_ceq_vector - set up the msix interrupt vector for
1095  * ceq
1096  * @rf: RDMA PCI function
1097  * @iwceq: ceq associated with the vector
1098  * @ceq_id: the id number of the iwceq
1099  * @msix_vec: interrupt vector information
1100  *
1101  * Allocate interrupt resources and enable irq handling
1102  * Return 0 if successful, otherwise return error
1103  */
1104 static int irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,
1105                                 u32 ceq_id, struct irdma_msix_vector *msix_vec)
1106 {
1107         int status;
1108
1109         if (rf->msix_shared && !ceq_id) {
1110                 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1,
1111                          "irdma-%s-AEQCEQ-0", dev_name(&rf->pcidev->dev));
1112                 tasklet_setup(&rf->dpc_tasklet, irdma_dpc);
1113                 status = request_irq(msix_vec->irq, irdma_irq_handler, 0,
1114                                      msix_vec->name, rf);
1115         } else {
1116                 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1,
1117                          "irdma-%s-CEQ-%d",
1118                          dev_name(&rf->pcidev->dev), ceq_id);
1119                 tasklet_setup(&iwceq->dpc_tasklet, irdma_ceq_dpc);
1120
1121                 status = request_irq(msix_vec->irq, irdma_ceq_handler, 0,
1122                                      msix_vec->name, iwceq);
1123         }
1124         cpumask_clear(&msix_vec->mask);
1125         cpumask_set_cpu(msix_vec->cpu_affinity, &msix_vec->mask);
1126         irq_update_affinity_hint(msix_vec->irq, &msix_vec->mask);
1127         if (status) {
1128                 ibdev_dbg(&rf->iwdev->ibdev, "ERR: ceq irq config fail\n");
1129                 return status;
1130         }
1131
1132         msix_vec->ceq_id = ceq_id;
1133         rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id, msix_vec->idx, true);
1134
1135         return 0;
1136 }
1137
1138 /**
1139  * irdma_cfg_aeq_vector - set up the msix vector for aeq
1140  * @rf: RDMA PCI function
1141  *
1142  * Allocate interrupt resources and enable irq handling
1143  * Return 0 if successful, otherwise return error
1144  */
1145 static int irdma_cfg_aeq_vector(struct irdma_pci_f *rf)
1146 {
1147         struct irdma_msix_vector *msix_vec = rf->iw_msixtbl;
1148         u32 ret = 0;
1149
1150         if (!rf->msix_shared) {
1151                 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1,
1152                          "irdma-%s-AEQ", dev_name(&rf->pcidev->dev));
1153                 tasklet_setup(&rf->dpc_tasklet, irdma_dpc);
1154                 ret = request_irq(msix_vec->irq, irdma_irq_handler, 0,
1155                                   msix_vec->name, rf);
1156         }
1157         if (ret) {
1158                 ibdev_dbg(&rf->iwdev->ibdev, "ERR: aeq irq config fail\n");
1159                 return -EINVAL;
1160         }
1161
1162         rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, true);
1163
1164         return 0;
1165 }
1166
1167 /**
1168  * irdma_create_ceq - create completion event queue
1169  * @rf: RDMA PCI function
1170  * @iwceq: pointer to the ceq resources to be created
1171  * @ceq_id: the id number of the iwceq
1172  * @vsi: SC vsi struct
1173  *
1174  * Return 0, if the ceq and the resources associated with it
1175  * are successfully created, otherwise return error
1176  */
1177 static int irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,
1178                             u32 ceq_id, struct irdma_sc_vsi *vsi)
1179 {
1180         int status;
1181         struct irdma_ceq_init_info info = {};
1182         struct irdma_sc_dev *dev = &rf->sc_dev;
1183         u64 scratch;
1184         u32 ceq_size;
1185
1186         info.ceq_id = ceq_id;
1187         iwceq->rf = rf;
1188         ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt,
1189                        dev->hw_attrs.max_hw_ceq_size);
1190         iwceq->mem.size = ALIGN(sizeof(struct irdma_ceqe) * ceq_size,
1191                                 IRDMA_CEQ_ALIGNMENT);
1192         iwceq->mem.va = dma_alloc_coherent(dev->hw->device, iwceq->mem.size,
1193                                            &iwceq->mem.pa, GFP_KERNEL);
1194         if (!iwceq->mem.va)
1195                 return -ENOMEM;
1196
1197         info.ceq_id = ceq_id;
1198         info.ceqe_base = iwceq->mem.va;
1199         info.ceqe_pa = iwceq->mem.pa;
1200         info.elem_cnt = ceq_size;
1201         iwceq->sc_ceq.ceq_id = ceq_id;
1202         info.dev = dev;
1203         info.vsi = vsi;
1204         scratch = (uintptr_t)&rf->cqp.sc_cqp;
1205         status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info);
1206         if (!status) {
1207                 if (dev->ceq_valid)
1208                         status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq,
1209                                                    IRDMA_OP_CEQ_CREATE);
1210                 else
1211                         status = irdma_sc_cceq_create(&iwceq->sc_ceq, scratch);
1212         }
1213
1214         if (status) {
1215                 dma_free_coherent(dev->hw->device, iwceq->mem.size,
1216                                   iwceq->mem.va, iwceq->mem.pa);
1217                 iwceq->mem.va = NULL;
1218         }
1219
1220         return status;
1221 }
1222
1223 /**
1224  * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource
1225  * @rf: RDMA PCI function
1226  *
1227  * Allocate a list for all device completion event queues
1228  * Create the ceq 0 and configure it's msix interrupt vector
1229  * Return 0, if successfully set up, otherwise return error
1230  */
1231 static int irdma_setup_ceq_0(struct irdma_pci_f *rf)
1232 {
1233         struct irdma_ceq *iwceq;
1234         struct irdma_msix_vector *msix_vec;
1235         u32 i;
1236         int status = 0;
1237         u32 num_ceqs;
1238
1239         num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs);
1240         rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL);
1241         if (!rf->ceqlist) {
1242                 status = -ENOMEM;
1243                 goto exit;
1244         }
1245
1246         iwceq = &rf->ceqlist[0];
1247         status = irdma_create_ceq(rf, iwceq, 0, &rf->default_vsi);
1248         if (status) {
1249                 ibdev_dbg(&rf->iwdev->ibdev, "ERR: create ceq status = %d\n",
1250                           status);
1251                 goto exit;
1252         }
1253
1254         spin_lock_init(&iwceq->ce_lock);
1255         i = rf->msix_shared ? 0 : 1;
1256         msix_vec = &rf->iw_msixtbl[i];
1257         iwceq->irq = msix_vec->irq;
1258         iwceq->msix_idx = msix_vec->idx;
1259         status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec);
1260         if (status) {
1261                 irdma_destroy_ceq(rf, iwceq);
1262                 goto exit;
1263         }
1264
1265         irdma_ena_intr(&rf->sc_dev, msix_vec->idx);
1266         rf->ceqs_count++;
1267
1268 exit:
1269         if (status && !rf->ceqs_count) {
1270                 kfree(rf->ceqlist);
1271                 rf->ceqlist = NULL;
1272                 return status;
1273         }
1274         rf->sc_dev.ceq_valid = true;
1275
1276         return 0;
1277 }
1278
1279 /**
1280  * irdma_setup_ceqs - manage the device ceq's and their interrupt resources
1281  * @rf: RDMA PCI function
1282  * @vsi: VSI structure for this CEQ
1283  *
1284  * Allocate a list for all device completion event queues
1285  * Create the ceq's and configure their msix interrupt vectors
1286  * Return 0, if ceqs are successfully set up, otherwise return error
1287  */
1288 static int irdma_setup_ceqs(struct irdma_pci_f *rf, struct irdma_sc_vsi *vsi)
1289 {
1290         u32 i;
1291         u32 ceq_id;
1292         struct irdma_ceq *iwceq;
1293         struct irdma_msix_vector *msix_vec;
1294         int status;
1295         u32 num_ceqs;
1296
1297         num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs);
1298         i = (rf->msix_shared) ? 1 : 2;
1299         for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) {
1300                 iwceq = &rf->ceqlist[ceq_id];
1301                 status = irdma_create_ceq(rf, iwceq, ceq_id, vsi);
1302                 if (status) {
1303                         ibdev_dbg(&rf->iwdev->ibdev,
1304                                   "ERR: create ceq status = %d\n", status);
1305                         goto del_ceqs;
1306                 }
1307                 spin_lock_init(&iwceq->ce_lock);
1308                 msix_vec = &rf->iw_msixtbl[i];
1309                 iwceq->irq = msix_vec->irq;
1310                 iwceq->msix_idx = msix_vec->idx;
1311                 status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec);
1312                 if (status) {
1313                         irdma_destroy_ceq(rf, iwceq);
1314                         goto del_ceqs;
1315                 }
1316                 irdma_ena_intr(&rf->sc_dev, msix_vec->idx);
1317                 rf->ceqs_count++;
1318         }
1319
1320         return 0;
1321
1322 del_ceqs:
1323         irdma_del_ceqs(rf);
1324
1325         return status;
1326 }
1327
1328 static int irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size)
1329 {
1330         struct irdma_aeq *aeq = &rf->aeq;
1331         dma_addr_t *pg_arr;
1332         u32 pg_cnt;
1333         int status;
1334
1335         if (rf->rdma_ver < IRDMA_GEN_2)
1336                 return -EOPNOTSUPP;
1337
1338         aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size;
1339         aeq->mem.va = vzalloc(aeq->mem.size);
1340
1341         if (!aeq->mem.va)
1342                 return -ENOMEM;
1343
1344         pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE);
1345         status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true);
1346         if (status) {
1347                 vfree(aeq->mem.va);
1348                 return status;
1349         }
1350
1351         pg_arr = (dma_addr_t *)aeq->palloc.level1.addr;
1352         status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt);
1353         if (status) {
1354                 irdma_free_pble(rf->pble_rsrc, &aeq->palloc);
1355                 vfree(aeq->mem.va);
1356                 return status;
1357         }
1358
1359         return 0;
1360 }
1361
1362 /**
1363  * irdma_create_aeq - create async event queue
1364  * @rf: RDMA PCI function
1365  *
1366  * Return 0, if the aeq and the resources associated with it
1367  * are successfully created, otherwise return error
1368  */
1369 static int irdma_create_aeq(struct irdma_pci_f *rf)
1370 {
1371         struct irdma_aeq_init_info info = {};
1372         struct irdma_sc_dev *dev = &rf->sc_dev;
1373         struct irdma_aeq *aeq = &rf->aeq;
1374         struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info;
1375         u32 aeq_size;
1376         u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1;
1377         int status;
1378
1379         aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt +
1380                    hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt;
1381         aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size);
1382
1383         aeq->mem.size = ALIGN(sizeof(struct irdma_sc_aeqe) * aeq_size,
1384                               IRDMA_AEQ_ALIGNMENT);
1385         aeq->mem.va = dma_alloc_coherent(dev->hw->device, aeq->mem.size,
1386                                          &aeq->mem.pa,
1387                                          GFP_KERNEL | __GFP_NOWARN);
1388         if (aeq->mem.va)
1389                 goto skip_virt_aeq;
1390
1391         /* physically mapped aeq failed. setup virtual aeq */
1392         status = irdma_create_virt_aeq(rf, aeq_size);
1393         if (status)
1394                 return status;
1395
1396         info.virtual_map = true;
1397         aeq->virtual_map = info.virtual_map;
1398         info.pbl_chunk_size = 1;
1399         info.first_pm_pbl_idx = aeq->palloc.level1.idx;
1400
1401 skip_virt_aeq:
1402         info.aeqe_base = aeq->mem.va;
1403         info.aeq_elem_pa = aeq->mem.pa;
1404         info.elem_cnt = aeq_size;
1405         info.dev = dev;
1406         info.msix_idx = rf->iw_msixtbl->idx;
1407         status = irdma_sc_aeq_init(&aeq->sc_aeq, &info);
1408         if (status)
1409                 goto err;
1410
1411         status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE);
1412         if (status)
1413                 goto err;
1414
1415         return 0;
1416
1417 err:
1418         if (aeq->virtual_map) {
1419                 irdma_destroy_virt_aeq(rf);
1420         } else {
1421                 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va,
1422                                   aeq->mem.pa);
1423                 aeq->mem.va = NULL;
1424         }
1425
1426         return status;
1427 }
1428
1429 /**
1430  * irdma_setup_aeq - set up the device aeq
1431  * @rf: RDMA PCI function
1432  *
1433  * Create the aeq and configure its msix interrupt vector
1434  * Return 0 if successful, otherwise return error
1435  */
1436 static int irdma_setup_aeq(struct irdma_pci_f *rf)
1437 {
1438         struct irdma_sc_dev *dev = &rf->sc_dev;
1439         int status;
1440
1441         status = irdma_create_aeq(rf);
1442         if (status)
1443                 return status;
1444
1445         status = irdma_cfg_aeq_vector(rf);
1446         if (status) {
1447                 irdma_destroy_aeq(rf);
1448                 return status;
1449         }
1450
1451         if (!rf->msix_shared)
1452                 irdma_ena_intr(dev, rf->iw_msixtbl[0].idx);
1453
1454         return 0;
1455 }
1456
1457 /**
1458  * irdma_initialize_ilq - create iwarp local queue for cm
1459  * @iwdev: irdma device
1460  *
1461  * Return 0 if successful, otherwise return error
1462  */
1463 static int irdma_initialize_ilq(struct irdma_device *iwdev)
1464 {
1465         struct irdma_puda_rsrc_info info = {};
1466         int status;
1467
1468         info.type = IRDMA_PUDA_RSRC_TYPE_ILQ;
1469         info.cq_id = 1;
1470         info.qp_id = 1;
1471         info.count = 1;
1472         info.pd_id = 1;
1473         info.abi_ver = IRDMA_ABI_VER;
1474         info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768);
1475         info.rq_size = info.sq_size;
1476         info.buf_size = 1024;
1477         info.tx_buf_cnt = 2 * info.sq_size;
1478         info.receive = irdma_receive_ilq;
1479         info.xmit_complete = irdma_free_sqbuf;
1480         status = irdma_puda_create_rsrc(&iwdev->vsi, &info);
1481         if (status)
1482                 ibdev_dbg(&iwdev->ibdev, "ERR: ilq create fail\n");
1483
1484         return status;
1485 }
1486
1487 /**
1488  * irdma_initialize_ieq - create iwarp exception queue
1489  * @iwdev: irdma device
1490  *
1491  * Return 0 if successful, otherwise return error
1492  */
1493 static int irdma_initialize_ieq(struct irdma_device *iwdev)
1494 {
1495         struct irdma_puda_rsrc_info info = {};
1496         int status;
1497
1498         info.type = IRDMA_PUDA_RSRC_TYPE_IEQ;
1499         info.cq_id = 2;
1500         info.qp_id = iwdev->vsi.exception_lan_q;
1501         info.count = 1;
1502         info.pd_id = 2;
1503         info.abi_ver = IRDMA_ABI_VER;
1504         info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768);
1505         info.rq_size = info.sq_size;
1506         info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD;
1507         info.tx_buf_cnt = 4096;
1508         status = irdma_puda_create_rsrc(&iwdev->vsi, &info);
1509         if (status)
1510                 ibdev_dbg(&iwdev->ibdev, "ERR: ieq create fail\n");
1511
1512         return status;
1513 }
1514
1515 /**
1516  * irdma_reinitialize_ieq - destroy and re-create ieq
1517  * @vsi: VSI structure
1518  */
1519 void irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi)
1520 {
1521         struct irdma_device *iwdev = vsi->back_vsi;
1522         struct irdma_pci_f *rf = iwdev->rf;
1523
1524         irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false);
1525         if (irdma_initialize_ieq(iwdev)) {
1526                 iwdev->rf->reset = true;
1527                 rf->gen_ops.request_reset(rf);
1528         }
1529 }
1530
1531 /**
1532  * irdma_hmc_setup - create hmc objects for the device
1533  * @rf: RDMA PCI function
1534  *
1535  * Set up the device private memory space for the number and size of
1536  * the hmc objects and create the objects
1537  * Return 0 if successful, otherwise return error
1538  */
1539 static int irdma_hmc_setup(struct irdma_pci_f *rf)
1540 {
1541         int status;
1542         u32 qpcnt;
1543
1544         qpcnt = rsrc_limits_table[rf->limits_sel].qplimit;
1545
1546         rf->sd_type = IRDMA_SD_TYPE_DIRECT;
1547         status = irdma_cfg_fpm_val(&rf->sc_dev, qpcnt);
1548         if (status)
1549                 return status;
1550
1551         status = irdma_create_hmc_objs(rf, true, rf->rdma_ver);
1552
1553         return status;
1554 }
1555
1556 /**
1557  * irdma_del_init_mem - deallocate memory resources
1558  * @rf: RDMA PCI function
1559  */
1560 static void irdma_del_init_mem(struct irdma_pci_f *rf)
1561 {
1562         struct irdma_sc_dev *dev = &rf->sc_dev;
1563
1564         kfree(dev->hmc_info->sd_table.sd_entry);
1565         dev->hmc_info->sd_table.sd_entry = NULL;
1566         vfree(rf->mem_rsrc);
1567         rf->mem_rsrc = NULL;
1568         dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va,
1569                           rf->obj_mem.pa);
1570         rf->obj_mem.va = NULL;
1571         if (rf->rdma_ver != IRDMA_GEN_1) {
1572                 bitmap_free(rf->allocated_ws_nodes);
1573                 rf->allocated_ws_nodes = NULL;
1574         }
1575         kfree(rf->ceqlist);
1576         rf->ceqlist = NULL;
1577         kfree(rf->iw_msixtbl);
1578         rf->iw_msixtbl = NULL;
1579         kfree(rf->hmc_info_mem);
1580         rf->hmc_info_mem = NULL;
1581 }
1582
1583 /**
1584  * irdma_initialize_dev - initialize device
1585  * @rf: RDMA PCI function
1586  *
1587  * Allocate memory for the hmc objects and initialize iwdev
1588  * Return 0 if successful, otherwise clean up the resources
1589  * and return error
1590  */
1591 static int irdma_initialize_dev(struct irdma_pci_f *rf)
1592 {
1593         int status;
1594         struct irdma_sc_dev *dev = &rf->sc_dev;
1595         struct irdma_device_init_info info = {};
1596         struct irdma_dma_mem mem;
1597         u32 size;
1598
1599         size = sizeof(struct irdma_hmc_pble_rsrc) +
1600                sizeof(struct irdma_hmc_info) +
1601                (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX);
1602
1603         rf->hmc_info_mem = kzalloc(size, GFP_KERNEL);
1604         if (!rf->hmc_info_mem)
1605                 return -ENOMEM;
1606
1607         rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem;
1608         dev->hmc_info = &rf->hw.hmc;
1609         dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *)
1610                                  (rf->pble_rsrc + 1);
1611
1612         status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE,
1613                                        IRDMA_FPM_QUERY_BUF_ALIGNMENT_M);
1614         if (status)
1615                 goto error;
1616
1617         info.fpm_query_buf_pa = mem.pa;
1618         info.fpm_query_buf = mem.va;
1619
1620         status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE,
1621                                        IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M);
1622         if (status)
1623                 goto error;
1624
1625         info.fpm_commit_buf_pa = mem.pa;
1626         info.fpm_commit_buf = mem.va;
1627
1628         info.bar0 = rf->hw.hw_addr;
1629         info.hmc_fn_id = rf->pf_id;
1630         info.hw = &rf->hw;
1631         status = irdma_sc_dev_init(rf->rdma_ver, &rf->sc_dev, &info);
1632         if (status)
1633                 goto error;
1634
1635         return status;
1636 error:
1637         kfree(rf->hmc_info_mem);
1638         rf->hmc_info_mem = NULL;
1639
1640         return status;
1641 }
1642
1643 /**
1644  * irdma_rt_deinit_hw - clean up the irdma device resources
1645  * @iwdev: irdma device
1646  *
1647  * remove the mac ip entry and ipv4/ipv6 addresses, destroy the
1648  * device queues and free the pble and the hmc objects
1649  */
1650 void irdma_rt_deinit_hw(struct irdma_device *iwdev)
1651 {
1652         ibdev_dbg(&iwdev->ibdev, "INIT: state = %d\n", iwdev->init_state);
1653
1654         switch (iwdev->init_state) {
1655         case IP_ADDR_REGISTERED:
1656                 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1657                         irdma_del_local_mac_entry(iwdev->rf,
1658                                                   (u8)iwdev->mac_ip_table_idx);
1659                 fallthrough;
1660         case AEQ_CREATED:
1661         case PBLE_CHUNK_MEM:
1662         case CEQS_CREATED:
1663         case IEQ_CREATED:
1664                 if (!iwdev->roce_mode)
1665                         irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ,
1666                                              iwdev->rf->reset);
1667                 fallthrough;
1668         case ILQ_CREATED:
1669                 if (!iwdev->roce_mode)
1670                         irdma_puda_dele_rsrc(&iwdev->vsi,
1671                                              IRDMA_PUDA_RSRC_TYPE_ILQ,
1672                                              iwdev->rf->reset);
1673                 break;
1674         default:
1675                 ibdev_warn(&iwdev->ibdev, "bad init_state = %d\n", iwdev->init_state);
1676                 break;
1677         }
1678
1679         irdma_cleanup_cm_core(&iwdev->cm_core);
1680         if (iwdev->vsi.pestat) {
1681                 irdma_vsi_stats_free(&iwdev->vsi);
1682                 kfree(iwdev->vsi.pestat);
1683         }
1684         if (iwdev->cleanup_wq)
1685                 destroy_workqueue(iwdev->cleanup_wq);
1686 }
1687
1688 static int irdma_setup_init_state(struct irdma_pci_f *rf)
1689 {
1690         int status;
1691
1692         status = irdma_save_msix_info(rf);
1693         if (status)
1694                 return status;
1695
1696         rf->hw.device = &rf->pcidev->dev;
1697         rf->obj_mem.size = ALIGN(8192, IRDMA_HW_PAGE_SIZE);
1698         rf->obj_mem.va = dma_alloc_coherent(rf->hw.device, rf->obj_mem.size,
1699                                             &rf->obj_mem.pa, GFP_KERNEL);
1700         if (!rf->obj_mem.va) {
1701                 status = -ENOMEM;
1702                 goto clean_msixtbl;
1703         }
1704
1705         rf->obj_next = rf->obj_mem;
1706         status = irdma_initialize_dev(rf);
1707         if (status)
1708                 goto clean_obj_mem;
1709
1710         return 0;
1711
1712 clean_obj_mem:
1713         dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va,
1714                           rf->obj_mem.pa);
1715         rf->obj_mem.va = NULL;
1716 clean_msixtbl:
1717         kfree(rf->iw_msixtbl);
1718         rf->iw_msixtbl = NULL;
1719         return status;
1720 }
1721
1722 /**
1723  * irdma_get_used_rsrc - determine resources used internally
1724  * @iwdev: irdma device
1725  *
1726  * Called at the end of open to get all internal allocations
1727  */
1728 static void irdma_get_used_rsrc(struct irdma_device *iwdev)
1729 {
1730         iwdev->rf->used_pds = find_first_zero_bit(iwdev->rf->allocated_pds,
1731                                                  iwdev->rf->max_pd);
1732         iwdev->rf->used_qps = find_first_zero_bit(iwdev->rf->allocated_qps,
1733                                                  iwdev->rf->max_qp);
1734         iwdev->rf->used_cqs = find_first_zero_bit(iwdev->rf->allocated_cqs,
1735                                                  iwdev->rf->max_cq);
1736         iwdev->rf->used_mrs = find_first_zero_bit(iwdev->rf->allocated_mrs,
1737                                                  iwdev->rf->max_mr);
1738 }
1739
1740 void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf)
1741 {
1742         enum init_completion_state state = rf->init_state;
1743
1744         rf->init_state = INVALID_STATE;
1745         if (rf->rsrc_created) {
1746                 irdma_destroy_aeq(rf);
1747                 irdma_destroy_pble_prm(rf->pble_rsrc);
1748                 irdma_del_ceqs(rf);
1749                 rf->rsrc_created = false;
1750         }
1751         switch (state) {
1752         case CEQ0_CREATED:
1753                 irdma_del_ceq_0(rf);
1754                 fallthrough;
1755         case CCQ_CREATED:
1756                 irdma_destroy_ccq(rf);
1757                 fallthrough;
1758         case HW_RSRC_INITIALIZED:
1759         case HMC_OBJS_CREATED:
1760                 irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true,
1761                                       rf->reset, rf->rdma_ver);
1762                 fallthrough;
1763         case CQP_CREATED:
1764                 irdma_destroy_cqp(rf);
1765                 fallthrough;
1766         case INITIAL_STATE:
1767                 irdma_del_init_mem(rf);
1768                 break;
1769         case INVALID_STATE:
1770         default:
1771                 ibdev_warn(&rf->iwdev->ibdev, "bad init_state = %d\n", rf->init_state);
1772                 break;
1773         }
1774 }
1775
1776 /**
1777  * irdma_rt_init_hw - Initializes runtime portion of HW
1778  * @iwdev: irdma device
1779  * @l2params: qos, tc, mtu info from netdev driver
1780  *
1781  * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma
1782  * device resource objects.
1783  */
1784 int irdma_rt_init_hw(struct irdma_device *iwdev,
1785                      struct irdma_l2params *l2params)
1786 {
1787         struct irdma_pci_f *rf = iwdev->rf;
1788         struct irdma_sc_dev *dev = &rf->sc_dev;
1789         struct irdma_vsi_init_info vsi_info = {};
1790         struct irdma_vsi_stats_info stats_info = {};
1791         int status;
1792
1793         vsi_info.dev = dev;
1794         vsi_info.back_vsi = iwdev;
1795         vsi_info.params = l2params;
1796         vsi_info.pf_data_vsi_num = iwdev->vsi_num;
1797         vsi_info.register_qset = rf->gen_ops.register_qset;
1798         vsi_info.unregister_qset = rf->gen_ops.unregister_qset;
1799         vsi_info.exception_lan_q = 2;
1800         irdma_sc_vsi_init(&iwdev->vsi, &vsi_info);
1801
1802         status = irdma_setup_cm_core(iwdev, rf->rdma_ver);
1803         if (status)
1804                 return status;
1805
1806         stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL);
1807         if (!stats_info.pestat) {
1808                 irdma_cleanup_cm_core(&iwdev->cm_core);
1809                 return -ENOMEM;
1810         }
1811         stats_info.fcn_id = dev->hmc_fn_id;
1812         status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info);
1813         if (status) {
1814                 irdma_cleanup_cm_core(&iwdev->cm_core);
1815                 kfree(stats_info.pestat);
1816                 return status;
1817         }
1818
1819         do {
1820                 if (!iwdev->roce_mode) {
1821                         status = irdma_initialize_ilq(iwdev);
1822                         if (status)
1823                                 break;
1824                         iwdev->init_state = ILQ_CREATED;
1825                         status = irdma_initialize_ieq(iwdev);
1826                         if (status)
1827                                 break;
1828                         iwdev->init_state = IEQ_CREATED;
1829                 }
1830                 if (!rf->rsrc_created) {
1831                         status = irdma_setup_ceqs(rf, &iwdev->vsi);
1832                         if (status)
1833                                 break;
1834
1835                         iwdev->init_state = CEQS_CREATED;
1836
1837                         status = irdma_hmc_init_pble(&rf->sc_dev,
1838                                                      rf->pble_rsrc);
1839                         if (status) {
1840                                 irdma_del_ceqs(rf);
1841                                 break;
1842                         }
1843
1844                         iwdev->init_state = PBLE_CHUNK_MEM;
1845
1846                         status = irdma_setup_aeq(rf);
1847                         if (status) {
1848                                 irdma_destroy_pble_prm(rf->pble_rsrc);
1849                                 irdma_del_ceqs(rf);
1850                                 break;
1851                         }
1852                         iwdev->init_state = AEQ_CREATED;
1853                         rf->rsrc_created = true;
1854                 }
1855
1856                 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1857                         irdma_alloc_set_mac(iwdev);
1858                 irdma_add_ip(iwdev);
1859                 iwdev->init_state = IP_ADDR_REGISTERED;
1860
1861                 /* handles asynch cleanup tasks - disconnect CM , free qp,
1862                  * free cq bufs
1863                  */
1864                 iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq",
1865                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
1866                 if (!iwdev->cleanup_wq)
1867                         return -ENOMEM;
1868                 irdma_get_used_rsrc(iwdev);
1869                 init_waitqueue_head(&iwdev->suspend_wq);
1870
1871                 return 0;
1872         } while (0);
1873
1874         dev_err(&rf->pcidev->dev, "HW runtime init FAIL status = %d last cmpl = %d\n",
1875                 status, iwdev->init_state);
1876         irdma_rt_deinit_hw(iwdev);
1877
1878         return status;
1879 }
1880
1881 /**
1882  * irdma_ctrl_init_hw - Initializes control portion of HW
1883  * @rf: RDMA PCI function
1884  *
1885  * Create admin queues, HMC obejcts and RF resource objects
1886  */
1887 int irdma_ctrl_init_hw(struct irdma_pci_f *rf)
1888 {
1889         struct irdma_sc_dev *dev = &rf->sc_dev;
1890         int status;
1891         do {
1892                 status = irdma_setup_init_state(rf);
1893                 if (status)
1894                         break;
1895                 rf->init_state = INITIAL_STATE;
1896
1897                 status = irdma_create_cqp(rf);
1898                 if (status)
1899                         break;
1900                 rf->init_state = CQP_CREATED;
1901
1902                 status = irdma_hmc_setup(rf);
1903                 if (status)
1904                         break;
1905                 rf->init_state = HMC_OBJS_CREATED;
1906
1907                 status = irdma_initialize_hw_rsrc(rf);
1908                 if (status)
1909                         break;
1910                 rf->init_state = HW_RSRC_INITIALIZED;
1911
1912                 status = irdma_create_ccq(rf);
1913                 if (status)
1914                         break;
1915                 rf->init_state = CCQ_CREATED;
1916
1917                 dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT;
1918                 if (rf->rdma_ver != IRDMA_GEN_1) {
1919                         status = irdma_get_rdma_features(dev);
1920                         if (status)
1921                                 break;
1922                 }
1923
1924                 status = irdma_setup_ceq_0(rf);
1925                 if (status)
1926                         break;
1927                 rf->init_state = CEQ0_CREATED;
1928                 /* Handles processing of CQP completions */
1929                 rf->cqp_cmpl_wq =
1930                         alloc_ordered_workqueue("cqp_cmpl_wq", WQ_HIGHPRI);
1931                 if (!rf->cqp_cmpl_wq) {
1932                         status = -ENOMEM;
1933                         break;
1934                 }
1935                 INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker);
1936                 irdma_sc_ccq_arm(dev->ccq);
1937                 return 0;
1938         } while (0);
1939
1940         dev_err(&rf->pcidev->dev, "IRDMA hardware initialization FAILED init_state=%d status=%d\n",
1941                 rf->init_state, status);
1942         irdma_ctrl_deinit_hw(rf);
1943         return status;
1944 }
1945
1946 /**
1947  * irdma_set_hw_rsrc - set hw memory resources.
1948  * @rf: RDMA PCI function
1949  */
1950 static void irdma_set_hw_rsrc(struct irdma_pci_f *rf)
1951 {
1952         rf->allocated_qps = (void *)(rf->mem_rsrc +
1953                    (sizeof(struct irdma_arp_entry) * rf->arp_table_size));
1954         rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)];
1955         rf->allocated_mrs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)];
1956         rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)];
1957         rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)];
1958         rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)];
1959         rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)];
1960         rf->qp_table = (struct irdma_qp **)
1961                 (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]);
1962         rf->cq_table = (struct irdma_cq **)(&rf->qp_table[rf->max_qp]);
1963
1964         spin_lock_init(&rf->rsrc_lock);
1965         spin_lock_init(&rf->arp_lock);
1966         spin_lock_init(&rf->qptable_lock);
1967         spin_lock_init(&rf->cqtable_lock);
1968         spin_lock_init(&rf->qh_list_lock);
1969 }
1970
1971 /**
1972  * irdma_calc_mem_rsrc_size - calculate memory resources size.
1973  * @rf: RDMA PCI function
1974  */
1975 static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf)
1976 {
1977         u32 rsrc_size;
1978
1979         rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size;
1980         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp);
1981         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr);
1982         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq);
1983         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd);
1984         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size);
1985         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah);
1986         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg);
1987         rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp;
1988         rsrc_size += sizeof(struct irdma_cq **) * rf->max_cq;
1989
1990         return rsrc_size;
1991 }
1992
1993 /**
1994  * irdma_initialize_hw_rsrc - initialize hw resource tracking array
1995  * @rf: RDMA PCI function
1996  */
1997 u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf)
1998 {
1999         u32 rsrc_size;
2000         u32 mrdrvbits;
2001         u32 ret;
2002
2003         if (rf->rdma_ver != IRDMA_GEN_1) {
2004                 rf->allocated_ws_nodes = bitmap_zalloc(IRDMA_MAX_WS_NODES,
2005                                                        GFP_KERNEL);
2006                 if (!rf->allocated_ws_nodes)
2007                         return -ENOMEM;
2008
2009                 set_bit(0, rf->allocated_ws_nodes);
2010                 rf->max_ws_node_id = IRDMA_MAX_WS_NODES;
2011         }
2012         rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size;
2013         rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt;
2014         rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt;
2015         rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt;
2016         rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds;
2017         rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt;
2018         rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt;
2019         rf->max_mcg = rf->max_qp;
2020
2021         rsrc_size = irdma_calc_mem_rsrc_size(rf);
2022         rf->mem_rsrc = vzalloc(rsrc_size);
2023         if (!rf->mem_rsrc) {
2024                 ret = -ENOMEM;
2025                 goto mem_rsrc_vzalloc_fail;
2026         }
2027
2028         rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc;
2029
2030         irdma_set_hw_rsrc(rf);
2031
2032         set_bit(0, rf->allocated_mrs);
2033         set_bit(0, rf->allocated_qps);
2034         set_bit(0, rf->allocated_cqs);
2035         set_bit(0, rf->allocated_pds);
2036         set_bit(0, rf->allocated_arps);
2037         set_bit(0, rf->allocated_ahs);
2038         set_bit(0, rf->allocated_mcgs);
2039         set_bit(2, rf->allocated_qps); /* qp 2 IEQ */
2040         set_bit(1, rf->allocated_qps); /* qp 1 ILQ */
2041         set_bit(1, rf->allocated_cqs);
2042         set_bit(1, rf->allocated_pds);
2043         set_bit(2, rf->allocated_cqs);
2044         set_bit(2, rf->allocated_pds);
2045
2046         INIT_LIST_HEAD(&rf->mc_qht_list.list);
2047         /* stag index mask has a minimum of 14 bits */
2048         mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14);
2049         rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits));
2050
2051         return 0;
2052
2053 mem_rsrc_vzalloc_fail:
2054         bitmap_free(rf->allocated_ws_nodes);
2055         rf->allocated_ws_nodes = NULL;
2056
2057         return ret;
2058 }
2059
2060 /**
2061  * irdma_cqp_ce_handler - handle cqp completions
2062  * @rf: RDMA PCI function
2063  * @cq: cq for cqp completions
2064  */
2065 void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq)
2066 {
2067         struct irdma_cqp_request *cqp_request;
2068         struct irdma_sc_dev *dev = &rf->sc_dev;
2069         u32 cqe_count = 0;
2070         struct irdma_ccq_cqe_info info;
2071         unsigned long flags;
2072         int ret;
2073
2074         do {
2075                 memset(&info, 0, sizeof(info));
2076                 spin_lock_irqsave(&rf->cqp.compl_lock, flags);
2077                 ret = irdma_sc_ccq_get_cqe_info(cq, &info);
2078                 spin_unlock_irqrestore(&rf->cqp.compl_lock, flags);
2079                 if (ret)
2080                         break;
2081
2082                 cqp_request = (struct irdma_cqp_request *)
2083                               (unsigned long)info.scratch;
2084                 if (info.error && irdma_cqp_crit_err(dev, cqp_request->info.cqp_cmd,
2085                                                      info.maj_err_code,
2086                                                      info.min_err_code))
2087                         ibdev_err(&rf->iwdev->ibdev, "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n",
2088                                   info.op_code, info.maj_err_code, info.min_err_code);
2089                 if (cqp_request) {
2090                         cqp_request->compl_info.maj_err_code = info.maj_err_code;
2091                         cqp_request->compl_info.min_err_code = info.min_err_code;
2092                         cqp_request->compl_info.op_ret_val = info.op_ret_val;
2093                         cqp_request->compl_info.error = info.error;
2094
2095                         if (cqp_request->waiting) {
2096                                 WRITE_ONCE(cqp_request->request_done, true);
2097                                 wake_up(&cqp_request->waitq);
2098                                 irdma_put_cqp_request(&rf->cqp, cqp_request);
2099                         } else {
2100                                 if (cqp_request->callback_fcn)
2101                                         cqp_request->callback_fcn(cqp_request);
2102                                 irdma_put_cqp_request(&rf->cqp, cqp_request);
2103                         }
2104                 }
2105
2106                 cqe_count++;
2107         } while (1);
2108
2109         if (cqe_count) {
2110                 irdma_process_bh(dev);
2111                 irdma_sc_ccq_arm(cq);
2112         }
2113 }
2114
2115 /**
2116  * cqp_compl_worker - Handle cqp completions
2117  * @work: Pointer to work structure
2118  */
2119 void cqp_compl_worker(struct work_struct *work)
2120 {
2121         struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f,
2122                                               cqp_cmpl_work);
2123         struct irdma_sc_cq *cq = &rf->ccq.sc_cq;
2124
2125         irdma_cqp_ce_handler(rf, cq);
2126 }
2127
2128 /**
2129  * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port
2130  * @cm_core: cm's core
2131  * @port: port to identify apbvt entry
2132  */
2133 static struct irdma_apbvt_entry *irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core,
2134                                                           u16 port)
2135 {
2136         struct irdma_apbvt_entry *entry;
2137
2138         hash_for_each_possible(cm_core->apbvt_hash_tbl, entry, hlist, port) {
2139                 if (entry->port == port) {
2140                         entry->use_cnt++;
2141                         return entry;
2142                 }
2143         }
2144
2145         return NULL;
2146 }
2147
2148 /**
2149  * irdma_next_iw_state - modify qp state
2150  * @iwqp: iwarp qp to modify
2151  * @state: next state for qp
2152  * @del_hash: del hash
2153  * @term: term message
2154  * @termlen: length of term message
2155  */
2156 void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term,
2157                          u8 termlen)
2158 {
2159         struct irdma_modify_qp_info info = {};
2160
2161         info.next_iwarp_state = state;
2162         info.remove_hash_idx = del_hash;
2163         info.cq_num_valid = true;
2164         info.arp_cache_idx_valid = true;
2165         info.dont_send_term = true;
2166         info.dont_send_fin = true;
2167         info.termlen = termlen;
2168
2169         if (term & IRDMAQP_TERM_SEND_TERM_ONLY)
2170                 info.dont_send_term = false;
2171         if (term & IRDMAQP_TERM_SEND_FIN_ONLY)
2172                 info.dont_send_fin = false;
2173         if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR)
2174                 info.reset_tcp_conn = true;
2175         iwqp->hw_iwarp_state = state;
2176         irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0);
2177         iwqp->iwarp_state = info.next_iwarp_state;
2178 }
2179
2180 /**
2181  * irdma_del_local_mac_entry - remove a mac entry from the hw
2182  * table
2183  * @rf: RDMA PCI function
2184  * @idx: the index of the mac ip address to delete
2185  */
2186 void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx)
2187 {
2188         struct irdma_cqp *iwcqp = &rf->cqp;
2189         struct irdma_cqp_request *cqp_request;
2190         struct cqp_cmds_info *cqp_info;
2191
2192         cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2193         if (!cqp_request)
2194                 return;
2195
2196         cqp_info = &cqp_request->info;
2197         cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY;
2198         cqp_info->post_sq = 1;
2199         cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp;
2200         cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request;
2201         cqp_info->in.u.del_local_mac_entry.entry_idx = idx;
2202         cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0;
2203
2204         irdma_handle_cqp_op(rf, cqp_request);
2205         irdma_put_cqp_request(iwcqp, cqp_request);
2206 }
2207
2208 /**
2209  * irdma_add_local_mac_entry - add a mac ip address entry to the
2210  * hw table
2211  * @rf: RDMA PCI function
2212  * @mac_addr: pointer to mac address
2213  * @idx: the index of the mac ip address to add
2214  */
2215 int irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx)
2216 {
2217         struct irdma_local_mac_entry_info *info;
2218         struct irdma_cqp *iwcqp = &rf->cqp;
2219         struct irdma_cqp_request *cqp_request;
2220         struct cqp_cmds_info *cqp_info;
2221         int status;
2222
2223         cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2224         if (!cqp_request)
2225                 return -ENOMEM;
2226
2227         cqp_info = &cqp_request->info;
2228         cqp_info->post_sq = 1;
2229         info = &cqp_info->in.u.add_local_mac_entry.info;
2230         ether_addr_copy(info->mac_addr, mac_addr);
2231         info->entry_idx = idx;
2232         cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request;
2233         cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY;
2234         cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp;
2235         cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request;
2236
2237         status = irdma_handle_cqp_op(rf, cqp_request);
2238         irdma_put_cqp_request(iwcqp, cqp_request);
2239
2240         return status;
2241 }
2242
2243 /**
2244  * irdma_alloc_local_mac_entry - allocate a mac entry
2245  * @rf: RDMA PCI function
2246  * @mac_tbl_idx: the index of the new mac address
2247  *
2248  * Allocate a mac address entry and update the mac_tbl_idx
2249  * to hold the index of the newly created mac address
2250  * Return 0 if successful, otherwise return error
2251  */
2252 int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx)
2253 {
2254         struct irdma_cqp *iwcqp = &rf->cqp;
2255         struct irdma_cqp_request *cqp_request;
2256         struct cqp_cmds_info *cqp_info;
2257         int status = 0;
2258
2259         cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2260         if (!cqp_request)
2261                 return -ENOMEM;
2262
2263         cqp_info = &cqp_request->info;
2264         cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY;
2265         cqp_info->post_sq = 1;
2266         cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp;
2267         cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request;
2268         status = irdma_handle_cqp_op(rf, cqp_request);
2269         if (!status)
2270                 *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val;
2271
2272         irdma_put_cqp_request(iwcqp, cqp_request);
2273
2274         return status;
2275 }
2276
2277 /**
2278  * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt
2279  * @iwdev: irdma device
2280  * @accel_local_port: port for apbvt
2281  * @add_port: add ordelete port
2282  */
2283 static int irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev,
2284                                       u16 accel_local_port, bool add_port)
2285 {
2286         struct irdma_apbvt_info *info;
2287         struct irdma_cqp_request *cqp_request;
2288         struct cqp_cmds_info *cqp_info;
2289         int status;
2290
2291         cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port);
2292         if (!cqp_request)
2293                 return -ENOMEM;
2294
2295         cqp_info = &cqp_request->info;
2296         info = &cqp_info->in.u.manage_apbvt_entry.info;
2297         memset(info, 0, sizeof(*info));
2298         info->add = add_port;
2299         info->port = accel_local_port;
2300         cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY;
2301         cqp_info->post_sq = 1;
2302         cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp;
2303         cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request;
2304         ibdev_dbg(&iwdev->ibdev, "DEV: %s: port=0x%04x\n",
2305                   (!add_port) ? "DELETE" : "ADD", accel_local_port);
2306
2307         status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2308         irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
2309
2310         return status;
2311 }
2312
2313 /**
2314  * irdma_add_apbvt - add tcp port to HW apbvt table
2315  * @iwdev: irdma device
2316  * @port: port for apbvt
2317  */
2318 struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port)
2319 {
2320         struct irdma_cm_core *cm_core = &iwdev->cm_core;
2321         struct irdma_apbvt_entry *entry;
2322         unsigned long flags;
2323
2324         spin_lock_irqsave(&cm_core->apbvt_lock, flags);
2325         entry = irdma_lookup_apbvt_entry(cm_core, port);
2326         if (entry) {
2327                 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2328                 return entry;
2329         }
2330
2331         entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
2332         if (!entry) {
2333                 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2334                 return NULL;
2335         }
2336
2337         entry->port = port;
2338         entry->use_cnt = 1;
2339         hash_add(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port);
2340         spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2341
2342         if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) {
2343                 kfree(entry);
2344                 return NULL;
2345         }
2346
2347         return entry;
2348 }
2349
2350 /**
2351  * irdma_del_apbvt - delete tcp port from HW apbvt table
2352  * @iwdev: irdma device
2353  * @entry: apbvt entry object
2354  */
2355 void irdma_del_apbvt(struct irdma_device *iwdev,
2356                      struct irdma_apbvt_entry *entry)
2357 {
2358         struct irdma_cm_core *cm_core = &iwdev->cm_core;
2359         unsigned long flags;
2360
2361         spin_lock_irqsave(&cm_core->apbvt_lock, flags);
2362         if (--entry->use_cnt) {
2363                 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2364                 return;
2365         }
2366
2367         hash_del(&entry->hlist);
2368         /* apbvt_lock is held across CQP delete APBVT OP (non-waiting) to
2369          * protect against race where add APBVT CQP can race ahead of the delete
2370          * APBVT for same port.
2371          */
2372         irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false);
2373         kfree(entry);
2374         spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2375 }
2376
2377 /**
2378  * irdma_manage_arp_cache - manage hw arp cache
2379  * @rf: RDMA PCI function
2380  * @mac_addr: mac address ptr
2381  * @ip_addr: ip addr for arp cache
2382  * @ipv4: flag inicating IPv4
2383  * @action: add, delete or modify
2384  */
2385 void irdma_manage_arp_cache(struct irdma_pci_f *rf,
2386                             const unsigned char *mac_addr,
2387                             u32 *ip_addr, bool ipv4, u32 action)
2388 {
2389         struct irdma_add_arp_cache_entry_info *info;
2390         struct irdma_cqp_request *cqp_request;
2391         struct cqp_cmds_info *cqp_info;
2392         int arp_index;
2393
2394         arp_index = irdma_arp_table(rf, ip_addr, ipv4, mac_addr, action);
2395         if (arp_index == -1)
2396                 return;
2397
2398         cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false);
2399         if (!cqp_request)
2400                 return;
2401
2402         cqp_info = &cqp_request->info;
2403         if (action == IRDMA_ARP_ADD) {
2404                 cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY;
2405                 info = &cqp_info->in.u.add_arp_cache_entry.info;
2406                 memset(info, 0, sizeof(*info));
2407                 info->arp_index = (u16)arp_index;
2408                 info->permanent = true;
2409                 ether_addr_copy(info->mac_addr, mac_addr);
2410                 cqp_info->in.u.add_arp_cache_entry.scratch =
2411                         (uintptr_t)cqp_request;
2412                 cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp;
2413         } else {
2414                 cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY;
2415                 cqp_info->in.u.del_arp_cache_entry.scratch =
2416                         (uintptr_t)cqp_request;
2417                 cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp;
2418                 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index;
2419         }
2420
2421         cqp_info->post_sq = 1;
2422         irdma_handle_cqp_op(rf, cqp_request);
2423         irdma_put_cqp_request(&rf->cqp, cqp_request);
2424 }
2425
2426 /**
2427  * irdma_send_syn_cqp_callback - do syn/ack after qhash
2428  * @cqp_request: qhash cqp completion
2429  */
2430 static void irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request)
2431 {
2432         struct irdma_cm_node *cm_node = cqp_request->param;
2433
2434         irdma_send_syn(cm_node, 1);
2435         irdma_rem_ref_cm_node(cm_node);
2436 }
2437
2438 /**
2439  * irdma_manage_qhash - add or modify qhash
2440  * @iwdev: irdma device
2441  * @cminfo: cm info for qhash
2442  * @etype: type (syn or quad)
2443  * @mtype: type of qhash
2444  * @cmnode: cmnode associated with connection
2445  * @wait: wait for completion
2446  */
2447 int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo,
2448                        enum irdma_quad_entry_type etype,
2449                        enum irdma_quad_hash_manage_type mtype, void *cmnode,
2450                        bool wait)
2451 {
2452         struct irdma_qhash_table_info *info;
2453         struct irdma_cqp *iwcqp = &iwdev->rf->cqp;
2454         struct irdma_cqp_request *cqp_request;
2455         struct cqp_cmds_info *cqp_info;
2456         struct irdma_cm_node *cm_node = cmnode;
2457         int status;
2458
2459         cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait);
2460         if (!cqp_request)
2461                 return -ENOMEM;
2462
2463         cqp_info = &cqp_request->info;
2464         info = &cqp_info->in.u.manage_qhash_table_entry.info;
2465         memset(info, 0, sizeof(*info));
2466         info->vsi = &iwdev->vsi;
2467         info->manage = mtype;
2468         info->entry_type = etype;
2469         if (cminfo->vlan_id < VLAN_N_VID) {
2470                 info->vlan_valid = true;
2471                 info->vlan_id = cminfo->vlan_id;
2472         } else {
2473                 info->vlan_valid = false;
2474         }
2475         info->ipv4_valid = cminfo->ipv4;
2476         info->user_pri = cminfo->user_pri;
2477         ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr);
2478         info->qp_num = cminfo->qh_qpid;
2479         info->dest_port = cminfo->loc_port;
2480         info->dest_ip[0] = cminfo->loc_addr[0];
2481         info->dest_ip[1] = cminfo->loc_addr[1];
2482         info->dest_ip[2] = cminfo->loc_addr[2];
2483         info->dest_ip[3] = cminfo->loc_addr[3];
2484         if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED ||
2485             etype == IRDMA_QHASH_TYPE_UDP_UNICAST ||
2486             etype == IRDMA_QHASH_TYPE_UDP_MCAST ||
2487             etype == IRDMA_QHASH_TYPE_ROCE_MCAST ||
2488             etype == IRDMA_QHASH_TYPE_ROCEV2_HW) {
2489                 info->src_port = cminfo->rem_port;
2490                 info->src_ip[0] = cminfo->rem_addr[0];
2491                 info->src_ip[1] = cminfo->rem_addr[1];
2492                 info->src_ip[2] = cminfo->rem_addr[2];
2493                 info->src_ip[3] = cminfo->rem_addr[3];
2494         }
2495         if (cmnode) {
2496                 cqp_request->callback_fcn = irdma_send_syn_cqp_callback;
2497                 cqp_request->param = cmnode;
2498                 if (!wait)
2499                         refcount_inc(&cm_node->refcnt);
2500         }
2501         if (info->ipv4_valid)
2502                 ibdev_dbg(&iwdev->ibdev,
2503                           "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI4 rem_addr=%pI4 mac=%pM, vlan_id=%d cm_node=%p\n",
2504                           (!mtype) ? "DELETE" : "ADD",
2505                           __builtin_return_address(0), info->dest_port,
2506                           info->src_port, info->dest_ip, info->src_ip,
2507                           info->mac_addr, cminfo->vlan_id,
2508                           cmnode ? cmnode : NULL);
2509         else
2510                 ibdev_dbg(&iwdev->ibdev,
2511                           "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI6 rem_addr=%pI6 mac=%pM, vlan_id=%d cm_node=%p\n",
2512                           (!mtype) ? "DELETE" : "ADD",
2513                           __builtin_return_address(0), info->dest_port,
2514                           info->src_port, info->dest_ip, info->src_ip,
2515                           info->mac_addr, cminfo->vlan_id,
2516                           cmnode ? cmnode : NULL);
2517
2518         cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp;
2519         cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request;
2520         cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY;
2521         cqp_info->post_sq = 1;
2522         status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2523         if (status && cm_node && !wait)
2524                 irdma_rem_ref_cm_node(cm_node);
2525
2526         irdma_put_cqp_request(iwcqp, cqp_request);
2527
2528         return status;
2529 }
2530
2531 /**
2532  * irdma_hw_flush_wqes_callback - Check return code after flush
2533  * @cqp_request: qhash cqp completion
2534  */
2535 static void irdma_hw_flush_wqes_callback(struct irdma_cqp_request *cqp_request)
2536 {
2537         struct irdma_qp_flush_info *hw_info;
2538         struct irdma_sc_qp *qp;
2539         struct irdma_qp *iwqp;
2540         struct cqp_cmds_info *cqp_info;
2541
2542         cqp_info = &cqp_request->info;
2543         hw_info = &cqp_info->in.u.qp_flush_wqes.info;
2544         qp = cqp_info->in.u.qp_flush_wqes.qp;
2545         iwqp = qp->qp_uk.back_qp;
2546
2547         if (cqp_request->compl_info.maj_err_code)
2548                 return;
2549
2550         if (hw_info->rq &&
2551             (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED ||
2552              cqp_request->compl_info.min_err_code == 0)) {
2553                 /* RQ WQE flush was requested but did not happen */
2554                 qp->qp_uk.rq_flush_complete = true;
2555         }
2556         if (hw_info->sq &&
2557             (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED ||
2558              cqp_request->compl_info.min_err_code == 0)) {
2559                 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) {
2560                         ibdev_err(&iwqp->iwdev->ibdev, "Flush QP[%d] failed, SQ has more work",
2561                                   qp->qp_uk.qp_id);
2562                         irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC);
2563                 }
2564                 qp->qp_uk.sq_flush_complete = true;
2565         }
2566 }
2567
2568 /**
2569  * irdma_hw_flush_wqes - flush qp's wqe
2570  * @rf: RDMA PCI function
2571  * @qp: hardware control qp
2572  * @info: info for flush
2573  * @wait: flag wait for completion
2574  */
2575 int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
2576                         struct irdma_qp_flush_info *info, bool wait)
2577 {
2578         int status;
2579         struct irdma_qp_flush_info *hw_info;
2580         struct irdma_cqp_request *cqp_request;
2581         struct cqp_cmds_info *cqp_info;
2582         struct irdma_qp *iwqp = qp->qp_uk.back_qp;
2583
2584         cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
2585         if (!cqp_request)
2586                 return -ENOMEM;
2587
2588         cqp_info = &cqp_request->info;
2589         if (!wait)
2590                 cqp_request->callback_fcn = irdma_hw_flush_wqes_callback;
2591         hw_info = &cqp_request->info.in.u.qp_flush_wqes.info;
2592         memcpy(hw_info, info, sizeof(*hw_info));
2593         cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES;
2594         cqp_info->post_sq = 1;
2595         cqp_info->in.u.qp_flush_wqes.qp = qp;
2596         cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request;
2597         status = irdma_handle_cqp_op(rf, cqp_request);
2598         if (status) {
2599                 qp->qp_uk.sq_flush_complete = true;
2600                 qp->qp_uk.rq_flush_complete = true;
2601                 irdma_put_cqp_request(&rf->cqp, cqp_request);
2602                 return status;
2603         }
2604
2605         if (!wait || cqp_request->compl_info.maj_err_code)
2606                 goto put_cqp;
2607
2608         if (info->rq) {
2609                 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED ||
2610                     cqp_request->compl_info.min_err_code == 0) {
2611                         /* RQ WQE flush was requested but did not happen */
2612                         qp->qp_uk.rq_flush_complete = true;
2613                 }
2614         }
2615         if (info->sq) {
2616                 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED ||
2617                     cqp_request->compl_info.min_err_code == 0) {
2618                         /*
2619                          * Handling case where WQE is posted to empty SQ when
2620                          * flush has not completed
2621                          */
2622                         if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) {
2623                                 struct irdma_cqp_request *new_req;
2624
2625                                 if (!qp->qp_uk.sq_flush_complete)
2626                                         goto put_cqp;
2627                                 qp->qp_uk.sq_flush_complete = false;
2628                                 qp->flush_sq = false;
2629
2630                                 info->rq = false;
2631                                 info->sq = true;
2632                                 new_req = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
2633                                 if (!new_req) {
2634                                         status = -ENOMEM;
2635                                         goto put_cqp;
2636                                 }
2637                                 cqp_info = &new_req->info;
2638                                 hw_info = &new_req->info.in.u.qp_flush_wqes.info;
2639                                 memcpy(hw_info, info, sizeof(*hw_info));
2640                                 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES;
2641                                 cqp_info->post_sq = 1;
2642                                 cqp_info->in.u.qp_flush_wqes.qp = qp;
2643                                 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)new_req;
2644
2645                                 status = irdma_handle_cqp_op(rf, new_req);
2646                                 if (new_req->compl_info.maj_err_code ||
2647                                     new_req->compl_info.min_err_code != IRDMA_CQP_COMPL_SQ_WQE_FLUSHED ||
2648                                     status) {
2649                                         ibdev_err(&iwqp->iwdev->ibdev, "fatal QP event: SQ in error but not flushed, qp: %d",
2650                                                   iwqp->ibqp.qp_num);
2651                                         qp->qp_uk.sq_flush_complete = false;
2652                                         irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC);
2653                                 }
2654                                 irdma_put_cqp_request(&rf->cqp, new_req);
2655                         } else {
2656                                 /* SQ WQE flush was requested but did not happen */
2657                                 qp->qp_uk.sq_flush_complete = true;
2658                         }
2659                 } else {
2660                         if (!IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring))
2661                                 qp->qp_uk.sq_flush_complete = true;
2662                 }
2663         }
2664
2665         ibdev_dbg(&rf->iwdev->ibdev,
2666                   "VERBS: qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n",
2667                   iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state,
2668                   iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state,
2669                   cqp_request->compl_info.maj_err_code,
2670                   cqp_request->compl_info.min_err_code);
2671 put_cqp:
2672         irdma_put_cqp_request(&rf->cqp, cqp_request);
2673
2674         return status;
2675 }
2676
2677 /**
2678  * irdma_gen_ae - generate AE
2679  * @rf: RDMA PCI function
2680  * @qp: qp associated with AE
2681  * @info: info for ae
2682  * @wait: wait for completion
2683  */
2684 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
2685                   struct irdma_gen_ae_info *info, bool wait)
2686 {
2687         struct irdma_gen_ae_info *ae_info;
2688         struct irdma_cqp_request *cqp_request;
2689         struct cqp_cmds_info *cqp_info;
2690
2691         cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
2692         if (!cqp_request)
2693                 return;
2694
2695         cqp_info = &cqp_request->info;
2696         ae_info = &cqp_request->info.in.u.gen_ae.info;
2697         memcpy(ae_info, info, sizeof(*ae_info));
2698         cqp_info->cqp_cmd = IRDMA_OP_GEN_AE;
2699         cqp_info->post_sq = 1;
2700         cqp_info->in.u.gen_ae.qp = qp;
2701         cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request;
2702
2703         irdma_handle_cqp_op(rf, cqp_request);
2704         irdma_put_cqp_request(&rf->cqp, cqp_request);
2705 }
2706
2707 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask)
2708 {
2709         struct irdma_qp_flush_info info = {};
2710         struct irdma_pci_f *rf = iwqp->iwdev->rf;
2711         u8 flush_code = iwqp->sc_qp.flush_code;
2712
2713         if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ))
2714                 return;
2715
2716         /* Set flush info fields*/
2717         info.sq = flush_mask & IRDMA_FLUSH_SQ;
2718         info.rq = flush_mask & IRDMA_FLUSH_RQ;
2719
2720         /* Generate userflush errors in CQE */
2721         info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2722         info.sq_minor_code = FLUSH_GENERAL_ERR;
2723         info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2724         info.rq_minor_code = FLUSH_GENERAL_ERR;
2725         info.userflushcode = true;
2726
2727         if (flush_mask & IRDMA_REFLUSH) {
2728                 if (info.sq)
2729                         iwqp->sc_qp.flush_sq = false;
2730                 if (info.rq)
2731                         iwqp->sc_qp.flush_rq = false;
2732         } else {
2733                 if (flush_code) {
2734                         if (info.sq && iwqp->sc_qp.sq_flush_code)
2735                                 info.sq_minor_code = flush_code;
2736                         if (info.rq && iwqp->sc_qp.rq_flush_code)
2737                                 info.rq_minor_code = flush_code;
2738                 }
2739                 if (!iwqp->user_mode)
2740                         queue_delayed_work(iwqp->iwdev->cleanup_wq,
2741                                            &iwqp->dwork_flush,
2742                                            msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
2743         }
2744
2745         /* Issue flush */
2746         (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info,
2747                                   flush_mask & IRDMA_FLUSH_WAIT);
2748         iwqp->flush_issued = true;
2749 }