drivers/infiniband/hw/ocrdma/ocrdma_sli.h

   1 /* This file is part of the Emulex RoCE Device Driver for
   2  * RoCE (RDMA over Converged Ethernet) adapters.
   3  * Copyright (C) 2012-2015 Emulex. All rights reserved.
   4  * EMULEX and SLI are trademarks of Emulex.
   5  * www.emulex.com
   6  *
   7  * This software is available to you under a choice of one of two licenses.
   8  * You may choose to be licensed under the terms of the GNU General Public
   9  * License (GPL) Version 2, available from the file COPYING in the main
  10  * directory of this source tree, or the BSD license below:
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  *
  16  * - Redistributions of source code must retain the above copyright notice,
  17  *   this list of conditions and the following disclaimer.
  18  *
  19  * - Redistributions in binary form must reproduce the above copyright
  20  *   notice, this list of conditions and the following disclaimer in
  21  *   the documentation and/or other materials provided with the distribution.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  24  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  32  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  33  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  *
  35  * Contact Information:
  36  * linux-drivers@emulex.com
  37  *
  38  * Emulex
  39  * 3333 Susan Street
  40  * Costa Mesa, CA 92626
  41  */
  42
  43 #ifndef __OCRDMA_SLI_H__
  44 #define __OCRDMA_SLI_H__
  45
  46 enum {
  47         OCRDMA_ASIC_GEN_SKH_R = 0x04,
  48         OCRDMA_ASIC_GEN_LANCER = 0x0B
  49 };
  50
  51 enum {
  52         OCRDMA_ASIC_REV_A0 = 0x00,
  53         OCRDMA_ASIC_REV_B0 = 0x10,
  54         OCRDMA_ASIC_REV_C0 = 0x20
  55 };
  56
  57 #define OCRDMA_SUBSYS_ROCE 10
  58 enum {
  59         OCRDMA_CMD_QUERY_CONFIG = 1,
  60         OCRDMA_CMD_ALLOC_PD = 2,
  61         OCRDMA_CMD_DEALLOC_PD = 3,
  62
  63         OCRDMA_CMD_CREATE_AH_TBL = 4,
  64         OCRDMA_CMD_DELETE_AH_TBL = 5,
  65
  66         OCRDMA_CMD_CREATE_QP = 6,
  67         OCRDMA_CMD_QUERY_QP = 7,
  68         OCRDMA_CMD_MODIFY_QP = 8 ,
  69         OCRDMA_CMD_DELETE_QP = 9,
  70
  71         OCRDMA_CMD_RSVD1 = 10,
  72         OCRDMA_CMD_ALLOC_LKEY = 11,
  73         OCRDMA_CMD_DEALLOC_LKEY = 12,
  74         OCRDMA_CMD_REGISTER_NSMR = 13,
  75         OCRDMA_CMD_REREGISTER_NSMR = 14,
  76         OCRDMA_CMD_REGISTER_NSMR_CONT = 15,
  77         OCRDMA_CMD_QUERY_NSMR = 16,
  78         OCRDMA_CMD_ALLOC_MW = 17,
  79         OCRDMA_CMD_QUERY_MW = 18,
  80
  81         OCRDMA_CMD_CREATE_SRQ = 19,
  82         OCRDMA_CMD_QUERY_SRQ = 20,
  83         OCRDMA_CMD_MODIFY_SRQ = 21,
  84         OCRDMA_CMD_DELETE_SRQ = 22,
  85
  86         OCRDMA_CMD_ATTACH_MCAST = 23,
  87         OCRDMA_CMD_DETACH_MCAST = 24,
  88
  89         OCRDMA_CMD_CREATE_RBQ = 25,
  90         OCRDMA_CMD_DESTROY_RBQ = 26,
  91
  92         OCRDMA_CMD_GET_RDMA_STATS = 27,
  93         OCRDMA_CMD_ALLOC_PD_RANGE = 28,
  94         OCRDMA_CMD_DEALLOC_PD_RANGE = 29,
  95
  96         OCRDMA_CMD_MAX
  97 };
  98
  99 #define OCRDMA_SUBSYS_COMMON 1
 100 enum {
 101         OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1 = 5,
 102         OCRDMA_CMD_CREATE_CQ            = 12,
 103         OCRDMA_CMD_CREATE_EQ            = 13,
 104         OCRDMA_CMD_CREATE_MQ            = 21,
 105         OCRDMA_CMD_GET_CTRL_ATTRIBUTES  = 32,
 106         OCRDMA_CMD_GET_FW_VER           = 35,
 107         OCRDMA_CMD_MODIFY_EQ_DELAY      = 41,
 108         OCRDMA_CMD_DELETE_MQ            = 53,
 109         OCRDMA_CMD_DELETE_CQ            = 54,
 110         OCRDMA_CMD_DELETE_EQ            = 55,
 111         OCRDMA_CMD_GET_FW_CONFIG        = 58,
 112         OCRDMA_CMD_CREATE_MQ_EXT        = 90,
 113         OCRDMA_CMD_PHY_DETAILS          = 102
 114 };
 115
 116 enum {
 117         QTYPE_EQ        = 1,
 118         QTYPE_CQ        = 2,
 119         QTYPE_MCCQ      = 3
 120 };
 121
 122 #define OCRDMA_MAX_SGID         16
 123
 124 #define OCRDMA_MAX_QP    2048
 125 #define OCRDMA_MAX_CQ    2048
 126 #define OCRDMA_MAX_STAG 16384
 127
 128 enum {
 129         OCRDMA_DB_RQ_OFFSET             = 0xE0,
 130         OCRDMA_DB_GEN2_RQ_OFFSET        = 0x100,
 131         OCRDMA_DB_SQ_OFFSET             = 0x60,
 132         OCRDMA_DB_GEN2_SQ_OFFSET        = 0x1C0,
 133         OCRDMA_DB_SRQ_OFFSET            = OCRDMA_DB_RQ_OFFSET,
 134         OCRDMA_DB_GEN2_SRQ_OFFSET       = OCRDMA_DB_GEN2_RQ_OFFSET,
 135         OCRDMA_DB_CQ_OFFSET             = 0x120,
 136         OCRDMA_DB_EQ_OFFSET             = OCRDMA_DB_CQ_OFFSET,
 137         OCRDMA_DB_MQ_OFFSET             = 0x140,
 138
 139         OCRDMA_DB_SQ_SHIFT              = 16,
 140         OCRDMA_DB_RQ_SHIFT              = 24
 141 };
 142
 143 #define OCRDMA_DB_CQ_RING_ID_MASK       0x3FF   /* bits 0 - 9 */
 144 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK  0x0C00   /* bits 10-11 of qid at 12-11 */
 145 /* qid #2 msbits at 12-11 */
 146 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT  0x1
 147 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT   16      /* bits 16 - 28 */
 148 /* Rearm bit */
 149 #define OCRDMA_DB_CQ_REARM_SHIFT        29      /* bit 29 */
 150 /* solicited bit */
 151 #define OCRDMA_DB_CQ_SOLICIT_SHIFT      31      /* bit 31 */
 152
 153 #define OCRDMA_EQ_ID_MASK               0x1FF   /* bits 0 - 8 */
 154 #define OCRDMA_EQ_ID_EXT_MASK           0x3e00  /* bits 9-13 */
 155 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT     2       /* qid bits 9-13 at 11-15 */
 156
 157 /* Clear the interrupt for this eq */
 158 #define OCRDMA_EQ_CLR_SHIFT             9       /* bit 9 */
 159 /* Must be 1 */
 160 #define OCRDMA_EQ_TYPE_SHIFT            10      /* bit 10 */
 161 /* Number of event entries processed */
 162 #define OCRDMA_NUM_EQE_SHIFT            16      /* bits 16 - 28 */
 163 /* Rearm bit */
 164 #define OCRDMA_REARM_SHIFT              29      /* bit 29 */
 165
 166 #define OCRDMA_MQ_ID_MASK               0x7FF   /* bits 0 - 10 */
 167 /* Number of entries posted */
 168 #define OCRDMA_MQ_NUM_MQE_SHIFT 16      /* bits 16 - 29 */
 169
 170 #define OCRDMA_MIN_HPAGE_SIZE   4096
 171
 172 #define OCRDMA_MIN_Q_PAGE_SIZE  4096
 173 #define OCRDMA_MAX_Q_PAGES      8
 174
 175 #define OCRDMA_SLI_ASIC_ID_OFFSET       0x9C
 176 #define OCRDMA_SLI_ASIC_REV_MASK        0x000000FF
 177 #define OCRDMA_SLI_ASIC_GEN_NUM_MASK    0x0000FF00
 178 #define OCRDMA_SLI_ASIC_GEN_NUM_SHIFT   0x08
 179 /*
 180 # 0: 4K Bytes
 181 # 1: 8K Bytes
 182 # 2: 16K Bytes
 183 # 3: 32K Bytes
 184 # 4: 64K Bytes
 185 # 5: 128K Bytes
 186 # 6: 256K Bytes
 187 # 7: 512K Bytes
 188 */
 189 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT      8
 190 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
 191
 192 #define MAX_OCRDMA_QP_PAGES             8
 193 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)
 194
 195 #define OCRDMA_CREATE_CQ_MAX_PAGES      4
 196 #define OCRDMA_DPP_CQE_SIZE             4
 197
 198 #define OCRDMA_GEN2_MAX_CQE 1024
 199 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
 200 #define OCRDMA_GEN2_WQE_SIZE 256
 201 #define OCRDMA_MAX_CQE  4095
 202 #define OCRDMA_CQ_PAGE_SIZE 16384
 203 #define OCRDMA_WQE_SIZE 128
 204 #define OCRDMA_WQE_STRIDE 8
 205 #define OCRDMA_WQE_ALIGN_BYTES 16
 206
 207 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES
 208
 209 enum {
 210         OCRDMA_MCH_OPCODE_SHIFT = 0,
 211         OCRDMA_MCH_OPCODE_MASK  = 0xFF,
 212         OCRDMA_MCH_SUBSYS_SHIFT = 8,
 213         OCRDMA_MCH_SUBSYS_MASK  = 0xFF00
 214 };
 215
 216 /* mailbox cmd header */
 217 struct ocrdma_mbx_hdr {
 218         u32 subsys_op;
 219         u32 timeout;            /* in seconds */
 220         u32 cmd_len;
 221         u32 rsvd_version;
 222 };
 223
 224 enum {
 225         OCRDMA_MBX_RSP_OPCODE_SHIFT     = 0,
 226         OCRDMA_MBX_RSP_OPCODE_MASK      = 0xFF,
 227         OCRDMA_MBX_RSP_SUBSYS_SHIFT     = 8,
 228         OCRDMA_MBX_RSP_SUBSYS_MASK      = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT,
 229
 230         OCRDMA_MBX_RSP_STATUS_SHIFT     = 0,
 231         OCRDMA_MBX_RSP_STATUS_MASK      = 0xFF,
 232         OCRDMA_MBX_RSP_ASTATUS_SHIFT    = 8,
 233         OCRDMA_MBX_RSP_ASTATUS_MASK     = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT
 234 };
 235
 236 /* mailbox cmd response */
 237 struct ocrdma_mbx_rsp {
 238         u32 subsys_op;
 239         u32 status;
 240         u32 rsp_len;
 241         u32 add_rsp_len;
 242 };
 243
 244 enum {
 245         OCRDMA_MQE_EMBEDDED     = 1,
 246         OCRDMA_MQE_NONEMBEDDED  = 0
 247 };
 248
 249 struct ocrdma_mqe_sge {
 250         u32 pa_lo;
 251         u32 pa_hi;
 252         u32 len;
 253 };
 254
 255 enum {
 256         OCRDMA_MQE_HDR_EMB_SHIFT        = 0,
 257         OCRDMA_MQE_HDR_EMB_MASK         = BIT(0),
 258         OCRDMA_MQE_HDR_SGE_CNT_SHIFT    = 3,
 259         OCRDMA_MQE_HDR_SGE_CNT_MASK     = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
 260         OCRDMA_MQE_HDR_SPECIAL_SHIFT    = 24,
 261         OCRDMA_MQE_HDR_SPECIAL_MASK     = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT
 262 };
 263
 264 struct ocrdma_mqe_hdr {
 265         u32 spcl_sge_cnt_emb;
 266         u32 pyld_len;
 267         u32 tag_lo;
 268         u32 tag_hi;
 269         u32 rsvd3;
 270 };
 271
 272 struct ocrdma_mqe_emb_cmd {
 273         struct ocrdma_mbx_hdr mch;
 274         u8 pyld[220];
 275 };
 276
 277 struct ocrdma_mqe {
 278         struct ocrdma_mqe_hdr hdr;
 279         union {
 280                 struct ocrdma_mqe_emb_cmd emb_req;
 281                 struct {
 282                         struct ocrdma_mqe_sge sge[19];
 283                 } nonemb_req;
 284                 u8 cmd[236];
 285                 struct ocrdma_mbx_rsp rsp;
 286         } u;
 287 };
 288
 289 #define OCRDMA_EQ_LEN       4096
 290 #define OCRDMA_MQ_CQ_LEN    256
 291 #define OCRDMA_MQ_LEN       128
 292
 293 #define PAGE_SHIFT_4K           12
 294 #define PAGE_SIZE_4K            (1 << PAGE_SHIFT_4K)
 295
 296 /* Returns number of pages spanned by the data starting at the given addr */
 297 #define PAGES_4K_SPANNED(_address, size) \
 298         ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) +     \
 299                         (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
 300
 301 struct ocrdma_delete_q_req {
 302         struct ocrdma_mbx_hdr req;
 303         u32 id;
 304 };
 305
 306 struct ocrdma_pa {
 307         u32 lo;
 308         u32 hi;
 309 };
 310
 311 #define MAX_OCRDMA_EQ_PAGES     8
 312 struct ocrdma_create_eq_req {
 313         struct ocrdma_mbx_hdr req;
 314         u32 num_pages;
 315         u32 valid;
 316         u32 cnt;
 317         u32 delay;
 318         u32 rsvd;
 319         struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES];
 320 };
 321
 322 enum {
 323         OCRDMA_CREATE_EQ_VALID  = BIT(29),
 324         OCRDMA_CREATE_EQ_CNT_SHIFT      = 26,
 325         OCRDMA_CREATE_CQ_DELAY_SHIFT    = 13,
 326 };
 327
 328 struct ocrdma_create_eq_rsp {
 329         struct ocrdma_mbx_rsp rsp;
 330         u32 vector_eqid;
 331 };
 332
 333 #define OCRDMA_EQ_MINOR_OTHER   0x1
 334
 335 struct ocrmda_set_eqd {
 336         u32 eq_id;
 337         u32 phase;
 338         u32 delay_multiplier;
 339 };
 340
 341 struct ocrdma_modify_eqd_cmd {
 342         struct ocrdma_mbx_hdr req;
 343         u32 num_eq;
 344         struct ocrmda_set_eqd set_eqd[8];
 345 } __packed;
 346
 347 struct ocrdma_modify_eqd_req {
 348         struct ocrdma_mqe_hdr hdr;
 349         struct ocrdma_modify_eqd_cmd cmd;
 350 };
 351
 352
 353 struct ocrdma_modify_eq_delay_rsp {
 354         struct ocrdma_mbx_rsp hdr;
 355         u32 rsvd0;
 356 } __packed;
 357
 358 enum {
 359         OCRDMA_MCQE_STATUS_SHIFT        = 0,
 360         OCRDMA_MCQE_STATUS_MASK         = 0xFFFF,
 361         OCRDMA_MCQE_ESTATUS_SHIFT       = 16,
 362         OCRDMA_MCQE_ESTATUS_MASK        = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
 363         OCRDMA_MCQE_CONS_SHIFT          = 27,
 364         OCRDMA_MCQE_CONS_MASK           = BIT(27),
 365         OCRDMA_MCQE_CMPL_SHIFT          = 28,
 366         OCRDMA_MCQE_CMPL_MASK           = BIT(28),
 367         OCRDMA_MCQE_AE_SHIFT            = 30,
 368         OCRDMA_MCQE_AE_MASK             = BIT(30),
 369         OCRDMA_MCQE_VALID_SHIFT         = 31,
 370         OCRDMA_MCQE_VALID_MASK          = BIT(31)
 371 };
 372
 373 struct ocrdma_mcqe {
 374         u32 status;
 375         u32 tag_lo;
 376         u32 tag_hi;
 377         u32 valid_ae_cmpl_cons;
 378 };
 379
 380 enum {
 381         OCRDMA_AE_MCQE_QPVALID          = BIT(31),
 382         OCRDMA_AE_MCQE_QPID_MASK        = 0xFFFF,
 383
 384         OCRDMA_AE_MCQE_CQVALID          = BIT(31),
 385         OCRDMA_AE_MCQE_CQID_MASK        = 0xFFFF,
 386         OCRDMA_AE_MCQE_VALID            = BIT(31),
 387         OCRDMA_AE_MCQE_AE               = BIT(30),
 388         OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
 389         OCRDMA_AE_MCQE_EVENT_TYPE_MASK  =
 390                                         0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,
 391         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8,
 392         OCRDMA_AE_MCQE_EVENT_CODE_MASK  =
 393                                         0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
 394 };
 395 struct ocrdma_ae_mcqe {
 396         u32 qpvalid_qpid;
 397         u32 cqvalid_cqid;
 398         u32 evt_tag;
 399         u32 valid_ae_event;
 400 };
 401
 402 enum {
 403         OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT = 0,
 404         OCRDMA_AE_PVID_MCQE_ENABLED_MASK  = 0xFF,
 405         OCRDMA_AE_PVID_MCQE_TAG_SHIFT = 16,
 406         OCRDMA_AE_PVID_MCQE_TAG_MASK = 0xFFFF << OCRDMA_AE_PVID_MCQE_TAG_SHIFT
 407 };
 408
 409 struct ocrdma_ae_pvid_mcqe {
 410         u32 tag_enabled;
 411         u32 event_tag;
 412         u32 rsvd1;
 413         u32 rsvd2;
 414 };
 415
 416 enum {
 417         OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT         = 16,
 418         OCRDMA_AE_MPA_MCQE_REQ_ID_MASK          = 0xFFFF <<
 419                                         OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,
 420
 421         OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT     = 8,
 422         OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK      = 0xFF <<
 423                                         OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,
 424         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT     = 16,
 425         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK      = 0xFF <<
 426                                         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
 427         OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT       = 30,
 428         OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK        = BIT(30),
 429         OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT    = 31,
 430         OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK     = BIT(31)
 431 };
 432
 433 struct ocrdma_ae_mpa_mcqe {
 434         u32 req_id;
 435         u32 w1;
 436         u32 w2;
 437         u32 valid_ae_event;
 438 };
 439
 440 enum {
 441         OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT    = 0,
 442         OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK     = 0xFFFF,
 443         OCRDMA_AE_QP_MCQE_QP_ID_SHIFT           = 16,
 444         OCRDMA_AE_QP_MCQE_QP_ID_MASK            = 0xFFFF <<
 445                                                 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,
 446
 447         OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT      = 8,
 448         OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK       = 0xFF <<
 449                                 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,
 450         OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT      = 16,
 451         OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK       = 0xFF <<
 452                                 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
 453         OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT        = 30,
 454         OCRDMA_AE_QP_MCQE_EVENT_AE_MASK         = BIT(30),
 455         OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT     = 31,
 456         OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK      = BIT(31)
 457 };
 458
 459 struct ocrdma_ae_qp_mcqe {
 460         u32 qp_id_state;
 461         u32 w1;
 462         u32 w2;
 463         u32 valid_ae_event;
 464 };
 465
 466 #define OCRDMA_ASYNC_RDMA_EVE_CODE 0x14
 467 #define OCRDMA_ASYNC_GRP5_EVE_CODE 0x5
 468
 469 enum ocrdma_async_grp5_events {
 470         OCRDMA_ASYNC_EVENT_QOS_VALUE    = 0x01,
 471         OCRDMA_ASYNC_EVENT_COS_VALUE    = 0x02,
 472         OCRDMA_ASYNC_EVENT_PVID_STATE   = 0x03
 473 };
 474
 475 enum OCRDMA_ASYNC_EVENT_TYPE {
 476         OCRDMA_CQ_ERROR                 = 0x00,
 477         OCRDMA_CQ_OVERRUN_ERROR         = 0x01,
 478         OCRDMA_CQ_QPCAT_ERROR           = 0x02,
 479         OCRDMA_QP_ACCESS_ERROR          = 0x03,
 480         OCRDMA_QP_COMM_EST_EVENT        = 0x04,
 481         OCRDMA_SQ_DRAINED_EVENT         = 0x05,
 482         OCRDMA_DEVICE_FATAL_EVENT       = 0x08,
 483         OCRDMA_SRQCAT_ERROR             = 0x0E,
 484         OCRDMA_SRQ_LIMIT_EVENT          = 0x0F,
 485         OCRDMA_QP_LAST_WQE_EVENT        = 0x10,
 486
 487         OCRDMA_MAX_ASYNC_ERRORS
 488 };
 489
 490 /* mailbox command request and responses */
 491 enum {
 492         OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT          = 2,
 493         OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK           = BIT(2),
 494         OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT        = 3,
 495         OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK         = BIT(3),
 496         OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT               = 8,
 497         OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK                = 0xFFFFFF <<
 498                                 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
 499
 500         OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT               = 16,
 501         OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK                = 0xFFFF <<
 502                                         OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,
 503         OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT         = 8,
 504         OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK          = 0xFF <<
 505                                 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,
 506
 507         OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT         = 0,
 508         OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK          = 0xFFFF,
 509         OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT        = 16,
 510         OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK         = 0xFFFF <<
 511                                 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT,
 512
 513         OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT       = 0,
 514         OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK        = 0xFFFF,
 515         OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT       = 16,
 516         OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK        = 0xFFFF <<
 517                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,
 518
 519         OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET        = 24,
 520         OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK          = 0xFF <<
 521                                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,
 522         OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET        = 16,
 523         OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK          = 0xFF <<
 524                                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,
 525         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET        = 0,
 526         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK          = 0xFFFF <<
 527                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,
 528
 529         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET             = 16,
 530         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK               = 0xFFFF <<
 531                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,
 532         OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET        = 0,
 533         OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK          = 0xFFFF <<
 534                                 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,
 535
 536         OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET         = 16,
 537         OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK           = 0xFFFF <<
 538                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,
 539         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET     = 0,
 540         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK       = 0xFFFF <<
 541                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,
 542
 543         OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET         = 0,
 544         OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK           = 0xFFFF <<
 545                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,
 546
 547         OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET     = 16,
 548         OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK       = 0xFFFF <<
 549                                 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
 550         OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET     = 0,
 551         OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK       = 0xFFFF <<
 552                                 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET,
 553
 554         OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET              = 16,
 555         OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK                = 0xFFFF <<
 556                                 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,
 557         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET     = 0,
 558         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK       = 0xFFFF <<
 559                                 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,
 560
 561         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET         = 16,
 562         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK           = 0xFFFF <<
 563                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,
 564         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET         = 0,
 565         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK           = 0xFFFF <<
 566                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,
 567 };
 568
 569 struct ocrdma_mbx_query_config {
 570         struct ocrdma_mqe_hdr hdr;
 571         struct ocrdma_mbx_rsp rsp;
 572         u32 qp_srq_cq_ird_ord;
 573         u32 max_pd_ca_ack_delay;
 574         u32 max_write_send_sge;
 575         u32 max_ird_ord_per_qp;
 576         u32 max_shared_ird_ord;
 577         u32 max_mr;
 578         u32 max_mr_size_hi;
 579         u32 max_mr_size_lo;
 580         u32 max_num_mr_pbl;
 581         u32 max_mw;
 582         u32 max_fmr;
 583         u32 max_pages_per_frmr;
 584         u32 max_mcast_group;
 585         u32 max_mcast_qp_attach;
 586         u32 max_total_mcast_qp_attach;
 587         u32 wqe_rqe_stride_max_dpp_cqs;
 588         u32 max_srq_rpir_qps;
 589         u32 max_dpp_pds_credits;
 590         u32 max_dpp_credits_pds_per_pd;
 591         u32 max_wqes_rqes_per_q;
 592         u32 max_cq_cqes_per_cq;
 593         u32 max_srq_rqe_sge;
 594 };
 595
 596 struct ocrdma_fw_ver_rsp {
 597         struct ocrdma_mqe_hdr hdr;
 598         struct ocrdma_mbx_rsp rsp;
 599
 600         u8 running_ver[32];
 601 };
 602
 603 struct ocrdma_fw_conf_rsp {
 604         struct ocrdma_mqe_hdr hdr;
 605         struct ocrdma_mbx_rsp rsp;
 606
 607         u32 config_num;
 608         u32 asic_revision;
 609         u32 phy_port;
 610         u32 fn_mode;
 611         struct {
 612                 u32 mode;
 613                 u32 nic_wqid_base;
 614                 u32 nic_wq_tot;
 615                 u32 prot_wqid_base;
 616                 u32 prot_wq_tot;
 617                 u32 prot_rqid_base;
 618                 u32 prot_rqid_tot;
 619                 u32 rsvd[6];
 620         } ulp[2];
 621         u32 fn_capabilities;
 622         u32 rsvd1;
 623         u32 rsvd2;
 624         u32 base_eqid;
 625         u32 max_eq;
 626
 627 };
 628
 629 enum {
 630         OCRDMA_FN_MODE_RDMA     = 0x4
 631 };
 632
 633 enum {
 634         OCRDMA_IF_TYPE_MASK             = 0xFFFF0000,
 635         OCRDMA_IF_TYPE_SHIFT            = 0x10,
 636         OCRDMA_PHY_TYPE_MASK            = 0x0000FFFF,
 637         OCRDMA_FUTURE_DETAILS_MASK      = 0xFFFF0000,
 638         OCRDMA_FUTURE_DETAILS_SHIFT     = 0x10,
 639         OCRDMA_EX_PHY_DETAILS_MASK      = 0x0000FFFF,
 640         OCRDMA_FSPEED_SUPP_MASK         = 0xFFFF0000,
 641         OCRDMA_FSPEED_SUPP_SHIFT        = 0x10,
 642         OCRDMA_ASPEED_SUPP_MASK         = 0x0000FFFF
 643 };
 644
 645 struct ocrdma_get_phy_info_rsp {
 646         struct ocrdma_mqe_hdr hdr;
 647         struct ocrdma_mbx_rsp rsp;
 648
 649         u32 ityp_ptyp;
 650         u32 misc_params;
 651         u32 ftrdtl_exphydtl;
 652         u32 fspeed_aspeed;
 653         u32 future_use[2];
 654 };
 655
 656 enum {
 657         OCRDMA_PHY_SPEED_ZERO = 0x0,
 658         OCRDMA_PHY_SPEED_10MBPS = 0x1,
 659         OCRDMA_PHY_SPEED_100MBPS = 0x2,
 660         OCRDMA_PHY_SPEED_1GBPS = 0x4,
 661         OCRDMA_PHY_SPEED_10GBPS = 0x8,
 662         OCRDMA_PHY_SPEED_40GBPS = 0x20
 663 };
 664
 665 enum {
 666         OCRDMA_PORT_NUM_MASK    = 0x3F,
 667         OCRDMA_PT_MASK          = 0xC0,
 668         OCRDMA_PT_SHIFT         = 0x6,
 669         OCRDMA_LINK_DUP_MASK    = 0x0000FF00,
 670         OCRDMA_LINK_DUP_SHIFT   = 0x8,
 671         OCRDMA_PHY_PS_MASK      = 0x00FF0000,
 672         OCRDMA_PHY_PS_SHIFT     = 0x10,
 673         OCRDMA_PHY_PFLT_MASK    = 0xFF000000,
 674         OCRDMA_PHY_PFLT_SHIFT   = 0x18,
 675         OCRDMA_QOS_LNKSP_MASK   = 0xFFFF0000,
 676         OCRDMA_QOS_LNKSP_SHIFT  = 0x10,
 677         OCRDMA_LLST_MASK        = 0xFF,
 678         OCRDMA_PLFC_MASK        = 0x00000400,
 679         OCRDMA_PLFC_SHIFT       = 0x8,
 680         OCRDMA_PLRFC_MASK       = 0x00000200,
 681         OCRDMA_PLRFC_SHIFT      = 0x8,
 682         OCRDMA_PLTFC_MASK       = 0x00000100,
 683         OCRDMA_PLTFC_SHIFT      = 0x8
 684 };
 685
 686 struct ocrdma_get_link_speed_rsp {
 687         struct ocrdma_mqe_hdr hdr;
 688         struct ocrdma_mbx_rsp rsp;
 689
 690         u32 pflt_pps_ld_pnum;
 691         u32 qos_lsp;
 692         u32 res_lls;
 693 };
 694
 695 enum {
 696         OCRDMA_PHYS_LINK_SPEED_ZERO = 0x0,
 697         OCRDMA_PHYS_LINK_SPEED_10MBPS = 0x1,
 698         OCRDMA_PHYS_LINK_SPEED_100MBPS = 0x2,
 699         OCRDMA_PHYS_LINK_SPEED_1GBPS = 0x3,
 700         OCRDMA_PHYS_LINK_SPEED_10GBPS = 0x4,
 701         OCRDMA_PHYS_LINK_SPEED_20GBPS = 0x5,
 702         OCRDMA_PHYS_LINK_SPEED_25GBPS = 0x6,
 703         OCRDMA_PHYS_LINK_SPEED_40GBPS = 0x7,
 704         OCRDMA_PHYS_LINK_SPEED_100GBPS = 0x8
 705 };
 706
 707 enum {
 708         OCRDMA_CREATE_CQ_VER2                   = 2,
 709         OCRDMA_CREATE_CQ_VER3                   = 3,
 710
 711         OCRDMA_CREATE_CQ_PAGE_CNT_MASK          = 0xFFFF,
 712         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT        = 16,
 713         OCRDMA_CREATE_CQ_PAGE_SIZE_MASK         = 0xFF,
 714
 715         OCRDMA_CREATE_CQ_COALESCWM_SHIFT        = 12,
 716         OCRDMA_CREATE_CQ_COALESCWM_MASK         = BIT(13) | BIT(12),
 717         OCRDMA_CREATE_CQ_FLAGS_NODELAY          = BIT(14),
 718         OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID       = BIT(15),
 719
 720         OCRDMA_CREATE_CQ_EQ_ID_MASK             = 0xFFFF,
 721         OCRDMA_CREATE_CQ_CQE_COUNT_MASK         = 0xFFFF
 722 };
 723
 724 enum {
 725         OCRDMA_CREATE_CQ_VER0                   = 0,
 726         OCRDMA_CREATE_CQ_DPP                    = 1,
 727         OCRDMA_CREATE_CQ_TYPE_SHIFT             = 24,
 728         OCRDMA_CREATE_CQ_EQID_SHIFT             = 22,
 729
 730         OCRDMA_CREATE_CQ_CNT_SHIFT              = 27,
 731         OCRDMA_CREATE_CQ_FLAGS_VALID            = BIT(29),
 732         OCRDMA_CREATE_CQ_FLAGS_EVENTABLE        = BIT(31),
 733         OCRDMA_CREATE_CQ_DEF_FLAGS              = OCRDMA_CREATE_CQ_FLAGS_VALID |
 734                                         OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
 735                                         OCRDMA_CREATE_CQ_FLAGS_NODELAY
 736 };
 737
 738 struct ocrdma_create_cq_cmd {
 739         struct ocrdma_mbx_hdr req;
 740         u32 pgsz_pgcnt;
 741         u32 ev_cnt_flags;
 742         u32 eqn;
 743         u32 pdid_cqecnt;
 744         u32 rsvd6;
 745         struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES];
 746 };
 747
 748 struct ocrdma_create_cq {
 749         struct ocrdma_mqe_hdr hdr;
 750         struct ocrdma_create_cq_cmd cmd;
 751 };
 752
 753 enum {
 754         OCRDMA_CREATE_CQ_CMD_PDID_SHIFT = 0x10
 755 };
 756
 757 enum {
 758         OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF
 759 };
 760
 761 struct ocrdma_create_cq_cmd_rsp {
 762         struct ocrdma_mbx_rsp rsp;
 763         u32 cq_id;
 764 };
 765
 766 struct ocrdma_create_cq_rsp {
 767         struct ocrdma_mqe_hdr hdr;
 768         struct ocrdma_create_cq_cmd_rsp rsp;
 769 };
 770
 771 enum {
 772         OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT         = 22,
 773         OCRDMA_CREATE_MQ_CQ_ID_SHIFT            = 16,
 774         OCRDMA_CREATE_MQ_RING_SIZE_SHIFT        = 16,
 775         OCRDMA_CREATE_MQ_VALID                  = BIT(31),
 776         OCRDMA_CREATE_MQ_ASYNC_CQ_VALID         = BIT(0)
 777 };
 778
 779 struct ocrdma_create_mq_req {
 780         struct ocrdma_mbx_hdr req;
 781         u32 cqid_pages;
 782         u32 async_event_bitmap;
 783         u32 async_cqid_ringsize;
 784         u32 valid;
 785         u32 async_cqid_valid;
 786         u32 rsvd;
 787         struct ocrdma_pa pa[8];
 788 };
 789
 790 struct ocrdma_create_mq_rsp {
 791         struct ocrdma_mbx_rsp rsp;
 792         u32 id;
 793 };
 794
 795 enum {
 796         OCRDMA_DESTROY_CQ_QID_SHIFT                     = 0,
 797         OCRDMA_DESTROY_CQ_QID_MASK                      = 0xFFFF,
 798         OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT        = 16,
 799         OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK         = 0xFFFF <<
 800                                 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
 801 };
 802
 803 struct ocrdma_destroy_cq {
 804         struct ocrdma_mqe_hdr hdr;
 805         struct ocrdma_mbx_hdr req;
 806
 807         u32 bypass_flush_qid;
 808 };
 809
 810 struct ocrdma_destroy_cq_rsp {
 811         struct ocrdma_mqe_hdr hdr;
 812         struct ocrdma_mbx_rsp rsp;
 813 };
 814
 815 enum {
 816         OCRDMA_QPT_GSI  = 1,
 817         OCRDMA_QPT_RC   = 2,
 818         OCRDMA_QPT_UD   = 4,
 819 };
 820
 821 enum {
 822         OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT        = 0,
 823         OCRDMA_CREATE_QP_REQ_PD_ID_MASK         = 0xFFFF,
 824         OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
 825         OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,
 826         OCRDMA_CREATE_QP_REQ_QPT_SHIFT          = 29,
 827         OCRDMA_CREATE_QP_REQ_QPT_MASK           = BIT(31) | BIT(30) | BIT(29),
 828
 829         OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT      = 0,
 830         OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK       = 0xFFFF,
 831         OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT      = 16,
 832         OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK       = 0xFFFF <<
 833                                         OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,
 834
 835         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT        = 0,
 836         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK         = 0xFFFF,
 837         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT         = 16,
 838         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK          = 0xFFFF <<
 839                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
 840
 841         OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT               = 0,
 842         OCRDMA_CREATE_QP_REQ_FMR_EN_MASK                = BIT(0),
 843         OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT          = 1,
 844         OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK           = BIT(1),
 845         OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT          = 2,
 846         OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK           = BIT(2),
 847         OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT             = 3,
 848         OCRDMA_CREATE_QP_REQ_INB_WREN_MASK              = BIT(3),
 849         OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT             = 4,
 850         OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK              = BIT(4),
 851         OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT              = 5,
 852         OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK               = BIT(5),
 853         OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT          = 6,
 854         OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK           = BIT(6),
 855         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT           = 7,
 856         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK            = BIT(7),
 857         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT        = 8,
 858         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK         = BIT(8),
 859         OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT         = 16,
 860         OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK          = 0xFFFF <<
 861                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
 862
 863         OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT              = 0,
 864         OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK               = 0xFFFF,
 865         OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT              = 16,
 866         OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK               = 0xFFFF <<
 867                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,
 868
 869         OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT         = 0,
 870         OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK          = 0xFFFF,
 871         OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT         = 16,
 872         OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK          = 0xFFFF <<
 873                                 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,
 874
 875         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT             = 0,
 876         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK              = 0xFFFF,
 877         OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT             = 16,
 878         OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK              = 0xFFFF <<
 879                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,
 880
 881         OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT              = 0,
 882         OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK               = 0xFFFF,
 883         OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT              = 16,
 884         OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK               = 0xFFFF <<
 885                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,
 886
 887         OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT            = 0,
 888         OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK             = 0xFFFF,
 889         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT           = 16,
 890         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK            = 0xFFFF <<
 891                                 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
 892 };
 893
 894 enum {
 895         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT   = 16,
 896         OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT     = 1
 897 };
 898
 899 #define MAX_OCRDMA_IRD_PAGES 4
 900
 901 enum ocrdma_qp_flags {
 902         OCRDMA_QP_MW_BIND       = 1,
 903         OCRDMA_QP_LKEY0         = (1 << 1),
 904         OCRDMA_QP_FAST_REG      = (1 << 2),
 905         OCRDMA_QP_INB_RD        = (1 << 6),
 906         OCRDMA_QP_INB_WR        = (1 << 7),
 907 };
 908
 909 enum ocrdma_qp_state {
 910         OCRDMA_QPS_RST          = 0,
 911         OCRDMA_QPS_INIT         = 1,
 912         OCRDMA_QPS_RTR          = 2,
 913         OCRDMA_QPS_RTS          = 3,
 914         OCRDMA_QPS_SQE          = 4,
 915         OCRDMA_QPS_SQ_DRAINING  = 5,
 916         OCRDMA_QPS_ERR          = 6,
 917         OCRDMA_QPS_SQD          = 7
 918 };
 919
 920 struct ocrdma_create_qp_req {
 921         struct ocrdma_mqe_hdr hdr;
 922         struct ocrdma_mbx_hdr req;
 923
 924         u32 type_pgsz_pdn;
 925         u32 max_wqe_rqe;
 926         u32 max_sge_send_write;
 927         u32 max_sge_recv_flags;
 928         u32 max_ord_ird;
 929         u32 num_wq_rq_pages;
 930         u32 wqe_rqe_size;
 931         u32 wq_rq_cqid;
 932         struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES];
 933         struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES];
 934         u32 dpp_credits_cqid;
 935         u32 rpir_lkey;
 936         struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES];
 937 };
 938
 939 enum {
 940         OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT                = 0,
 941         OCRDMA_CREATE_QP_RSP_QP_ID_MASK                 = 0xFFFF,
 942
 943         OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT              = 0,
 944         OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK               = 0xFFFF,
 945         OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT              = 16,
 946         OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK               = 0xFFFF <<
 947                                 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,
 948
 949         OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT        = 0,
 950         OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK         = 0xFFFF,
 951         OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT         = 16,
 952         OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK          = 0xFFFF <<
 953                                 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,
 954
 955         OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT         = 16,
 956         OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK          = 0xFFFF <<
 957                                 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,
 958
 959         OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT              = 0,
 960         OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK               = 0xFFFF,
 961         OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT              = 16,
 962         OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK               = 0xFFFF <<
 963                                 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,
 964
 965         OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT                = 0,
 966         OCRDMA_CREATE_QP_RSP_RQ_ID_MASK                 = 0xFFFF,
 967         OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT                = 16,
 968         OCRDMA_CREATE_QP_RSP_SQ_ID_MASK                 = 0xFFFF <<
 969                                 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
 970
 971         OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK           = BIT(0),
 972         OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT      = 1,
 973         OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK       = 0x7FFF <<
 974                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
 975         OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT          = 16,
 976         OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK           = 0xFFFF <<
 977                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,
 978 };
 979
 980 struct ocrdma_create_qp_rsp {
 981         struct ocrdma_mqe_hdr hdr;
 982         struct ocrdma_mbx_rsp rsp;
 983
 984         u32 qp_id;
 985         u32 max_wqe_rqe;
 986         u32 max_sge_send_write;
 987         u32 max_sge_recv;
 988         u32 max_ord_ird;
 989         u32 sq_rq_id;
 990         u32 dpp_response;
 991 };
 992
 993 struct ocrdma_destroy_qp {
 994         struct ocrdma_mqe_hdr hdr;
 995         struct ocrdma_mbx_hdr req;
 996         u32 qp_id;
 997 };
 998
 999 struct ocrdma_destroy_qp_rsp {
1000         struct ocrdma_mqe_hdr hdr;
1001         struct ocrdma_mbx_rsp rsp;
1002 };
1003
1004 enum {
1005         OCRDMA_MODIFY_QP_ID_SHIFT       = 0,
1006         OCRDMA_MODIFY_QP_ID_MASK        = 0xFFFF,
1007
1008         OCRDMA_QP_PARA_QPS_VALID        = BIT(0),
1009         OCRDMA_QP_PARA_SQD_ASYNC_VALID  = BIT(1),
1010         OCRDMA_QP_PARA_PKEY_VALID       = BIT(2),
1011         OCRDMA_QP_PARA_QKEY_VALID       = BIT(3),
1012         OCRDMA_QP_PARA_PMTU_VALID       = BIT(4),
1013         OCRDMA_QP_PARA_ACK_TO_VALID     = BIT(5),
1014         OCRDMA_QP_PARA_RETRY_CNT_VALID  = BIT(6),
1015         OCRDMA_QP_PARA_RRC_VALID        = BIT(7),
1016         OCRDMA_QP_PARA_RQPSN_VALID      = BIT(8),
1017         OCRDMA_QP_PARA_MAX_IRD_VALID    = BIT(9),
1018         OCRDMA_QP_PARA_MAX_ORD_VALID    = BIT(10),
1019         OCRDMA_QP_PARA_RNT_VALID        = BIT(11),
1020         OCRDMA_QP_PARA_SQPSN_VALID      = BIT(12),
1021         OCRDMA_QP_PARA_DST_QPN_VALID    = BIT(13),
1022         OCRDMA_QP_PARA_MAX_WQE_VALID    = BIT(14),
1023         OCRDMA_QP_PARA_MAX_RQE_VALID    = BIT(15),
1024         OCRDMA_QP_PARA_SGE_SEND_VALID   = BIT(16),
1025         OCRDMA_QP_PARA_SGE_RECV_VALID   = BIT(17),
1026         OCRDMA_QP_PARA_SGE_WR_VALID     = BIT(18),
1027         OCRDMA_QP_PARA_INB_RDEN_VALID   = BIT(19),
1028         OCRDMA_QP_PARA_INB_WREN_VALID   = BIT(20),
1029         OCRDMA_QP_PARA_FLOW_LBL_VALID   = BIT(21),
1030         OCRDMA_QP_PARA_BIND_EN_VALID    = BIT(22),
1031         OCRDMA_QP_PARA_ZLKEY_EN_VALID   = BIT(23),
1032         OCRDMA_QP_PARA_FMR_EN_VALID     = BIT(24),
1033         OCRDMA_QP_PARA_INBAT_EN_VALID   = BIT(25),
1034         OCRDMA_QP_PARA_VLAN_EN_VALID    = BIT(26),
1035
1036         OCRDMA_MODIFY_QP_FLAGS_RD       = BIT(0),
1037         OCRDMA_MODIFY_QP_FLAGS_WR       = BIT(1),
1038         OCRDMA_MODIFY_QP_FLAGS_SEND     = BIT(2),
1039         OCRDMA_MODIFY_QP_FLAGS_ATOMIC   = BIT(3)
1040 };
1041
1042 enum {
1043         OCRDMA_QP_PARAMS_SRQ_ID_SHIFT           = 0,
1044         OCRDMA_QP_PARAMS_SRQ_ID_MASK            = 0xFFFF,
1045
1046         OCRDMA_QP_PARAMS_MAX_RQE_SHIFT          = 0,
1047         OCRDMA_QP_PARAMS_MAX_RQE_MASK           = 0xFFFF,
1048         OCRDMA_QP_PARAMS_MAX_WQE_SHIFT          = 16,
1049         OCRDMA_QP_PARAMS_MAX_WQE_MASK           = 0xFFFF <<
1050             OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,
1051
1052         OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT    = 0,
1053         OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK     = 0xFFFF,
1054         OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT     = 16,
1055         OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK      = 0xFFFF <<
1056                                         OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
1057
1058         OCRDMA_QP_PARAMS_FLAGS_FMR_EN           = BIT(0),
1059         OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN        = BIT(1),
1060         OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN       = BIT(2),
1061         OCRDMA_QP_PARAMS_FLAGS_INBWR_EN         = BIT(3),
1062         OCRDMA_QP_PARAMS_FLAGS_INBRD_EN         = BIT(4),
1063         OCRDMA_QP_PARAMS_STATE_SHIFT            = 5,
1064         OCRDMA_QP_PARAMS_STATE_MASK             = BIT(5) | BIT(6) | BIT(7),
1065         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC        = BIT(8),
1066         OCRDMA_QP_PARAMS_FLAGS_INB_ATEN         = BIT(9),
1067         OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT     = 16,
1068         OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK      = 0xFFFF <<
1069                                         OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
1070
1071         OCRDMA_QP_PARAMS_MAX_IRD_SHIFT          = 0,
1072         OCRDMA_QP_PARAMS_MAX_IRD_MASK           = 0xFFFF,
1073         OCRDMA_QP_PARAMS_MAX_ORD_SHIFT          = 16,
1074         OCRDMA_QP_PARAMS_MAX_ORD_MASK           = 0xFFFF <<
1075                                         OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,
1076
1077         OCRDMA_QP_PARAMS_RQ_CQID_SHIFT          = 0,
1078         OCRDMA_QP_PARAMS_RQ_CQID_MASK           = 0xFFFF,
1079         OCRDMA_QP_PARAMS_WQ_CQID_SHIFT          = 16,
1080         OCRDMA_QP_PARAMS_WQ_CQID_MASK           = 0xFFFF <<
1081                                         OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,
1082
1083         OCRDMA_QP_PARAMS_RQ_PSN_SHIFT           = 0,
1084         OCRDMA_QP_PARAMS_RQ_PSN_MASK            = 0xFFFFFF,
1085         OCRDMA_QP_PARAMS_HOP_LMT_SHIFT          = 24,
1086         OCRDMA_QP_PARAMS_HOP_LMT_MASK           = 0xFF <<
1087                                         OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
1088
1089         OCRDMA_QP_PARAMS_SQ_PSN_SHIFT           = 0,
1090         OCRDMA_QP_PARAMS_SQ_PSN_MASK            = 0xFFFFFF,
1091         OCRDMA_QP_PARAMS_TCLASS_SHIFT           = 24,
1092         OCRDMA_QP_PARAMS_TCLASS_MASK            = 0xFF <<
1093                                         OCRDMA_QP_PARAMS_TCLASS_SHIFT,
1094
1095         OCRDMA_QP_PARAMS_DEST_QPN_SHIFT         = 0,
1096         OCRDMA_QP_PARAMS_DEST_QPN_MASK          = 0xFFFFFF,
1097         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT    = 24,
1098         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK     = 0x7 <<
1099                                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,
1100         OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT      = 27,
1101         OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK       = 0x1F <<
1102                                         OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,
1103
1104         OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT       = 0,
1105         OCRDMA_QP_PARAMS_PKEY_INDEX_MASK        = 0xFFFF,
1106         OCRDMA_QP_PARAMS_PATH_MTU_SHIFT         = 18,
1107         OCRDMA_QP_PARAMS_PATH_MTU_MASK          = 0x3FFF <<
1108                                         OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,
1109
1110         OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT       = 0,
1111         OCRDMA_QP_PARAMS_FLOW_LABEL_MASK        = 0xFFFFF,
1112         OCRDMA_QP_PARAMS_SL_SHIFT               = 20,
1113         OCRDMA_QP_PARAMS_SL_MASK                = 0xF <<
1114                                         OCRDMA_QP_PARAMS_SL_SHIFT,
1115         OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT        = 24,
1116         OCRDMA_QP_PARAMS_RETRY_CNT_MASK         = 0x7 <<
1117                                         OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,
1118         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT    = 27,
1119         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK     = 0x1F <<
1120                                         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,
1121
1122         OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT    = 0,
1123         OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK     = 0xFFFF,
1124         OCRDMA_QP_PARAMS_VLAN_SHIFT             = 16,
1125         OCRDMA_QP_PARAMS_VLAN_MASK              = 0xFFFF <<
1126                                         OCRDMA_QP_PARAMS_VLAN_SHIFT
1127 };
1128
1129 struct ocrdma_qp_params {
1130         u32 id;
1131         u32 max_wqe_rqe;
1132         u32 max_sge_send_write;
1133         u32 max_sge_recv_flags;
1134         u32 max_ord_ird;
1135         u32 wq_rq_cqid;
1136         u32 hop_lmt_rq_psn;
1137         u32 tclass_sq_psn;
1138         u32 ack_to_rnr_rtc_dest_qpn;
1139         u32 path_mtu_pkey_indx;
1140         u32 rnt_rc_sl_fl;
1141         u8 sgid[16];
1142         u8 dgid[16];
1143         u32 dmac_b0_to_b3;
1144         u32 vlan_dmac_b4_to_b5;
1145         u32 qkey;
1146 };
1147
1148
1149 struct ocrdma_modify_qp {
1150         struct ocrdma_mqe_hdr hdr;
1151         struct ocrdma_mbx_hdr req;
1152
1153         struct ocrdma_qp_params params;
1154         u32 flags;
1155         u32 rdma_flags;
1156         u32 num_outstanding_atomic_rd;
1157 };
1158
1159 enum {
1160         OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT      = 0,
1161         OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK       = 0xFFFF,
1162         OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT      = 16,
1163         OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK       = 0xFFFF <<
1164                                         OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,
1165
1166         OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT      = 0,
1167         OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK       = 0xFFFF,
1168         OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT      = 16,
1169         OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK       = 0xFFFF <<
1170                                         OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
1171 };
1172
1173 struct ocrdma_modify_qp_rsp {
1174         struct ocrdma_mqe_hdr hdr;
1175         struct ocrdma_mbx_rsp rsp;
1176
1177         u32 max_wqe_rqe;
1178         u32 max_ord_ird;
1179 };
1180
1181 struct ocrdma_query_qp {
1182         struct ocrdma_mqe_hdr hdr;
1183         struct ocrdma_mbx_hdr req;
1184
1185 #define OCRDMA_QUERY_UP_QP_ID_SHIFT     0
1186 #define OCRDMA_QUERY_UP_QP_ID_MASK      0xFFFFFF
1187         u32 qp_id;
1188 };
1189
1190 struct ocrdma_query_qp_rsp {
1191         struct ocrdma_mqe_hdr hdr;
1192         struct ocrdma_mbx_rsp rsp;
1193         struct ocrdma_qp_params params;
1194         u32 dpp_credits_cqid;
1195         u32 rbq_id;
1196 };
1197
1198 enum {
1199         OCRDMA_CREATE_SRQ_PD_ID_SHIFT           = 0,
1200         OCRDMA_CREATE_SRQ_PD_ID_MASK            = 0xFFFF,
1201         OCRDMA_CREATE_SRQ_PG_SZ_SHIFT           = 16,
1202         OCRDMA_CREATE_SRQ_PG_SZ_MASK            = 0x3 <<
1203                                         OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,
1204
1205         OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT         = 0,
1206         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT    = 16,
1207         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK     = 0xFFFF <<
1208                                         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,
1209
1210         OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT        = 0,
1211         OCRDMA_CREATE_SRQ_RQE_SIZE_MASK         = 0xFFFF,
1212         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT    = 16,
1213         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK     = 0xFFFF <<
1214                                         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
1215 };
1216
1217 struct ocrdma_create_srq {
1218         struct ocrdma_mqe_hdr hdr;
1219         struct ocrdma_mbx_hdr req;
1220
1221         u32 pgsz_pdid;
1222         u32 max_sge_rqe;
1223         u32 pages_rqe_sz;
1224         struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES];
1225 };
1226
1227 enum {
1228         OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT                      = 0,
1229         OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK                       = 0xFFFFFF,
1230
1231         OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT           = 0,
1232         OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK            = 0xFFFF,
1233         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT      = 16,
1234         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK       = 0xFFFF <<
1235                         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
1236 };
1237
1238 struct ocrdma_create_srq_rsp {
1239         struct ocrdma_mqe_hdr hdr;
1240         struct ocrdma_mbx_rsp rsp;
1241
1242         u32 id;
1243         u32 max_sge_rqe_allocated;
1244 };
1245
1246 enum {
1247         OCRDMA_MODIFY_SRQ_ID_SHIFT      = 0,
1248         OCRDMA_MODIFY_SRQ_ID_MASK       = 0xFFFFFF,
1249
1250         OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0,
1251         OCRDMA_MODIFY_SRQ_MAX_RQE_MASK  = 0xFFFF,
1252         OCRDMA_MODIFY_SRQ_LIMIT_SHIFT   = 16,
1253         OCRDMA_MODIFY_SRQ__LIMIT_MASK   = 0xFFFF <<
1254                                         OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
1255 };
1256
1257 struct ocrdma_modify_srq {
1258         struct ocrdma_mqe_hdr hdr;
1259         struct ocrdma_mbx_rsp rep;
1260
1261         u32 id;
1262         u32 limit_max_rqe;
1263 };
1264
1265 enum {
1266         OCRDMA_QUERY_SRQ_ID_SHIFT       = 0,
1267         OCRDMA_QUERY_SRQ_ID_MASK        = 0xFFFFFF
1268 };
1269
1270 struct ocrdma_query_srq {
1271         struct ocrdma_mqe_hdr hdr;
1272         struct ocrdma_mbx_rsp req;
1273
1274         u32 id;
1275 };
1276
1277 enum {
1278         OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT        = 0,
1279         OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK         = 0xFFFF,
1280         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT      = 16,
1281         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK       = 0xFFFF <<
1282                                         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,
1283
1284         OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0,
1285         OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK  = 0xFFFF,
1286         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT    = 16,
1287         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK     = 0xFFFF <<
1288                                         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
1289 };
1290
1291 struct ocrdma_query_srq_rsp {
1292         struct ocrdma_mqe_hdr hdr;
1293         struct ocrdma_mbx_rsp req;
1294
1295         u32 max_rqe_pdid;
1296         u32 srq_lmt_max_sge;
1297 };
1298
1299 enum {
1300         OCRDMA_DESTROY_SRQ_ID_SHIFT     = 0,
1301         OCRDMA_DESTROY_SRQ_ID_MASK      = 0xFFFFFF
1302 };
1303
1304 struct ocrdma_destroy_srq {
1305         struct ocrdma_mqe_hdr hdr;
1306         struct ocrdma_mbx_rsp req;
1307
1308         u32 id;
1309 };
1310
1311 enum {
1312         OCRDMA_ALLOC_PD_ENABLE_DPP      = BIT(16),
1313         OCRDMA_DPP_PAGE_SIZE            = 4096
1314 };
1315
1316 struct ocrdma_alloc_pd {
1317         struct ocrdma_mqe_hdr hdr;
1318         struct ocrdma_mbx_hdr req;
1319         u32 enable_dpp_rsvd;
1320 };
1321
1322 enum {
1323         OCRDMA_ALLOC_PD_RSP_DPP                 = BIT(16),
1324         OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT      = 20,
1325         OCRDMA_ALLOC_PD_RSP_PDID_MASK           = 0xFFFF,
1326 };
1327
1328 struct ocrdma_alloc_pd_rsp {
1329         struct ocrdma_mqe_hdr hdr;
1330         struct ocrdma_mbx_rsp rsp;
1331         u32 dpp_page_pdid;
1332 };
1333
1334 struct ocrdma_dealloc_pd {
1335         struct ocrdma_mqe_hdr hdr;
1336         struct ocrdma_mbx_hdr req;
1337         u32 id;
1338 };
1339
1340 struct ocrdma_dealloc_pd_rsp {
1341         struct ocrdma_mqe_hdr hdr;
1342         struct ocrdma_mbx_rsp rsp;
1343 };
1344
1345 struct ocrdma_alloc_pd_range {
1346         struct ocrdma_mqe_hdr hdr;
1347         struct ocrdma_mbx_hdr req;
1348         u32 enable_dpp_rsvd;
1349         u32 pd_count;
1350 };
1351
1352 struct ocrdma_alloc_pd_range_rsp {
1353         struct ocrdma_mqe_hdr hdr;
1354         struct ocrdma_mbx_rsp rsp;
1355         u32 dpp_page_pdid;
1356         u32 pd_count;
1357 };
1358
1359 enum {
1360         OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK = 0xFFFF,
1361 };
1362
1363 struct ocrdma_dealloc_pd_range {
1364         struct ocrdma_mqe_hdr hdr;
1365         struct ocrdma_mbx_hdr req;
1366         u32 start_pd_id;
1367         u32 pd_count;
1368 };
1369
1370 struct ocrdma_dealloc_pd_range_rsp {
1371         struct ocrdma_mqe_hdr hdr;
1372         struct ocrdma_mbx_hdr req;
1373         u32 rsvd;
1374 };
1375
1376 enum {
1377         OCRDMA_ADDR_CHECK_ENABLE        = 1,
1378         OCRDMA_ADDR_CHECK_DISABLE       = 0
1379 };
1380
1381 enum {
1382         OCRDMA_ALLOC_LKEY_PD_ID_SHIFT           = 0,
1383         OCRDMA_ALLOC_LKEY_PD_ID_MASK            = 0xFFFF,
1384
1385         OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT      = 0,
1386         OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK       = BIT(0),
1387         OCRDMA_ALLOC_LKEY_FMR_SHIFT             = 1,
1388         OCRDMA_ALLOC_LKEY_FMR_MASK              = BIT(1),
1389         OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT      = 2,
1390         OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK       = BIT(2),
1391         OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT       = 3,
1392         OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK        = BIT(3),
1393         OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT       = 4,
1394         OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK        = BIT(4),
1395         OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT        = 5,
1396         OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK         = BIT(5),
1397         OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK    = BIT(6),
1398         OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT   = 6,
1399         OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT        = 16,
1400         OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK         = 0xFFFF <<
1401                                                 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
1402 };
1403
1404 struct ocrdma_alloc_lkey {
1405         struct ocrdma_mqe_hdr hdr;
1406         struct ocrdma_mbx_hdr req;
1407
1408         u32 pdid;
1409         u32 pbl_sz_flags;
1410 };
1411
1412 struct ocrdma_alloc_lkey_rsp {
1413         struct ocrdma_mqe_hdr hdr;
1414         struct ocrdma_mbx_rsp rsp;
1415
1416         u32 lrkey;
1417         u32 num_pbl_rsvd;
1418 };
1419
1420 struct ocrdma_dealloc_lkey {
1421         struct ocrdma_mqe_hdr hdr;
1422         struct ocrdma_mbx_hdr req;
1423
1424         u32 lkey;
1425         u32 rsvd_frmr;
1426 };
1427
1428 struct ocrdma_dealloc_lkey_rsp {
1429         struct ocrdma_mqe_hdr hdr;
1430         struct ocrdma_mbx_rsp rsp;
1431 };
1432
1433 #define MAX_OCRDMA_NSMR_PBL    (u32)22
1434 #define MAX_OCRDMA_PBL_SIZE     65536
1435 #define MAX_OCRDMA_PBL_PER_LKEY 32767
1436
1437 enum {
1438         OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT       = 0,
1439         OCRDMA_REG_NSMR_LRKEY_INDEX_MASK        = 0xFFFFFF,
1440         OCRDMA_REG_NSMR_LRKEY_SHIFT             = 24,
1441         OCRDMA_REG_NSMR_LRKEY_MASK              = 0xFF <<
1442                                         OCRDMA_REG_NSMR_LRKEY_SHIFT,
1443
1444         OCRDMA_REG_NSMR_PD_ID_SHIFT             = 0,
1445         OCRDMA_REG_NSMR_PD_ID_MASK              = 0xFFFF,
1446         OCRDMA_REG_NSMR_NUM_PBL_SHIFT           = 16,
1447         OCRDMA_REG_NSMR_NUM_PBL_MASK            = 0xFFFF <<
1448                                         OCRDMA_REG_NSMR_NUM_PBL_SHIFT,
1449
1450         OCRDMA_REG_NSMR_PBE_SIZE_SHIFT          = 0,
1451         OCRDMA_REG_NSMR_PBE_SIZE_MASK           = 0xFFFF,
1452         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT        = 16,
1453         OCRDMA_REG_NSMR_HPAGE_SIZE_MASK         = 0xFF <<
1454                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
1455         OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT       = 24,
1456         OCRDMA_REG_NSMR_BIND_MEMWIN_MASK        = BIT(24),
1457         OCRDMA_REG_NSMR_ZB_SHIFT                = 25,
1458         OCRDMA_REG_NSMR_ZB_SHIFT_MASK           = BIT(25),
1459         OCRDMA_REG_NSMR_REMOTE_INV_SHIFT        = 26,
1460         OCRDMA_REG_NSMR_REMOTE_INV_MASK         = BIT(26),
1461         OCRDMA_REG_NSMR_REMOTE_WR_SHIFT         = 27,
1462         OCRDMA_REG_NSMR_REMOTE_WR_MASK          = BIT(27),
1463         OCRDMA_REG_NSMR_REMOTE_RD_SHIFT         = 28,
1464         OCRDMA_REG_NSMR_REMOTE_RD_MASK          = BIT(28),
1465         OCRDMA_REG_NSMR_LOCAL_WR_SHIFT          = 29,
1466         OCRDMA_REG_NSMR_LOCAL_WR_MASK           = BIT(29),
1467         OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT     = 30,
1468         OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK      = BIT(30),
1469         OCRDMA_REG_NSMR_LAST_SHIFT              = 31,
1470         OCRDMA_REG_NSMR_LAST_MASK               = BIT(31)
1471 };
1472
1473 struct ocrdma_reg_nsmr {
1474         struct ocrdma_mqe_hdr hdr;
1475         struct ocrdma_mbx_hdr cmd;
1476
1477         u32 fr_mr;
1478         u32 num_pbl_pdid;
1479         u32 flags_hpage_pbe_sz;
1480         u32 totlen_low;
1481         u32 totlen_high;
1482         u32 fbo_low;
1483         u32 fbo_high;
1484         u32 va_loaddr;
1485         u32 va_hiaddr;
1486         struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1487 };
1488
1489 enum {
1490         OCRDMA_REG_NSMR_CONT_PBL_SHIFT          = 0,
1491         OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK     = 0xFFFF,
1492         OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT      = 16,
1493         OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK       = 0xFFFF <<
1494                                         OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
1495
1496         OCRDMA_REG_NSMR_CONT_LAST_SHIFT         = 31,
1497         OCRDMA_REG_NSMR_CONT_LAST_MASK          = BIT(31)
1498 };
1499
1500 struct ocrdma_reg_nsmr_cont {
1501         struct ocrdma_mqe_hdr hdr;
1502         struct ocrdma_mbx_hdr cmd;
1503
1504         u32 lrkey;
1505         u32 num_pbl_offset;
1506         u32 last;
1507
1508         struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1509 };
1510
1511 struct ocrdma_pbe {
1512         u32 pa_hi;
1513         u32 pa_lo;
1514 };
1515
1516 enum {
1517         OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT       = 16,
1518         OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK        = 0xFFFF0000
1519 };
1520 struct ocrdma_reg_nsmr_rsp {
1521         struct ocrdma_mqe_hdr hdr;
1522         struct ocrdma_mbx_rsp rsp;
1523
1524         u32 lrkey;
1525         u32 num_pbl;
1526 };
1527
1528 enum {
1529         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT      = 0,
1530         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK       = 0xFFFFFF,
1531         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT            = 24,
1532         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK             = 0xFF <<
1533                                         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,
1534
1535         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT          = 16,
1536         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK           = 0xFFFF <<
1537                                         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
1538 };
1539
1540 struct ocrdma_reg_nsmr_cont_rsp {
1541         struct ocrdma_mqe_hdr hdr;
1542         struct ocrdma_mbx_rsp rsp;
1543
1544         u32 lrkey_key_index;
1545         u32 num_pbl;
1546 };
1547
1548 enum {
1549         OCRDMA_ALLOC_MW_PD_ID_SHIFT     = 0,
1550         OCRDMA_ALLOC_MW_PD_ID_MASK      = 0xFFFF
1551 };
1552
1553 struct ocrdma_alloc_mw {
1554         struct ocrdma_mqe_hdr hdr;
1555         struct ocrdma_mbx_hdr req;
1556
1557         u32 pdid;
1558 };
1559
1560 enum {
1561         OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT   = 0,
1562         OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK    = 0xFFFFFF
1563 };
1564
1565 struct ocrdma_alloc_mw_rsp {
1566         struct ocrdma_mqe_hdr hdr;
1567         struct ocrdma_mbx_rsp rsp;
1568
1569         u32 lrkey_index;
1570 };
1571
1572 struct ocrdma_attach_mcast {
1573         struct ocrdma_mqe_hdr hdr;
1574         struct ocrdma_mbx_hdr req;
1575         u32 qp_id;
1576         u8 mgid[16];
1577         u32 mac_b0_to_b3;
1578         u32 vlan_mac_b4_to_b5;
1579 };
1580
1581 struct ocrdma_attach_mcast_rsp {
1582         struct ocrdma_mqe_hdr hdr;
1583         struct ocrdma_mbx_rsp rsp;
1584 };
1585
1586 struct ocrdma_detach_mcast {
1587         struct ocrdma_mqe_hdr hdr;
1588         struct ocrdma_mbx_hdr req;
1589         u32 qp_id;
1590         u8 mgid[16];
1591         u32 mac_b0_to_b3;
1592         u32 vlan_mac_b4_to_b5;
1593 };
1594
1595 struct ocrdma_detach_mcast_rsp {
1596         struct ocrdma_mqe_hdr hdr;
1597         struct ocrdma_mbx_rsp rsp;
1598 };
1599
1600 enum {
1601         OCRDMA_CREATE_AH_NUM_PAGES_SHIFT        = 19,
1602         OCRDMA_CREATE_AH_NUM_PAGES_MASK         = 0xF <<
1603                                         OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,
1604
1605         OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT        = 16,
1606         OCRDMA_CREATE_AH_PAGE_SIZE_MASK         = 0x7 <<
1607                                         OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,
1608
1609         OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT       = 23,
1610         OCRDMA_CREATE_AH_ENTRY_SIZE_MASK        = 0x1FF <<
1611                                         OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,
1612 };
1613
1614 #define OCRDMA_AH_TBL_PAGES 8
1615
1616 struct ocrdma_create_ah_tbl {
1617         struct ocrdma_mqe_hdr hdr;
1618         struct ocrdma_mbx_hdr req;
1619
1620         u32 ah_conf;
1621         struct ocrdma_pa tbl_addr[8];
1622 };
1623
1624 struct ocrdma_create_ah_tbl_rsp {
1625         struct ocrdma_mqe_hdr hdr;
1626         struct ocrdma_mbx_rsp rsp;
1627         u32 ahid;
1628 };
1629
1630 struct ocrdma_delete_ah_tbl {
1631         struct ocrdma_mqe_hdr hdr;
1632         struct ocrdma_mbx_hdr req;
1633         u32 ahid;
1634 };
1635
1636 struct ocrdma_delete_ah_tbl_rsp {
1637         struct ocrdma_mqe_hdr hdr;
1638         struct ocrdma_mbx_rsp rsp;
1639 };
1640
1641 enum {
1642         OCRDMA_EQE_VALID_SHIFT          = 0,
1643         OCRDMA_EQE_VALID_MASK           = BIT(0),
1644         OCRDMA_EQE_MAJOR_CODE_MASK      = 0x0E,
1645         OCRDMA_EQE_MAJOR_CODE_SHIFT     = 0x01,
1646         OCRDMA_EQE_FOR_CQE_MASK         = 0xFFFE,
1647         OCRDMA_EQE_RESOURCE_ID_SHIFT    = 16,
1648         OCRDMA_EQE_RESOURCE_ID_MASK     = 0xFFFF <<
1649                                 OCRDMA_EQE_RESOURCE_ID_SHIFT,
1650 };
1651
1652 enum major_code {
1653         OCRDMA_MAJOR_CODE_COMPLETION    = 0x00,
1654         OCRDMA_MAJOR_CODE_SENTINAL      = 0x01
1655 };
1656
1657 struct ocrdma_eqe {
1658         u32 id_valid;
1659 };
1660
1661 enum OCRDMA_CQE_STATUS {
1662         OCRDMA_CQE_SUCCESS = 0,
1663         OCRDMA_CQE_LOC_LEN_ERR,
1664         OCRDMA_CQE_LOC_QP_OP_ERR,
1665         OCRDMA_CQE_LOC_EEC_OP_ERR,
1666         OCRDMA_CQE_LOC_PROT_ERR,
1667         OCRDMA_CQE_WR_FLUSH_ERR,
1668         OCRDMA_CQE_MW_BIND_ERR,
1669         OCRDMA_CQE_BAD_RESP_ERR,
1670         OCRDMA_CQE_LOC_ACCESS_ERR,
1671         OCRDMA_CQE_REM_INV_REQ_ERR,
1672         OCRDMA_CQE_REM_ACCESS_ERR,
1673         OCRDMA_CQE_REM_OP_ERR,
1674         OCRDMA_CQE_RETRY_EXC_ERR,
1675         OCRDMA_CQE_RNR_RETRY_EXC_ERR,
1676         OCRDMA_CQE_LOC_RDD_VIOL_ERR,
1677         OCRDMA_CQE_REM_INV_RD_REQ_ERR,
1678         OCRDMA_CQE_REM_ABORT_ERR,
1679         OCRDMA_CQE_INV_EECN_ERR,
1680         OCRDMA_CQE_INV_EEC_STATE_ERR,
1681         OCRDMA_CQE_FATAL_ERR,
1682         OCRDMA_CQE_RESP_TIMEOUT_ERR,
1683         OCRDMA_CQE_GENERAL_ERR,
1684
1685         OCRDMA_MAX_CQE_ERR
1686 };
1687
1688 enum {
1689         /* w0 */
1690         OCRDMA_CQE_WQEIDX_SHIFT         = 0,
1691         OCRDMA_CQE_WQEIDX_MASK          = 0xFFFF,
1692
1693         /* w1 */
1694         OCRDMA_CQE_UD_XFER_LEN_SHIFT    = 16,
1695         OCRDMA_CQE_PKEY_SHIFT           = 0,
1696         OCRDMA_CQE_PKEY_MASK            = 0xFFFF,
1697
1698         /* w2 */
1699         OCRDMA_CQE_QPN_SHIFT            = 0,
1700         OCRDMA_CQE_QPN_MASK             = 0x0000FFFF,
1701
1702         OCRDMA_CQE_BUFTAG_SHIFT         = 16,
1703         OCRDMA_CQE_BUFTAG_MASK          = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT,
1704
1705         /* w3 */
1706         OCRDMA_CQE_UD_STATUS_SHIFT      = 24,
1707         OCRDMA_CQE_UD_STATUS_MASK       = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
1708         OCRDMA_CQE_STATUS_SHIFT         = 16,
1709         OCRDMA_CQE_STATUS_MASK          = 0xFF << OCRDMA_CQE_STATUS_SHIFT,
1710         OCRDMA_CQE_VALID                = BIT(31),
1711         OCRDMA_CQE_INVALIDATE           = BIT(30),
1712         OCRDMA_CQE_QTYPE                = BIT(29),
1713         OCRDMA_CQE_IMM                  = BIT(28),
1714         OCRDMA_CQE_WRITE_IMM            = BIT(27),
1715         OCRDMA_CQE_QTYPE_SQ             = 0,
1716         OCRDMA_CQE_QTYPE_RQ             = 1,
1717         OCRDMA_CQE_SRCQP_MASK           = 0xFFFFFF
1718 };
1719
1720 struct ocrdma_cqe {
1721         union {
1722                 /* w0 to w2 */
1723                 struct {
1724                         u32 wqeidx;
1725                         u32 bytes_xfered;
1726                         u32 qpn;
1727                 } wq;
1728                 struct {
1729                         u32 lkey_immdt;
1730                         u32 rxlen;
1731                         u32 buftag_qpn;
1732                 } rq;
1733                 struct {
1734                         u32 lkey_immdt;
1735                         u32 rxlen_pkey;
1736                         u32 buftag_qpn;
1737                 } ud;
1738                 struct {
1739                         u32 word_0;
1740                         u32 word_1;
1741                         u32 qpn;
1742                 } cmn;
1743         };
1744         u32 flags_status_srcqpn;        /* w3 */
1745 };
1746
1747 struct ocrdma_sge {
1748         u32 addr_hi;
1749         u32 addr_lo;
1750         u32 lrkey;
1751         u32 len;
1752 };
1753
1754 enum {
1755         OCRDMA_FLAG_SIG         = 0x1,
1756         OCRDMA_FLAG_INV         = 0x2,
1757         OCRDMA_FLAG_FENCE_L     = 0x4,
1758         OCRDMA_FLAG_FENCE_R     = 0x8,
1759         OCRDMA_FLAG_SOLICIT     = 0x10,
1760         OCRDMA_FLAG_IMM         = 0x20,
1761         OCRDMA_FLAG_AH_VLAN_PR  = 0x40,
1762
1763         /* Stag flags */
1764         OCRDMA_LKEY_FLAG_LOCAL_WR       = 0x1,
1765         OCRDMA_LKEY_FLAG_REMOTE_RD      = 0x2,
1766         OCRDMA_LKEY_FLAG_REMOTE_WR      = 0x4,
1767         OCRDMA_LKEY_FLAG_VATO           = 0x8,
1768 };
1769
1770 enum OCRDMA_WQE_OPCODE {
1771         OCRDMA_WRITE            = 0x06,
1772         OCRDMA_READ             = 0x0C,
1773         OCRDMA_RESV0            = 0x02,
1774         OCRDMA_SEND             = 0x00,
1775         OCRDMA_CMP_SWP          = 0x14,
1776         OCRDMA_BIND_MW          = 0x10,
1777         OCRDMA_FR_MR            = 0x11,
1778         OCRDMA_RESV1            = 0x0A,
1779         OCRDMA_LKEY_INV         = 0x15,
1780         OCRDMA_FETCH_ADD        = 0x13,
1781         OCRDMA_POST_RQ          = 0x12
1782 };
1783
1784 enum {
1785         OCRDMA_TYPE_INLINE      = 0x0,
1786         OCRDMA_TYPE_LKEY        = 0x1,
1787 };
1788
1789 enum {
1790         OCRDMA_WQE_OPCODE_SHIFT         = 0,
1791         OCRDMA_WQE_OPCODE_MASK          = 0x0000001F,
1792         OCRDMA_WQE_FLAGS_SHIFT          = 5,
1793         OCRDMA_WQE_TYPE_SHIFT           = 16,
1794         OCRDMA_WQE_TYPE_MASK            = 0x00030000,
1795         OCRDMA_WQE_SIZE_SHIFT           = 18,
1796         OCRDMA_WQE_SIZE_MASK            = 0xFF,
1797         OCRDMA_WQE_NXT_WQE_SIZE_SHIFT   = 25,
1798
1799         OCRDMA_WQE_LKEY_FLAGS_SHIFT     = 0,
1800         OCRDMA_WQE_LKEY_FLAGS_MASK      = 0xF
1801 };
1802
1803 /* header WQE for all the SQ and RQ operations */
1804 struct ocrdma_hdr_wqe {
1805         u32 cw;
1806         union {
1807                 u32 rsvd_tag;
1808                 u32 rsvd_lkey_flags;
1809         };
1810         union {
1811                 u32 immdt;
1812                 u32 lkey;
1813         };
1814         u32 total_len;
1815 };
1816
1817 struct ocrdma_ewqe_ud_hdr {
1818         u32 rsvd_dest_qpn;
1819         u32 qkey;
1820         u32 rsvd_ahid;
1821         u32 rsvd;
1822 };
1823
1824 /* extended wqe followed by hdr_wqe for Fast Memory register */
1825 struct ocrdma_ewqe_fr {
1826         u32 va_hi;
1827         u32 va_lo;
1828         u32 fbo_hi;
1829         u32 fbo_lo;
1830         u32 size_sge;
1831         u32 num_sges;
1832         u32 rsvd;
1833         u32 rsvd2;
1834 };
1835
1836 struct ocrdma_eth_basic {
1837         u8 dmac[6];
1838         u8 smac[6];
1839         __be16 eth_type;
1840 } __packed;
1841
1842 struct ocrdma_eth_vlan {
1843         u8 dmac[6];
1844         u8 smac[6];
1845         __be16 eth_type;
1846         __be16 vlan_tag;
1847 #define OCRDMA_ROCE_ETH_TYPE 0x8915
1848         __be16 roce_eth_type;
1849 } __packed;
1850
1851 struct ocrdma_grh {
1852         __be32  tclass_flow;
1853         __be32  pdid_hoplimit;
1854         u8      sgid[16];
1855         u8      dgid[16];
1856         u16     rsvd;
1857 } __packed;
1858
1859 #define OCRDMA_AV_VALID         BIT(7)
1860 #define OCRDMA_AV_VLAN_VALID    BIT(1)
1861
1862 struct ocrdma_av {
1863         struct ocrdma_eth_vlan eth_hdr;
1864         struct ocrdma_grh grh;
1865         u32 valid;
1866 } __packed;
1867
1868 struct ocrdma_rsrc_stats {
1869         u32 dpp_pds;
1870         u32 non_dpp_pds;
1871         u32 rc_dpp_qps;
1872         u32 uc_dpp_qps;
1873         u32 ud_dpp_qps;
1874         u32 rc_non_dpp_qps;
1875         u32 rsvd;
1876         u32 uc_non_dpp_qps;
1877         u32 ud_non_dpp_qps;
1878         u32 rsvd1;
1879         u32 srqs;
1880         u32 rbqs;
1881         u32 r64K_nsmr;
1882         u32 r64K_to_2M_nsmr;
1883         u32 r2M_to_44M_nsmr;
1884         u32 r44M_to_1G_nsmr;
1885         u32 r1G_to_4G_nsmr;
1886         u32 nsmr_count_4G_to_32G;
1887         u32 r32G_to_64G_nsmr;
1888         u32 r64G_to_128G_nsmr;
1889         u32 r128G_to_higher_nsmr;
1890         u32 embedded_nsmr;
1891         u32 frmr;
1892         u32 prefetch_qps;
1893         u32 ondemand_qps;
1894         u32 phy_mr;
1895         u32 mw;
1896         u32 rsvd2[7];
1897 };
1898
1899 struct ocrdma_db_err_stats {
1900         u32 sq_doorbell_errors;
1901         u32 cq_doorbell_errors;
1902         u32 rq_srq_doorbell_errors;
1903         u32 cq_overflow_errors;
1904         u32 rsvd[4];
1905 };
1906
1907 struct ocrdma_wqe_stats {
1908         u32 large_send_rc_wqes_lo;
1909         u32 large_send_rc_wqes_hi;
1910         u32 large_write_rc_wqes_lo;
1911         u32 large_write_rc_wqes_hi;
1912         u32 rsvd[4];
1913         u32 read_wqes_lo;
1914         u32 read_wqes_hi;
1915         u32 frmr_wqes_lo;
1916         u32 frmr_wqes_hi;
1917         u32 mw_bind_wqes_lo;
1918         u32 mw_bind_wqes_hi;
1919         u32 invalidate_wqes_lo;
1920         u32 invalidate_wqes_hi;
1921         u32 rsvd1[2];
1922         u32 dpp_wqe_drops;
1923         u32 rsvd2[5];
1924 };
1925
1926 struct ocrdma_tx_stats {
1927         u32 send_pkts_lo;
1928         u32 send_pkts_hi;
1929         u32 write_pkts_lo;
1930         u32 write_pkts_hi;
1931         u32 read_pkts_lo;
1932         u32 read_pkts_hi;
1933         u32 read_rsp_pkts_lo;
1934         u32 read_rsp_pkts_hi;
1935         u32 ack_pkts_lo;
1936         u32 ack_pkts_hi;
1937         u32 send_bytes_lo;
1938         u32 send_bytes_hi;
1939         u32 write_bytes_lo;
1940         u32 write_bytes_hi;
1941         u32 read_req_bytes_lo;
1942         u32 read_req_bytes_hi;
1943         u32 read_rsp_bytes_lo;
1944         u32 read_rsp_bytes_hi;
1945         u32 ack_timeouts;
1946         u32 rsvd[5];
1947 };
1948
1949
1950 struct ocrdma_tx_qp_err_stats {
1951         u32 local_length_errors;
1952         u32 local_protection_errors;
1953         u32 local_qp_operation_errors;
1954         u32 retry_count_exceeded_errors;
1955         u32 rnr_retry_count_exceeded_errors;
1956         u32 rsvd[3];
1957 };
1958
1959 struct ocrdma_rx_stats {
1960         u32 roce_frame_bytes_lo;
1961         u32 roce_frame_bytes_hi;
1962         u32 roce_frame_icrc_drops;
1963         u32 roce_frame_payload_len_drops;
1964         u32 ud_drops;
1965         u32 qp1_drops;
1966         u32 psn_error_request_packets;
1967         u32 psn_error_resp_packets;
1968         u32 rnr_nak_timeouts;
1969         u32 rnr_nak_receives;
1970         u32 roce_frame_rxmt_drops;
1971         u32 nak_count_psn_sequence_errors;
1972         u32 rc_drop_count_lookup_errors;
1973         u32 rq_rnr_naks;
1974         u32 srq_rnr_naks;
1975         u32 roce_frames_lo;
1976         u32 roce_frames_hi;
1977         u32 rsvd;
1978 };
1979
1980 struct ocrdma_rx_qp_err_stats {
1981         u32 nak_invalid_requst_errors;
1982         u32 nak_remote_operation_errors;
1983         u32 nak_count_remote_access_errors;
1984         u32 local_length_errors;
1985         u32 local_protection_errors;
1986         u32 local_qp_operation_errors;
1987         u32 rsvd[2];
1988 };
1989
1990 struct ocrdma_tx_dbg_stats {
1991         u32 data[100];
1992 };
1993
1994 struct ocrdma_rx_dbg_stats {
1995         u32 data[200];
1996 };
1997
1998 struct ocrdma_rdma_stats_req {
1999         struct ocrdma_mbx_hdr hdr;
2000         u8 reset_stats;
2001         u8 rsvd[3];
2002 } __packed;
2003
2004 struct ocrdma_rdma_stats_resp {
2005         struct ocrdma_mbx_hdr hdr;
2006         struct ocrdma_rsrc_stats act_rsrc_stats;
2007         struct ocrdma_rsrc_stats th_rsrc_stats;
2008         struct ocrdma_db_err_stats      db_err_stats;
2009         struct ocrdma_wqe_stats         wqe_stats;
2010         struct ocrdma_tx_stats          tx_stats;
2011         struct ocrdma_tx_qp_err_stats   tx_qp_err_stats;
2012         struct ocrdma_rx_stats          rx_stats;
2013         struct ocrdma_rx_qp_err_stats   rx_qp_err_stats;
2014         struct ocrdma_tx_dbg_stats      tx_dbg_stats;
2015         struct ocrdma_rx_dbg_stats      rx_dbg_stats;
2016 } __packed;
2017
2018 enum {
2019         OCRDMA_HBA_ATTRB_EPROM_VER_LO_MASK      = 0xFF,
2020         OCRDMA_HBA_ATTRB_EPROM_VER_HI_MASK      = 0xFF00,
2021         OCRDMA_HBA_ATTRB_EPROM_VER_HI_SHIFT     = 0x08,
2022         OCRDMA_HBA_ATTRB_CDBLEN_MASK            = 0xFFFF,
2023         OCRDMA_HBA_ATTRB_ASIC_REV_MASK          = 0xFF0000,
2024         OCRDMA_HBA_ATTRB_ASIC_REV_SHIFT         = 0x10,
2025         OCRDMA_HBA_ATTRB_GUID0_MASK             = 0xFF000000,
2026         OCRDMA_HBA_ATTRB_GUID0_SHIFT            = 0x18,
2027         OCRDMA_HBA_ATTRB_GUID13_MASK            = 0xFF,
2028         OCRDMA_HBA_ATTRB_GUID14_MASK            = 0xFF00,
2029         OCRDMA_HBA_ATTRB_GUID14_SHIFT           = 0x08,
2030         OCRDMA_HBA_ATTRB_GUID15_MASK            = 0xFF0000,
2031         OCRDMA_HBA_ATTRB_GUID15_SHIFT           = 0x10,
2032         OCRDMA_HBA_ATTRB_PCNT_MASK              = 0xFF000000,
2033         OCRDMA_HBA_ATTRB_PCNT_SHIFT             = 0x18,
2034         OCRDMA_HBA_ATTRB_LDTOUT_MASK            = 0xFFFF,
2035         OCRDMA_HBA_ATTRB_ISCSI_VER_MASK         = 0xFF0000,
2036         OCRDMA_HBA_ATTRB_ISCSI_VER_SHIFT        = 0x10,
2037         OCRDMA_HBA_ATTRB_MFUNC_DEV_MASK         = 0xFF000000,
2038         OCRDMA_HBA_ATTRB_MFUNC_DEV_SHIFT        = 0x18,
2039         OCRDMA_HBA_ATTRB_CV_MASK                = 0xFF,
2040         OCRDMA_HBA_ATTRB_HBA_ST_MASK            = 0xFF00,
2041         OCRDMA_HBA_ATTRB_HBA_ST_SHIFT           = 0x08,
2042         OCRDMA_HBA_ATTRB_MAX_DOMS_MASK          = 0xFF0000,
2043         OCRDMA_HBA_ATTRB_MAX_DOMS_SHIFT         = 0x10,
2044         OCRDMA_HBA_ATTRB_PTNUM_MASK             = 0x3F000000,
2045         OCRDMA_HBA_ATTRB_PTNUM_SHIFT            = 0x18,
2046         OCRDMA_HBA_ATTRB_PT_MASK                = 0xC0000000,
2047         OCRDMA_HBA_ATTRB_PT_SHIFT               = 0x1E,
2048         OCRDMA_HBA_ATTRB_ISCSI_FET_MASK         = 0xFF,
2049         OCRDMA_HBA_ATTRB_ASIC_GEN_MASK          = 0xFF00,
2050         OCRDMA_HBA_ATTRB_ASIC_GEN_SHIFT         = 0x08,
2051         OCRDMA_HBA_ATTRB_PCI_VID_MASK           = 0xFFFF,
2052         OCRDMA_HBA_ATTRB_PCI_DID_MASK           = 0xFFFF0000,
2053         OCRDMA_HBA_ATTRB_PCI_DID_SHIFT          = 0x10,
2054         OCRDMA_HBA_ATTRB_PCI_SVID_MASK          = 0xFFFF,
2055         OCRDMA_HBA_ATTRB_PCI_SSID_MASK          = 0xFFFF0000,
2056         OCRDMA_HBA_ATTRB_PCI_SSID_SHIFT         = 0x10,
2057         OCRDMA_HBA_ATTRB_PCI_BUSNUM_MASK        = 0xFF,
2058         OCRDMA_HBA_ATTRB_PCI_DEVNUM_MASK        = 0xFF00,
2059         OCRDMA_HBA_ATTRB_PCI_DEVNUM_SHIFT       = 0x08,
2060         OCRDMA_HBA_ATTRB_PCI_FUNCNUM_MASK       = 0xFF0000,
2061         OCRDMA_HBA_ATTRB_PCI_FUNCNUM_SHIFT      = 0x10,
2062         OCRDMA_HBA_ATTRB_IF_TYPE_MASK           = 0xFF000000,
2063         OCRDMA_HBA_ATTRB_IF_TYPE_SHIFT          = 0x18,
2064         OCRDMA_HBA_ATTRB_NETFIL_MASK            =0xFF
2065 };
2066
2067 struct mgmt_hba_attribs {
2068         u8 flashrom_version_string[32];
2069         u8 manufacturer_name[32];
2070         u32 supported_modes;
2071         u32 rsvd_eprom_verhi_verlo;
2072         u32 mbx_ds_ver;
2073         u32 epfw_ds_ver;
2074         u8 ncsi_ver_string[12];
2075         u32 default_extended_timeout;
2076         u8 controller_model_number[32];
2077         u8 controller_description[64];
2078         u8 controller_serial_number[32];
2079         u8 ip_version_string[32];
2080         u8 firmware_version_string[32];
2081         u8 bios_version_string[32];
2082         u8 redboot_version_string[32];
2083         u8 driver_version_string[32];
2084         u8 fw_on_flash_version_string[32];
2085         u32 functionalities_supported;
2086         u32 guid0_asicrev_cdblen;
2087         u8 generational_guid[12];
2088         u32 portcnt_guid15;
2089         u32 mfuncdev_iscsi_ldtout;
2090         u32 ptpnum_maxdoms_hbast_cv;
2091         u32 firmware_post_status;
2092         u32 hba_mtu[8];
2093         u32 res_asicgen_iscsi_feaures;
2094         u32 rsvd1[3];
2095 };
2096
2097 struct mgmt_controller_attrib {
2098         struct mgmt_hba_attribs hba_attribs;
2099         u32 pci_did_vid;
2100         u32 pci_ssid_svid;
2101         u32 ityp_fnum_devnum_bnum;
2102         u32 uid_hi;
2103         u32 uid_lo;
2104         u32 res_nnetfil;
2105         u32 rsvd0[4];
2106 };
2107
2108 struct ocrdma_get_ctrl_attribs_rsp {
2109         struct ocrdma_mbx_hdr hdr;
2110         struct mgmt_controller_attrib ctrl_attribs;
2111 };
2112
2113 #define OCRDMA_SUBSYS_DCBX 0x10
2114
2115 enum OCRDMA_DCBX_OPCODE {
2116         OCRDMA_CMD_GET_DCBX_CONFIG = 0x01
2117 };
2118
2119 enum OCRDMA_DCBX_PARAM_TYPE {
2120         OCRDMA_PARAMETER_TYPE_ADMIN     = 0x00,
2121         OCRDMA_PARAMETER_TYPE_OPER      = 0x01,
2122         OCRDMA_PARAMETER_TYPE_PEER      = 0x02
2123 };
2124
2125 enum OCRDMA_DCBX_APP_PROTO {
2126         OCRDMA_APP_PROTO_ROCE   = 0x8915
2127 };
2128
2129 enum OCRDMA_DCBX_PROTO {
2130         OCRDMA_PROTO_SELECT_L2  = 0x00,
2131         OCRDMA_PROTO_SELECT_L4  = 0x01
2132 };
2133
2134 enum OCRDMA_DCBX_APP_PARAM {
2135         OCRDMA_APP_PARAM_APP_PROTO_MASK = 0xFFFF,
2136         OCRDMA_APP_PARAM_PROTO_SEL_MASK = 0xFF,
2137         OCRDMA_APP_PARAM_PROTO_SEL_SHIFT = 0x10,
2138         OCRDMA_APP_PARAM_VALID_MASK     = 0xFF,
2139         OCRDMA_APP_PARAM_VALID_SHIFT    = 0x18
2140 };
2141
2142 enum OCRDMA_DCBX_STATE_FLAGS {
2143         OCRDMA_STATE_FLAG_ENABLED       = 0x01,
2144         OCRDMA_STATE_FLAG_ADDVERTISED   = 0x02,
2145         OCRDMA_STATE_FLAG_WILLING       = 0x04,
2146         OCRDMA_STATE_FLAG_SYNC          = 0x08,
2147         OCRDMA_STATE_FLAG_UNSUPPORTED   = 0x40000000,
2148         OCRDMA_STATE_FLAG_NEG_FAILD     = 0x80000000
2149 };
2150
2151 enum OCRDMA_TCV_AEV_OPV_ST {
2152         OCRDMA_DCBX_TC_SUPPORT_MASK     = 0xFF,
2153         OCRDMA_DCBX_TC_SUPPORT_SHIFT    = 0x18,
2154         OCRDMA_DCBX_APP_ENTRY_SHIFT     = 0x10,
2155         OCRDMA_DCBX_OP_PARAM_SHIFT      = 0x08,
2156         OCRDMA_DCBX_STATE_MASK          = 0xFF
2157 };
2158
2159 struct ocrdma_app_parameter {
2160         u32 valid_proto_app;
2161         u32 oui;
2162         u32 app_prio[2];
2163 };
2164
2165 struct ocrdma_dcbx_cfg {
2166         u32 tcv_aev_opv_st;
2167         u32 tc_state;
2168         u32 pfc_state;
2169         u32 qcn_state;
2170         u32 appl_state;
2171         u32 ll_state;
2172         u32 tc_bw[2];
2173         u32 tc_prio[8];
2174         u32 pfc_prio[2];
2175         struct ocrdma_app_parameter app_param[15];
2176 };
2177
2178 struct ocrdma_get_dcbx_cfg_req {
2179         struct ocrdma_mbx_hdr hdr;
2180         u32 param_type;
2181 } __packed;
2182
2183 struct ocrdma_get_dcbx_cfg_rsp {
2184         struct ocrdma_mbx_rsp hdr;
2185         struct ocrdma_dcbx_cfg cfg;
2186 } __packed;
2187
2188 #endif                          /* __OCRDMA_SLI_H__ */