1 /* QLogic qedr NIC Driver
2 * Copyright (c) 2015-2016 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/pci.h>
36 #include <linux/idr.h>
37 #include <rdma/ib_addr.h>
38 #include <linux/qed/qed_if.h>
39 #include <linux/qed/qed_chain.h>
40 #include <linux/qed/qed_rdma_if.h>
41 #include <linux/qed/qede_rdma.h>
42 #include <linux/qed/roce_common.h>
43 #include "qedr_hsi_rdma.h"
45 #define QEDR_NODE_DESC "QLogic 579xx RoCE HCA"
46 #define DP_NAME(dev) ((dev)->ibdev.name)
47 #define IS_IWARP(_dev) ((_dev)->rdma_type == QED_RDMA_TYPE_IWARP)
48 #define IS_ROCE(_dev) ((_dev)->rdma_type == QED_RDMA_TYPE_ROCE)
50 #define DP_DEBUG(dev, module, fmt, ...) \
51 pr_debug("(%s) " module ": " fmt, \
52 DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__)
54 #define QEDR_MSG_INIT "INIT"
55 #define QEDR_MSG_MISC "MISC"
56 #define QEDR_MSG_CQ " CQ"
57 #define QEDR_MSG_MR " MR"
58 #define QEDR_MSG_RQ " RQ"
59 #define QEDR_MSG_SQ " SQ"
60 #define QEDR_MSG_QP " QP"
61 #define QEDR_MSG_GSI " GSI"
62 #define QEDR_MSG_IWARP " IW"
64 #define QEDR_CQ_MAGIC_NUMBER (0x11223344)
66 #define FW_PAGE_SIZE (RDMA_RING_PAGE_SIZE)
67 #define FW_PAGE_SHIFT (12)
74 struct qed_sb_info *sb;
81 #define QEDR_MAX_SGID 128
83 struct qedr_device_attr {
95 u8 max_qp_resp_rd_atomic_resc;
96 u8 max_qp_req_rd_atomic_resc;
97 u64 max_dev_resp_rd_atomic_resc;
105 u32 max_mr_mw_fmr_pbl;
106 u64 max_mr_mw_fmr_size;
119 u32 bad_pkey_counter;
120 struct qed_rdma_events events;
123 #define QEDR_ENET_STATE_BIT (0)
126 struct ib_device ibdev;
127 struct qed_dev *cdev;
128 struct pci_dev *pdev;
129 struct net_device *ndev;
131 enum ib_atomic_cap atomic_cap;
134 struct qedr_device_attr attr;
136 const struct qed_rdma_ops *ops;
137 struct qed_int_info int_info;
139 struct qed_sb_info *sb_array;
140 struct qedr_cnq *cnq_array;
144 void __iomem *db_addr;
149 union ib_gid *sgid_tbl;
151 /* Lock for sgid table */
152 spinlock_t sgid_lock;
162 u8 gsi_ll2_mac_address[ETH_ALEN];
164 struct qedr_cq *gsi_sqcq;
165 struct qedr_cq *gsi_rqcq;
166 struct qedr_qp *gsi_qp;
167 enum qed_rdma_type rdma_type;
168 spinlock_t idr_lock; /* Protect qpidr data-structure */
170 struct workqueue_struct *iwarp_wq;
173 unsigned long enet_state;
178 #define QEDR_MAX_SQ_PBL (0x8000)
179 #define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *))
180 #define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge))
181 #define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \
182 QEDR_SQE_ELEMENT_SIZE)
183 #define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
184 QEDR_SQE_ELEMENT_SIZE)
185 #define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\
186 (RDMA_RING_PAGE_SIZE) / \
187 (QEDR_SQE_ELEMENT_SIZE) /\
188 (QEDR_MAX_SQE_ELEMENTS_PER_SQE))
190 #define QEDR_MAX_RQ_PBL (0x2000)
191 #define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *))
192 #define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge))
193 #define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE)
194 #define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
195 QEDR_RQE_ELEMENT_SIZE)
196 #define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\
197 (RDMA_RING_PAGE_SIZE) / \
198 (QEDR_RQE_ELEMENT_SIZE) /\
199 (QEDR_MAX_RQE_ELEMENTS_PER_RQE))
201 #define QEDR_CQE_SIZE (sizeof(union rdma_cqe))
202 #define QEDR_MAX_CQE_PBL_SIZE (512 * 1024)
203 #define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \
205 #define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \
206 (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE))
208 #define QEDR_ROCE_MAX_CNQ_SIZE (0x4000)
210 #define QEDR_MAX_PORT (1)
211 #define QEDR_PORT (1)
213 #define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
215 #define QEDR_ROCE_PKEY_MAX 1
216 #define QEDR_ROCE_PKEY_TABLE_LEN 1
217 #define QEDR_ROCE_PKEY_DEFAULT 0xffff
220 struct list_head list_entry;
225 struct qedr_ucontext {
226 struct ib_ucontext ibucontext;
227 struct qedr_dev *dev;
234 struct list_head mm_head;
236 /* Lock to protect mm list */
237 struct mutex mm_list_lock;
241 struct rdma_pwm_val32_data data;
251 struct qedr_pbl_info {
260 struct ib_umem *umem;
261 struct qedr_pbl_info pbl_info;
262 struct qedr_pbl *pbl_tbl;
270 enum qedr_cq_type cq_type;
275 /* Lock to protect multiplem CQ's */
278 struct qed_chain pbl;
280 void __iomem *db_addr;
284 union rdma_cqe *latest_cqe;
285 union rdma_cqe *toggle_cqe;
297 struct qedr_ucontext *uctx;
305 struct list_head entry;
309 struct rdma_pwm_val16_data data;
313 struct qedr_qp_hwq_info {
315 struct qed_chain pbl;
328 union db_prod32 db_data;
330 void __iomem *iwarp_db2;
331 union db_prod32 iwarp_db2_data;
334 #define QEDR_INC_SW_IDX(p_info, index) \
336 p_info->index = (p_info->index + 1) & \
337 qed_chain_get_capacity(p_info->pbl) \
340 enum qedr_qp_err_bitmap {
341 QEDR_QP_ERR_SQ_FULL = 1,
342 QEDR_QP_ERR_RQ_FULL = 2,
343 QEDR_QP_ERR_BAD_SR = 4,
344 QEDR_QP_ERR_BAD_RR = 8,
345 QEDR_QP_ERR_SQ_PBL_FULL = 16,
346 QEDR_QP_ERR_RQ_PBL_FULL = 32,
350 struct ib_qp ibqp; /* must be first */
351 struct qedr_dev *dev;
352 struct qedr_iw_ep *ep;
353 struct qedr_qp_hwq_info sq;
354 struct qedr_qp_hwq_info rq;
360 struct qedr_cq *sq_cq;
361 struct qedr_cq *rq_cq;
362 struct qedr_srq *srq;
363 enum qed_roce_qp_state state;
366 enum ib_qp_type qp_type;
367 struct qed_rdma_qp *qed_qp;
377 /* Relevant to qps created from kernel space only (ULPs) */
386 enum ib_wc_opcode opcode;
390 dma_addr_t icrc_mapping;
398 struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE];
406 /* Relevant to qps created from user space only (applications) */
407 struct qedr_userq usq;
408 struct qedr_userq urq;
415 struct rdma_ah_attr attr;
426 struct qedr_pbl *pbl_table;
427 struct qedr_pbl_info pbl_info;
428 struct list_head free_pbl_list;
429 struct list_head inuse_pbl_list;
431 u32 completed_handled;
436 struct ib_umem *umem;
438 struct qed_rdma_register_tid_in_params hw_mr;
439 enum qedr_mr_type type;
441 struct qedr_dev *dev;
448 #define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT)))
450 #define QEDR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \
451 RDMA_CQE_RESPONDER_IMM_FLG_SHIFT)
452 #define QEDR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \
453 RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT)
454 #define QEDR_RESP_INV (RDMA_CQE_RESPONDER_INV_FLG_MASK << \
455 RDMA_CQE_RESPONDER_INV_FLG_SHIFT)
457 static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info)
459 info->cons = (info->cons + 1) % info->max_wr;
463 static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info)
465 info->prod = (info->prod + 1) % info->max_wr;
468 static inline int qedr_get_dmac(struct qedr_dev *dev,
469 struct rdma_ah_attr *ah_attr, u8 *mac_addr)
471 union ib_gid zero_sgid = { { 0 } };
473 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
476 if (!memcmp(&grh->dgid, &zero_sgid, sizeof(union ib_gid))) {
477 DP_ERR(dev, "Local port GID not supported\n");
478 eth_zero_addr(mac_addr);
482 memcpy(&in6, grh->dgid.raw, sizeof(in6));
483 dmac = rdma_ah_retrieve_dmac(ah_attr);
486 ether_addr_copy(mac_addr, dmac);
491 struct qedr_iw_listener {
492 struct qedr_dev *dev;
493 struct iw_cm_id *cm_id;
499 struct qedr_dev *dev;
500 struct iw_cm_id *cm_id;
507 struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext)
509 return container_of(ibucontext, struct qedr_ucontext, ibucontext);
512 static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev)
514 return container_of(ibdev, struct qedr_dev, ibdev);
517 static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd)
519 return container_of(ibpd, struct qedr_pd, ibpd);
522 static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq)
524 return container_of(ibcq, struct qedr_cq, ibcq);
527 static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp)
529 return container_of(ibqp, struct qedr_qp, ibqp);
532 static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah)
534 return container_of(ibah, struct qedr_ah, ibah);
537 static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr)
539 return container_of(ibmr, struct qedr_mr, ibmr);