drivers/iommu/ipmmu-vmsa.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * IOMMU API for Renesas VMSA-compatible IPMMU
   4  * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
   5  *
   6  * Copyright (C) 2014-2020 Renesas Electronics Corporation
   7  */
   8
   9 #include <linux/bitmap.h>
  10 #include <linux/delay.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/err.h>
  13 #include <linux/export.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/io-pgtable.h>
  18 #include <linux/iommu.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/sizes.h>
  24 #include <linux/slab.h>
  25 #include <linux/sys_soc.h>
  26
  27 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
  28 #include <asm/dma-iommu.h>
  29 #else
  30 #define arm_iommu_create_mapping(...)   NULL
  31 #define arm_iommu_attach_device(...)    -ENODEV
  32 #define arm_iommu_release_mapping(...)  do {} while (0)
  33 #define arm_iommu_detach_device(...)    do {} while (0)
  34 #endif
  35
  36 #define IPMMU_CTX_MAX           16U
  37 #define IPMMU_CTX_INVALID       -1
  38
  39 #define IPMMU_UTLB_MAX          64U
  40
  41 struct ipmmu_features {
  42         bool use_ns_alias_offset;
  43         bool has_cache_leaf_nodes;
  44         unsigned int number_of_contexts;
  45         unsigned int num_utlbs;
  46         bool setup_imbuscr;
  47         bool twobit_imttbcr_sl0;
  48         bool reserved_context;
  49         bool cache_snoop;
  50         unsigned int ctx_offset_base;
  51         unsigned int ctx_offset_stride;
  52         unsigned int utlb_offset_base;
  53 };
  54
  55 struct ipmmu_vmsa_device {
  56         struct device *dev;
  57         void __iomem *base;
  58         struct iommu_device iommu;
  59         struct ipmmu_vmsa_device *root;
  60         const struct ipmmu_features *features;
  61         unsigned int num_ctx;
  62         spinlock_t lock;                        /* Protects ctx and domains[] */
  63         DECLARE_BITMAP(ctx, IPMMU_CTX_MAX);
  64         struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX];
  65         s8 utlb_ctx[IPMMU_UTLB_MAX];
  66
  67         struct iommu_group *group;
  68         struct dma_iommu_mapping *mapping;
  69 };
  70
  71 struct ipmmu_vmsa_domain {
  72         struct ipmmu_vmsa_device *mmu;
  73         struct iommu_domain io_domain;
  74
  75         struct io_pgtable_cfg cfg;
  76         struct io_pgtable_ops *iop;
  77
  78         unsigned int context_id;
  79         struct mutex mutex;                     /* Protects mappings */
  80 };
  81
  82 static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom)
  83 {
  84         return container_of(dom, struct ipmmu_vmsa_domain, io_domain);
  85 }
  86
  87 static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev)
  88 {
  89         return dev_iommu_priv_get(dev);
  90 }
  91
  92 #define TLB_LOOP_TIMEOUT                100     /* 100us */
  93
  94 /* -----------------------------------------------------------------------------
  95  * Registers Definition
  96  */
  97
  98 #define IM_NS_ALIAS_OFFSET              0x800
  99
 100 /* MMU "context" registers */
 101 #define IMCTR                           0x0000          /* R-Car Gen2/3 */
 102 #define IMCTR_INTEN                     (1 << 2)        /* R-Car Gen2/3 */
 103 #define IMCTR_FLUSH                     (1 << 1)        /* R-Car Gen2/3 */
 104 #define IMCTR_MMUEN                     (1 << 0)        /* R-Car Gen2/3 */
 105
 106 #define IMTTBCR                         0x0008          /* R-Car Gen2/3 */
 107 #define IMTTBCR_EAE                     (1 << 31)       /* R-Car Gen2/3 */
 108 #define IMTTBCR_SH0_INNER_SHAREABLE     (3 << 12)       /* R-Car Gen2 only */
 109 #define IMTTBCR_ORGN0_WB_WA             (1 << 10)       /* R-Car Gen2 only */
 110 #define IMTTBCR_IRGN0_WB_WA             (1 << 8)        /* R-Car Gen2 only */
 111 #define IMTTBCR_SL0_TWOBIT_LVL_1        (2 << 6)        /* R-Car Gen3 only */
 112 #define IMTTBCR_SL0_LVL_1               (1 << 4)        /* R-Car Gen2 only */
 113
 114 #define IMBUSCR                         0x000c          /* R-Car Gen2 only */
 115 #define IMBUSCR_DVM                     (1 << 2)        /* R-Car Gen2 only */
 116 #define IMBUSCR_BUSSEL_MASK             (3 << 0)        /* R-Car Gen2 only */
 117
 118 #define IMTTLBR0                        0x0010          /* R-Car Gen2/3 */
 119 #define IMTTUBR0                        0x0014          /* R-Car Gen2/3 */
 120
 121 #define IMSTR                           0x0020          /* R-Car Gen2/3 */
 122 #define IMSTR_MHIT                      (1 << 4)        /* R-Car Gen2/3 */
 123 #define IMSTR_ABORT                     (1 << 2)        /* R-Car Gen2/3 */
 124 #define IMSTR_PF                        (1 << 1)        /* R-Car Gen2/3 */
 125 #define IMSTR_TF                        (1 << 0)        /* R-Car Gen2/3 */
 126
 127 #define IMMAIR0                         0x0028          /* R-Car Gen2/3 */
 128
 129 #define IMELAR                          0x0030          /* R-Car Gen2/3, IMEAR on R-Car Gen2 */
 130 #define IMEUAR                          0x0034          /* R-Car Gen3 only */
 131
 132 /* uTLB registers */
 133 #define IMUCTR(n)                       ((n) < 32 ? IMUCTR0(n) : IMUCTR32(n))
 134 #define IMUCTR0(n)                      (0x0300 + ((n) * 16))           /* R-Car Gen2/3 */
 135 #define IMUCTR32(n)                     (0x0600 + (((n) - 32) * 16))    /* R-Car Gen3 only */
 136 #define IMUCTR_TTSEL_MMU(n)             ((n) << 4)      /* R-Car Gen2/3 */
 137 #define IMUCTR_FLUSH                    (1 << 1)        /* R-Car Gen2/3 */
 138 #define IMUCTR_MMUEN                    (1 << 0)        /* R-Car Gen2/3 */
 139
 140 #define IMUASID(n)                      ((n) < 32 ? IMUASID0(n) : IMUASID32(n))
 141 #define IMUASID0(n)                     (0x0308 + ((n) * 16))           /* R-Car Gen2/3 */
 142 #define IMUASID32(n)                    (0x0608 + (((n) - 32) * 16))    /* R-Car Gen3 only */
 143
 144 /* -----------------------------------------------------------------------------
 145  * Root device handling
 146  */
 147
 148 static struct platform_driver ipmmu_driver;
 149
 150 static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu)
 151 {
 152         return mmu->root == mmu;
 153 }
 154
 155 static int __ipmmu_check_device(struct device *dev, void *data)
 156 {
 157         struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev);
 158         struct ipmmu_vmsa_device **rootp = data;
 159
 160         if (ipmmu_is_root(mmu))
 161                 *rootp = mmu;
 162
 163         return 0;
 164 }
 165
 166 static struct ipmmu_vmsa_device *ipmmu_find_root(void)
 167 {
 168         struct ipmmu_vmsa_device *root = NULL;
 169
 170         return driver_for_each_device(&ipmmu_driver.driver, NULL, &root,
 171                                       __ipmmu_check_device) == 0 ? root : NULL;
 172 }
 173
 174 /* -----------------------------------------------------------------------------
 175  * Read/Write Access
 176  */
 177
 178 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset)
 179 {
 180         return ioread32(mmu->base + offset);
 181 }
 182
 183 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset,
 184                         u32 data)
 185 {
 186         iowrite32(data, mmu->base + offset);
 187 }
 188
 189 static unsigned int ipmmu_ctx_reg(struct ipmmu_vmsa_device *mmu,
 190                                   unsigned int context_id, unsigned int reg)
 191 {
 192         unsigned int base = mmu->features->ctx_offset_base;
 193
 194         if (context_id > 7)
 195                 base += 0x800 - 8 * 0x40;
 196
 197         return base + context_id * mmu->features->ctx_offset_stride + reg;
 198 }
 199
 200 static u32 ipmmu_ctx_read(struct ipmmu_vmsa_device *mmu,
 201                           unsigned int context_id, unsigned int reg)
 202 {
 203         return ipmmu_read(mmu, ipmmu_ctx_reg(mmu, context_id, reg));
 204 }
 205
 206 static void ipmmu_ctx_write(struct ipmmu_vmsa_device *mmu,
 207                             unsigned int context_id, unsigned int reg, u32 data)
 208 {
 209         ipmmu_write(mmu, ipmmu_ctx_reg(mmu, context_id, reg), data);
 210 }
 211
 212 static u32 ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain,
 213                                unsigned int reg)
 214 {
 215         return ipmmu_ctx_read(domain->mmu->root, domain->context_id, reg);
 216 }
 217
 218 static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain,
 219                                  unsigned int reg, u32 data)
 220 {
 221         ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data);
 222 }
 223
 224 static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain,
 225                                 unsigned int reg, u32 data)
 226 {
 227         if (domain->mmu != domain->mmu->root)
 228                 ipmmu_ctx_write(domain->mmu, domain->context_id, reg, data);
 229
 230         ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data);
 231 }
 232
 233 static u32 ipmmu_utlb_reg(struct ipmmu_vmsa_device *mmu, unsigned int reg)
 234 {
 235         return mmu->features->utlb_offset_base + reg;
 236 }
 237
 238 static void ipmmu_imuasid_write(struct ipmmu_vmsa_device *mmu,
 239                                 unsigned int utlb, u32 data)
 240 {
 241         ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUASID(utlb)), data);
 242 }
 243
 244 static void ipmmu_imuctr_write(struct ipmmu_vmsa_device *mmu,
 245                                unsigned int utlb, u32 data)
 246 {
 247         ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUCTR(utlb)), data);
 248 }
 249
 250 /* -----------------------------------------------------------------------------
 251  * TLB and microTLB Management
 252  */
 253
 254 /* Wait for any pending TLB invalidations to complete */
 255 static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain)
 256 {
 257         unsigned int count = 0;
 258
 259         while (ipmmu_ctx_read_root(domain, IMCTR) & IMCTR_FLUSH) {
 260                 cpu_relax();
 261                 if (++count == TLB_LOOP_TIMEOUT) {
 262                         dev_err_ratelimited(domain->mmu->dev,
 263                         "TLB sync timed out -- MMU may be deadlocked\n");
 264                         return;
 265                 }
 266                 udelay(1);
 267         }
 268 }
 269
 270 static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain)
 271 {
 272         u32 reg;
 273
 274         reg = ipmmu_ctx_read_root(domain, IMCTR);
 275         reg |= IMCTR_FLUSH;
 276         ipmmu_ctx_write_all(domain, IMCTR, reg);
 277
 278         ipmmu_tlb_sync(domain);
 279 }
 280
 281 /*
 282  * Enable MMU translation for the microTLB.
 283  */
 284 static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain,
 285                               unsigned int utlb)
 286 {
 287         struct ipmmu_vmsa_device *mmu = domain->mmu;
 288
 289         /*
 290          * TODO: Reference-count the microTLB as several bus masters can be
 291          * connected to the same microTLB.
 292          */
 293
 294         /* TODO: What should we set the ASID to ? */
 295         ipmmu_imuasid_write(mmu, utlb, 0);
 296         /* TODO: Do we need to flush the microTLB ? */
 297         ipmmu_imuctr_write(mmu, utlb, IMUCTR_TTSEL_MMU(domain->context_id) |
 298                                       IMUCTR_FLUSH | IMUCTR_MMUEN);
 299         mmu->utlb_ctx[utlb] = domain->context_id;
 300 }
 301
 302 static void ipmmu_tlb_flush_all(void *cookie)
 303 {
 304         struct ipmmu_vmsa_domain *domain = cookie;
 305
 306         ipmmu_tlb_invalidate(domain);
 307 }
 308
 309 static void ipmmu_tlb_flush(unsigned long iova, size_t size,
 310                                 size_t granule, void *cookie)
 311 {
 312         ipmmu_tlb_flush_all(cookie);
 313 }
 314
 315 static const struct iommu_flush_ops ipmmu_flush_ops = {
 316         .tlb_flush_all = ipmmu_tlb_flush_all,
 317         .tlb_flush_walk = ipmmu_tlb_flush,
 318 };
 319
 320 /* -----------------------------------------------------------------------------
 321  * Domain/Context Management
 322  */
 323
 324 static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device *mmu,
 325                                          struct ipmmu_vmsa_domain *domain)
 326 {
 327         unsigned long flags;
 328         int ret;
 329
 330         spin_lock_irqsave(&mmu->lock, flags);
 331
 332         ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx);
 333         if (ret != mmu->num_ctx) {
 334                 mmu->domains[ret] = domain;
 335                 set_bit(ret, mmu->ctx);
 336         } else
 337                 ret = -EBUSY;
 338
 339         spin_unlock_irqrestore(&mmu->lock, flags);
 340
 341         return ret;
 342 }
 343
 344 static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu,
 345                                       unsigned int context_id)
 346 {
 347         unsigned long flags;
 348
 349         spin_lock_irqsave(&mmu->lock, flags);
 350
 351         clear_bit(context_id, mmu->ctx);
 352         mmu->domains[context_id] = NULL;
 353
 354         spin_unlock_irqrestore(&mmu->lock, flags);
 355 }
 356
 357 static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain)
 358 {
 359         u64 ttbr;
 360         u32 tmp;
 361
 362         /* TTBR0 */
 363         ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr;
 364         ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr);
 365         ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32);
 366
 367         /*
 368          * TTBCR
 369          * We use long descriptors and allocate the whole 32-bit VA space to
 370          * TTBR0.
 371          */
 372         if (domain->mmu->features->twobit_imttbcr_sl0)
 373                 tmp = IMTTBCR_SL0_TWOBIT_LVL_1;
 374         else
 375                 tmp = IMTTBCR_SL0_LVL_1;
 376
 377         if (domain->mmu->features->cache_snoop)
 378                 tmp |= IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
 379                        IMTTBCR_IRGN0_WB_WA;
 380
 381         ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE | tmp);
 382
 383         /* MAIR0 */
 384         ipmmu_ctx_write_root(domain, IMMAIR0,
 385                              domain->cfg.arm_lpae_s1_cfg.mair);
 386
 387         /* IMBUSCR */
 388         if (domain->mmu->features->setup_imbuscr)
 389                 ipmmu_ctx_write_root(domain, IMBUSCR,
 390                                      ipmmu_ctx_read_root(domain, IMBUSCR) &
 391                                      ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
 392
 393         /*
 394          * IMSTR
 395          * Clear all interrupt flags.
 396          */
 397         ipmmu_ctx_write_root(domain, IMSTR, ipmmu_ctx_read_root(domain, IMSTR));
 398
 399         /*
 400          * IMCTR
 401          * Enable the MMU and interrupt generation. The long-descriptor
 402          * translation table format doesn't use TEX remapping. Don't enable AF
 403          * software management as we have no use for it. Flush the TLB as
 404          * required when modifying the context registers.
 405          */
 406         ipmmu_ctx_write_all(domain, IMCTR,
 407                             IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
 408 }
 409
 410 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
 411 {
 412         int ret;
 413
 414         /*
 415          * Allocate the page table operations.
 416          *
 417          * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
 418          * access, Long-descriptor format" that the NStable bit being set in a
 419          * table descriptor will result in the NStable and NS bits of all child
 420          * entries being ignored and considered as being set. The IPMMU seems
 421          * not to comply with this, as it generates a secure access page fault
 422          * if any of the NStable and NS bits isn't set when running in
 423          * non-secure mode.
 424          */
 425         domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS;
 426         domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K;
 427         domain->cfg.ias = 32;
 428         domain->cfg.oas = 40;
 429         domain->cfg.tlb = &ipmmu_flush_ops;
 430         domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32);
 431         domain->io_domain.geometry.force_aperture = true;
 432         /*
 433          * TODO: Add support for coherent walk through CCI with DVM and remove
 434          * cache handling. For now, delegate it to the io-pgtable code.
 435          */
 436         domain->cfg.coherent_walk = false;
 437         domain->cfg.iommu_dev = domain->mmu->root->dev;
 438
 439         /*
 440          * Find an unused context.
 441          */
 442         ret = ipmmu_domain_allocate_context(domain->mmu->root, domain);
 443         if (ret < 0)
 444                 return ret;
 445
 446         domain->context_id = ret;
 447
 448         domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
 449                                            domain);
 450         if (!domain->iop) {
 451                 ipmmu_domain_free_context(domain->mmu->root,
 452                                           domain->context_id);
 453                 return -EINVAL;
 454         }
 455
 456         ipmmu_domain_setup_context(domain);
 457         return 0;
 458 }
 459
 460 static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
 461 {
 462         if (!domain->mmu)
 463                 return;
 464
 465         /*
 466          * Disable the context. Flush the TLB as required when modifying the
 467          * context registers.
 468          *
 469          * TODO: Is TLB flush really needed ?
 470          */
 471         ipmmu_ctx_write_all(domain, IMCTR, IMCTR_FLUSH);
 472         ipmmu_tlb_sync(domain);
 473         ipmmu_domain_free_context(domain->mmu->root, domain->context_id);
 474 }
 475
 476 /* -----------------------------------------------------------------------------
 477  * Fault Handling
 478  */
 479
 480 static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
 481 {
 482         const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF;
 483         struct ipmmu_vmsa_device *mmu = domain->mmu;
 484         unsigned long iova;
 485         u32 status;
 486
 487         status = ipmmu_ctx_read_root(domain, IMSTR);
 488         if (!(status & err_mask))
 489                 return IRQ_NONE;
 490
 491         iova = ipmmu_ctx_read_root(domain, IMELAR);
 492         if (IS_ENABLED(CONFIG_64BIT))
 493                 iova |= (u64)ipmmu_ctx_read_root(domain, IMEUAR) << 32;
 494
 495         /*
 496          * Clear the error status flags. Unlike traditional interrupt flag
 497          * registers that must be cleared by writing 1, this status register
 498          * seems to require 0. The error address register must be read before,
 499          * otherwise its value will be 0.
 500          */
 501         ipmmu_ctx_write_root(domain, IMSTR, 0);
 502
 503         /* Log fatal errors. */
 504         if (status & IMSTR_MHIT)
 505                 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%lx\n",
 506                                     iova);
 507         if (status & IMSTR_ABORT)
 508                 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%lx\n",
 509                                     iova);
 510
 511         if (!(status & (IMSTR_PF | IMSTR_TF)))
 512                 return IRQ_NONE;
 513
 514         /*
 515          * Try to handle page faults and translation faults.
 516          *
 517          * TODO: We need to look up the faulty device based on the I/O VA. Use
 518          * the IOMMU device for now.
 519          */
 520         if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0))
 521                 return IRQ_HANDLED;
 522
 523         dev_err_ratelimited(mmu->dev,
 524                             "Unhandled fault: status 0x%08x iova 0x%lx\n",
 525                             status, iova);
 526
 527         return IRQ_HANDLED;
 528 }
 529
 530 static irqreturn_t ipmmu_irq(int irq, void *dev)
 531 {
 532         struct ipmmu_vmsa_device *mmu = dev;
 533         irqreturn_t status = IRQ_NONE;
 534         unsigned int i;
 535         unsigned long flags;
 536
 537         spin_lock_irqsave(&mmu->lock, flags);
 538
 539         /*
 540          * Check interrupts for all active contexts.
 541          */
 542         for (i = 0; i < mmu->num_ctx; i++) {
 543                 if (!mmu->domains[i])
 544                         continue;
 545                 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED)
 546                         status = IRQ_HANDLED;
 547         }
 548
 549         spin_unlock_irqrestore(&mmu->lock, flags);
 550
 551         return status;
 552 }
 553
 554 /* -----------------------------------------------------------------------------
 555  * IOMMU Operations
 556  */
 557
 558 static struct iommu_domain *ipmmu_domain_alloc(unsigned type)
 559 {
 560         struct ipmmu_vmsa_domain *domain;
 561
 562         if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
 563                 return NULL;
 564
 565         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 566         if (!domain)
 567                 return NULL;
 568
 569         mutex_init(&domain->mutex);
 570
 571         return &domain->io_domain;
 572 }
 573
 574 static void ipmmu_domain_free(struct iommu_domain *io_domain)
 575 {
 576         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 577
 578         /*
 579          * Free the domain resources. We assume that all devices have already
 580          * been detached.
 581          */
 582         ipmmu_domain_destroy_context(domain);
 583         free_io_pgtable_ops(domain->iop);
 584         kfree(domain);
 585 }
 586
 587 static int ipmmu_attach_device(struct iommu_domain *io_domain,
 588                                struct device *dev)
 589 {
 590         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 591         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 592         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 593         unsigned int i;
 594         int ret = 0;
 595
 596         if (!mmu) {
 597                 dev_err(dev, "Cannot attach to IPMMU\n");
 598                 return -ENXIO;
 599         }
 600
 601         mutex_lock(&domain->mutex);
 602
 603         if (!domain->mmu) {
 604                 /* The domain hasn't been used yet, initialize it. */
 605                 domain->mmu = mmu;
 606                 ret = ipmmu_domain_init_context(domain);
 607                 if (ret < 0) {
 608                         dev_err(dev, "Unable to initialize IPMMU context\n");
 609                         domain->mmu = NULL;
 610                 } else {
 611                         dev_info(dev, "Using IPMMU context %u\n",
 612                                  domain->context_id);
 613                 }
 614         } else if (domain->mmu != mmu) {
 615                 /*
 616                  * Something is wrong, we can't attach two devices using
 617                  * different IOMMUs to the same domain.
 618                  */
 619                 ret = -EINVAL;
 620         } else
 621                 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id);
 622
 623         mutex_unlock(&domain->mutex);
 624
 625         if (ret < 0)
 626                 return ret;
 627
 628         for (i = 0; i < fwspec->num_ids; ++i)
 629                 ipmmu_utlb_enable(domain, fwspec->ids[i]);
 630
 631         return 0;
 632 }
 633
 634 static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova,
 635                      phys_addr_t paddr, size_t pgsize, size_t pgcount,
 636                      int prot, gfp_t gfp, size_t *mapped)
 637 {
 638         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 639
 640         return domain->iop->map_pages(domain->iop, iova, paddr, pgsize, pgcount,
 641                                       prot, gfp, mapped);
 642 }
 643
 644 static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
 645                           size_t pgsize, size_t pgcount,
 646                           struct iommu_iotlb_gather *gather)
 647 {
 648         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 649
 650         return domain->iop->unmap_pages(domain->iop, iova, pgsize, pgcount, gather);
 651 }
 652
 653 static void ipmmu_flush_iotlb_all(struct iommu_domain *io_domain)
 654 {
 655         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 656
 657         if (domain->mmu)
 658                 ipmmu_tlb_flush_all(domain);
 659 }
 660
 661 static void ipmmu_iotlb_sync(struct iommu_domain *io_domain,
 662                              struct iommu_iotlb_gather *gather)
 663 {
 664         ipmmu_flush_iotlb_all(io_domain);
 665 }
 666
 667 static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain,
 668                                       dma_addr_t iova)
 669 {
 670         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 671
 672         /* TODO: Is locking needed ? */
 673
 674         return domain->iop->iova_to_phys(domain->iop, iova);
 675 }
 676
 677 static int ipmmu_init_platform_device(struct device *dev,
 678                                       struct of_phandle_args *args)
 679 {
 680         struct platform_device *ipmmu_pdev;
 681
 682         ipmmu_pdev = of_find_device_by_node(args->np);
 683         if (!ipmmu_pdev)
 684                 return -ENODEV;
 685
 686         dev_iommu_priv_set(dev, platform_get_drvdata(ipmmu_pdev));
 687
 688         return 0;
 689 }
 690
 691 static const struct soc_device_attribute soc_needs_opt_in[] = {
 692         { .family = "R-Car Gen3", },
 693         { .family = "R-Car Gen4", },
 694         { .family = "RZ/G2", },
 695         { /* sentinel */ }
 696 };
 697
 698 static const struct soc_device_attribute soc_denylist[] = {
 699         { .soc_id = "r8a774a1", },
 700         { .soc_id = "r8a7795", .revision = "ES1.*" },
 701         { .soc_id = "r8a7795", .revision = "ES2.*" },
 702         { .soc_id = "r8a7796", },
 703         { /* sentinel */ }
 704 };
 705
 706 static const char * const devices_allowlist[] = {
 707         "ee100000.mmc",
 708         "ee120000.mmc",
 709         "ee140000.mmc",
 710         "ee160000.mmc"
 711 };
 712
 713 static bool ipmmu_device_is_allowed(struct device *dev)
 714 {
 715         unsigned int i;
 716
 717         /*
 718          * R-Car Gen3/4 and RZ/G2 use the allow list to opt-in devices.
 719          * For Other SoCs, this returns true anyway.
 720          */
 721         if (!soc_device_match(soc_needs_opt_in))
 722                 return true;
 723
 724         /* Check whether this SoC can use the IPMMU correctly or not */
 725         if (soc_device_match(soc_denylist))
 726                 return false;
 727
 728         /* Check whether this device can work with the IPMMU */
 729         for (i = 0; i < ARRAY_SIZE(devices_allowlist); i++) {
 730                 if (!strcmp(dev_name(dev), devices_allowlist[i]))
 731                         return true;
 732         }
 733
 734         /* Otherwise, do not allow use of IPMMU */
 735         return false;
 736 }
 737
 738 static int ipmmu_of_xlate(struct device *dev,
 739                           struct of_phandle_args *spec)
 740 {
 741         if (!ipmmu_device_is_allowed(dev))
 742                 return -ENODEV;
 743
 744         iommu_fwspec_add_ids(dev, spec->args, 1);
 745
 746         /* Initialize once - xlate() will call multiple times */
 747         if (to_ipmmu(dev))
 748                 return 0;
 749
 750         return ipmmu_init_platform_device(dev, spec);
 751 }
 752
 753 static int ipmmu_init_arm_mapping(struct device *dev)
 754 {
 755         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 756         int ret;
 757
 758         /*
 759          * Create the ARM mapping, used by the ARM DMA mapping core to allocate
 760          * VAs. This will allocate a corresponding IOMMU domain.
 761          *
 762          * TODO:
 763          * - Create one mapping per context (TLB).
 764          * - Make the mapping size configurable ? We currently use a 2GB mapping
 765          *   at a 1GB offset to ensure that NULL VAs will fault.
 766          */
 767         if (!mmu->mapping) {
 768                 struct dma_iommu_mapping *mapping;
 769
 770                 mapping = arm_iommu_create_mapping(&platform_bus_type,
 771                                                    SZ_1G, SZ_2G);
 772                 if (IS_ERR(mapping)) {
 773                         dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n");
 774                         ret = PTR_ERR(mapping);
 775                         goto error;
 776                 }
 777
 778                 mmu->mapping = mapping;
 779         }
 780
 781         /* Attach the ARM VA mapping to the device. */
 782         ret = arm_iommu_attach_device(dev, mmu->mapping);
 783         if (ret < 0) {
 784                 dev_err(dev, "Failed to attach device to VA mapping\n");
 785                 goto error;
 786         }
 787
 788         return 0;
 789
 790 error:
 791         if (mmu->mapping)
 792                 arm_iommu_release_mapping(mmu->mapping);
 793
 794         return ret;
 795 }
 796
 797 static struct iommu_device *ipmmu_probe_device(struct device *dev)
 798 {
 799         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 800
 801         /*
 802          * Only let through devices that have been verified in xlate()
 803          */
 804         if (!mmu)
 805                 return ERR_PTR(-ENODEV);
 806
 807         return &mmu->iommu;
 808 }
 809
 810 static void ipmmu_probe_finalize(struct device *dev)
 811 {
 812         int ret = 0;
 813
 814         if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA))
 815                 ret = ipmmu_init_arm_mapping(dev);
 816
 817         if (ret)
 818                 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n");
 819 }
 820
 821 static void ipmmu_release_device(struct device *dev)
 822 {
 823         arm_iommu_detach_device(dev);
 824 }
 825
 826 static struct iommu_group *ipmmu_find_group(struct device *dev)
 827 {
 828         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 829         struct iommu_group *group;
 830
 831         if (mmu->group)
 832                 return iommu_group_ref_get(mmu->group);
 833
 834         group = iommu_group_alloc();
 835         if (!IS_ERR(group))
 836                 mmu->group = group;
 837
 838         return group;
 839 }
 840
 841 static const struct iommu_ops ipmmu_ops = {
 842         .domain_alloc = ipmmu_domain_alloc,
 843         .probe_device = ipmmu_probe_device,
 844         .release_device = ipmmu_release_device,
 845         .probe_finalize = ipmmu_probe_finalize,
 846         .device_group = IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA)
 847                         ? generic_device_group : ipmmu_find_group,
 848         .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
 849         .of_xlate = ipmmu_of_xlate,
 850         .default_domain_ops = &(const struct iommu_domain_ops) {
 851                 .attach_dev     = ipmmu_attach_device,
 852                 .map_pages      = ipmmu_map,
 853                 .unmap_pages    = ipmmu_unmap,
 854                 .flush_iotlb_all = ipmmu_flush_iotlb_all,
 855                 .iotlb_sync     = ipmmu_iotlb_sync,
 856                 .iova_to_phys   = ipmmu_iova_to_phys,
 857                 .free           = ipmmu_domain_free,
 858         }
 859 };
 860
 861 /* -----------------------------------------------------------------------------
 862  * Probe/remove and init
 863  */
 864
 865 static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
 866 {
 867         unsigned int i;
 868
 869         /* Disable all contexts. */
 870         for (i = 0; i < mmu->num_ctx; ++i)
 871                 ipmmu_ctx_write(mmu, i, IMCTR, 0);
 872 }
 873
 874 static const struct ipmmu_features ipmmu_features_default = {
 875         .use_ns_alias_offset = true,
 876         .has_cache_leaf_nodes = false,
 877         .number_of_contexts = 1, /* software only tested with one context */
 878         .num_utlbs = 32,
 879         .setup_imbuscr = true,
 880         .twobit_imttbcr_sl0 = false,
 881         .reserved_context = false,
 882         .cache_snoop = true,
 883         .ctx_offset_base = 0,
 884         .ctx_offset_stride = 0x40,
 885         .utlb_offset_base = 0,
 886 };
 887
 888 static const struct ipmmu_features ipmmu_features_rcar_gen3 = {
 889         .use_ns_alias_offset = false,
 890         .has_cache_leaf_nodes = true,
 891         .number_of_contexts = 8,
 892         .num_utlbs = 48,
 893         .setup_imbuscr = false,
 894         .twobit_imttbcr_sl0 = true,
 895         .reserved_context = true,
 896         .cache_snoop = false,
 897         .ctx_offset_base = 0,
 898         .ctx_offset_stride = 0x40,
 899         .utlb_offset_base = 0,
 900 };
 901
 902 static const struct ipmmu_features ipmmu_features_rcar_gen4 = {
 903         .use_ns_alias_offset = false,
 904         .has_cache_leaf_nodes = true,
 905         .number_of_contexts = 16,
 906         .num_utlbs = 64,
 907         .setup_imbuscr = false,
 908         .twobit_imttbcr_sl0 = true,
 909         .reserved_context = true,
 910         .cache_snoop = false,
 911         .ctx_offset_base = 0x10000,
 912         .ctx_offset_stride = 0x1040,
 913         .utlb_offset_base = 0x3000,
 914 };
 915
 916 static const struct of_device_id ipmmu_of_ids[] = {
 917         {
 918                 .compatible = "renesas,ipmmu-vmsa",
 919                 .data = &ipmmu_features_default,
 920         }, {
 921                 .compatible = "renesas,ipmmu-r8a774a1",
 922                 .data = &ipmmu_features_rcar_gen3,
 923         }, {
 924                 .compatible = "renesas,ipmmu-r8a774b1",
 925                 .data = &ipmmu_features_rcar_gen3,
 926         }, {
 927                 .compatible = "renesas,ipmmu-r8a774c0",
 928                 .data = &ipmmu_features_rcar_gen3,
 929         }, {
 930                 .compatible = "renesas,ipmmu-r8a774e1",
 931                 .data = &ipmmu_features_rcar_gen3,
 932         }, {
 933                 .compatible = "renesas,ipmmu-r8a7795",
 934                 .data = &ipmmu_features_rcar_gen3,
 935         }, {
 936                 .compatible = "renesas,ipmmu-r8a7796",
 937                 .data = &ipmmu_features_rcar_gen3,
 938         }, {
 939                 .compatible = "renesas,ipmmu-r8a77961",
 940                 .data = &ipmmu_features_rcar_gen3,
 941         }, {
 942                 .compatible = "renesas,ipmmu-r8a77965",
 943                 .data = &ipmmu_features_rcar_gen3,
 944         }, {
 945                 .compatible = "renesas,ipmmu-r8a77970",
 946                 .data = &ipmmu_features_rcar_gen3,
 947         }, {
 948                 .compatible = "renesas,ipmmu-r8a77980",
 949                 .data = &ipmmu_features_rcar_gen3,
 950         }, {
 951                 .compatible = "renesas,ipmmu-r8a77990",
 952                 .data = &ipmmu_features_rcar_gen3,
 953         }, {
 954                 .compatible = "renesas,ipmmu-r8a77995",
 955                 .data = &ipmmu_features_rcar_gen3,
 956         }, {
 957                 .compatible = "renesas,ipmmu-r8a779a0",
 958                 .data = &ipmmu_features_rcar_gen4,
 959         }, {
 960                 .compatible = "renesas,rcar-gen4-ipmmu-vmsa",
 961                 .data = &ipmmu_features_rcar_gen4,
 962         }, {
 963                 /* Terminator */
 964         },
 965 };
 966
 967 static int ipmmu_probe(struct platform_device *pdev)
 968 {
 969         struct ipmmu_vmsa_device *mmu;
 970         struct resource *res;
 971         int irq;
 972         int ret;
 973
 974         mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL);
 975         if (!mmu) {
 976                 dev_err(&pdev->dev, "cannot allocate device data\n");
 977                 return -ENOMEM;
 978         }
 979
 980         mmu->dev = &pdev->dev;
 981         spin_lock_init(&mmu->lock);
 982         bitmap_zero(mmu->ctx, IPMMU_CTX_MAX);
 983         mmu->features = of_device_get_match_data(&pdev->dev);
 984         memset(mmu->utlb_ctx, IPMMU_CTX_INVALID, mmu->features->num_utlbs);
 985         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
 986         if (ret)
 987                 return ret;
 988
 989         /* Map I/O memory and request IRQ. */
 990         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 991         mmu->base = devm_ioremap_resource(&pdev->dev, res);
 992         if (IS_ERR(mmu->base))
 993                 return PTR_ERR(mmu->base);
 994
 995         /*
 996          * The IPMMU has two register banks, for secure and non-secure modes.
 997          * The bank mapped at the beginning of the IPMMU address space
 998          * corresponds to the running mode of the CPU. When running in secure
 999          * mode the non-secure register bank is also available at an offset.
1000          *
1001          * Secure mode operation isn't clearly documented and is thus currently
1002          * not implemented in the driver. Furthermore, preliminary tests of
1003          * non-secure operation with the main register bank were not successful.
1004          * Offset the registers base unconditionally to point to the non-secure
1005          * alias space for now.
1006          */
1007         if (mmu->features->use_ns_alias_offset)
1008                 mmu->base += IM_NS_ALIAS_OFFSET;
1009
1010         mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts);
1011
1012         /*
1013          * Determine if this IPMMU instance is a root device by checking for
1014          * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property.
1015          */
1016         if (!mmu->features->has_cache_leaf_nodes ||
1017             !of_find_property(pdev->dev.of_node, "renesas,ipmmu-main", NULL))
1018                 mmu->root = mmu;
1019         else
1020                 mmu->root = ipmmu_find_root();
1021
1022         /*
1023          * Wait until the root device has been registered for sure.
1024          */
1025         if (!mmu->root)
1026                 return -EPROBE_DEFER;
1027
1028         /* Root devices have mandatory IRQs */
1029         if (ipmmu_is_root(mmu)) {
1030                 irq = platform_get_irq(pdev, 0);
1031                 if (irq < 0)
1032                         return irq;
1033
1034                 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0,
1035                                        dev_name(&pdev->dev), mmu);
1036                 if (ret < 0) {
1037                         dev_err(&pdev->dev, "failed to request IRQ %d\n", irq);
1038                         return ret;
1039                 }
1040
1041                 ipmmu_device_reset(mmu);
1042
1043                 if (mmu->features->reserved_context) {
1044                         dev_info(&pdev->dev, "IPMMU context 0 is reserved\n");
1045                         set_bit(0, mmu->ctx);
1046                 }
1047         }
1048
1049         /*
1050          * Register the IPMMU to the IOMMU subsystem in the following cases:
1051          * - R-Car Gen2 IPMMU (all devices registered)
1052          * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device)
1053          */
1054         if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) {
1055                 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL,
1056                                              dev_name(&pdev->dev));
1057                 if (ret)
1058                         return ret;
1059
1060                 ret = iommu_device_register(&mmu->iommu, &ipmmu_ops, &pdev->dev);
1061                 if (ret)
1062                         return ret;
1063         }
1064
1065         /*
1066          * We can't create the ARM mapping here as it requires the bus to have
1067          * an IOMMU, which only happens when bus_set_iommu() is called in
1068          * ipmmu_init() after the probe function returns.
1069          */
1070
1071         platform_set_drvdata(pdev, mmu);
1072
1073         return 0;
1074 }
1075
1076 static int ipmmu_remove(struct platform_device *pdev)
1077 {
1078         struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev);
1079
1080         iommu_device_sysfs_remove(&mmu->iommu);
1081         iommu_device_unregister(&mmu->iommu);
1082
1083         arm_iommu_release_mapping(mmu->mapping);
1084
1085         ipmmu_device_reset(mmu);
1086
1087         return 0;
1088 }
1089
1090 #ifdef CONFIG_PM_SLEEP
1091 static int ipmmu_resume_noirq(struct device *dev)
1092 {
1093         struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev);
1094         unsigned int i;
1095
1096         /* Reset root MMU and restore contexts */
1097         if (ipmmu_is_root(mmu)) {
1098                 ipmmu_device_reset(mmu);
1099
1100                 for (i = 0; i < mmu->num_ctx; i++) {
1101                         if (!mmu->domains[i])
1102                                 continue;
1103
1104                         ipmmu_domain_setup_context(mmu->domains[i]);
1105                 }
1106         }
1107
1108         /* Re-enable active micro-TLBs */
1109         for (i = 0; i < mmu->features->num_utlbs; i++) {
1110                 if (mmu->utlb_ctx[i] == IPMMU_CTX_INVALID)
1111                         continue;
1112
1113                 ipmmu_utlb_enable(mmu->root->domains[mmu->utlb_ctx[i]], i);
1114         }
1115
1116         return 0;
1117 }
1118
1119 static const struct dev_pm_ops ipmmu_pm  = {
1120         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, ipmmu_resume_noirq)
1121 };
1122 #define DEV_PM_OPS      &ipmmu_pm
1123 #else
1124 #define DEV_PM_OPS      NULL
1125 #endif /* CONFIG_PM_SLEEP */
1126
1127 static struct platform_driver ipmmu_driver = {
1128         .driver = {
1129                 .name = "ipmmu-vmsa",
1130                 .of_match_table = of_match_ptr(ipmmu_of_ids),
1131                 .pm = DEV_PM_OPS,
1132         },
1133         .probe = ipmmu_probe,
1134         .remove = ipmmu_remove,
1135 };
1136 builtin_platform_driver(ipmmu_driver);