8 select MULTI_IRQ_HANDLER
16 select MULTI_IRQ_HANDLER
17 select IRQ_DOMAIN_HIERARCHY
22 select GENERIC_IRQ_CHIP
27 select MULTI_IRQ_HANDLER
31 default 4 if ARCH_S5PV210
35 The maximum number of VICs available in the system, for
40 select GENERIC_IRQ_CHIP
42 select MULTI_IRQ_HANDLER
47 select GENERIC_IRQ_CHIP
49 select MULTI_IRQ_HANDLER
55 select GENERIC_IRQ_CHIP
64 select GENERIC_IRQ_CHIP
67 config CLPS711X_IRQCHIP
69 depends on ARCH_CLPS711X
71 select MULTI_IRQ_HANDLER
81 select GENERIC_IRQ_CHIP
87 select MULTI_IRQ_HANDLER
89 config RENESAS_INTC_IRQPIN
100 select GENERIC_IRQ_CHIP
102 config VERSATILE_FPGA_IRQ
106 config VERSATILE_FPGA_IRQ_NR
109 depends on VERSATILE_FPGA_IRQ
118 Support for a CROSSBAR ip that precedes the main interrupt controller.
119 The primary irqchip invokes the crossbar's callback which inturn allocates
120 a free irq and configures the IP. Thus the peripheral interrupts are
121 routed to one of the free irqchip interrupt lines.
124 tristate "Keystone 2 IRQ controller IP"
125 depends on ARCH_KEYSTONE
127 Support for Texas Instruments Keystone 2 IRQ controller IP which
128 is part of the Keystone 2 IPC mechanism