drivers/irqchip/irq-gic-v3-its.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/acpi_iort.h>
   9 #include <linux/bitfield.h>
  10 #include <linux/bitmap.h>
  11 #include <linux/cpu.h>
  12 #include <linux/crash_dump.h>
  13 #include <linux/delay.h>
  14 #include <linux/dma-iommu.h>
  15 #include <linux/efi.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/list.h>
  19 #include <linux/log2.h>
  20 #include <linux/memblock.h>
  21 #include <linux/mm.h>
  22 #include <linux/msi.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/of_pci.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/percpu.h>
  29 #include <linux/slab.h>
  30 #include <linux/syscore_ops.h>
  31
  32 #include <linux/irqchip.h>
  33 #include <linux/irqchip/arm-gic-v3.h>
  34 #include <linux/irqchip/arm-gic-v4.h>
  35
  36 #include <asm/cputype.h>
  37 #include <asm/exception.h>
  38
  39 #include "irq-gic-common.h"
  40
  41 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING           (1ULL << 0)
  42 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375       (1ULL << 1)
  43 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144       (1ULL << 2)
  44 #define ITS_FLAGS_SAVE_SUSPEND_STATE            (1ULL << 3)
  45
  46 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING     (1 << 0)
  47 #define RDIST_FLAGS_RD_TABLES_PREALLOCATED      (1 << 1)
  48
  49 static u32 lpi_id_bits;
  50
  51 /*
  52  * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
  53  * deal with (one configuration byte per interrupt). PENDBASE has to
  54  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
  55  */
  56 #define LPI_NRBITS              lpi_id_bits
  57 #define LPI_PROPBASE_SZ         ALIGN(BIT(LPI_NRBITS), SZ_64K)
  58 #define LPI_PENDBASE_SZ         ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
  59
  60 #define LPI_PROP_DEFAULT_PRIO   GICD_INT_DEF_PRI
  61
  62 /*
  63  * Collection structure - just an ID, and a redistributor address to
  64  * ping. We use one per CPU as a bag of interrupts assigned to this
  65  * CPU.
  66  */
  67 struct its_collection {
  68         u64                     target_address;
  69         u16                     col_id;
  70 };
  71
  72 /*
  73  * The ITS_BASER structure - contains memory information, cached
  74  * value of BASER register configuration and ITS page size.
  75  */
  76 struct its_baser {
  77         void            *base;
  78         u64             val;
  79         u32             order;
  80         u32             psz;
  81 };
  82
  83 struct its_device;
  84
  85 /*
  86  * The ITS structure - contains most of the infrastructure, with the
  87  * top-level MSI domain, the command queue, the collections, and the
  88  * list of devices writing to it.
  89  *
  90  * dev_alloc_lock has to be taken for device allocations, while the
  91  * spinlock must be taken to parse data structures such as the device
  92  * list.
  93  */
  94 struct its_node {
  95         raw_spinlock_t          lock;
  96         struct mutex            dev_alloc_lock;
  97         struct list_head        entry;
  98         void __iomem            *base;
  99         phys_addr_t             phys_base;
 100         struct its_cmd_block    *cmd_base;
 101         struct its_cmd_block    *cmd_write;
 102         struct its_baser        tables[GITS_BASER_NR_REGS];
 103         struct its_collection   *collections;
 104         struct fwnode_handle    *fwnode_handle;
 105         u64                     (*get_msi_base)(struct its_device *its_dev);
 106         u64                     typer;
 107         u64                     cbaser_save;
 108         u32                     ctlr_save;
 109         u32                     mpidr;
 110         struct list_head        its_device_list;
 111         u64                     flags;
 112         unsigned long           list_nr;
 113         int                     numa_node;
 114         unsigned int            msi_domain_flags;
 115         u32                     pre_its_base; /* for Socionext Synquacer */
 116         int                     vlpi_redist_offset;
 117 };
 118
 119 #define is_v4(its)              (!!((its)->typer & GITS_TYPER_VLPIS))
 120 #define is_v4_1(its)            (!!((its)->typer & GITS_TYPER_VMAPP))
 121 #define device_ids(its)         (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
 122
 123 #define ITS_ITT_ALIGN           SZ_256
 124
 125 /* The maximum number of VPEID bits supported by VLPI commands */
 126 #define ITS_MAX_VPEID_BITS                                              \
 127         ({                                                              \
 128                 int nvpeid = 16;                                        \
 129                 if (gic_rdists->has_rvpeid &&                           \
 130                     gic_rdists->gicd_typer2 & GICD_TYPER2_VIL)          \
 131                         nvpeid = 1 + (gic_rdists->gicd_typer2 &         \
 132                                       GICD_TYPER2_VID);                 \
 133                                                                         \
 134                 nvpeid;                                                 \
 135         })
 136 #define ITS_MAX_VPEID           (1 << (ITS_MAX_VPEID_BITS))
 137
 138 /* Convert page order to size in bytes */
 139 #define PAGE_ORDER_TO_SIZE(o)   (PAGE_SIZE << (o))
 140
 141 struct event_lpi_map {
 142         unsigned long           *lpi_map;
 143         u16                     *col_map;
 144         irq_hw_number_t         lpi_base;
 145         int                     nr_lpis;
 146         raw_spinlock_t          vlpi_lock;
 147         struct its_vm           *vm;
 148         struct its_vlpi_map     *vlpi_maps;
 149         int                     nr_vlpis;
 150 };
 151
 152 /*
 153  * The ITS view of a device - belongs to an ITS, owns an interrupt
 154  * translation table, and a list of interrupts.  If it some of its
 155  * LPIs are injected into a guest (GICv4), the event_map.vm field
 156  * indicates which one.
 157  */
 158 struct its_device {
 159         struct list_head        entry;
 160         struct its_node         *its;
 161         struct event_lpi_map    event_map;
 162         void                    *itt;
 163         u32                     nr_ites;
 164         u32                     device_id;
 165         bool                    shared;
 166 };
 167
 168 static struct {
 169         raw_spinlock_t          lock;
 170         struct its_device       *dev;
 171         struct its_vpe          **vpes;
 172         int                     next_victim;
 173 } vpe_proxy;
 174
 175 static LIST_HEAD(its_nodes);
 176 static DEFINE_RAW_SPINLOCK(its_lock);
 177 static struct rdists *gic_rdists;
 178 static struct irq_domain *its_parent;
 179
 180 static unsigned long its_list_map;
 181 static u16 vmovp_seq_num;
 182 static DEFINE_RAW_SPINLOCK(vmovp_lock);
 183
 184 static DEFINE_IDA(its_vpeid_ida);
 185
 186 #define gic_data_rdist()                (raw_cpu_ptr(gic_rdists->rdist))
 187 #define gic_data_rdist_cpu(cpu)         (per_cpu_ptr(gic_rdists->rdist, cpu))
 188 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
 189 #define gic_data_rdist_vlpi_base()      (gic_data_rdist_rd_base() + SZ_128K)
 190
 191 static u16 get_its_list(struct its_vm *vm)
 192 {
 193         struct its_node *its;
 194         unsigned long its_list = 0;
 195
 196         list_for_each_entry(its, &its_nodes, entry) {
 197                 if (!is_v4(its))
 198                         continue;
 199
 200                 if (vm->vlpi_count[its->list_nr])
 201                         __set_bit(its->list_nr, &its_list);
 202         }
 203
 204         return (u16)its_list;
 205 }
 206
 207 static inline u32 its_get_event_id(struct irq_data *d)
 208 {
 209         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 210         return d->hwirq - its_dev->event_map.lpi_base;
 211 }
 212
 213 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
 214                                                u32 event)
 215 {
 216         struct its_node *its = its_dev->its;
 217
 218         return its->collections + its_dev->event_map.col_map[event];
 219 }
 220
 221 static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev,
 222                                                u32 event)
 223 {
 224         if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis))
 225                 return NULL;
 226
 227         return &its_dev->event_map.vlpi_maps[event];
 228 }
 229
 230 static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
 231 {
 232         if (irqd_is_forwarded_to_vcpu(d)) {
 233                 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 234                 u32 event = its_get_event_id(d);
 235
 236                 return dev_event_to_vlpi_map(its_dev, event);
 237         }
 238
 239         return NULL;
 240 }
 241
 242 static int irq_to_cpuid(struct irq_data *d)
 243 {
 244         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 245         struct its_vlpi_map *map = get_vlpi_map(d);
 246
 247         if (map)
 248                 return map->vpe->col_idx;
 249
 250         return its_dev->event_map.col_map[its_get_event_id(d)];
 251 }
 252
 253 static struct its_collection *valid_col(struct its_collection *col)
 254 {
 255         if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
 256                 return NULL;
 257
 258         return col;
 259 }
 260
 261 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
 262 {
 263         if (valid_col(its->collections + vpe->col_idx))
 264                 return vpe;
 265
 266         return NULL;
 267 }
 268
 269 /*
 270  * ITS command descriptors - parameters to be encoded in a command
 271  * block.
 272  */
 273 struct its_cmd_desc {
 274         union {
 275                 struct {
 276                         struct its_device *dev;
 277                         u32 event_id;
 278                 } its_inv_cmd;
 279
 280                 struct {
 281                         struct its_device *dev;
 282                         u32 event_id;
 283                 } its_clear_cmd;
 284
 285                 struct {
 286                         struct its_device *dev;
 287                         u32 event_id;
 288                 } its_int_cmd;
 289
 290                 struct {
 291                         struct its_device *dev;
 292                         int valid;
 293                 } its_mapd_cmd;
 294
 295                 struct {
 296                         struct its_collection *col;
 297                         int valid;
 298                 } its_mapc_cmd;
 299
 300                 struct {
 301                         struct its_device *dev;
 302                         u32 phys_id;
 303                         u32 event_id;
 304                 } its_mapti_cmd;
 305
 306                 struct {
 307                         struct its_device *dev;
 308                         struct its_collection *col;
 309                         u32 event_id;
 310                 } its_movi_cmd;
 311
 312                 struct {
 313                         struct its_device *dev;
 314                         u32 event_id;
 315                 } its_discard_cmd;
 316
 317                 struct {
 318                         struct its_collection *col;
 319                 } its_invall_cmd;
 320
 321                 struct {
 322                         struct its_vpe *vpe;
 323                 } its_vinvall_cmd;
 324
 325                 struct {
 326                         struct its_vpe *vpe;
 327                         struct its_collection *col;
 328                         bool valid;
 329                 } its_vmapp_cmd;
 330
 331                 struct {
 332                         struct its_vpe *vpe;
 333                         struct its_device *dev;
 334                         u32 virt_id;
 335                         u32 event_id;
 336                         bool db_enabled;
 337                 } its_vmapti_cmd;
 338
 339                 struct {
 340                         struct its_vpe *vpe;
 341                         struct its_device *dev;
 342                         u32 event_id;
 343                         bool db_enabled;
 344                 } its_vmovi_cmd;
 345
 346                 struct {
 347                         struct its_vpe *vpe;
 348                         struct its_collection *col;
 349                         u16 seq_num;
 350                         u16 its_list;
 351                 } its_vmovp_cmd;
 352
 353                 struct {
 354                         struct its_vpe *vpe;
 355                 } its_invdb_cmd;
 356         };
 357 };
 358
 359 /*
 360  * The ITS command block, which is what the ITS actually parses.
 361  */
 362 struct its_cmd_block {
 363         union {
 364                 u64     raw_cmd[4];
 365                 __le64  raw_cmd_le[4];
 366         };
 367 };
 368
 369 #define ITS_CMD_QUEUE_SZ                SZ_64K
 370 #define ITS_CMD_QUEUE_NR_ENTRIES        (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
 371
 372 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
 373                                                     struct its_cmd_block *,
 374                                                     struct its_cmd_desc *);
 375
 376 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
 377                                               struct its_cmd_block *,
 378                                               struct its_cmd_desc *);
 379
 380 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
 381 {
 382         u64 mask = GENMASK_ULL(h, l);
 383         *raw_cmd &= ~mask;
 384         *raw_cmd |= (val << l) & mask;
 385 }
 386
 387 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
 388 {
 389         its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
 390 }
 391
 392 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
 393 {
 394         its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
 395 }
 396
 397 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
 398 {
 399         its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
 400 }
 401
 402 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
 403 {
 404         its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
 405 }
 406
 407 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
 408 {
 409         its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
 410 }
 411
 412 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
 413 {
 414         its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
 415 }
 416
 417 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
 418 {
 419         its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
 420 }
 421
 422 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
 423 {
 424         its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
 425 }
 426
 427 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
 428 {
 429         its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
 430 }
 431
 432 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
 433 {
 434         its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
 435 }
 436
 437 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
 438 {
 439         its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
 440 }
 441
 442 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
 443 {
 444         its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
 445 }
 446
 447 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
 448 {
 449         its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
 450 }
 451
 452 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
 453 {
 454         its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
 455 }
 456
 457 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
 458 {
 459         its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
 460 }
 461
 462 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
 463 {
 464         its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
 465 }
 466
 467 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
 468 {
 469         its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
 470 }
 471
 472 static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa)
 473 {
 474         its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16);
 475 }
 476
 477 static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc)
 478 {
 479         its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8);
 480 }
 481
 482 static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz)
 483 {
 484         its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9);
 485 }
 486
 487 static void its_encode_vmapp_default_db(struct its_cmd_block *cmd,
 488                                         u32 vpe_db_lpi)
 489 {
 490         its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0);
 491 }
 492
 493 static void its_encode_vmovp_default_db(struct its_cmd_block *cmd,
 494                                         u32 vpe_db_lpi)
 495 {
 496         its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0);
 497 }
 498
 499 static void its_encode_db(struct its_cmd_block *cmd, bool db)
 500 {
 501         its_mask_encode(&cmd->raw_cmd[2], db, 63, 63);
 502 }
 503
 504 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
 505 {
 506         /* Let's fixup BE commands */
 507         cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]);
 508         cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]);
 509         cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]);
 510         cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]);
 511 }
 512
 513 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
 514                                                  struct its_cmd_block *cmd,
 515                                                  struct its_cmd_desc *desc)
 516 {
 517         unsigned long itt_addr;
 518         u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
 519
 520         itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
 521         itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
 522
 523         its_encode_cmd(cmd, GITS_CMD_MAPD);
 524         its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
 525         its_encode_size(cmd, size - 1);
 526         its_encode_itt(cmd, itt_addr);
 527         its_encode_valid(cmd, desc->its_mapd_cmd.valid);
 528
 529         its_fixup_cmd(cmd);
 530
 531         return NULL;
 532 }
 533
 534 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
 535                                                  struct its_cmd_block *cmd,
 536                                                  struct its_cmd_desc *desc)
 537 {
 538         its_encode_cmd(cmd, GITS_CMD_MAPC);
 539         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 540         its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
 541         its_encode_valid(cmd, desc->its_mapc_cmd.valid);
 542
 543         its_fixup_cmd(cmd);
 544
 545         return desc->its_mapc_cmd.col;
 546 }
 547
 548 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
 549                                                   struct its_cmd_block *cmd,
 550                                                   struct its_cmd_desc *desc)
 551 {
 552         struct its_collection *col;
 553
 554         col = dev_event_to_col(desc->its_mapti_cmd.dev,
 555                                desc->its_mapti_cmd.event_id);
 556
 557         its_encode_cmd(cmd, GITS_CMD_MAPTI);
 558         its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
 559         its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
 560         its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
 561         its_encode_collection(cmd, col->col_id);
 562
 563         its_fixup_cmd(cmd);
 564
 565         return valid_col(col);
 566 }
 567
 568 static struct its_collection *its_build_movi_cmd(struct its_node *its,
 569                                                  struct its_cmd_block *cmd,
 570                                                  struct its_cmd_desc *desc)
 571 {
 572         struct its_collection *col;
 573
 574         col = dev_event_to_col(desc->its_movi_cmd.dev,
 575                                desc->its_movi_cmd.event_id);
 576
 577         its_encode_cmd(cmd, GITS_CMD_MOVI);
 578         its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
 579         its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
 580         its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
 581
 582         its_fixup_cmd(cmd);
 583
 584         return valid_col(col);
 585 }
 586
 587 static struct its_collection *its_build_discard_cmd(struct its_node *its,
 588                                                     struct its_cmd_block *cmd,
 589                                                     struct its_cmd_desc *desc)
 590 {
 591         struct its_collection *col;
 592
 593         col = dev_event_to_col(desc->its_discard_cmd.dev,
 594                                desc->its_discard_cmd.event_id);
 595
 596         its_encode_cmd(cmd, GITS_CMD_DISCARD);
 597         its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
 598         its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
 599
 600         its_fixup_cmd(cmd);
 601
 602         return valid_col(col);
 603 }
 604
 605 static struct its_collection *its_build_inv_cmd(struct its_node *its,
 606                                                 struct its_cmd_block *cmd,
 607                                                 struct its_cmd_desc *desc)
 608 {
 609         struct its_collection *col;
 610
 611         col = dev_event_to_col(desc->its_inv_cmd.dev,
 612                                desc->its_inv_cmd.event_id);
 613
 614         its_encode_cmd(cmd, GITS_CMD_INV);
 615         its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
 616         its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
 617
 618         its_fixup_cmd(cmd);
 619
 620         return valid_col(col);
 621 }
 622
 623 static struct its_collection *its_build_int_cmd(struct its_node *its,
 624                                                 struct its_cmd_block *cmd,
 625                                                 struct its_cmd_desc *desc)
 626 {
 627         struct its_collection *col;
 628
 629         col = dev_event_to_col(desc->its_int_cmd.dev,
 630                                desc->its_int_cmd.event_id);
 631
 632         its_encode_cmd(cmd, GITS_CMD_INT);
 633         its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
 634         its_encode_event_id(cmd, desc->its_int_cmd.event_id);
 635
 636         its_fixup_cmd(cmd);
 637
 638         return valid_col(col);
 639 }
 640
 641 static struct its_collection *its_build_clear_cmd(struct its_node *its,
 642                                                   struct its_cmd_block *cmd,
 643                                                   struct its_cmd_desc *desc)
 644 {
 645         struct its_collection *col;
 646
 647         col = dev_event_to_col(desc->its_clear_cmd.dev,
 648                                desc->its_clear_cmd.event_id);
 649
 650         its_encode_cmd(cmd, GITS_CMD_CLEAR);
 651         its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
 652         its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
 653
 654         its_fixup_cmd(cmd);
 655
 656         return valid_col(col);
 657 }
 658
 659 static struct its_collection *its_build_invall_cmd(struct its_node *its,
 660                                                    struct its_cmd_block *cmd,
 661                                                    struct its_cmd_desc *desc)
 662 {
 663         its_encode_cmd(cmd, GITS_CMD_INVALL);
 664         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 665
 666         its_fixup_cmd(cmd);
 667
 668         return NULL;
 669 }
 670
 671 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
 672                                              struct its_cmd_block *cmd,
 673                                              struct its_cmd_desc *desc)
 674 {
 675         its_encode_cmd(cmd, GITS_CMD_VINVALL);
 676         its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
 677
 678         its_fixup_cmd(cmd);
 679
 680         return valid_vpe(its, desc->its_vinvall_cmd.vpe);
 681 }
 682
 683 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
 684                                            struct its_cmd_block *cmd,
 685                                            struct its_cmd_desc *desc)
 686 {
 687         unsigned long vpt_addr, vconf_addr;
 688         u64 target;
 689         bool alloc;
 690
 691         its_encode_cmd(cmd, GITS_CMD_VMAPP);
 692         its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
 693         its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
 694
 695         if (!desc->its_vmapp_cmd.valid) {
 696                 if (is_v4_1(its)) {
 697                         alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count);
 698                         its_encode_alloc(cmd, alloc);
 699                 }
 700
 701                 goto out;
 702         }
 703
 704         vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
 705         target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
 706
 707         its_encode_target(cmd, target);
 708         its_encode_vpt_addr(cmd, vpt_addr);
 709         its_encode_vpt_size(cmd, LPI_NRBITS - 1);
 710
 711         if (!is_v4_1(its))
 712                 goto out;
 713
 714         vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page));
 715
 716         alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);
 717
 718         its_encode_alloc(cmd, alloc);
 719
 720         /* We can only signal PTZ when alloc==1. Why do we have two bits? */
 721         its_encode_ptz(cmd, alloc);
 722         its_encode_vconf_addr(cmd, vconf_addr);
 723         its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi);
 724
 725 out:
 726         its_fixup_cmd(cmd);
 727
 728         return valid_vpe(its, desc->its_vmapp_cmd.vpe);
 729 }
 730
 731 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
 732                                             struct its_cmd_block *cmd,
 733                                             struct its_cmd_desc *desc)
 734 {
 735         u32 db;
 736
 737         if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled)
 738                 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
 739         else
 740                 db = 1023;
 741
 742         its_encode_cmd(cmd, GITS_CMD_VMAPTI);
 743         its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
 744         its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
 745         its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
 746         its_encode_db_phys_id(cmd, db);
 747         its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
 748
 749         its_fixup_cmd(cmd);
 750
 751         return valid_vpe(its, desc->its_vmapti_cmd.vpe);
 752 }
 753
 754 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
 755                                            struct its_cmd_block *cmd,
 756                                            struct its_cmd_desc *desc)
 757 {
 758         u32 db;
 759
 760         if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled)
 761                 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
 762         else
 763                 db = 1023;
 764
 765         its_encode_cmd(cmd, GITS_CMD_VMOVI);
 766         its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
 767         its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
 768         its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
 769         its_encode_db_phys_id(cmd, db);
 770         its_encode_db_valid(cmd, true);
 771
 772         its_fixup_cmd(cmd);
 773
 774         return valid_vpe(its, desc->its_vmovi_cmd.vpe);
 775 }
 776
 777 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
 778                                            struct its_cmd_block *cmd,
 779                                            struct its_cmd_desc *desc)
 780 {
 781         u64 target;
 782
 783         target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
 784         its_encode_cmd(cmd, GITS_CMD_VMOVP);
 785         its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
 786         its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
 787         its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
 788         its_encode_target(cmd, target);
 789
 790         if (is_v4_1(its)) {
 791                 its_encode_db(cmd, true);
 792                 its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi);
 793         }
 794
 795         its_fixup_cmd(cmd);
 796
 797         return valid_vpe(its, desc->its_vmovp_cmd.vpe);
 798 }
 799
 800 static struct its_vpe *its_build_vinv_cmd(struct its_node *its,
 801                                           struct its_cmd_block *cmd,
 802                                           struct its_cmd_desc *desc)
 803 {
 804         struct its_vlpi_map *map;
 805
 806         map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev,
 807                                     desc->its_inv_cmd.event_id);
 808
 809         its_encode_cmd(cmd, GITS_CMD_INV);
 810         its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
 811         its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
 812
 813         its_fixup_cmd(cmd);
 814
 815         return valid_vpe(its, map->vpe);
 816 }
 817
 818 static struct its_vpe *its_build_vint_cmd(struct its_node *its,
 819                                           struct its_cmd_block *cmd,
 820                                           struct its_cmd_desc *desc)
 821 {
 822         struct its_vlpi_map *map;
 823
 824         map = dev_event_to_vlpi_map(desc->its_int_cmd.dev,
 825                                     desc->its_int_cmd.event_id);
 826
 827         its_encode_cmd(cmd, GITS_CMD_INT);
 828         its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
 829         its_encode_event_id(cmd, desc->its_int_cmd.event_id);
 830
 831         its_fixup_cmd(cmd);
 832
 833         return valid_vpe(its, map->vpe);
 834 }
 835
 836 static struct its_vpe *its_build_vclear_cmd(struct its_node *its,
 837                                             struct its_cmd_block *cmd,
 838                                             struct its_cmd_desc *desc)
 839 {
 840         struct its_vlpi_map *map;
 841
 842         map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev,
 843                                     desc->its_clear_cmd.event_id);
 844
 845         its_encode_cmd(cmd, GITS_CMD_CLEAR);
 846         its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
 847         its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
 848
 849         its_fixup_cmd(cmd);
 850
 851         return valid_vpe(its, map->vpe);
 852 }
 853
 854 static struct its_vpe *its_build_invdb_cmd(struct its_node *its,
 855                                            struct its_cmd_block *cmd,
 856                                            struct its_cmd_desc *desc)
 857 {
 858         if (WARN_ON(!is_v4_1(its)))
 859                 return NULL;
 860
 861         its_encode_cmd(cmd, GITS_CMD_INVDB);
 862         its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id);
 863
 864         its_fixup_cmd(cmd);
 865
 866         return valid_vpe(its, desc->its_invdb_cmd.vpe);
 867 }
 868
 869 static u64 its_cmd_ptr_to_offset(struct its_node *its,
 870                                  struct its_cmd_block *ptr)
 871 {
 872         return (ptr - its->cmd_base) * sizeof(*ptr);
 873 }
 874
 875 static int its_queue_full(struct its_node *its)
 876 {
 877         int widx;
 878         int ridx;
 879
 880         widx = its->cmd_write - its->cmd_base;
 881         ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
 882
 883         /* This is incredibly unlikely to happen, unless the ITS locks up. */
 884         if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
 885                 return 1;
 886
 887         return 0;
 888 }
 889
 890 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
 891 {
 892         struct its_cmd_block *cmd;
 893         u32 count = 1000000;    /* 1s! */
 894
 895         while (its_queue_full(its)) {
 896                 count--;
 897                 if (!count) {
 898                         pr_err_ratelimited("ITS queue not draining\n");
 899                         return NULL;
 900                 }
 901                 cpu_relax();
 902                 udelay(1);
 903         }
 904
 905         cmd = its->cmd_write++;
 906
 907         /* Handle queue wrapping */
 908         if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
 909                 its->cmd_write = its->cmd_base;
 910
 911         /* Clear command  */
 912         cmd->raw_cmd[0] = 0;
 913         cmd->raw_cmd[1] = 0;
 914         cmd->raw_cmd[2] = 0;
 915         cmd->raw_cmd[3] = 0;
 916
 917         return cmd;
 918 }
 919
 920 static struct its_cmd_block *its_post_commands(struct its_node *its)
 921 {
 922         u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
 923
 924         writel_relaxed(wr, its->base + GITS_CWRITER);
 925
 926         return its->cmd_write;
 927 }
 928
 929 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
 930 {
 931         /*
 932          * Make sure the commands written to memory are observable by
 933          * the ITS.
 934          */
 935         if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
 936                 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
 937         else
 938                 dsb(ishst);
 939 }
 940
 941 static int its_wait_for_range_completion(struct its_node *its,
 942                                          u64    prev_idx,
 943                                          struct its_cmd_block *to)
 944 {
 945         u64 rd_idx, to_idx, linear_idx;
 946         u32 count = 1000000;    /* 1s! */
 947
 948         /* Linearize to_idx if the command set has wrapped around */
 949         to_idx = its_cmd_ptr_to_offset(its, to);
 950         if (to_idx < prev_idx)
 951                 to_idx += ITS_CMD_QUEUE_SZ;
 952
 953         linear_idx = prev_idx;
 954
 955         while (1) {
 956                 s64 delta;
 957
 958                 rd_idx = readl_relaxed(its->base + GITS_CREADR);
 959
 960                 /*
 961                  * Compute the read pointer progress, taking the
 962                  * potential wrap-around into account.
 963                  */
 964                 delta = rd_idx - prev_idx;
 965                 if (rd_idx < prev_idx)
 966                         delta += ITS_CMD_QUEUE_SZ;
 967
 968                 linear_idx += delta;
 969                 if (linear_idx >= to_idx)
 970                         break;
 971
 972                 count--;
 973                 if (!count) {
 974                         pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
 975                                            to_idx, linear_idx);
 976                         return -1;
 977                 }
 978                 prev_idx = rd_idx;
 979                 cpu_relax();
 980                 udelay(1);
 981         }
 982
 983         return 0;
 984 }
 985
 986 /* Warning, macro hell follows */
 987 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn)       \
 988 void name(struct its_node *its,                                         \
 989           buildtype builder,                                            \
 990           struct its_cmd_desc *desc)                                    \
 991 {                                                                       \
 992         struct its_cmd_block *cmd, *sync_cmd, *next_cmd;                \
 993         synctype *sync_obj;                                             \
 994         unsigned long flags;                                            \
 995         u64 rd_idx;                                                     \
 996                                                                         \
 997         raw_spin_lock_irqsave(&its->lock, flags);                       \
 998                                                                         \
 999         cmd = its_allocate_entry(its);                                  \
1000         if (!cmd) {             /* We're soooooo screewed... */         \
1001                 raw_spin_unlock_irqrestore(&its->lock, flags);          \
1002                 return;                                                 \
1003         }                                                               \
1004         sync_obj = builder(its, cmd, desc);                             \
1005         its_flush_cmd(its, cmd);                                        \
1006                                                                         \
1007         if (sync_obj) {                                                 \
1008                 sync_cmd = its_allocate_entry(its);                     \
1009                 if (!sync_cmd)                                          \
1010                         goto post;                                      \
1011                                                                         \
1012                 buildfn(its, sync_cmd, sync_obj);                       \
1013                 its_flush_cmd(its, sync_cmd);                           \
1014         }                                                               \
1015                                                                         \
1016 post:                                                                   \
1017         rd_idx = readl_relaxed(its->base + GITS_CREADR);                \
1018         next_cmd = its_post_commands(its);                              \
1019         raw_spin_unlock_irqrestore(&its->lock, flags);                  \
1020                                                                         \
1021         if (its_wait_for_range_completion(its, rd_idx, next_cmd))       \
1022                 pr_err_ratelimited("ITS cmd %ps failed\n", builder);    \
1023 }
1024
1025 static void its_build_sync_cmd(struct its_node *its,
1026                                struct its_cmd_block *sync_cmd,
1027                                struct its_collection *sync_col)
1028 {
1029         its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
1030         its_encode_target(sync_cmd, sync_col->target_address);
1031
1032         its_fixup_cmd(sync_cmd);
1033 }
1034
1035 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
1036                              struct its_collection, its_build_sync_cmd)
1037
1038 static void its_build_vsync_cmd(struct its_node *its,
1039                                 struct its_cmd_block *sync_cmd,
1040                                 struct its_vpe *sync_vpe)
1041 {
1042         its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
1043         its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
1044
1045         its_fixup_cmd(sync_cmd);
1046 }
1047
1048 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
1049                              struct its_vpe, its_build_vsync_cmd)
1050
1051 static void its_send_int(struct its_device *dev, u32 event_id)
1052 {
1053         struct its_cmd_desc desc;
1054
1055         desc.its_int_cmd.dev = dev;
1056         desc.its_int_cmd.event_id = event_id;
1057
1058         its_send_single_command(dev->its, its_build_int_cmd, &desc);
1059 }
1060
1061 static void its_send_clear(struct its_device *dev, u32 event_id)
1062 {
1063         struct its_cmd_desc desc;
1064
1065         desc.its_clear_cmd.dev = dev;
1066         desc.its_clear_cmd.event_id = event_id;
1067
1068         its_send_single_command(dev->its, its_build_clear_cmd, &desc);
1069 }
1070
1071 static void its_send_inv(struct its_device *dev, u32 event_id)
1072 {
1073         struct its_cmd_desc desc;
1074
1075         desc.its_inv_cmd.dev = dev;
1076         desc.its_inv_cmd.event_id = event_id;
1077
1078         its_send_single_command(dev->its, its_build_inv_cmd, &desc);
1079 }
1080
1081 static void its_send_mapd(struct its_device *dev, int valid)
1082 {
1083         struct its_cmd_desc desc;
1084
1085         desc.its_mapd_cmd.dev = dev;
1086         desc.its_mapd_cmd.valid = !!valid;
1087
1088         its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
1089 }
1090
1091 static void its_send_mapc(struct its_node *its, struct its_collection *col,
1092                           int valid)
1093 {
1094         struct its_cmd_desc desc;
1095
1096         desc.its_mapc_cmd.col = col;
1097         desc.its_mapc_cmd.valid = !!valid;
1098
1099         its_send_single_command(its, its_build_mapc_cmd, &desc);
1100 }
1101
1102 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
1103 {
1104         struct its_cmd_desc desc;
1105
1106         desc.its_mapti_cmd.dev = dev;
1107         desc.its_mapti_cmd.phys_id = irq_id;
1108         desc.its_mapti_cmd.event_id = id;
1109
1110         its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
1111 }
1112
1113 static void its_send_movi(struct its_device *dev,
1114                           struct its_collection *col, u32 id)
1115 {
1116         struct its_cmd_desc desc;
1117
1118         desc.its_movi_cmd.dev = dev;
1119         desc.its_movi_cmd.col = col;
1120         desc.its_movi_cmd.event_id = id;
1121
1122         its_send_single_command(dev->its, its_build_movi_cmd, &desc);
1123 }
1124
1125 static void its_send_discard(struct its_device *dev, u32 id)
1126 {
1127         struct its_cmd_desc desc;
1128
1129         desc.its_discard_cmd.dev = dev;
1130         desc.its_discard_cmd.event_id = id;
1131
1132         its_send_single_command(dev->its, its_build_discard_cmd, &desc);
1133 }
1134
1135 static void its_send_invall(struct its_node *its, struct its_collection *col)
1136 {
1137         struct its_cmd_desc desc;
1138
1139         desc.its_invall_cmd.col = col;
1140
1141         its_send_single_command(its, its_build_invall_cmd, &desc);
1142 }
1143
1144 static void its_send_vmapti(struct its_device *dev, u32 id)
1145 {
1146         struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1147         struct its_cmd_desc desc;
1148
1149         desc.its_vmapti_cmd.vpe = map->vpe;
1150         desc.its_vmapti_cmd.dev = dev;
1151         desc.its_vmapti_cmd.virt_id = map->vintid;
1152         desc.its_vmapti_cmd.event_id = id;
1153         desc.its_vmapti_cmd.db_enabled = map->db_enabled;
1154
1155         its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
1156 }
1157
1158 static void its_send_vmovi(struct its_device *dev, u32 id)
1159 {
1160         struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1161         struct its_cmd_desc desc;
1162
1163         desc.its_vmovi_cmd.vpe = map->vpe;
1164         desc.its_vmovi_cmd.dev = dev;
1165         desc.its_vmovi_cmd.event_id = id;
1166         desc.its_vmovi_cmd.db_enabled = map->db_enabled;
1167
1168         its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
1169 }
1170
1171 static void its_send_vmapp(struct its_node *its,
1172                            struct its_vpe *vpe, bool valid)
1173 {
1174         struct its_cmd_desc desc;
1175
1176         desc.its_vmapp_cmd.vpe = vpe;
1177         desc.its_vmapp_cmd.valid = valid;
1178         desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
1179
1180         its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
1181 }
1182
1183 static void its_send_vmovp(struct its_vpe *vpe)
1184 {
1185         struct its_cmd_desc desc = {};
1186         struct its_node *its;
1187         unsigned long flags;
1188         int col_id = vpe->col_idx;
1189
1190         desc.its_vmovp_cmd.vpe = vpe;
1191
1192         if (!its_list_map) {
1193                 its = list_first_entry(&its_nodes, struct its_node, entry);
1194                 desc.its_vmovp_cmd.col = &its->collections[col_id];
1195                 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1196                 return;
1197         }
1198
1199         /*
1200          * Yet another marvel of the architecture. If using the
1201          * its_list "feature", we need to make sure that all ITSs
1202          * receive all VMOVP commands in the same order. The only way
1203          * to guarantee this is to make vmovp a serialization point.
1204          *
1205          * Wall <-- Head.
1206          */
1207         raw_spin_lock_irqsave(&vmovp_lock, flags);
1208
1209         desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1210         desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1211
1212         /* Emit VMOVPs */
1213         list_for_each_entry(its, &its_nodes, entry) {
1214                 if (!is_v4(its))
1215                         continue;
1216
1217                 if (!vpe->its_vm->vlpi_count[its->list_nr])
1218                         continue;
1219
1220                 desc.its_vmovp_cmd.col = &its->collections[col_id];
1221                 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1222         }
1223
1224         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1225 }
1226
1227 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1228 {
1229         struct its_cmd_desc desc;
1230
1231         desc.its_vinvall_cmd.vpe = vpe;
1232         its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1233 }
1234
1235 static void its_send_vinv(struct its_device *dev, u32 event_id)
1236 {
1237         struct its_cmd_desc desc;
1238
1239         /*
1240          * There is no real VINV command. This is just a normal INV,
1241          * with a VSYNC instead of a SYNC.
1242          */
1243         desc.its_inv_cmd.dev = dev;
1244         desc.its_inv_cmd.event_id = event_id;
1245
1246         its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc);
1247 }
1248
1249 static void its_send_vint(struct its_device *dev, u32 event_id)
1250 {
1251         struct its_cmd_desc desc;
1252
1253         /*
1254          * There is no real VINT command. This is just a normal INT,
1255          * with a VSYNC instead of a SYNC.
1256          */
1257         desc.its_int_cmd.dev = dev;
1258         desc.its_int_cmd.event_id = event_id;
1259
1260         its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc);
1261 }
1262
1263 static void its_send_vclear(struct its_device *dev, u32 event_id)
1264 {
1265         struct its_cmd_desc desc;
1266
1267         /*
1268          * There is no real VCLEAR command. This is just a normal CLEAR,
1269          * with a VSYNC instead of a SYNC.
1270          */
1271         desc.its_clear_cmd.dev = dev;
1272         desc.its_clear_cmd.event_id = event_id;
1273
1274         its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc);
1275 }
1276
1277 static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)
1278 {
1279         struct its_cmd_desc desc;
1280
1281         desc.its_invdb_cmd.vpe = vpe;
1282         its_send_single_vcommand(its, its_build_invdb_cmd, &desc);
1283 }
1284
1285 /*
1286  * irqchip functions - assumes MSI, mostly.
1287  */
1288 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1289 {
1290         struct its_vlpi_map *map = get_vlpi_map(d);
1291         irq_hw_number_t hwirq;
1292         void *va;
1293         u8 *cfg;
1294
1295         if (map) {
1296                 va = page_address(map->vm->vprop_page);
1297                 hwirq = map->vintid;
1298
1299                 /* Remember the updated property */
1300                 map->properties &= ~clr;
1301                 map->properties |= set | LPI_PROP_GROUP1;
1302         } else {
1303                 va = gic_rdists->prop_table_va;
1304                 hwirq = d->hwirq;
1305         }
1306
1307         cfg = va + hwirq - 8192;
1308         *cfg &= ~clr;
1309         *cfg |= set | LPI_PROP_GROUP1;
1310
1311         /*
1312          * Make the above write visible to the redistributors.
1313          * And yes, we're flushing exactly: One. Single. Byte.
1314          * Humpf...
1315          */
1316         if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1317                 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1318         else
1319                 dsb(ishst);
1320 }
1321
1322 static void wait_for_syncr(void __iomem *rdbase)
1323 {
1324         while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
1325                 cpu_relax();
1326 }
1327
1328 static void direct_lpi_inv(struct irq_data *d)
1329 {
1330         struct its_vlpi_map *map = get_vlpi_map(d);
1331         void __iomem *rdbase;
1332         u64 val;
1333
1334         if (map) {
1335                 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1336
1337                 WARN_ON(!is_v4_1(its_dev->its));
1338
1339                 val  = GICR_INVLPIR_V;
1340                 val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id);
1341                 val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid);
1342         } else {
1343                 val = d->hwirq;
1344         }
1345
1346         /* Target the redistributor this LPI is currently routed to */
1347         rdbase = per_cpu_ptr(gic_rdists->rdist, irq_to_cpuid(d))->rd_base;
1348         gic_write_lpir(val, rdbase + GICR_INVLPIR);
1349
1350         wait_for_syncr(rdbase);
1351 }
1352
1353 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1354 {
1355         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1356
1357         lpi_write_config(d, clr, set);
1358         if (gic_rdists->has_direct_lpi &&
1359             (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d)))
1360                 direct_lpi_inv(d);
1361         else if (!irqd_is_forwarded_to_vcpu(d))
1362                 its_send_inv(its_dev, its_get_event_id(d));
1363         else
1364                 its_send_vinv(its_dev, its_get_event_id(d));
1365 }
1366
1367 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1368 {
1369         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1370         u32 event = its_get_event_id(d);
1371         struct its_vlpi_map *map;
1372
1373         /*
1374          * GICv4.1 does away with the per-LPI nonsense, nothing to do
1375          * here.
1376          */
1377         if (is_v4_1(its_dev->its))
1378                 return;
1379
1380         map = dev_event_to_vlpi_map(its_dev, event);
1381
1382         if (map->db_enabled == enable)
1383                 return;
1384
1385         map->db_enabled = enable;
1386
1387         /*
1388          * More fun with the architecture:
1389          *
1390          * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1391          * value or to 1023, depending on the enable bit. But that
1392          * would be issueing a mapping for an /existing/ DevID+EventID
1393          * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1394          * to the /same/ vPE, using this opportunity to adjust the
1395          * doorbell. Mouahahahaha. We loves it, Precious.
1396          */
1397         its_send_vmovi(its_dev, event);
1398 }
1399
1400 static void its_mask_irq(struct irq_data *d)
1401 {
1402         if (irqd_is_forwarded_to_vcpu(d))
1403                 its_vlpi_set_doorbell(d, false);
1404
1405         lpi_update_config(d, LPI_PROP_ENABLED, 0);
1406 }
1407
1408 static void its_unmask_irq(struct irq_data *d)
1409 {
1410         if (irqd_is_forwarded_to_vcpu(d))
1411                 its_vlpi_set_doorbell(d, true);
1412
1413         lpi_update_config(d, 0, LPI_PROP_ENABLED);
1414 }
1415
1416 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1417                             bool force)
1418 {
1419         unsigned int cpu;
1420         const struct cpumask *cpu_mask = cpu_online_mask;
1421         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1422         struct its_collection *target_col;
1423         u32 id = its_get_event_id(d);
1424
1425         /* A forwarded interrupt should use irq_set_vcpu_affinity */
1426         if (irqd_is_forwarded_to_vcpu(d))
1427                 return -EINVAL;
1428
1429        /* lpi cannot be routed to a redistributor that is on a foreign node */
1430         if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1431                 if (its_dev->its->numa_node >= 0) {
1432                         cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1433                         if (!cpumask_intersects(mask_val, cpu_mask))
1434                                 return -EINVAL;
1435                 }
1436         }
1437
1438         cpu = cpumask_any_and(mask_val, cpu_mask);
1439
1440         if (cpu >= nr_cpu_ids)
1441                 return -EINVAL;
1442
1443         /* don't set the affinity when the target cpu is same as current one */
1444         if (cpu != its_dev->event_map.col_map[id]) {
1445                 target_col = &its_dev->its->collections[cpu];
1446                 its_send_movi(its_dev, target_col, id);
1447                 its_dev->event_map.col_map[id] = cpu;
1448                 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1449         }
1450
1451         return IRQ_SET_MASK_OK_DONE;
1452 }
1453
1454 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1455 {
1456         struct its_node *its = its_dev->its;
1457
1458         return its->phys_base + GITS_TRANSLATER;
1459 }
1460
1461 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1462 {
1463         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1464         struct its_node *its;
1465         u64 addr;
1466
1467         its = its_dev->its;
1468         addr = its->get_msi_base(its_dev);
1469
1470         msg->address_lo         = lower_32_bits(addr);
1471         msg->address_hi         = upper_32_bits(addr);
1472         msg->data               = its_get_event_id(d);
1473
1474         iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1475 }
1476
1477 static int its_irq_set_irqchip_state(struct irq_data *d,
1478                                      enum irqchip_irq_state which,
1479                                      bool state)
1480 {
1481         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1482         u32 event = its_get_event_id(d);
1483
1484         if (which != IRQCHIP_STATE_PENDING)
1485                 return -EINVAL;
1486
1487         if (irqd_is_forwarded_to_vcpu(d)) {
1488                 if (state)
1489                         its_send_vint(its_dev, event);
1490                 else
1491                         its_send_vclear(its_dev, event);
1492         } else {
1493                 if (state)
1494                         its_send_int(its_dev, event);
1495                 else
1496                         its_send_clear(its_dev, event);
1497         }
1498
1499         return 0;
1500 }
1501
1502 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1503 {
1504         unsigned long flags;
1505
1506         /* Not using the ITS list? Everything is always mapped. */
1507         if (!its_list_map)
1508                 return;
1509
1510         raw_spin_lock_irqsave(&vmovp_lock, flags);
1511
1512         /*
1513          * If the VM wasn't mapped yet, iterate over the vpes and get
1514          * them mapped now.
1515          */
1516         vm->vlpi_count[its->list_nr]++;
1517
1518         if (vm->vlpi_count[its->list_nr] == 1) {
1519                 int i;
1520
1521                 for (i = 0; i < vm->nr_vpes; i++) {
1522                         struct its_vpe *vpe = vm->vpes[i];
1523                         struct irq_data *d = irq_get_irq_data(vpe->irq);
1524
1525                         /* Map the VPE to the first possible CPU */
1526                         vpe->col_idx = cpumask_first(cpu_online_mask);
1527                         its_send_vmapp(its, vpe, true);
1528                         its_send_vinvall(its, vpe);
1529                         irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1530                 }
1531         }
1532
1533         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1534 }
1535
1536 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1537 {
1538         unsigned long flags;
1539
1540         /* Not using the ITS list? Everything is always mapped. */
1541         if (!its_list_map)
1542                 return;
1543
1544         raw_spin_lock_irqsave(&vmovp_lock, flags);
1545
1546         if (!--vm->vlpi_count[its->list_nr]) {
1547                 int i;
1548
1549                 for (i = 0; i < vm->nr_vpes; i++)
1550                         its_send_vmapp(its, vm->vpes[i], false);
1551         }
1552
1553         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1554 }
1555
1556 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1557 {
1558         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1559         u32 event = its_get_event_id(d);
1560         int ret = 0;
1561
1562         if (!info->map)
1563                 return -EINVAL;
1564
1565         raw_spin_lock(&its_dev->event_map.vlpi_lock);
1566
1567         if (!its_dev->event_map.vm) {
1568                 struct its_vlpi_map *maps;
1569
1570                 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1571                                GFP_ATOMIC);
1572                 if (!maps) {
1573                         ret = -ENOMEM;
1574                         goto out;
1575                 }
1576
1577                 its_dev->event_map.vm = info->map->vm;
1578                 its_dev->event_map.vlpi_maps = maps;
1579         } else if (its_dev->event_map.vm != info->map->vm) {
1580                 ret = -EINVAL;
1581                 goto out;
1582         }
1583
1584         /* Get our private copy of the mapping information */
1585         its_dev->event_map.vlpi_maps[event] = *info->map;
1586
1587         if (irqd_is_forwarded_to_vcpu(d)) {
1588                 /* Already mapped, move it around */
1589                 its_send_vmovi(its_dev, event);
1590         } else {
1591                 /* Ensure all the VPEs are mapped on this ITS */
1592                 its_map_vm(its_dev->its, info->map->vm);
1593
1594                 /*
1595                  * Flag the interrupt as forwarded so that we can
1596                  * start poking the virtual property table.
1597                  */
1598                 irqd_set_forwarded_to_vcpu(d);
1599
1600                 /* Write out the property to the prop table */
1601                 lpi_write_config(d, 0xff, info->map->properties);
1602
1603                 /* Drop the physical mapping */
1604                 its_send_discard(its_dev, event);
1605
1606                 /* and install the virtual one */
1607                 its_send_vmapti(its_dev, event);
1608
1609                 /* Increment the number of VLPIs */
1610                 its_dev->event_map.nr_vlpis++;
1611         }
1612
1613 out:
1614         raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1615         return ret;
1616 }
1617
1618 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1619 {
1620         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1621         struct its_vlpi_map *map;
1622         int ret = 0;
1623
1624         raw_spin_lock(&its_dev->event_map.vlpi_lock);
1625
1626         map = get_vlpi_map(d);
1627
1628         if (!its_dev->event_map.vm || !map) {
1629                 ret = -EINVAL;
1630                 goto out;
1631         }
1632
1633         /* Copy our mapping information to the incoming request */
1634         *info->map = *map;
1635
1636 out:
1637         raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1638         return ret;
1639 }
1640
1641 static int its_vlpi_unmap(struct irq_data *d)
1642 {
1643         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1644         u32 event = its_get_event_id(d);
1645         int ret = 0;
1646
1647         raw_spin_lock(&its_dev->event_map.vlpi_lock);
1648
1649         if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1650                 ret = -EINVAL;
1651                 goto out;
1652         }
1653
1654         /* Drop the virtual mapping */
1655         its_send_discard(its_dev, event);
1656
1657         /* and restore the physical one */
1658         irqd_clr_forwarded_to_vcpu(d);
1659         its_send_mapti(its_dev, d->hwirq, event);
1660         lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1661                                     LPI_PROP_ENABLED |
1662                                     LPI_PROP_GROUP1));
1663
1664         /* Potentially unmap the VM from this ITS */
1665         its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1666
1667         /*
1668          * Drop the refcount and make the device available again if
1669          * this was the last VLPI.
1670          */
1671         if (!--its_dev->event_map.nr_vlpis) {
1672                 its_dev->event_map.vm = NULL;
1673                 kfree(its_dev->event_map.vlpi_maps);
1674         }
1675
1676 out:
1677         raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1678         return ret;
1679 }
1680
1681 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1682 {
1683         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1684
1685         if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1686                 return -EINVAL;
1687
1688         if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1689                 lpi_update_config(d, 0xff, info->config);
1690         else
1691                 lpi_write_config(d, 0xff, info->config);
1692         its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1693
1694         return 0;
1695 }
1696
1697 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1698 {
1699         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1700         struct its_cmd_info *info = vcpu_info;
1701
1702         /* Need a v4 ITS */
1703         if (!is_v4(its_dev->its))
1704                 return -EINVAL;
1705
1706         /* Unmap request? */
1707         if (!info)
1708                 return its_vlpi_unmap(d);
1709
1710         switch (info->cmd_type) {
1711         case MAP_VLPI:
1712                 return its_vlpi_map(d, info);
1713
1714         case GET_VLPI:
1715                 return its_vlpi_get(d, info);
1716
1717         case PROP_UPDATE_VLPI:
1718         case PROP_UPDATE_AND_INV_VLPI:
1719                 return its_vlpi_prop_update(d, info);
1720
1721         default:
1722                 return -EINVAL;
1723         }
1724 }
1725
1726 static struct irq_chip its_irq_chip = {
1727         .name                   = "ITS",
1728         .irq_mask               = its_mask_irq,
1729         .irq_unmask             = its_unmask_irq,
1730         .irq_eoi                = irq_chip_eoi_parent,
1731         .irq_set_affinity       = its_set_affinity,
1732         .irq_compose_msi_msg    = its_irq_compose_msi_msg,
1733         .irq_set_irqchip_state  = its_irq_set_irqchip_state,
1734         .irq_set_vcpu_affinity  = its_irq_set_vcpu_affinity,
1735 };
1736
1737
1738 /*
1739  * How we allocate LPIs:
1740  *
1741  * lpi_range_list contains ranges of LPIs that are to available to
1742  * allocate from. To allocate LPIs, just pick the first range that
1743  * fits the required allocation, and reduce it by the required
1744  * amount. Once empty, remove the range from the list.
1745  *
1746  * To free a range of LPIs, add a free range to the list, sort it and
1747  * merge the result if the new range happens to be adjacent to an
1748  * already free block.
1749  *
1750  * The consequence of the above is that allocation is cost is low, but
1751  * freeing is expensive. We assumes that freeing rarely occurs.
1752  */
1753 #define ITS_MAX_LPI_NRBITS      16 /* 64K LPIs */
1754
1755 static DEFINE_MUTEX(lpi_range_lock);
1756 static LIST_HEAD(lpi_range_list);
1757
1758 struct lpi_range {
1759         struct list_head        entry;
1760         u32                     base_id;
1761         u32                     span;
1762 };
1763
1764 static struct lpi_range *mk_lpi_range(u32 base, u32 span)
1765 {
1766         struct lpi_range *range;
1767
1768         range = kmalloc(sizeof(*range), GFP_KERNEL);
1769         if (range) {
1770                 range->base_id = base;
1771                 range->span = span;
1772         }
1773
1774         return range;
1775 }
1776
1777 static int alloc_lpi_range(u32 nr_lpis, u32 *base)
1778 {
1779         struct lpi_range *range, *tmp;
1780         int err = -ENOSPC;
1781
1782         mutex_lock(&lpi_range_lock);
1783
1784         list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
1785                 if (range->span >= nr_lpis) {
1786                         *base = range->base_id;
1787                         range->base_id += nr_lpis;
1788                         range->span -= nr_lpis;
1789
1790                         if (range->span == 0) {
1791                                 list_del(&range->entry);
1792                                 kfree(range);
1793                         }
1794
1795                         err = 0;
1796                         break;
1797                 }
1798         }
1799
1800         mutex_unlock(&lpi_range_lock);
1801
1802         pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
1803         return err;
1804 }
1805
1806 static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
1807 {
1808         if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
1809                 return;
1810         if (a->base_id + a->span != b->base_id)
1811                 return;
1812         b->base_id = a->base_id;
1813         b->span += a->span;
1814         list_del(&a->entry);
1815         kfree(a);
1816 }
1817
1818 static int free_lpi_range(u32 base, u32 nr_lpis)
1819 {
1820         struct lpi_range *new, *old;
1821
1822         new = mk_lpi_range(base, nr_lpis);
1823         if (!new)
1824                 return -ENOMEM;
1825
1826         mutex_lock(&lpi_range_lock);
1827
1828         list_for_each_entry_reverse(old, &lpi_range_list, entry) {
1829                 if (old->base_id < base)
1830                         break;
1831         }
1832         /*
1833          * old is the last element with ->base_id smaller than base,
1834          * so new goes right after it. If there are no elements with
1835          * ->base_id smaller than base, &old->entry ends up pointing
1836          * at the head of the list, and inserting new it the start of
1837          * the list is the right thing to do in that case as well.
1838          */
1839         list_add(&new->entry, &old->entry);
1840         /*
1841          * Now check if we can merge with the preceding and/or
1842          * following ranges.
1843          */
1844         merge_lpi_ranges(old, new);
1845         merge_lpi_ranges(new, list_next_entry(new, entry));
1846
1847         mutex_unlock(&lpi_range_lock);
1848         return 0;
1849 }
1850
1851 static int __init its_lpi_init(u32 id_bits)
1852 {
1853         u32 lpis = (1UL << id_bits) - 8192;
1854         u32 numlpis;
1855         int err;
1856
1857         numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
1858
1859         if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
1860                 lpis = numlpis;
1861                 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
1862                         lpis);
1863         }
1864
1865         /*
1866          * Initializing the allocator is just the same as freeing the
1867          * full range of LPIs.
1868          */
1869         err = free_lpi_range(8192, lpis);
1870         pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
1871         return err;
1872 }
1873
1874 static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
1875 {
1876         unsigned long *bitmap = NULL;
1877         int err = 0;
1878
1879         do {
1880                 err = alloc_lpi_range(nr_irqs, base);
1881                 if (!err)
1882                         break;
1883
1884                 nr_irqs /= 2;
1885         } while (nr_irqs > 0);
1886
1887         if (!nr_irqs)
1888                 err = -ENOSPC;
1889
1890         if (err)
1891                 goto out;
1892
1893         bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
1894         if (!bitmap)
1895                 goto out;
1896
1897         *nr_ids = nr_irqs;
1898
1899 out:
1900         if (!bitmap)
1901                 *base = *nr_ids = 0;
1902
1903         return bitmap;
1904 }
1905
1906 static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
1907 {
1908         WARN_ON(free_lpi_range(base, nr_ids));
1909         kfree(bitmap);
1910 }
1911
1912 static void gic_reset_prop_table(void *va)
1913 {
1914         /* Priority 0xa0, Group-1, disabled */
1915         memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
1916
1917         /* Make sure the GIC will observe the written configuration */
1918         gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
1919 }
1920
1921 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
1922 {
1923         struct page *prop_page;
1924
1925         prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
1926         if (!prop_page)
1927                 return NULL;
1928
1929         gic_reset_prop_table(page_address(prop_page));
1930
1931         return prop_page;
1932 }
1933
1934 static void its_free_prop_table(struct page *prop_page)
1935 {
1936         free_pages((unsigned long)page_address(prop_page),
1937                    get_order(LPI_PROPBASE_SZ));
1938 }
1939
1940 static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
1941 {
1942         phys_addr_t start, end, addr_end;
1943         u64 i;
1944
1945         /*
1946          * We don't bother checking for a kdump kernel as by
1947          * construction, the LPI tables are out of this kernel's
1948          * memory map.
1949          */
1950         if (is_kdump_kernel())
1951                 return true;
1952
1953         addr_end = addr + size - 1;
1954
1955         for_each_reserved_mem_region(i, &start, &end) {
1956                 if (addr >= start && addr_end <= end)
1957                         return true;
1958         }
1959
1960         /* Not found, not a good sign... */
1961         pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
1962                 &addr, &addr_end);
1963         add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
1964         return false;
1965 }
1966
1967 static int gic_reserve_range(phys_addr_t addr, unsigned long size)
1968 {
1969         if (efi_enabled(EFI_CONFIG_TABLES))
1970                 return efi_mem_reserve_persistent(addr, size);
1971
1972         return 0;
1973 }
1974
1975 static int __init its_setup_lpi_prop_table(void)
1976 {
1977         if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
1978                 u64 val;
1979
1980                 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
1981                 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
1982
1983                 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
1984                 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
1985                                                      LPI_PROPBASE_SZ,
1986                                                      MEMREMAP_WB);
1987                 gic_reset_prop_table(gic_rdists->prop_table_va);
1988         } else {
1989                 struct page *page;
1990
1991                 lpi_id_bits = min_t(u32,
1992                                     GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
1993                                     ITS_MAX_LPI_NRBITS);
1994                 page = its_allocate_prop_table(GFP_NOWAIT);
1995                 if (!page) {
1996                         pr_err("Failed to allocate PROPBASE\n");
1997                         return -ENOMEM;
1998                 }
1999
2000                 gic_rdists->prop_table_pa = page_to_phys(page);
2001                 gic_rdists->prop_table_va = page_address(page);
2002                 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
2003                                           LPI_PROPBASE_SZ));
2004         }
2005
2006         pr_info("GICv3: using LPI property table @%pa\n",
2007                 &gic_rdists->prop_table_pa);
2008
2009         return its_lpi_init(lpi_id_bits);
2010 }
2011
2012 static const char *its_base_type_string[] = {
2013         [GITS_BASER_TYPE_DEVICE]        = "Devices",
2014         [GITS_BASER_TYPE_VCPU]          = "Virtual CPUs",
2015         [GITS_BASER_TYPE_RESERVED3]     = "Reserved (3)",
2016         [GITS_BASER_TYPE_COLLECTION]    = "Interrupt Collections",
2017         [GITS_BASER_TYPE_RESERVED5]     = "Reserved (5)",
2018         [GITS_BASER_TYPE_RESERVED6]     = "Reserved (6)",
2019         [GITS_BASER_TYPE_RESERVED7]     = "Reserved (7)",
2020 };
2021
2022 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
2023 {
2024         u32 idx = baser - its->tables;
2025
2026         return gits_read_baser(its->base + GITS_BASER + (idx << 3));
2027 }
2028
2029 static void its_write_baser(struct its_node *its, struct its_baser *baser,
2030                             u64 val)
2031 {
2032         u32 idx = baser - its->tables;
2033
2034         gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
2035         baser->val = its_read_baser(its, baser);
2036 }
2037
2038 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
2039                            u64 cache, u64 shr, u32 psz, u32 order,
2040                            bool indirect)
2041 {
2042         u64 val = its_read_baser(its, baser);
2043         u64 esz = GITS_BASER_ENTRY_SIZE(val);
2044         u64 type = GITS_BASER_TYPE(val);
2045         u64 baser_phys, tmp;
2046         u32 alloc_pages;
2047         struct page *page;
2048         void *base;
2049
2050 retry_alloc_baser:
2051         alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
2052         if (alloc_pages > GITS_BASER_PAGES_MAX) {
2053                 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
2054                         &its->phys_base, its_base_type_string[type],
2055                         alloc_pages, GITS_BASER_PAGES_MAX);
2056                 alloc_pages = GITS_BASER_PAGES_MAX;
2057                 order = get_order(GITS_BASER_PAGES_MAX * psz);
2058         }
2059
2060         page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
2061         if (!page)
2062                 return -ENOMEM;
2063
2064         base = (void *)page_address(page);
2065         baser_phys = virt_to_phys(base);
2066
2067         /* Check if the physical address of the memory is above 48bits */
2068         if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
2069
2070                 /* 52bit PA is supported only when PageSize=64K */
2071                 if (psz != SZ_64K) {
2072                         pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
2073                         free_pages((unsigned long)base, order);
2074                         return -ENXIO;
2075                 }
2076
2077                 /* Convert 52bit PA to 48bit field */
2078                 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
2079         }
2080
2081 retry_baser:
2082         val = (baser_phys                                        |
2083                 (type << GITS_BASER_TYPE_SHIFT)                  |
2084                 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT)       |
2085                 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT)    |
2086                 cache                                            |
2087                 shr                                              |
2088                 GITS_BASER_VALID);
2089
2090         val |=  indirect ? GITS_BASER_INDIRECT : 0x0;
2091
2092         switch (psz) {
2093         case SZ_4K:
2094                 val |= GITS_BASER_PAGE_SIZE_4K;
2095                 break;
2096         case SZ_16K:
2097                 val |= GITS_BASER_PAGE_SIZE_16K;
2098                 break;
2099         case SZ_64K:
2100                 val |= GITS_BASER_PAGE_SIZE_64K;
2101                 break;
2102         }
2103
2104         its_write_baser(its, baser, val);
2105         tmp = baser->val;
2106
2107         if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
2108                 /*
2109                  * Shareability didn't stick. Just use
2110                  * whatever the read reported, which is likely
2111                  * to be the only thing this redistributor
2112                  * supports. If that's zero, make it
2113                  * non-cacheable as well.
2114                  */
2115                 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
2116                 if (!shr) {
2117                         cache = GITS_BASER_nC;
2118                         gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
2119                 }
2120                 goto retry_baser;
2121         }
2122
2123         if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
2124                 /*
2125                  * Page size didn't stick. Let's try a smaller
2126                  * size and retry. If we reach 4K, then
2127                  * something is horribly wrong...
2128                  */
2129                 free_pages((unsigned long)base, order);
2130                 baser->base = NULL;
2131
2132                 switch (psz) {
2133                 case SZ_16K:
2134                         psz = SZ_4K;
2135                         goto retry_alloc_baser;
2136                 case SZ_64K:
2137                         psz = SZ_16K;
2138                         goto retry_alloc_baser;
2139                 }
2140         }
2141
2142         if (val != tmp) {
2143                 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
2144                        &its->phys_base, its_base_type_string[type],
2145                        val, tmp);
2146                 free_pages((unsigned long)base, order);
2147                 return -ENXIO;
2148         }
2149
2150         baser->order = order;
2151         baser->base = base;
2152         baser->psz = psz;
2153         tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
2154
2155         pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
2156                 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
2157                 its_base_type_string[type],
2158                 (unsigned long)virt_to_phys(base),
2159                 indirect ? "indirect" : "flat", (int)esz,
2160                 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
2161
2162         return 0;
2163 }
2164
2165 static bool its_parse_indirect_baser(struct its_node *its,
2166                                      struct its_baser *baser,
2167                                      u32 psz, u32 *order, u32 ids)
2168 {
2169         u64 tmp = its_read_baser(its, baser);
2170         u64 type = GITS_BASER_TYPE(tmp);
2171         u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
2172         u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
2173         u32 new_order = *order;
2174         bool indirect = false;
2175
2176         /* No need to enable Indirection if memory requirement < (psz*2)bytes */
2177         if ((esz << ids) > (psz * 2)) {
2178                 /*
2179                  * Find out whether hw supports a single or two-level table by
2180                  * table by reading bit at offset '62' after writing '1' to it.
2181                  */
2182                 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
2183                 indirect = !!(baser->val & GITS_BASER_INDIRECT);
2184
2185                 if (indirect) {
2186                         /*
2187                          * The size of the lvl2 table is equal to ITS page size
2188                          * which is 'psz'. For computing lvl1 table size,
2189                          * subtract ID bits that sparse lvl2 table from 'ids'
2190                          * which is reported by ITS hardware times lvl1 table
2191                          * entry size.
2192                          */
2193                         ids -= ilog2(psz / (int)esz);
2194                         esz = GITS_LVL1_ENTRY_SIZE;
2195                 }
2196         }
2197
2198         /*
2199          * Allocate as many entries as required to fit the
2200          * range of device IDs that the ITS can grok... The ID
2201          * space being incredibly sparse, this results in a
2202          * massive waste of memory if two-level device table
2203          * feature is not supported by hardware.
2204          */
2205         new_order = max_t(u32, get_order(esz << ids), new_order);
2206         if (new_order >= MAX_ORDER) {
2207                 new_order = MAX_ORDER - 1;
2208                 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
2209                 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n",
2210                         &its->phys_base, its_base_type_string[type],
2211                         device_ids(its), ids);
2212         }
2213
2214         *order = new_order;
2215
2216         return indirect;
2217 }
2218
2219 static u32 compute_common_aff(u64 val)
2220 {
2221         u32 aff, clpiaff;
2222
2223         aff = FIELD_GET(GICR_TYPER_AFFINITY, val);
2224         clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val);
2225
2226         return aff & ~(GENMASK(31, 0) >> (clpiaff * 8));
2227 }
2228
2229 static u32 compute_its_aff(struct its_node *its)
2230 {
2231         u64 val;
2232         u32 svpet;
2233
2234         /*
2235          * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute
2236          * the resulting affinity. We then use that to see if this match
2237          * our own affinity.
2238          */
2239         svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
2240         val  = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet);
2241         val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr);
2242         return compute_common_aff(val);
2243 }
2244
2245 static struct its_node *find_sibling_its(struct its_node *cur_its)
2246 {
2247         struct its_node *its;
2248         u32 aff;
2249
2250         if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer))
2251                 return NULL;
2252
2253         aff = compute_its_aff(cur_its);
2254
2255         list_for_each_entry(its, &its_nodes, entry) {
2256                 u64 baser;
2257
2258                 if (!is_v4_1(its) || its == cur_its)
2259                         continue;
2260
2261                 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2262                         continue;
2263
2264                 if (aff != compute_its_aff(its))
2265                         continue;
2266
2267                 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2268                 baser = its->tables[2].val;
2269                 if (!(baser & GITS_BASER_VALID))
2270                         continue;
2271
2272                 return its;
2273         }
2274
2275         return NULL;
2276 }
2277
2278 static void its_free_tables(struct its_node *its)
2279 {
2280         int i;
2281
2282         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2283                 if (its->tables[i].base) {
2284                         free_pages((unsigned long)its->tables[i].base,
2285                                    its->tables[i].order);
2286                         its->tables[i].base = NULL;
2287                 }
2288         }
2289 }
2290
2291 static int its_alloc_tables(struct its_node *its)
2292 {
2293         u64 shr = GITS_BASER_InnerShareable;
2294         u64 cache = GITS_BASER_RaWaWb;
2295         u32 psz = SZ_64K;
2296         int err, i;
2297
2298         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
2299                 /* erratum 24313: ignore memory access type */
2300                 cache = GITS_BASER_nCnB;
2301
2302         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2303                 struct its_baser *baser = its->tables + i;
2304                 u64 val = its_read_baser(its, baser);
2305                 u64 type = GITS_BASER_TYPE(val);
2306                 u32 order = get_order(psz);
2307                 bool indirect = false;
2308
2309                 switch (type) {
2310                 case GITS_BASER_TYPE_NONE:
2311                         continue;
2312
2313                 case GITS_BASER_TYPE_DEVICE:
2314                         indirect = its_parse_indirect_baser(its, baser,
2315                                                             psz, &order,
2316                                                             device_ids(its));
2317                         break;
2318
2319                 case GITS_BASER_TYPE_VCPU:
2320                         if (is_v4_1(its)) {
2321                                 struct its_node *sibling;
2322
2323                                 WARN_ON(i != 2);
2324                                 if ((sibling = find_sibling_its(its))) {
2325                                         *baser = sibling->tables[2];
2326                                         its_write_baser(its, baser, baser->val);
2327                                         continue;
2328                                 }
2329                         }
2330
2331                         indirect = its_parse_indirect_baser(its, baser,
2332                                                             psz, &order,
2333                                                             ITS_MAX_VPEID_BITS);
2334                         break;
2335                 }
2336
2337                 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
2338                 if (err < 0) {
2339                         its_free_tables(its);
2340                         return err;
2341                 }
2342
2343                 /* Update settings which will be used for next BASERn */
2344                 psz = baser->psz;
2345                 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
2346                 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
2347         }
2348
2349         return 0;
2350 }
2351
2352 static u64 inherit_vpe_l1_table_from_its(void)
2353 {
2354         struct its_node *its;
2355         u64 val;
2356         u32 aff;
2357
2358         val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2359         aff = compute_common_aff(val);
2360
2361         list_for_each_entry(its, &its_nodes, entry) {
2362                 u64 baser, addr;
2363
2364                 if (!is_v4_1(its))
2365                         continue;
2366
2367                 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2368                         continue;
2369
2370                 if (aff != compute_its_aff(its))
2371                         continue;
2372
2373                 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2374                 baser = its->tables[2].val;
2375                 if (!(baser & GITS_BASER_VALID))
2376                         continue;
2377
2378                 /* We have a winner! */
2379                 val  = GICR_VPROPBASER_4_1_VALID;
2380                 if (baser & GITS_BASER_INDIRECT)
2381                         val |= GICR_VPROPBASER_4_1_INDIRECT;
2382                 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE,
2383                                   FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser));
2384                 switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) {
2385                 case GIC_PAGE_SIZE_64K:
2386                         addr = GITS_BASER_ADDR_48_to_52(baser);
2387                         break;
2388                 default:
2389                         addr = baser & GENMASK_ULL(47, 12);
2390                         break;
2391                 }
2392                 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12);
2393                 val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK,
2394                                   FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser));
2395                 val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK,
2396                                   FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser));
2397                 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1);
2398
2399                 return val;
2400         }
2401
2402         return 0;
2403 }
2404
2405 static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
2406 {
2407         u32 aff;
2408         u64 val;
2409         int cpu;
2410
2411         val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2412         aff = compute_common_aff(val);
2413
2414         for_each_possible_cpu(cpu) {
2415                 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2416                 u32 tmp;
2417
2418                 if (!base || cpu == smp_processor_id())
2419                         continue;
2420
2421                 val = gic_read_typer(base + GICR_TYPER);
2422                 tmp = compute_common_aff(val);
2423                 if (tmp != aff)
2424                         continue;
2425
2426                 /*
2427                  * At this point, we have a victim. This particular CPU
2428                  * has already booted, and has an affinity that matches
2429                  * ours wrt CommonLPIAff. Let's use its own VPROPBASER.
2430                  * Make sure we don't write the Z bit in that case.
2431                  */
2432                 val = gits_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2433                 val &= ~GICR_VPROPBASER_4_1_Z;
2434
2435                 *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask;
2436
2437                 return val;
2438         }
2439
2440         return 0;
2441 }
2442
2443 static int allocate_vpe_l1_table(void)
2444 {
2445         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2446         u64 val, gpsz, npg, pa;
2447         unsigned int psz = SZ_64K;
2448         unsigned int np, epp, esz;
2449         struct page *page;
2450
2451         if (!gic_rdists->has_rvpeid)
2452                 return 0;
2453
2454         /*
2455          * if VPENDBASER.Valid is set, disable any previously programmed
2456          * VPE by setting PendingLast while clearing Valid. This has the
2457          * effect of making sure no doorbell will be generated and we can
2458          * then safely clear VPROPBASER.Valid.
2459          */
2460         if (gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid)
2461                 gits_write_vpendbaser(GICR_VPENDBASER_PendingLast,
2462                                       vlpi_base + GICR_VPENDBASER);
2463
2464         /*
2465          * If we can inherit the configuration from another RD, let's do
2466          * so. Otherwise, we have to go through the allocation process. We
2467          * assume that all RDs have the exact same requirements, as
2468          * nothing will work otherwise.
2469          */
2470         val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask);
2471         if (val & GICR_VPROPBASER_4_1_VALID)
2472                 goto out;
2473
2474         gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_KERNEL);
2475         if (!gic_data_rdist()->vpe_table_mask)
2476                 return -ENOMEM;
2477
2478         val = inherit_vpe_l1_table_from_its();
2479         if (val & GICR_VPROPBASER_4_1_VALID)
2480                 goto out;
2481
2482         /* First probe the page size */
2483         val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K);
2484         gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2485         val = gits_read_vpropbaser(vlpi_base + GICR_VPROPBASER);
2486         gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2487         esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val);
2488
2489         switch (gpsz) {
2490         default:
2491                 gpsz = GIC_PAGE_SIZE_4K;
2492                 /* fall through */
2493         case GIC_PAGE_SIZE_4K:
2494                 psz = SZ_4K;
2495                 break;
2496         case GIC_PAGE_SIZE_16K:
2497                 psz = SZ_16K;
2498                 break;
2499         case GIC_PAGE_SIZE_64K:
2500                 psz = SZ_64K;
2501                 break;
2502         }
2503
2504         /*
2505          * Start populating the register from scratch, including RO fields
2506          * (which we want to print in debug cases...)
2507          */
2508         val = 0;
2509         val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz);
2510         val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz);
2511
2512         /* How many entries per GIC page? */
2513         esz++;
2514         epp = psz / (esz * SZ_8);
2515
2516         /*
2517          * If we need more than just a single L1 page, flag the table
2518          * as indirect and compute the number of required L1 pages.
2519          */
2520         if (epp < ITS_MAX_VPEID) {
2521                 int nl2;
2522
2523                 val |= GICR_VPROPBASER_4_1_INDIRECT;
2524
2525                 /* Number of L2 pages required to cover the VPEID space */
2526                 nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);
2527
2528                 /* Number of L1 pages to point to the L2 pages */
2529                 npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
2530         } else {
2531                 npg = 1;
2532         }
2533
2534         val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg);
2535
2536         /* Right, that's the number of CPU pages we need for L1 */
2537         np = DIV_ROUND_UP(npg * psz, PAGE_SIZE);
2538
2539         pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
2540                  np, npg, psz, epp, esz);
2541         page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(np * PAGE_SIZE));
2542         if (!page)
2543                 return -ENOMEM;
2544
2545         gic_data_rdist()->vpe_l1_page = page;
2546         pa = virt_to_phys(page_address(page));
2547         WARN_ON(!IS_ALIGNED(pa, psz));
2548
2549         val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12);
2550         val |= GICR_VPROPBASER_RaWb;
2551         val |= GICR_VPROPBASER_InnerShareable;
2552         val |= GICR_VPROPBASER_4_1_Z;
2553         val |= GICR_VPROPBASER_4_1_VALID;
2554
2555 out:
2556         gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2557         cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask);
2558
2559         pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n",
2560                  smp_processor_id(), val,
2561                  cpumask_pr_args(gic_data_rdist()->vpe_table_mask));
2562
2563         return 0;
2564 }
2565
2566 static int its_alloc_collections(struct its_node *its)
2567 {
2568         int i;
2569
2570         its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
2571                                    GFP_KERNEL);
2572         if (!its->collections)
2573                 return -ENOMEM;
2574
2575         for (i = 0; i < nr_cpu_ids; i++)
2576                 its->collections[i].target_address = ~0ULL;
2577
2578         return 0;
2579 }
2580
2581 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2582 {
2583         struct page *pend_page;
2584
2585         pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2586                                 get_order(LPI_PENDBASE_SZ));
2587         if (!pend_page)
2588                 return NULL;
2589
2590         /* Make sure the GIC will observe the zero-ed page */
2591         gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2592
2593         return pend_page;
2594 }
2595
2596 static void its_free_pending_table(struct page *pt)
2597 {
2598         free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2599 }
2600
2601 /*
2602  * Booting with kdump and LPIs enabled is generally fine. Any other
2603  * case is wrong in the absence of firmware/EFI support.
2604  */
2605 static bool enabled_lpis_allowed(void)
2606 {
2607         phys_addr_t addr;
2608         u64 val;
2609
2610         /* Check whether the property table is in a reserved region */
2611         val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2612         addr = val & GENMASK_ULL(51, 12);
2613
2614         return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2615 }
2616
2617 static int __init allocate_lpi_tables(void)
2618 {
2619         u64 val;
2620         int err, cpu;
2621
2622         /*
2623          * If LPIs are enabled while we run this from the boot CPU,
2624          * flag the RD tables as pre-allocated if the stars do align.
2625          */
2626         val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2627         if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2628                 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2629                                       RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2630                 pr_info("GICv3: Using preallocated redistributor tables\n");
2631         }
2632
2633         err = its_setup_lpi_prop_table();
2634         if (err)
2635                 return err;
2636
2637         /*
2638          * We allocate all the pending tables anyway, as we may have a
2639          * mix of RDs that have had LPIs enabled, and some that
2640          * don't. We'll free the unused ones as each CPU comes online.
2641          */
2642         for_each_possible_cpu(cpu) {
2643                 struct page *pend_page;
2644
2645                 pend_page = its_allocate_pending_table(GFP_NOWAIT);
2646                 if (!pend_page) {
2647                         pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
2648                         return -ENOMEM;
2649                 }
2650
2651                 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
2652         }
2653
2654         return 0;
2655 }
2656
2657 static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
2658 {
2659         u32 count = 1000000;    /* 1s! */
2660         bool clean;
2661         u64 val;
2662
2663         val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2664         val &= ~GICR_VPENDBASER_Valid;
2665         val &= ~clr;
2666         val |= set;
2667         gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2668
2669         do {
2670                 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2671                 clean = !(val & GICR_VPENDBASER_Dirty);
2672                 if (!clean) {
2673                         count--;
2674                         cpu_relax();
2675                         udelay(1);
2676                 }
2677         } while (!clean && count);
2678
2679         if (unlikely(val & GICR_VPENDBASER_Dirty)) {
2680                 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
2681                 val |= GICR_VPENDBASER_PendingLast;
2682         }
2683
2684         return val;
2685 }
2686
2687 static void its_cpu_init_lpis(void)
2688 {
2689         void __iomem *rbase = gic_data_rdist_rd_base();
2690         struct page *pend_page;
2691         phys_addr_t paddr;
2692         u64 val, tmp;
2693
2694         if (gic_data_rdist()->lpi_enabled)
2695                 return;
2696
2697         val = readl_relaxed(rbase + GICR_CTLR);
2698         if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
2699             (val & GICR_CTLR_ENABLE_LPIS)) {
2700                 /*
2701                  * Check that we get the same property table on all
2702                  * RDs. If we don't, this is hopeless.
2703                  */
2704                 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
2705                 paddr &= GENMASK_ULL(51, 12);
2706                 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
2707                         add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2708
2709                 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2710                 paddr &= GENMASK_ULL(51, 16);
2711
2712                 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
2713                 its_free_pending_table(gic_data_rdist()->pend_page);
2714                 gic_data_rdist()->pend_page = NULL;
2715
2716                 goto out;
2717         }
2718
2719         pend_page = gic_data_rdist()->pend_page;
2720         paddr = page_to_phys(pend_page);
2721         WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
2722
2723         /* set PROPBASE */
2724         val = (gic_rdists->prop_table_pa |
2725                GICR_PROPBASER_InnerShareable |
2726                GICR_PROPBASER_RaWaWb |
2727                ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
2728
2729         gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2730         tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
2731
2732         if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
2733                 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
2734                         /*
2735                          * The HW reports non-shareable, we must
2736                          * remove the cacheability attributes as
2737                          * well.
2738                          */
2739                         val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
2740                                  GICR_PROPBASER_CACHEABILITY_MASK);
2741                         val |= GICR_PROPBASER_nC;
2742                         gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2743                 }
2744                 pr_info_once("GIC: using cache flushing for LPI property table\n");
2745                 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
2746         }
2747
2748         /* set PENDBASE */
2749         val = (page_to_phys(pend_page) |
2750                GICR_PENDBASER_InnerShareable |
2751                GICR_PENDBASER_RaWaWb);
2752
2753         gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2754         tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2755
2756         if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
2757                 /*
2758                  * The HW reports non-shareable, we must remove the
2759                  * cacheability attributes as well.
2760                  */
2761                 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
2762                          GICR_PENDBASER_CACHEABILITY_MASK);
2763                 val |= GICR_PENDBASER_nC;
2764                 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2765         }
2766
2767         /* Enable LPIs */
2768         val = readl_relaxed(rbase + GICR_CTLR);
2769         val |= GICR_CTLR_ENABLE_LPIS;
2770         writel_relaxed(val, rbase + GICR_CTLR);
2771
2772         if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) {
2773                 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2774
2775                 /*
2776                  * It's possible for CPU to receive VLPIs before it is
2777                  * sheduled as a vPE, especially for the first CPU, and the
2778                  * VLPI with INTID larger than 2^(IDbits+1) will be considered
2779                  * as out of range and dropped by GIC.
2780                  * So we initialize IDbits to known value to avoid VLPI drop.
2781                  */
2782                 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2783                 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
2784                         smp_processor_id(), val);
2785                 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2786
2787                 /*
2788                  * Also clear Valid bit of GICR_VPENDBASER, in case some
2789                  * ancient programming gets left in and has possibility of
2790                  * corrupting memory.
2791                  */
2792                 val = its_clear_vpend_valid(vlpi_base, 0, 0);
2793                 WARN_ON(val & GICR_VPENDBASER_Dirty);
2794         }
2795
2796         if (allocate_vpe_l1_table()) {
2797                 /*
2798                  * If the allocation has failed, we're in massive trouble.
2799                  * Disable direct injection, and pray that no VM was
2800                  * already running...
2801                  */
2802                 gic_rdists->has_rvpeid = false;
2803                 gic_rdists->has_vlpis = false;
2804         }
2805
2806         /* Make sure the GIC has seen the above */
2807         dsb(sy);
2808 out:
2809         gic_data_rdist()->lpi_enabled = true;
2810         pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
2811                 smp_processor_id(),
2812                 gic_data_rdist()->pend_page ? "allocated" : "reserved",
2813                 &paddr);
2814 }
2815
2816 static void its_cpu_init_collection(struct its_node *its)
2817 {
2818         int cpu = smp_processor_id();
2819         u64 target;
2820
2821         /* avoid cross node collections and its mapping */
2822         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
2823                 struct device_node *cpu_node;
2824
2825                 cpu_node = of_get_cpu_node(cpu, NULL);
2826                 if (its->numa_node != NUMA_NO_NODE &&
2827                         its->numa_node != of_node_to_nid(cpu_node))
2828                         return;
2829         }
2830
2831         /*
2832          * We now have to bind each collection to its target
2833          * redistributor.
2834          */
2835         if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
2836                 /*
2837                  * This ITS wants the physical address of the
2838                  * redistributor.
2839                  */
2840                 target = gic_data_rdist()->phys_base;
2841         } else {
2842                 /* This ITS wants a linear CPU number. */
2843                 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2844                 target = GICR_TYPER_CPU_NUMBER(target) << 16;
2845         }
2846
2847         /* Perform collection mapping */
2848         its->collections[cpu].target_address = target;
2849         its->collections[cpu].col_id = cpu;
2850
2851         its_send_mapc(its, &its->collections[cpu], 1);
2852         its_send_invall(its, &its->collections[cpu]);
2853 }
2854
2855 static void its_cpu_init_collections(void)
2856 {
2857         struct its_node *its;
2858
2859         raw_spin_lock(&its_lock);
2860
2861         list_for_each_entry(its, &its_nodes, entry)
2862                 its_cpu_init_collection(its);
2863
2864         raw_spin_unlock(&its_lock);
2865 }
2866
2867 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
2868 {
2869         struct its_device *its_dev = NULL, *tmp;
2870         unsigned long flags;
2871
2872         raw_spin_lock_irqsave(&its->lock, flags);
2873
2874         list_for_each_entry(tmp, &its->its_device_list, entry) {
2875                 if (tmp->device_id == dev_id) {
2876                         its_dev = tmp;
2877                         break;
2878                 }
2879         }
2880
2881         raw_spin_unlock_irqrestore(&its->lock, flags);
2882
2883         return its_dev;
2884 }
2885
2886 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
2887 {
2888         int i;
2889
2890         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2891                 if (GITS_BASER_TYPE(its->tables[i].val) == type)
2892                         return &its->tables[i];
2893         }
2894
2895         return NULL;
2896 }
2897
2898 static bool its_alloc_table_entry(struct its_node *its,
2899                                   struct its_baser *baser, u32 id)
2900 {
2901         struct page *page;
2902         u32 esz, idx;
2903         __le64 *table;
2904
2905         /* Don't allow device id that exceeds single, flat table limit */
2906         esz = GITS_BASER_ENTRY_SIZE(baser->val);
2907         if (!(baser->val & GITS_BASER_INDIRECT))
2908                 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
2909
2910         /* Compute 1st level table index & check if that exceeds table limit */
2911         idx = id >> ilog2(baser->psz / esz);
2912         if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
2913                 return false;
2914
2915         table = baser->base;
2916
2917         /* Allocate memory for 2nd level table */
2918         if (!table[idx]) {
2919                 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
2920                                         get_order(baser->psz));
2921                 if (!page)
2922                         return false;
2923
2924                 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2925                 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2926                         gic_flush_dcache_to_poc(page_address(page), baser->psz);
2927
2928                 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2929
2930                 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2931                 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2932                         gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2933
2934                 /* Ensure updated table contents are visible to ITS hardware */
2935                 dsb(sy);
2936         }
2937
2938         return true;
2939 }
2940
2941 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
2942 {
2943         struct its_baser *baser;
2944
2945         baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
2946
2947         /* Don't allow device id that exceeds ITS hardware limit */
2948         if (!baser)
2949                 return (ilog2(dev_id) < device_ids(its));
2950
2951         return its_alloc_table_entry(its, baser, dev_id);
2952 }
2953
2954 static bool its_alloc_vpe_table(u32 vpe_id)
2955 {
2956         struct its_node *its;
2957
2958         /*
2959          * Make sure the L2 tables are allocated on *all* v4 ITSs. We
2960          * could try and only do it on ITSs corresponding to devices
2961          * that have interrupts targeted at this VPE, but the
2962          * complexity becomes crazy (and you have tons of memory
2963          * anyway, right?).
2964          */
2965         list_for_each_entry(its, &its_nodes, entry) {
2966                 struct its_baser *baser;
2967
2968                 if (!is_v4(its))
2969                         continue;
2970
2971                 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
2972                 if (!baser)
2973                         return false;
2974
2975                 if (!its_alloc_table_entry(its, baser, vpe_id))
2976                         return false;
2977         }
2978
2979         return true;
2980 }
2981
2982 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2983                                             int nvecs, bool alloc_lpis)
2984 {
2985         struct its_device *dev;
2986         unsigned long *lpi_map = NULL;
2987         unsigned long flags;
2988         u16 *col_map = NULL;
2989         void *itt;
2990         int lpi_base;
2991         int nr_lpis;
2992         int nr_ites;
2993         int sz;
2994
2995         if (!its_alloc_device_table(its, dev_id))
2996                 return NULL;
2997
2998         if (WARN_ON(!is_power_of_2(nvecs)))
2999                 nvecs = roundup_pow_of_two(nvecs);
3000
3001         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
3002         /*
3003          * Even if the device wants a single LPI, the ITT must be
3004          * sized as a power of two (and you need at least one bit...).
3005          */
3006         nr_ites = max(2, nvecs);
3007         sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
3008         sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
3009         itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
3010         if (alloc_lpis) {
3011                 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
3012                 if (lpi_map)
3013                         col_map = kcalloc(nr_lpis, sizeof(*col_map),
3014                                           GFP_KERNEL);
3015         } else {
3016                 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
3017                 nr_lpis = 0;
3018                 lpi_base = 0;
3019         }
3020
3021         if (!dev || !itt ||  !col_map || (!lpi_map && alloc_lpis)) {
3022                 kfree(dev);
3023                 kfree(itt);
3024                 kfree(lpi_map);
3025                 kfree(col_map);
3026                 return NULL;
3027         }
3028
3029         gic_flush_dcache_to_poc(itt, sz);
3030
3031         dev->its = its;
3032         dev->itt = itt;
3033         dev->nr_ites = nr_ites;
3034         dev->event_map.lpi_map = lpi_map;
3035         dev->event_map.col_map = col_map;
3036         dev->event_map.lpi_base = lpi_base;
3037         dev->event_map.nr_lpis = nr_lpis;
3038         raw_spin_lock_init(&dev->event_map.vlpi_lock);
3039         dev->device_id = dev_id;
3040         INIT_LIST_HEAD(&dev->entry);
3041
3042         raw_spin_lock_irqsave(&its->lock, flags);
3043         list_add(&dev->entry, &its->its_device_list);
3044         raw_spin_unlock_irqrestore(&its->lock, flags);
3045
3046         /* Map device to its ITT */
3047         its_send_mapd(dev, 1);
3048
3049         return dev;
3050 }
3051
3052 static void its_free_device(struct its_device *its_dev)
3053 {
3054         unsigned long flags;
3055
3056         raw_spin_lock_irqsave(&its_dev->its->lock, flags);
3057         list_del(&its_dev->entry);
3058         raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
3059         kfree(its_dev->event_map.col_map);
3060         kfree(its_dev->itt);
3061         kfree(its_dev);
3062 }
3063
3064 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
3065 {
3066         int idx;
3067
3068         /* Find a free LPI region in lpi_map and allocate them. */
3069         idx = bitmap_find_free_region(dev->event_map.lpi_map,
3070                                       dev->event_map.nr_lpis,
3071                                       get_count_order(nvecs));
3072         if (idx < 0)
3073                 return -ENOSPC;
3074
3075         *hwirq = dev->event_map.lpi_base + idx;
3076
3077         return 0;
3078 }
3079
3080 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
3081                            int nvec, msi_alloc_info_t *info)
3082 {
3083         struct its_node *its;
3084         struct its_device *its_dev;
3085         struct msi_domain_info *msi_info;
3086         u32 dev_id;
3087         int err = 0;
3088
3089         /*
3090          * We ignore "dev" entirely, and rely on the dev_id that has
3091          * been passed via the scratchpad. This limits this domain's
3092          * usefulness to upper layers that definitely know that they
3093          * are built on top of the ITS.
3094          */
3095         dev_id = info->scratchpad[0].ul;
3096
3097         msi_info = msi_get_domain_info(domain);
3098         its = msi_info->data;
3099
3100         if (!gic_rdists->has_direct_lpi &&
3101             vpe_proxy.dev &&
3102             vpe_proxy.dev->its == its &&
3103             dev_id == vpe_proxy.dev->device_id) {
3104                 /* Bad luck. Get yourself a better implementation */
3105                 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
3106                           dev_id);
3107                 return -EINVAL;
3108         }
3109
3110         mutex_lock(&its->dev_alloc_lock);
3111         its_dev = its_find_device(its, dev_id);
3112         if (its_dev) {
3113                 /*
3114                  * We already have seen this ID, probably through
3115                  * another alias (PCI bridge of some sort). No need to
3116                  * create the device.
3117                  */
3118                 its_dev->shared = true;
3119                 pr_debug("Reusing ITT for devID %x\n", dev_id);
3120                 goto out;
3121         }
3122
3123         its_dev = its_create_device(its, dev_id, nvec, true);
3124         if (!its_dev) {
3125                 err = -ENOMEM;
3126                 goto out;
3127         }
3128
3129         pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
3130 out:
3131         mutex_unlock(&its->dev_alloc_lock);
3132         info->scratchpad[0].ptr = its_dev;
3133         return err;
3134 }
3135
3136 static struct msi_domain_ops its_msi_domain_ops = {
3137         .msi_prepare    = its_msi_prepare,
3138 };
3139
3140 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
3141                                     unsigned int virq,
3142                                     irq_hw_number_t hwirq)
3143 {
3144         struct irq_fwspec fwspec;
3145
3146         if (irq_domain_get_of_node(domain->parent)) {
3147                 fwspec.fwnode = domain->parent->fwnode;
3148                 fwspec.param_count = 3;
3149                 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
3150                 fwspec.param[1] = hwirq;
3151                 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
3152         } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
3153                 fwspec.fwnode = domain->parent->fwnode;
3154                 fwspec.param_count = 2;
3155                 fwspec.param[0] = hwirq;
3156                 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
3157         } else {
3158                 return -EINVAL;
3159         }
3160
3161         return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
3162 }
3163
3164 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3165                                 unsigned int nr_irqs, void *args)
3166 {
3167         msi_alloc_info_t *info = args;
3168         struct its_device *its_dev = info->scratchpad[0].ptr;
3169         struct its_node *its = its_dev->its;
3170         irq_hw_number_t hwirq;
3171         int err;
3172         int i;
3173
3174         err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
3175         if (err)
3176                 return err;
3177
3178         err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
3179         if (err)
3180                 return err;
3181
3182         for (i = 0; i < nr_irqs; i++) {
3183                 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
3184                 if (err)
3185                         return err;
3186
3187                 irq_domain_set_hwirq_and_chip(domain, virq + i,
3188                                               hwirq + i, &its_irq_chip, its_dev);
3189                 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i)));
3190                 pr_debug("ID:%d pID:%d vID:%d\n",
3191                          (int)(hwirq + i - its_dev->event_map.lpi_base),
3192                          (int)(hwirq + i), virq + i);
3193         }
3194
3195         return 0;
3196 }
3197
3198 static int its_irq_domain_activate(struct irq_domain *domain,
3199                                    struct irq_data *d, bool reserve)
3200 {
3201         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3202         u32 event = its_get_event_id(d);
3203         const struct cpumask *cpu_mask = cpu_online_mask;
3204         int cpu;
3205
3206         /* get the cpu_mask of local node */
3207         if (its_dev->its->numa_node >= 0)
3208                 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
3209
3210         /* Bind the LPI to the first possible CPU */
3211         cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
3212         if (cpu >= nr_cpu_ids) {
3213                 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
3214                         return -EINVAL;
3215
3216                 cpu = cpumask_first(cpu_online_mask);
3217         }
3218
3219         its_dev->event_map.col_map[event] = cpu;
3220         irq_data_update_effective_affinity(d, cpumask_of(cpu));
3221
3222         /* Map the GIC IRQ and event to the device */
3223         its_send_mapti(its_dev, d->hwirq, event);
3224         return 0;
3225 }
3226
3227 static void its_irq_domain_deactivate(struct irq_domain *domain,
3228                                       struct irq_data *d)
3229 {
3230         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3231         u32 event = its_get_event_id(d);
3232
3233         /* Stop the delivery of interrupts */
3234         its_send_discard(its_dev, event);
3235 }
3236
3237 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
3238                                 unsigned int nr_irqs)
3239 {
3240         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
3241         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3242         struct its_node *its = its_dev->its;
3243         int i;
3244
3245         bitmap_release_region(its_dev->event_map.lpi_map,
3246                               its_get_event_id(irq_domain_get_irq_data(domain, virq)),
3247                               get_count_order(nr_irqs));
3248
3249         for (i = 0; i < nr_irqs; i++) {
3250                 struct irq_data *data = irq_domain_get_irq_data(domain,
3251                                                                 virq + i);
3252                 /* Nuke the entry in the domain */
3253                 irq_domain_reset_irq_data(data);
3254         }
3255
3256         mutex_lock(&its->dev_alloc_lock);
3257
3258         /*
3259          * If all interrupts have been freed, start mopping the
3260          * floor. This is conditionned on the device not being shared.
3261          */
3262         if (!its_dev->shared &&
3263             bitmap_empty(its_dev->event_map.lpi_map,
3264                          its_dev->event_map.nr_lpis)) {
3265                 its_lpi_free(its_dev->event_map.lpi_map,
3266                              its_dev->event_map.lpi_base,
3267                              its_dev->event_map.nr_lpis);
3268
3269                 /* Unmap device/itt */
3270                 its_send_mapd(its_dev, 0);
3271                 its_free_device(its_dev);
3272         }
3273
3274         mutex_unlock(&its->dev_alloc_lock);
3275
3276         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3277 }
3278
3279 static const struct irq_domain_ops its_domain_ops = {
3280         .alloc                  = its_irq_domain_alloc,
3281         .free                   = its_irq_domain_free,
3282         .activate               = its_irq_domain_activate,
3283         .deactivate             = its_irq_domain_deactivate,
3284 };
3285
3286 /*
3287  * This is insane.
3288  *
3289  * If a GICv4.0 doesn't implement Direct LPIs (which is extremely
3290  * likely), the only way to perform an invalidate is to use a fake
3291  * device to issue an INV command, implying that the LPI has first
3292  * been mapped to some event on that device. Since this is not exactly
3293  * cheap, we try to keep that mapping around as long as possible, and
3294  * only issue an UNMAP if we're short on available slots.
3295  *
3296  * Broken by design(tm).
3297  *
3298  * GICv4.1, on the other hand, mandates that we're able to invalidate
3299  * by writing to a MMIO register. It doesn't implement the whole of
3300  * DirectLPI, but that's good enough. And most of the time, we don't
3301  * even have to invalidate anything, as the redistributor can be told
3302  * whether to generate a doorbell or not (we thus leave it enabled,
3303  * always).
3304  */
3305 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
3306 {
3307         /* GICv4.1 doesn't use a proxy, so nothing to do here */
3308         if (gic_rdists->has_rvpeid)
3309                 return;
3310
3311         /* Already unmapped? */
3312         if (vpe->vpe_proxy_event == -1)
3313                 return;
3314
3315         its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
3316         vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
3317
3318         /*
3319          * We don't track empty slots at all, so let's move the
3320          * next_victim pointer if we can quickly reuse that slot
3321          * instead of nuking an existing entry. Not clear that this is
3322          * always a win though, and this might just generate a ripple
3323          * effect... Let's just hope VPEs don't migrate too often.
3324          */
3325         if (vpe_proxy.vpes[vpe_proxy.next_victim])
3326                 vpe_proxy.next_victim = vpe->vpe_proxy_event;
3327
3328         vpe->vpe_proxy_event = -1;
3329 }
3330
3331 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
3332 {
3333         /* GICv4.1 doesn't use a proxy, so nothing to do here */
3334         if (gic_rdists->has_rvpeid)
3335                 return;
3336
3337         if (!gic_rdists->has_direct_lpi) {
3338                 unsigned long flags;
3339
3340                 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3341                 its_vpe_db_proxy_unmap_locked(vpe);
3342                 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3343         }
3344 }
3345
3346 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
3347 {
3348         /* GICv4.1 doesn't use a proxy, so nothing to do here */
3349         if (gic_rdists->has_rvpeid)
3350                 return;
3351
3352         /* Already mapped? */
3353         if (vpe->vpe_proxy_event != -1)
3354                 return;
3355
3356         /* This slot was already allocated. Kick the other VPE out. */
3357         if (vpe_proxy.vpes[vpe_proxy.next_victim])
3358                 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
3359
3360         /* Map the new VPE instead */
3361         vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
3362         vpe->vpe_proxy_event = vpe_proxy.next_victim;
3363         vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
3364
3365         vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
3366         its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
3367 }
3368
3369 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
3370 {
3371         unsigned long flags;
3372         struct its_collection *target_col;
3373
3374         /* GICv4.1 doesn't use a proxy, so nothing to do here */
3375         if (gic_rdists->has_rvpeid)
3376                 return;
3377
3378         if (gic_rdists->has_direct_lpi) {
3379                 void __iomem *rdbase;
3380
3381                 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
3382                 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3383                 wait_for_syncr(rdbase);
3384
3385                 return;
3386         }
3387
3388         raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3389
3390         its_vpe_db_proxy_map_locked(vpe);
3391
3392         target_col = &vpe_proxy.dev->its->collections[to];
3393         its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
3394         vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
3395
3396         raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3397 }
3398
3399 static int its_vpe_set_affinity(struct irq_data *d,
3400                                 const struct cpumask *mask_val,
3401                                 bool force)
3402 {
3403         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3404         int from, cpu = cpumask_first(mask_val);
3405
3406         /*
3407          * Changing affinity is mega expensive, so let's be as lazy as
3408          * we can and only do it if we really have to. Also, if mapped
3409          * into the proxy device, we need to move the doorbell
3410          * interrupt to its new location.
3411          */
3412         if (vpe->col_idx == cpu)
3413                 goto out;
3414
3415         from = vpe->col_idx;
3416         vpe->col_idx = cpu;
3417
3418         /*
3419          * GICv4.1 allows us to skip VMOVP if moving to a cpu whose RD
3420          * is sharing its VPE table with the current one.
3421          */
3422         if (gic_data_rdist_cpu(cpu)->vpe_table_mask &&
3423             cpumask_test_cpu(from, gic_data_rdist_cpu(cpu)->vpe_table_mask))
3424                 goto out;
3425
3426         its_send_vmovp(vpe);
3427         its_vpe_db_proxy_move(vpe, from, cpu);
3428
3429 out:
3430         irq_data_update_effective_affinity(d, cpumask_of(cpu));
3431
3432         return IRQ_SET_MASK_OK_DONE;
3433 }
3434
3435 static void its_vpe_schedule(struct its_vpe *vpe)
3436 {
3437         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3438         u64 val;
3439
3440         /* Schedule the VPE */
3441         val  = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
3442                 GENMASK_ULL(51, 12);
3443         val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3444         val |= GICR_VPROPBASER_RaWb;
3445         val |= GICR_VPROPBASER_InnerShareable;
3446         gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3447
3448         val  = virt_to_phys(page_address(vpe->vpt_page)) &
3449                 GENMASK_ULL(51, 16);
3450         val |= GICR_VPENDBASER_RaWaWb;
3451         val |= GICR_VPENDBASER_NonShareable;
3452         /*
3453          * There is no good way of finding out if the pending table is
3454          * empty as we can race against the doorbell interrupt very
3455          * easily. So in the end, vpe->pending_last is only an
3456          * indication that the vcpu has something pending, not one
3457          * that the pending table is empty. A good implementation
3458          * would be able to read its coarse map pretty quickly anyway,
3459          * making this a tolerable issue.
3460          */
3461         val |= GICR_VPENDBASER_PendingLast;
3462         val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
3463         val |= GICR_VPENDBASER_Valid;
3464         gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3465 }
3466
3467 static void its_vpe_deschedule(struct its_vpe *vpe)
3468 {
3469         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3470         u64 val;
3471
3472         val = its_clear_vpend_valid(vlpi_base, 0, 0);
3473
3474         vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
3475         vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
3476 }
3477
3478 static void its_vpe_invall(struct its_vpe *vpe)
3479 {
3480         struct its_node *its;
3481
3482         list_for_each_entry(its, &its_nodes, entry) {
3483                 if (!is_v4(its))
3484                         continue;
3485
3486                 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
3487                         continue;
3488
3489                 /*
3490                  * Sending a VINVALL to a single ITS is enough, as all
3491                  * we need is to reach the redistributors.
3492                  */
3493                 its_send_vinvall(its, vpe);
3494                 return;
3495         }
3496 }
3497
3498 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
3499 {
3500         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3501         struct its_cmd_info *info = vcpu_info;
3502
3503         switch (info->cmd_type) {
3504         case SCHEDULE_VPE:
3505                 its_vpe_schedule(vpe);
3506                 return 0;
3507
3508         case DESCHEDULE_VPE:
3509                 its_vpe_deschedule(vpe);
3510                 return 0;
3511
3512         case INVALL_VPE:
3513                 its_vpe_invall(vpe);
3514                 return 0;
3515
3516         default:
3517                 return -EINVAL;
3518         }
3519 }
3520
3521 static void its_vpe_send_cmd(struct its_vpe *vpe,
3522                              void (*cmd)(struct its_device *, u32))
3523 {
3524         unsigned long flags;
3525
3526         raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3527
3528         its_vpe_db_proxy_map_locked(vpe);
3529         cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
3530
3531         raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3532 }
3533
3534 static void its_vpe_send_inv(struct irq_data *d)
3535 {
3536         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3537
3538         if (gic_rdists->has_direct_lpi) {
3539                 void __iomem *rdbase;
3540
3541                 /* Target the redistributor this VPE is currently known on */
3542                 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3543                 gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR);
3544                 wait_for_syncr(rdbase);
3545         } else {
3546                 its_vpe_send_cmd(vpe, its_send_inv);
3547         }
3548 }
3549
3550 static void its_vpe_mask_irq(struct irq_data *d)
3551 {
3552         /*
3553          * We need to unmask the LPI, which is described by the parent
3554          * irq_data. Instead of calling into the parent (which won't
3555          * exactly do the right thing, let's simply use the
3556          * parent_data pointer. Yes, I'm naughty.
3557          */
3558         lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
3559         its_vpe_send_inv(d);
3560 }
3561
3562 static void its_vpe_unmask_irq(struct irq_data *d)
3563 {
3564         /* Same hack as above... */
3565         lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
3566         its_vpe_send_inv(d);
3567 }
3568
3569 static int its_vpe_set_irqchip_state(struct irq_data *d,
3570                                      enum irqchip_irq_state which,
3571                                      bool state)
3572 {
3573         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3574
3575         if (which != IRQCHIP_STATE_PENDING)
3576                 return -EINVAL;
3577
3578         if (gic_rdists->has_direct_lpi) {
3579                 void __iomem *rdbase;
3580
3581                 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3582                 if (state) {
3583                         gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
3584                 } else {
3585                         gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3586                         wait_for_syncr(rdbase);
3587                 }
3588         } else {
3589                 if (state)
3590                         its_vpe_send_cmd(vpe, its_send_int);
3591                 else
3592                         its_vpe_send_cmd(vpe, its_send_clear);
3593         }
3594
3595         return 0;
3596 }
3597
3598 static struct irq_chip its_vpe_irq_chip = {
3599         .name                   = "GICv4-vpe",
3600         .irq_mask               = its_vpe_mask_irq,
3601         .irq_unmask             = its_vpe_unmask_irq,
3602         .irq_eoi                = irq_chip_eoi_parent,
3603         .irq_set_affinity       = its_vpe_set_affinity,
3604         .irq_set_irqchip_state  = its_vpe_set_irqchip_state,
3605         .irq_set_vcpu_affinity  = its_vpe_set_vcpu_affinity,
3606 };
3607
3608 static struct its_node *find_4_1_its(void)
3609 {
3610         static struct its_node *its = NULL;
3611
3612         if (!its) {
3613                 list_for_each_entry(its, &its_nodes, entry) {
3614                         if (is_v4_1(its))
3615                                 return its;
3616                 }
3617
3618                 /* Oops? */
3619                 its = NULL;
3620         }
3621
3622         return its;
3623 }
3624
3625 static void its_vpe_4_1_send_inv(struct irq_data *d)
3626 {
3627         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3628         struct its_node *its;
3629
3630         /*
3631          * GICv4.1 wants doorbells to be invalidated using the
3632          * INVDB command in order to be broadcast to all RDs. Send
3633          * it to the first valid ITS, and let the HW do its magic.
3634          */
3635         its = find_4_1_its();
3636         if (its)
3637                 its_send_invdb(its, vpe);
3638 }
3639
3640 static void its_vpe_4_1_mask_irq(struct irq_data *d)
3641 {
3642         lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
3643         its_vpe_4_1_send_inv(d);
3644 }
3645
3646 static void its_vpe_4_1_unmask_irq(struct irq_data *d)
3647 {
3648         lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
3649         its_vpe_4_1_send_inv(d);
3650 }
3651
3652 static void its_vpe_4_1_schedule(struct its_vpe *vpe,
3653                                  struct its_cmd_info *info)
3654 {
3655         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3656         u64 val = 0;
3657
3658         /* Schedule the VPE */
3659         val |= GICR_VPENDBASER_Valid;
3660         val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0;
3661         val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0;
3662         val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);
3663
3664         gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3665 }
3666
3667 static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
3668                                    struct its_cmd_info *info)
3669 {
3670         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3671         u64 val;
3672
3673         if (info->req_db) {
3674                 /*
3675                  * vPE is going to block: make the vPE non-resident with
3676                  * PendingLast clear and DB set. The GIC guarantees that if
3677                  * we read-back PendingLast clear, then a doorbell will be
3678                  * delivered when an interrupt comes.
3679                  */
3680                 val = its_clear_vpend_valid(vlpi_base,
3681                                             GICR_VPENDBASER_PendingLast,
3682                                             GICR_VPENDBASER_4_1_DB);
3683                 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
3684         } else {
3685                 /*
3686                  * We're not blocking, so just make the vPE non-resident
3687                  * with PendingLast set, indicating that we'll be back.
3688                  */
3689                 val = its_clear_vpend_valid(vlpi_base,
3690                                             0,
3691                                             GICR_VPENDBASER_PendingLast);
3692                 vpe->pending_last = true;
3693         }
3694 }
3695
3696 static void its_vpe_4_1_invall(struct its_vpe *vpe)
3697 {
3698         void __iomem *rdbase;
3699         u64 val;
3700
3701         val  = GICR_INVALLR_V;
3702         val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);
3703
3704         /* Target the redistributor this vPE is currently known on */
3705         rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3706         gic_write_lpir(val, rdbase + GICR_INVALLR);
3707 }
3708
3709 static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
3710 {
3711         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3712         struct its_cmd_info *info = vcpu_info;
3713
3714         switch (info->cmd_type) {
3715         case SCHEDULE_VPE:
3716                 its_vpe_4_1_schedule(vpe, info);
3717                 return 0;
3718
3719         case DESCHEDULE_VPE:
3720                 its_vpe_4_1_deschedule(vpe, info);
3721                 return 0;
3722
3723         case INVALL_VPE:
3724                 its_vpe_4_1_invall(vpe);
3725                 return 0;
3726
3727         default:
3728                 return -EINVAL;
3729         }
3730 }
3731
3732 static struct irq_chip its_vpe_4_1_irq_chip = {
3733         .name                   = "GICv4.1-vpe",
3734         .irq_mask               = its_vpe_4_1_mask_irq,
3735         .irq_unmask             = its_vpe_4_1_unmask_irq,
3736         .irq_eoi                = irq_chip_eoi_parent,
3737         .irq_set_affinity       = its_vpe_set_affinity,
3738         .irq_set_vcpu_affinity  = its_vpe_4_1_set_vcpu_affinity,
3739 };
3740
3741 static int its_vpe_id_alloc(void)
3742 {
3743         return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
3744 }
3745
3746 static void its_vpe_id_free(u16 id)
3747 {
3748         ida_simple_remove(&its_vpeid_ida, id);
3749 }
3750
3751 static int its_vpe_init(struct its_vpe *vpe)
3752 {
3753         struct page *vpt_page;
3754         int vpe_id;
3755
3756         /* Allocate vpe_id */
3757         vpe_id = its_vpe_id_alloc();
3758         if (vpe_id < 0)
3759                 return vpe_id;
3760
3761         /* Allocate VPT */
3762         vpt_page = its_allocate_pending_table(GFP_KERNEL);
3763         if (!vpt_page) {
3764                 its_vpe_id_free(vpe_id);
3765                 return -ENOMEM;
3766         }
3767
3768         if (!its_alloc_vpe_table(vpe_id)) {
3769                 its_vpe_id_free(vpe_id);
3770                 its_free_pending_table(vpt_page);
3771                 return -ENOMEM;
3772         }
3773
3774         vpe->vpe_id = vpe_id;
3775         vpe->vpt_page = vpt_page;
3776         if (gic_rdists->has_rvpeid)
3777                 atomic_set(&vpe->vmapp_count, 0);
3778         else
3779                 vpe->vpe_proxy_event = -1;
3780
3781         return 0;
3782 }
3783
3784 static void its_vpe_teardown(struct its_vpe *vpe)
3785 {
3786         its_vpe_db_proxy_unmap(vpe);
3787         its_vpe_id_free(vpe->vpe_id);
3788         its_free_pending_table(vpe->vpt_page);
3789 }
3790
3791 static void its_vpe_irq_domain_free(struct irq_domain *domain,
3792                                     unsigned int virq,
3793                                     unsigned int nr_irqs)
3794 {
3795         struct its_vm *vm = domain->host_data;
3796         int i;
3797
3798         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3799
3800         for (i = 0; i < nr_irqs; i++) {
3801                 struct irq_data *data = irq_domain_get_irq_data(domain,
3802                                                                 virq + i);
3803                 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
3804
3805                 BUG_ON(vm != vpe->its_vm);
3806
3807                 clear_bit(data->hwirq, vm->db_bitmap);
3808                 its_vpe_teardown(vpe);
3809                 irq_domain_reset_irq_data(data);
3810         }
3811
3812         if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
3813                 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
3814                 its_free_prop_table(vm->vprop_page);
3815         }
3816 }
3817
3818 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3819                                     unsigned int nr_irqs, void *args)
3820 {
3821         struct irq_chip *irqchip = &its_vpe_irq_chip;
3822         struct its_vm *vm = args;
3823         unsigned long *bitmap;
3824         struct page *vprop_page;
3825         int base, nr_ids, i, err = 0;
3826
3827         BUG_ON(!vm);
3828
3829         bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
3830         if (!bitmap)
3831                 return -ENOMEM;
3832
3833         if (nr_ids < nr_irqs) {
3834                 its_lpi_free(bitmap, base, nr_ids);
3835                 return -ENOMEM;
3836         }
3837
3838         vprop_page = its_allocate_prop_table(GFP_KERNEL);
3839         if (!vprop_page) {
3840                 its_lpi_free(bitmap, base, nr_ids);
3841                 return -ENOMEM;
3842         }
3843
3844         vm->db_bitmap = bitmap;
3845         vm->db_lpi_base = base;
3846         vm->nr_db_lpis = nr_ids;
3847         vm->vprop_page = vprop_page;
3848
3849         if (gic_rdists->has_rvpeid)
3850                 irqchip = &its_vpe_4_1_irq_chip;
3851
3852         for (i = 0; i < nr_irqs; i++) {
3853                 vm->vpes[i]->vpe_db_lpi = base + i;
3854                 err = its_vpe_init(vm->vpes[i]);
3855                 if (err)
3856                         break;
3857                 err = its_irq_gic_domain_alloc(domain, virq + i,
3858                                                vm->vpes[i]->vpe_db_lpi);
3859                 if (err)
3860                         break;
3861                 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
3862                                               irqchip, vm->vpes[i]);
3863                 set_bit(i, bitmap);
3864         }
3865
3866         if (err) {
3867                 if (i > 0)
3868                         its_vpe_irq_domain_free(domain, virq, i - 1);
3869
3870                 its_lpi_free(bitmap, base, nr_ids);
3871                 its_free_prop_table(vprop_page);
3872         }
3873
3874         return err;
3875 }
3876
3877 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
3878                                        struct irq_data *d, bool reserve)
3879 {
3880         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3881         struct its_node *its;
3882
3883         /* If we use the list map, we issue VMAPP on demand... */
3884         if (its_list_map)
3885                 return 0;
3886
3887         /* Map the VPE to the first possible CPU */
3888         vpe->col_idx = cpumask_first(cpu_online_mask);
3889
3890         list_for_each_entry(its, &its_nodes, entry) {
3891                 if (!is_v4(its))
3892                         continue;
3893
3894                 its_send_vmapp(its, vpe, true);
3895                 its_send_vinvall(its, vpe);
3896         }
3897
3898         irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
3899
3900         return 0;
3901 }
3902
3903 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
3904                                           struct irq_data *d)
3905 {
3906         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3907         struct its_node *its;
3908
3909         /*
3910          * If we use the list map, we unmap the VPE once no VLPIs are
3911          * associated with the VM.
3912          */
3913         if (its_list_map)
3914                 return;
3915
3916         list_for_each_entry(its, &its_nodes, entry) {
3917                 if (!is_v4(its))
3918                         continue;
3919
3920                 its_send_vmapp(its, vpe, false);
3921         }
3922 }
3923
3924 static const struct irq_domain_ops its_vpe_domain_ops = {
3925         .alloc                  = its_vpe_irq_domain_alloc,
3926         .free                   = its_vpe_irq_domain_free,
3927         .activate               = its_vpe_irq_domain_activate,
3928         .deactivate             = its_vpe_irq_domain_deactivate,
3929 };
3930
3931 static int its_force_quiescent(void __iomem *base)
3932 {
3933         u32 count = 1000000;    /* 1s */
3934         u32 val;
3935
3936         val = readl_relaxed(base + GITS_CTLR);
3937         /*
3938          * GIC architecture specification requires the ITS to be both
3939          * disabled and quiescent for writes to GITS_BASER<n> or
3940          * GITS_CBASER to not have UNPREDICTABLE results.
3941          */
3942         if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
3943                 return 0;
3944
3945         /* Disable the generation of all interrupts to this ITS */
3946         val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
3947         writel_relaxed(val, base + GITS_CTLR);
3948
3949         /* Poll GITS_CTLR and wait until ITS becomes quiescent */
3950         while (1) {
3951                 val = readl_relaxed(base + GITS_CTLR);
3952                 if (val & GITS_CTLR_QUIESCENT)
3953                         return 0;
3954
3955                 count--;
3956                 if (!count)
3957                         return -EBUSY;
3958
3959                 cpu_relax();
3960                 udelay(1);
3961         }
3962 }
3963
3964 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
3965 {
3966         struct its_node *its = data;
3967
3968         /* erratum 22375: only alloc 8MB table size (20 bits) */
3969         its->typer &= ~GITS_TYPER_DEVBITS;
3970         its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1);
3971         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
3972
3973         return true;
3974 }
3975
3976 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
3977 {
3978         struct its_node *its = data;
3979
3980         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
3981
3982         return true;
3983 }
3984
3985 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
3986 {
3987         struct its_node *its = data;
3988
3989         /* On QDF2400, the size of the ITE is 16Bytes */
3990         its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE;
3991         its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1);
3992
3993         return true;
3994 }
3995
3996 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
3997 {
3998         struct its_node *its = its_dev->its;
3999
4000         /*
4001          * The Socionext Synquacer SoC has a so-called 'pre-ITS',
4002          * which maps 32-bit writes targeted at a separate window of
4003          * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
4004          * with device ID taken from bits [device_id_bits + 1:2] of
4005          * the window offset.
4006          */
4007         return its->pre_its_base + (its_dev->device_id << 2);
4008 }
4009
4010 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
4011 {
4012         struct its_node *its = data;
4013         u32 pre_its_window[2];
4014         u32 ids;
4015
4016         if (!fwnode_property_read_u32_array(its->fwnode_handle,
4017                                            "socionext,synquacer-pre-its",
4018                                            pre_its_window,
4019                                            ARRAY_SIZE(pre_its_window))) {
4020
4021                 its->pre_its_base = pre_its_window[0];
4022                 its->get_msi_base = its_irq_get_msi_base_pre_its;
4023
4024                 ids = ilog2(pre_its_window[1]) - 2;
4025                 if (device_ids(its) > ids) {
4026                         its->typer &= ~GITS_TYPER_DEVBITS;
4027                         its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1);
4028                 }
4029
4030                 /* the pre-ITS breaks isolation, so disable MSI remapping */
4031                 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
4032                 return true;
4033         }
4034         return false;
4035 }
4036
4037 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
4038 {
4039         struct its_node *its = data;
4040
4041         /*
4042          * Hip07 insists on using the wrong address for the VLPI
4043          * page. Trick it into doing the right thing...
4044          */
4045         its->vlpi_redist_offset = SZ_128K;
4046         return true;
4047 }
4048
4049 static const struct gic_quirk its_quirks[] = {
4050 #ifdef CONFIG_CAVIUM_ERRATUM_22375
4051         {
4052                 .desc   = "ITS: Cavium errata 22375, 24313",
4053                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
4054                 .mask   = 0xffff0fff,
4055                 .init   = its_enable_quirk_cavium_22375,
4056         },
4057 #endif
4058 #ifdef CONFIG_CAVIUM_ERRATUM_23144
4059         {
4060                 .desc   = "ITS: Cavium erratum 23144",
4061                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
4062                 .mask   = 0xffff0fff,
4063                 .init   = its_enable_quirk_cavium_23144,
4064         },
4065 #endif
4066 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
4067         {
4068                 .desc   = "ITS: QDF2400 erratum 0065",
4069                 .iidr   = 0x00001070, /* QDF2400 ITS rev 1.x */
4070                 .mask   = 0xffffffff,
4071                 .init   = its_enable_quirk_qdf2400_e0065,
4072         },
4073 #endif
4074 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
4075         {
4076                 /*
4077                  * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4078                  * implementation, but with a 'pre-ITS' added that requires
4079                  * special handling in software.
4080                  */
4081                 .desc   = "ITS: Socionext Synquacer pre-ITS",
4082                 .iidr   = 0x0001143b,
4083                 .mask   = 0xffffffff,
4084                 .init   = its_enable_quirk_socionext_synquacer,
4085         },
4086 #endif
4087 #ifdef CONFIG_HISILICON_ERRATUM_161600802
4088         {
4089                 .desc   = "ITS: Hip07 erratum 161600802",
4090                 .iidr   = 0x00000004,
4091                 .mask   = 0xffffffff,
4092                 .init   = its_enable_quirk_hip07_161600802,
4093         },
4094 #endif
4095         {
4096         }
4097 };
4098
4099 static void its_enable_quirks(struct its_node *its)
4100 {
4101         u32 iidr = readl_relaxed(its->base + GITS_IIDR);
4102
4103         gic_enable_quirks(iidr, its_quirks, its);
4104 }
4105
4106 static int its_save_disable(void)
4107 {
4108         struct its_node *its;
4109         int err = 0;
4110
4111         raw_spin_lock(&its_lock);
4112         list_for_each_entry(its, &its_nodes, entry) {
4113                 void __iomem *base;
4114
4115                 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
4116                         continue;
4117
4118                 base = its->base;
4119                 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
4120                 err = its_force_quiescent(base);
4121                 if (err) {
4122                         pr_err("ITS@%pa: failed to quiesce: %d\n",
4123                                &its->phys_base, err);
4124                         writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4125                         goto err;
4126                 }
4127
4128                 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
4129         }
4130
4131 err:
4132         if (err) {
4133                 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
4134                         void __iomem *base;
4135
4136                         if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
4137                                 continue;
4138
4139                         base = its->base;
4140                         writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4141                 }
4142         }
4143         raw_spin_unlock(&its_lock);
4144
4145         return err;
4146 }
4147
4148 static void its_restore_enable(void)
4149 {
4150         struct its_node *its;
4151         int ret;
4152
4153         raw_spin_lock(&its_lock);
4154         list_for_each_entry(its, &its_nodes, entry) {
4155                 void __iomem *base;
4156                 int i;
4157
4158                 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
4159                         continue;
4160
4161                 base = its->base;
4162
4163                 /*
4164                  * Make sure that the ITS is disabled. If it fails to quiesce,
4165                  * don't restore it since writing to CBASER or BASER<n>
4166                  * registers is undefined according to the GIC v3 ITS
4167                  * Specification.
4168                  */
4169                 ret = its_force_quiescent(base);
4170                 if (ret) {
4171                         pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
4172                                &its->phys_base, ret);
4173                         continue;
4174                 }
4175
4176                 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
4177
4178                 /*
4179                  * Writing CBASER resets CREADR to 0, so make CWRITER and
4180                  * cmd_write line up with it.
4181                  */
4182                 its->cmd_write = its->cmd_base;
4183                 gits_write_cwriter(0, base + GITS_CWRITER);
4184
4185                 /* Restore GITS_BASER from the value cache. */
4186                 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
4187                         struct its_baser *baser = &its->tables[i];
4188
4189                         if (!(baser->val & GITS_BASER_VALID))
4190                                 continue;
4191
4192                         its_write_baser(its, baser, baser->val);
4193                 }
4194                 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4195
4196                 /*
4197                  * Reinit the collection if it's stored in the ITS. This is
4198                  * indicated by the col_id being less than the HCC field.
4199                  * CID < HCC as specified in the GIC v3 Documentation.
4200                  */
4201                 if (its->collections[smp_processor_id()].col_id <
4202                     GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
4203                         its_cpu_init_collection(its);
4204         }
4205         raw_spin_unlock(&its_lock);
4206 }
4207
4208 static struct syscore_ops its_syscore_ops = {
4209         .suspend = its_save_disable,
4210         .resume = its_restore_enable,
4211 };
4212
4213 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
4214 {
4215         struct irq_domain *inner_domain;
4216         struct msi_domain_info *info;
4217
4218         info = kzalloc(sizeof(*info), GFP_KERNEL);
4219         if (!info)
4220                 return -ENOMEM;
4221
4222         inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
4223         if (!inner_domain) {
4224                 kfree(info);
4225                 return -ENOMEM;
4226         }
4227
4228         inner_domain->parent = its_parent;
4229         irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
4230         inner_domain->flags |= its->msi_domain_flags;
4231         info->ops = &its_msi_domain_ops;
4232         info->data = its;
4233         inner_domain->host_data = info;
4234
4235         return 0;
4236 }
4237
4238 static int its_init_vpe_domain(void)
4239 {
4240         struct its_node *its;
4241         u32 devid;
4242         int entries;
4243
4244         if (gic_rdists->has_direct_lpi) {
4245                 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
4246                 return 0;
4247         }
4248
4249         /* Any ITS will do, even if not v4 */
4250         its = list_first_entry(&its_nodes, struct its_node, entry);
4251
4252         entries = roundup_pow_of_two(nr_cpu_ids);
4253         vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
4254                                  GFP_KERNEL);
4255         if (!vpe_proxy.vpes) {
4256                 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
4257                 return -ENOMEM;
4258         }
4259
4260         /* Use the last possible DevID */
4261         devid = GENMASK(device_ids(its) - 1, 0);
4262         vpe_proxy.dev = its_create_device(its, devid, entries, false);
4263         if (!vpe_proxy.dev) {
4264                 kfree(vpe_proxy.vpes);
4265                 pr_err("ITS: Can't allocate GICv4 proxy device\n");
4266                 return -ENOMEM;
4267         }
4268
4269         BUG_ON(entries > vpe_proxy.dev->nr_ites);
4270
4271         raw_spin_lock_init(&vpe_proxy.lock);
4272         vpe_proxy.next_victim = 0;
4273         pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
4274                 devid, vpe_proxy.dev->nr_ites);
4275
4276         return 0;
4277 }
4278
4279 static int __init its_compute_its_list_map(struct resource *res,
4280                                            void __iomem *its_base)
4281 {
4282         int its_number;
4283         u32 ctlr;
4284
4285         /*
4286          * This is assumed to be done early enough that we're
4287          * guaranteed to be single-threaded, hence no
4288          * locking. Should this change, we should address
4289          * this.
4290          */
4291         its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
4292         if (its_number >= GICv4_ITS_LIST_MAX) {
4293                 pr_err("ITS@%pa: No ITSList entry available!\n",
4294                        &res->start);
4295                 return -EINVAL;
4296         }
4297
4298         ctlr = readl_relaxed(its_base + GITS_CTLR);
4299         ctlr &= ~GITS_CTLR_ITS_NUMBER;
4300         ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
4301         writel_relaxed(ctlr, its_base + GITS_CTLR);
4302         ctlr = readl_relaxed(its_base + GITS_CTLR);
4303         if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
4304                 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
4305                 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
4306         }
4307
4308         if (test_and_set_bit(its_number, &its_list_map)) {
4309                 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
4310                        &res->start, its_number);
4311                 return -EINVAL;
4312         }
4313
4314         return its_number;
4315 }
4316
4317 static int __init its_probe_one(struct resource *res,
4318                                 struct fwnode_handle *handle, int numa_node)
4319 {
4320         struct its_node *its;
4321         void __iomem *its_base;
4322         u32 val, ctlr;
4323         u64 baser, tmp, typer;
4324         struct page *page;
4325         int err;
4326
4327         its_base = ioremap(res->start, resource_size(res));
4328         if (!its_base) {
4329                 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
4330                 return -ENOMEM;
4331         }
4332
4333         val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
4334         if (val != 0x30 && val != 0x40) {
4335                 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
4336                 err = -ENODEV;
4337                 goto out_unmap;
4338         }
4339
4340         err = its_force_quiescent(its_base);
4341         if (err) {
4342                 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
4343                 goto out_unmap;
4344         }
4345
4346         pr_info("ITS %pR\n", res);
4347
4348         its = kzalloc(sizeof(*its), GFP_KERNEL);
4349         if (!its) {
4350                 err = -ENOMEM;
4351                 goto out_unmap;
4352         }
4353
4354         raw_spin_lock_init(&its->lock);
4355         mutex_init(&its->dev_alloc_lock);
4356         INIT_LIST_HEAD(&its->entry);
4357         INIT_LIST_HEAD(&its->its_device_list);
4358         typer = gic_read_typer(its_base + GITS_TYPER);
4359         its->typer = typer;
4360         its->base = its_base;
4361         its->phys_base = res->start;
4362         if (is_v4(its)) {
4363                 if (!(typer & GITS_TYPER_VMOVP)) {
4364                         err = its_compute_its_list_map(res, its_base);
4365                         if (err < 0)
4366                                 goto out_free_its;
4367
4368                         its->list_nr = err;
4369
4370                         pr_info("ITS@%pa: Using ITS number %d\n",
4371                                 &res->start, err);
4372                 } else {
4373                         pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
4374                 }
4375
4376                 if (is_v4_1(its)) {
4377                         u32 svpet = FIELD_GET(GITS_TYPER_SVPET, typer);
4378                         its->mpidr = readl_relaxed(its_base + GITS_MPIDR);
4379
4380                         pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n",
4381                                 &res->start, its->mpidr, svpet);
4382                 }
4383         }
4384
4385         its->numa_node = numa_node;
4386
4387         page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
4388                                 get_order(ITS_CMD_QUEUE_SZ));
4389         if (!page) {
4390                 err = -ENOMEM;
4391                 goto out_free_its;
4392         }
4393         its->cmd_base = (void *)page_address(page);
4394         its->cmd_write = its->cmd_base;
4395         its->fwnode_handle = handle;
4396         its->get_msi_base = its_irq_get_msi_base;
4397         its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
4398
4399         its_enable_quirks(its);
4400
4401         err = its_alloc_tables(its);
4402         if (err)
4403                 goto out_free_cmd;
4404
4405         err = its_alloc_collections(its);
4406         if (err)
4407                 goto out_free_tables;
4408
4409         baser = (virt_to_phys(its->cmd_base)    |
4410                  GITS_CBASER_RaWaWb             |
4411                  GITS_CBASER_InnerShareable     |
4412                  (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
4413                  GITS_CBASER_VALID);
4414
4415         gits_write_cbaser(baser, its->base + GITS_CBASER);
4416         tmp = gits_read_cbaser(its->base + GITS_CBASER);
4417
4418         if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
4419                 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
4420                         /*
4421                          * The HW reports non-shareable, we must
4422                          * remove the cacheability attributes as
4423                          * well.
4424                          */
4425                         baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
4426                                    GITS_CBASER_CACHEABILITY_MASK);
4427                         baser |= GITS_CBASER_nC;
4428                         gits_write_cbaser(baser, its->base + GITS_CBASER);
4429                 }
4430                 pr_info("ITS: using cache flushing for cmd queue\n");
4431                 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
4432         }
4433
4434         gits_write_cwriter(0, its->base + GITS_CWRITER);
4435         ctlr = readl_relaxed(its->base + GITS_CTLR);
4436         ctlr |= GITS_CTLR_ENABLE;
4437         if (is_v4(its))
4438                 ctlr |= GITS_CTLR_ImDe;
4439         writel_relaxed(ctlr, its->base + GITS_CTLR);
4440
4441         if (GITS_TYPER_HCC(typer))
4442                 its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE;
4443
4444         err = its_init_domain(handle, its);
4445         if (err)
4446                 goto out_free_tables;
4447
4448         raw_spin_lock(&its_lock);
4449         list_add(&its->entry, &its_nodes);
4450         raw_spin_unlock(&its_lock);
4451
4452         return 0;
4453
4454 out_free_tables:
4455         its_free_tables(its);
4456 out_free_cmd:
4457         free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
4458 out_free_its:
4459         kfree(its);
4460 out_unmap:
4461         iounmap(its_base);
4462         pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
4463         return err;
4464 }
4465
4466 static bool gic_rdists_supports_plpis(void)
4467 {
4468         return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
4469 }
4470
4471 static int redist_disable_lpis(void)
4472 {
4473         void __iomem *rbase = gic_data_rdist_rd_base();
4474         u64 timeout = USEC_PER_SEC;
4475         u64 val;
4476
4477         if (!gic_rdists_supports_plpis()) {
4478                 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
4479                 return -ENXIO;
4480         }
4481
4482         val = readl_relaxed(rbase + GICR_CTLR);
4483         if (!(val & GICR_CTLR_ENABLE_LPIS))
4484                 return 0;
4485
4486         /*
4487          * If coming via a CPU hotplug event, we don't need to disable
4488          * LPIs before trying to re-enable them. They are already
4489          * configured and all is well in the world.
4490          *
4491          * If running with preallocated tables, there is nothing to do.
4492          */
4493         if (gic_data_rdist()->lpi_enabled ||
4494             (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
4495                 return 0;
4496
4497         /*
4498          * From that point on, we only try to do some damage control.
4499          */
4500         pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
4501                 smp_processor_id());
4502         add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
4503
4504         /* Disable LPIs */
4505         val &= ~GICR_CTLR_ENABLE_LPIS;
4506         writel_relaxed(val, rbase + GICR_CTLR);
4507
4508         /* Make sure any change to GICR_CTLR is observable by the GIC */
4509         dsb(sy);
4510
4511         /*
4512          * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
4513          * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
4514          * Error out if we time out waiting for RWP to clear.
4515          */
4516         while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
4517                 if (!timeout) {
4518                         pr_err("CPU%d: Timeout while disabling LPIs\n",
4519                                smp_processor_id());
4520                         return -ETIMEDOUT;
4521                 }
4522                 udelay(1);
4523                 timeout--;
4524         }
4525
4526         /*
4527          * After it has been written to 1, it is IMPLEMENTATION
4528          * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
4529          * cleared to 0. Error out if clearing the bit failed.
4530          */
4531         if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
4532                 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
4533                 return -EBUSY;
4534         }
4535
4536         return 0;
4537 }
4538
4539 int its_cpu_init(void)
4540 {
4541         if (!list_empty(&its_nodes)) {
4542                 int ret;
4543
4544                 ret = redist_disable_lpis();
4545                 if (ret)
4546                         return ret;
4547
4548                 its_cpu_init_lpis();
4549                 its_cpu_init_collections();
4550         }
4551
4552         return 0;
4553 }
4554
4555 static const struct of_device_id its_device_id[] = {
4556         {       .compatible     = "arm,gic-v3-its",     },
4557         {},
4558 };
4559
4560 static int __init its_of_probe(struct device_node *node)
4561 {
4562         struct device_node *np;
4563         struct resource res;
4564
4565         for (np = of_find_matching_node(node, its_device_id); np;
4566              np = of_find_matching_node(np, its_device_id)) {
4567                 if (!of_device_is_available(np))
4568                         continue;
4569                 if (!of_property_read_bool(np, "msi-controller")) {
4570                         pr_warn("%pOF: no msi-controller property, ITS ignored\n",
4571                                 np);
4572                         continue;
4573                 }
4574
4575                 if (of_address_to_resource(np, 0, &res)) {
4576                         pr_warn("%pOF: no regs?\n", np);
4577                         continue;
4578                 }
4579
4580                 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
4581         }
4582         return 0;
4583 }
4584
4585 #ifdef CONFIG_ACPI
4586
4587 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
4588
4589 #ifdef CONFIG_ACPI_NUMA
4590 struct its_srat_map {
4591         /* numa node id */
4592         u32     numa_node;
4593         /* GIC ITS ID */
4594         u32     its_id;
4595 };
4596
4597 static struct its_srat_map *its_srat_maps __initdata;
4598 static int its_in_srat __initdata;
4599
4600 static int __init acpi_get_its_numa_node(u32 its_id)
4601 {
4602         int i;
4603
4604         for (i = 0; i < its_in_srat; i++) {
4605                 if (its_id == its_srat_maps[i].its_id)
4606                         return its_srat_maps[i].numa_node;
4607         }
4608         return NUMA_NO_NODE;
4609 }
4610
4611 static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
4612                                           const unsigned long end)
4613 {
4614         return 0;
4615 }
4616
4617 static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
4618                          const unsigned long end)
4619 {
4620         int node;
4621         struct acpi_srat_gic_its_affinity *its_affinity;
4622
4623         its_affinity = (struct acpi_srat_gic_its_affinity *)header;
4624         if (!its_affinity)
4625                 return -EINVAL;
4626
4627         if (its_affinity->header.length < sizeof(*its_affinity)) {
4628                 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
4629                         its_affinity->header.length);
4630                 return -EINVAL;
4631         }
4632
4633         node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
4634
4635         if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
4636                 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
4637                 return 0;
4638         }
4639
4640         its_srat_maps[its_in_srat].numa_node = node;
4641         its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
4642         its_in_srat++;
4643         pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
4644                 its_affinity->proximity_domain, its_affinity->its_id, node);
4645
4646         return 0;
4647 }
4648
4649 static void __init acpi_table_parse_srat_its(void)
4650 {
4651         int count;
4652
4653         count = acpi_table_parse_entries(ACPI_SIG_SRAT,
4654                         sizeof(struct acpi_table_srat),
4655                         ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
4656                         gic_acpi_match_srat_its, 0);
4657         if (count <= 0)
4658                 return;
4659
4660         its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
4661                                       GFP_KERNEL);
4662         if (!its_srat_maps) {
4663                 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
4664                 return;
4665         }
4666
4667         acpi_table_parse_entries(ACPI_SIG_SRAT,
4668                         sizeof(struct acpi_table_srat),
4669                         ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
4670                         gic_acpi_parse_srat_its, 0);
4671 }
4672
4673 /* free the its_srat_maps after ITS probing */
4674 static void __init acpi_its_srat_maps_free(void)
4675 {
4676         kfree(its_srat_maps);
4677 }
4678 #else
4679 static void __init acpi_table_parse_srat_its(void)      { }
4680 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
4681 static void __init acpi_its_srat_maps_free(void) { }
4682 #endif
4683
4684 static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
4685                                           const unsigned long end)
4686 {
4687         struct acpi_madt_generic_translator *its_entry;
4688         struct fwnode_handle *dom_handle;
4689         struct resource res;
4690         int err;
4691
4692         its_entry = (struct acpi_madt_generic_translator *)header;
4693         memset(&res, 0, sizeof(res));
4694         res.start = its_entry->base_address;
4695         res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
4696         res.flags = IORESOURCE_MEM;
4697
4698         dom_handle = irq_domain_alloc_fwnode(&res.start);
4699         if (!dom_handle) {
4700                 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
4701                        &res.start);
4702                 return -ENOMEM;
4703         }
4704
4705         err = iort_register_domain_token(its_entry->translation_id, res.start,
4706                                          dom_handle);
4707         if (err) {
4708                 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
4709                        &res.start, its_entry->translation_id);
4710                 goto dom_err;
4711         }
4712
4713         err = its_probe_one(&res, dom_handle,
4714                         acpi_get_its_numa_node(its_entry->translation_id));
4715         if (!err)
4716                 return 0;
4717
4718         iort_deregister_domain_token(its_entry->translation_id);
4719 dom_err:
4720         irq_domain_free_fwnode(dom_handle);
4721         return err;
4722 }
4723
4724 static void __init its_acpi_probe(void)
4725 {
4726         acpi_table_parse_srat_its();
4727         acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
4728                               gic_acpi_parse_madt_its, 0);
4729         acpi_its_srat_maps_free();
4730 }
4731 #else
4732 static void __init its_acpi_probe(void) { }
4733 #endif
4734
4735 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
4736                     struct irq_domain *parent_domain)
4737 {
4738         struct device_node *of_node;
4739         struct its_node *its;
4740         bool has_v4 = false;
4741         int err;
4742
4743         gic_rdists = rdists;
4744
4745         its_parent = parent_domain;
4746         of_node = to_of_node(handle);
4747         if (of_node)
4748                 its_of_probe(of_node);
4749         else
4750                 its_acpi_probe();
4751
4752         if (list_empty(&its_nodes)) {
4753                 pr_warn("ITS: No ITS available, not enabling LPIs\n");
4754                 return -ENXIO;
4755         }
4756
4757         err = allocate_lpi_tables();
4758         if (err)
4759                 return err;
4760
4761         list_for_each_entry(its, &its_nodes, entry)
4762                 has_v4 |= is_v4(its);
4763
4764         if (has_v4 & rdists->has_vlpis) {
4765                 if (its_init_vpe_domain() ||
4766                     its_init_v4(parent_domain, &its_vpe_domain_ops)) {
4767                         rdists->has_vlpis = false;
4768                         pr_err("ITS: Disabling GICv4 support\n");
4769                 }
4770         }
4771
4772         register_syscore_ops(&its_syscore_ops);
4773
4774         return 0;
4775 }