drivers/irqchip/irq-mips-gic.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   8  */
   9 #include <linux/bitmap.h>
  10 #include <linux/clocksource.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14 #include <linux/irqchip/mips-gic.h>
  15 #include <linux/sched.h>
  16 #include <linux/smp.h>
  17
  18 #include <asm/setup.h>
  19 #include <asm/traps.h>
  20
  21 unsigned int gic_present;
  22
  23 struct gic_pcpu_mask {
  24         DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
  25 };
  26
  27 static void __iomem *gic_base;
  28 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
  29 static DEFINE_SPINLOCK(gic_lock);
  30 static struct irq_domain *gic_irq_domain;
  31 static int gic_shared_intrs;
  32 static int gic_vpes;
  33 static unsigned int gic_cpu_pin;
  34 static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
  35
  36 static void __gic_irq_dispatch(void);
  37
  38 static inline unsigned int gic_read(unsigned int reg)
  39 {
  40         return __raw_readl(gic_base + reg);
  41 }
  42
  43 static inline void gic_write(unsigned int reg, unsigned int val)
  44 {
  45         __raw_writel(val, gic_base + reg);
  46 }
  47
  48 static inline void gic_update_bits(unsigned int reg, unsigned int mask,
  49                                    unsigned int val)
  50 {
  51         unsigned int regval;
  52
  53         regval = gic_read(reg);
  54         regval &= ~mask;
  55         regval |= val;
  56         gic_write(reg, regval);
  57 }
  58
  59 static inline void gic_reset_mask(unsigned int intr)
  60 {
  61         gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr),
  62                   1 << GIC_INTR_BIT(intr));
  63 }
  64
  65 static inline void gic_set_mask(unsigned int intr)
  66 {
  67         gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr),
  68                   1 << GIC_INTR_BIT(intr));
  69 }
  70
  71 static inline void gic_set_polarity(unsigned int intr, unsigned int pol)
  72 {
  73         gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) +
  74                         GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr),
  75                         pol << GIC_INTR_BIT(intr));
  76 }
  77
  78 static inline void gic_set_trigger(unsigned int intr, unsigned int trig)
  79 {
  80         gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
  81                         GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr),
  82                         trig << GIC_INTR_BIT(intr));
  83 }
  84
  85 static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual)
  86 {
  87         gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr),
  88                         1 << GIC_INTR_BIT(intr),
  89                         dual << GIC_INTR_BIT(intr));
  90 }
  91
  92 static inline void gic_map_to_pin(unsigned int intr, unsigned int pin)
  93 {
  94         gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) +
  95                   GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin);
  96 }
  97
  98 static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe)
  99 {
 100         gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) +
 101                   GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe),
 102                   GIC_SH_MAP_TO_VPE_REG_BIT(vpe));
 103 }
 104
 105 #ifdef CONFIG_CLKSRC_MIPS_GIC
 106 cycle_t gic_read_count(void)
 107 {
 108         unsigned int hi, hi2, lo;
 109
 110         do {
 111                 hi = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
 112                 lo = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
 113                 hi2 = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
 114         } while (hi2 != hi);
 115
 116         return (((cycle_t) hi) << 32) + lo;
 117 }
 118
 119 unsigned int gic_get_count_width(void)
 120 {
 121         unsigned int bits, config;
 122
 123         config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
 124         bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>
 125                          GIC_SH_CONFIG_COUNTBITS_SHF);
 126
 127         return bits;
 128 }
 129
 130 void gic_write_compare(cycle_t cnt)
 131 {
 132         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
 133                                 (int)(cnt >> 32));
 134         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
 135                                 (int)(cnt & 0xffffffff));
 136 }
 137
 138 void gic_write_cpu_compare(cycle_t cnt, int cpu)
 139 {
 140         unsigned long flags;
 141
 142         local_irq_save(flags);
 143
 144         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
 145         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
 146                                 (int)(cnt >> 32));
 147         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
 148                                 (int)(cnt & 0xffffffff));
 149
 150         local_irq_restore(flags);
 151 }
 152
 153 cycle_t gic_read_compare(void)
 154 {
 155         unsigned int hi, lo;
 156
 157         hi = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));
 158         lo = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));
 159
 160         return (((cycle_t) hi) << 32) + lo;
 161 }
 162 #endif
 163
 164 static bool gic_local_irq_is_routable(int intr)
 165 {
 166         u32 vpe_ctl;
 167
 168         /* All local interrupts are routable in EIC mode. */
 169         if (cpu_has_veic)
 170                 return true;
 171
 172         vpe_ctl = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
 173         switch (intr) {
 174         case GIC_LOCAL_INT_TIMER:
 175                 return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
 176         case GIC_LOCAL_INT_PERFCTR:
 177                 return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK;
 178         case GIC_LOCAL_INT_FDC:
 179                 return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK;
 180         case GIC_LOCAL_INT_SWINT0:
 181         case GIC_LOCAL_INT_SWINT1:
 182                 return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK;
 183         default:
 184                 return true;
 185         }
 186 }
 187
 188 unsigned int gic_get_timer_pending(void)
 189 {
 190         unsigned int vpe_pending;
 191
 192         vpe_pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
 193         return vpe_pending & GIC_VPE_PEND_TIMER_MSK;
 194 }
 195
 196 static void gic_bind_eic_interrupt(int irq, int set)
 197 {
 198         /* Convert irq vector # to hw int # */
 199         irq -= GIC_PIN_TO_VEC_OFFSET;
 200
 201         /* Set irq to use shadow set */
 202         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) +
 203                   GIC_VPE_EIC_SS(irq), set);
 204 }
 205
 206 void gic_send_ipi(unsigned int intr)
 207 {
 208         gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr));
 209 }
 210
 211 int gic_get_c0_compare_int(void)
 212 {
 213         if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
 214                 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 215         return irq_create_mapping(gic_irq_domain,
 216                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
 217 }
 218
 219 int gic_get_c0_perfcount_int(void)
 220 {
 221         if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
 222                 /* Is the erformance counter shared with the timer? */
 223                 if (cp0_perfcount_irq < 0)
 224                         return -1;
 225                 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 226         }
 227         return irq_create_mapping(gic_irq_domain,
 228                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
 229 }
 230
 231 static unsigned int gic_get_int(void)
 232 {
 233         unsigned int i;
 234         unsigned long *pcpu_mask;
 235         unsigned long pending_reg, intrmask_reg;
 236         DECLARE_BITMAP(pending, GIC_MAX_INTRS);
 237         DECLARE_BITMAP(intrmask, GIC_MAX_INTRS);
 238
 239         /* Get per-cpu bitmaps */
 240         pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
 241
 242         pending_reg = GIC_REG(SHARED, GIC_SH_PEND);
 243         intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK);
 244
 245         for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) {
 246                 pending[i] = gic_read(pending_reg);
 247                 intrmask[i] = gic_read(intrmask_reg);
 248                 pending_reg += 0x4;
 249                 intrmask_reg += 0x4;
 250         }
 251
 252         bitmap_and(pending, pending, intrmask, gic_shared_intrs);
 253         bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
 254
 255         return find_first_bit(pending, gic_shared_intrs);
 256 }
 257
 258 static void gic_mask_irq(struct irq_data *d)
 259 {
 260         gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
 261 }
 262
 263 static void gic_unmask_irq(struct irq_data *d)
 264 {
 265         gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
 266 }
 267
 268 static void gic_ack_irq(struct irq_data *d)
 269 {
 270         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 271
 272         gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq));
 273 }
 274
 275 static int gic_set_type(struct irq_data *d, unsigned int type)
 276 {
 277         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 278         unsigned long flags;
 279         bool is_edge;
 280
 281         spin_lock_irqsave(&gic_lock, flags);
 282         switch (type & IRQ_TYPE_SENSE_MASK) {
 283         case IRQ_TYPE_EDGE_FALLING:
 284                 gic_set_polarity(irq, GIC_POL_NEG);
 285                 gic_set_trigger(irq, GIC_TRIG_EDGE);
 286                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
 287                 is_edge = true;
 288                 break;
 289         case IRQ_TYPE_EDGE_RISING:
 290                 gic_set_polarity(irq, GIC_POL_POS);
 291                 gic_set_trigger(irq, GIC_TRIG_EDGE);
 292                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
 293                 is_edge = true;
 294                 break;
 295         case IRQ_TYPE_EDGE_BOTH:
 296                 /* polarity is irrelevant in this case */
 297                 gic_set_trigger(irq, GIC_TRIG_EDGE);
 298                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE);
 299                 is_edge = true;
 300                 break;
 301         case IRQ_TYPE_LEVEL_LOW:
 302                 gic_set_polarity(irq, GIC_POL_NEG);
 303                 gic_set_trigger(irq, GIC_TRIG_LEVEL);
 304                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
 305                 is_edge = false;
 306                 break;
 307         case IRQ_TYPE_LEVEL_HIGH:
 308         default:
 309                 gic_set_polarity(irq, GIC_POL_POS);
 310                 gic_set_trigger(irq, GIC_TRIG_LEVEL);
 311                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
 312                 is_edge = false;
 313                 break;
 314         }
 315
 316         if (is_edge) {
 317                 __irq_set_chip_handler_name_locked(d->irq,
 318                                                    &gic_edge_irq_controller,
 319                                                    handle_edge_irq, NULL);
 320         } else {
 321                 __irq_set_chip_handler_name_locked(d->irq,
 322                                                    &gic_level_irq_controller,
 323                                                    handle_level_irq, NULL);
 324         }
 325         spin_unlock_irqrestore(&gic_lock, flags);
 326
 327         return 0;
 328 }
 329
 330 #ifdef CONFIG_SMP
 331 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 332                             bool force)
 333 {
 334         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 335         cpumask_t       tmp = CPU_MASK_NONE;
 336         unsigned long   flags;
 337         int             i;
 338
 339         cpumask_and(&tmp, cpumask, cpu_online_mask);
 340         if (cpus_empty(tmp))
 341                 return -EINVAL;
 342
 343         /* Assumption : cpumask refers to a single CPU */
 344         spin_lock_irqsave(&gic_lock, flags);
 345
 346         /* Re-route this IRQ */
 347         gic_map_to_vpe(irq, first_cpu(tmp));
 348
 349         /* Update the pcpu_masks */
 350         for (i = 0; i < NR_CPUS; i++)
 351                 clear_bit(irq, pcpu_masks[i].pcpu_mask);
 352         set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
 353
 354         cpumask_copy(d->affinity, cpumask);
 355         spin_unlock_irqrestore(&gic_lock, flags);
 356
 357         return IRQ_SET_MASK_OK_NOCOPY;
 358 }
 359 #endif
 360
 361 static struct irq_chip gic_level_irq_controller = {
 362         .name                   =       "MIPS GIC",
 363         .irq_mask               =       gic_mask_irq,
 364         .irq_unmask             =       gic_unmask_irq,
 365         .irq_set_type           =       gic_set_type,
 366 #ifdef CONFIG_SMP
 367         .irq_set_affinity       =       gic_set_affinity,
 368 #endif
 369 };
 370
 371 static struct irq_chip gic_edge_irq_controller = {
 372         .name                   =       "MIPS GIC",
 373         .irq_ack                =       gic_ack_irq,
 374         .irq_mask               =       gic_mask_irq,
 375         .irq_unmask             =       gic_unmask_irq,
 376         .irq_set_type           =       gic_set_type,
 377 #ifdef CONFIG_SMP
 378         .irq_set_affinity       =       gic_set_affinity,
 379 #endif
 380 };
 381
 382 static unsigned int gic_get_local_int(void)
 383 {
 384         unsigned long pending, masked;
 385
 386         pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
 387         masked = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_MASK));
 388
 389         bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
 390
 391         return find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
 392 }
 393
 394 static void gic_mask_local_irq(struct irq_data *d)
 395 {
 396         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 397
 398         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
 399 }
 400
 401 static void gic_unmask_local_irq(struct irq_data *d)
 402 {
 403         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 404
 405         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
 406 }
 407
 408 static struct irq_chip gic_local_irq_controller = {
 409         .name                   =       "MIPS GIC Local",
 410         .irq_mask               =       gic_mask_local_irq,
 411         .irq_unmask             =       gic_unmask_local_irq,
 412 };
 413
 414 static void gic_mask_local_irq_all_vpes(struct irq_data *d)
 415 {
 416         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 417         int i;
 418         unsigned long flags;
 419
 420         spin_lock_irqsave(&gic_lock, flags);
 421         for (i = 0; i < gic_vpes; i++) {
 422                 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 423                 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
 424         }
 425         spin_unlock_irqrestore(&gic_lock, flags);
 426 }
 427
 428 static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
 429 {
 430         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 431         int i;
 432         unsigned long flags;
 433
 434         spin_lock_irqsave(&gic_lock, flags);
 435         for (i = 0; i < gic_vpes; i++) {
 436                 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 437                 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
 438         }
 439         spin_unlock_irqrestore(&gic_lock, flags);
 440 }
 441
 442 static struct irq_chip gic_all_vpes_local_irq_controller = {
 443         .name                   =       "MIPS GIC Local",
 444         .irq_mask               =       gic_mask_local_irq_all_vpes,
 445         .irq_unmask             =       gic_unmask_local_irq_all_vpes,
 446 };
 447
 448 static void __gic_irq_dispatch(void)
 449 {
 450         unsigned int intr, virq;
 451
 452         while ((intr = gic_get_local_int()) != GIC_NUM_LOCAL_INTRS) {
 453                 virq = irq_linear_revmap(gic_irq_domain,
 454                                          GIC_LOCAL_TO_HWIRQ(intr));
 455                 do_IRQ(virq);
 456         }
 457
 458         while ((intr = gic_get_int()) != gic_shared_intrs) {
 459                 virq = irq_linear_revmap(gic_irq_domain,
 460                                          GIC_SHARED_TO_HWIRQ(intr));
 461                 do_IRQ(virq);
 462         }
 463 }
 464
 465 static void gic_irq_dispatch(unsigned int irq, struct irq_desc *desc)
 466 {
 467         __gic_irq_dispatch();
 468 }
 469
 470 #ifdef CONFIG_MIPS_GIC_IPI
 471 static int gic_resched_int_base;
 472 static int gic_call_int_base;
 473
 474 unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
 475 {
 476         return gic_resched_int_base + cpu;
 477 }
 478
 479 unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
 480 {
 481         return gic_call_int_base + cpu;
 482 }
 483
 484 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
 485 {
 486         scheduler_ipi();
 487
 488         return IRQ_HANDLED;
 489 }
 490
 491 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
 492 {
 493         smp_call_function_interrupt();
 494
 495         return IRQ_HANDLED;
 496 }
 497
 498 static struct irqaction irq_resched = {
 499         .handler        = ipi_resched_interrupt,
 500         .flags          = IRQF_PERCPU,
 501         .name           = "IPI resched"
 502 };
 503
 504 static struct irqaction irq_call = {
 505         .handler        = ipi_call_interrupt,
 506         .flags          = IRQF_PERCPU,
 507         .name           = "IPI call"
 508 };
 509
 510 static __init void gic_ipi_init_one(unsigned int intr, int cpu,
 511                                     struct irqaction *action)
 512 {
 513         int virq = irq_create_mapping(gic_irq_domain,
 514                                       GIC_SHARED_TO_HWIRQ(intr));
 515         int i;
 516
 517         gic_map_to_vpe(intr, cpu);
 518         for (i = 0; i < NR_CPUS; i++)
 519                 clear_bit(intr, pcpu_masks[i].pcpu_mask);
 520         set_bit(intr, pcpu_masks[cpu].pcpu_mask);
 521
 522         irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
 523
 524         irq_set_handler(virq, handle_percpu_irq);
 525         setup_irq(virq, action);
 526 }
 527
 528 static __init void gic_ipi_init(void)
 529 {
 530         int i;
 531
 532         /* Use last 2 * NR_CPUS interrupts as IPIs */
 533         gic_resched_int_base = gic_shared_intrs - nr_cpu_ids;
 534         gic_call_int_base = gic_resched_int_base - nr_cpu_ids;
 535
 536         for (i = 0; i < nr_cpu_ids; i++) {
 537                 gic_ipi_init_one(gic_call_int_base + i, i, &irq_call);
 538                 gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched);
 539         }
 540 }
 541 #else
 542 static inline void gic_ipi_init(void)
 543 {
 544 }
 545 #endif
 546
 547 static void __init gic_basic_init(void)
 548 {
 549         unsigned int i;
 550
 551         board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 552
 553         /* Setup defaults */
 554         for (i = 0; i < gic_shared_intrs; i++) {
 555                 gic_set_polarity(i, GIC_POL_POS);
 556                 gic_set_trigger(i, GIC_TRIG_LEVEL);
 557                 gic_reset_mask(i);
 558         }
 559
 560         for (i = 0; i < gic_vpes; i++) {
 561                 unsigned int j;
 562
 563                 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 564                 for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
 565                         if (!gic_local_irq_is_routable(j))
 566                                 continue;
 567                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
 568                 }
 569         }
 570 }
 571
 572 static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq,
 573                                     irq_hw_number_t hw)
 574 {
 575         int intr = GIC_HWIRQ_TO_LOCAL(hw);
 576         int ret = 0;
 577         int i;
 578         unsigned long flags;
 579
 580         if (!gic_local_irq_is_routable(intr))
 581                 return -EPERM;
 582
 583         /*
 584          * HACK: These are all really percpu interrupts, but the rest
 585          * of the MIPS kernel code does not use the percpu IRQ API for
 586          * the CP0 timer and performance counter interrupts.
 587          */
 588         if (intr != GIC_LOCAL_INT_TIMER && intr != GIC_LOCAL_INT_PERFCTR) {
 589                 irq_set_chip_and_handler(virq,
 590                                          &gic_local_irq_controller,
 591                                          handle_percpu_devid_irq);
 592                 irq_set_percpu_devid(virq);
 593         } else {
 594                 irq_set_chip_and_handler(virq,
 595                                          &gic_all_vpes_local_irq_controller,
 596                                          handle_percpu_irq);
 597         }
 598
 599         spin_lock_irqsave(&gic_lock, flags);
 600         for (i = 0; i < gic_vpes; i++) {
 601                 u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin;
 602
 603                 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 604
 605                 switch (intr) {
 606                 case GIC_LOCAL_INT_WD:
 607                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
 608                         break;
 609                 case GIC_LOCAL_INT_COMPARE:
 610                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val);
 611                         break;
 612                 case GIC_LOCAL_INT_TIMER:
 613                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val);
 614                         break;
 615                 case GIC_LOCAL_INT_PERFCTR:
 616                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), val);
 617                         break;
 618                 case GIC_LOCAL_INT_SWINT0:
 619                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), val);
 620                         break;
 621                 case GIC_LOCAL_INT_SWINT1:
 622                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), val);
 623                         break;
 624                 case GIC_LOCAL_INT_FDC:
 625                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
 626                         break;
 627                 default:
 628                         pr_err("Invalid local IRQ %d\n", intr);
 629                         ret = -EINVAL;
 630                         break;
 631                 }
 632         }
 633         spin_unlock_irqrestore(&gic_lock, flags);
 634
 635         return ret;
 636 }
 637
 638 static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
 639                                      irq_hw_number_t hw)
 640 {
 641         int intr = GIC_HWIRQ_TO_SHARED(hw);
 642         unsigned long flags;
 643
 644         irq_set_chip_and_handler(virq, &gic_level_irq_controller,
 645                                  handle_level_irq);
 646
 647         spin_lock_irqsave(&gic_lock, flags);
 648         gic_map_to_pin(intr, gic_cpu_pin);
 649         /* Map to VPE 0 by default */
 650         gic_map_to_vpe(intr, 0);
 651         set_bit(intr, pcpu_masks[0].pcpu_mask);
 652         spin_unlock_irqrestore(&gic_lock, flags);
 653
 654         return 0;
 655 }
 656
 657 static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
 658                               irq_hw_number_t hw)
 659 {
 660         if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS)
 661                 return gic_local_irq_domain_map(d, virq, hw);
 662         return gic_shared_irq_domain_map(d, virq, hw);
 663 }
 664
 665 static struct irq_domain_ops gic_irq_domain_ops = {
 666         .map = gic_irq_domain_map,
 667         .xlate = irq_domain_xlate_twocell,
 668 };
 669
 670 void __init gic_init(unsigned long gic_base_addr,
 671                      unsigned long gic_addrspace_size, unsigned int cpu_vec,
 672                      unsigned int irqbase)
 673 {
 674         unsigned int gicconfig;
 675
 676         gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
 677
 678         gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
 679         gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
 680                    GIC_SH_CONFIG_NUMINTRS_SHF;
 681         gic_shared_intrs = ((gic_shared_intrs + 1) * 8);
 682
 683         gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
 684                   GIC_SH_CONFIG_NUMVPES_SHF;
 685         gic_vpes = gic_vpes + 1;
 686
 687         if (cpu_has_veic) {
 688                 /* Always use vector 1 in EIC mode */
 689                 gic_cpu_pin = 0;
 690                 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
 691                                __gic_irq_dispatch);
 692         } else {
 693                 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
 694                 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
 695                                         gic_irq_dispatch);
 696         }
 697
 698         gic_irq_domain = irq_domain_add_simple(NULL, GIC_NUM_LOCAL_INTRS +
 699                                                gic_shared_intrs, irqbase,
 700                                                &gic_irq_domain_ops, NULL);
 701         if (!gic_irq_domain)
 702                 panic("Failed to add GIC IRQ domain");
 703
 704         gic_basic_init();
 705
 706         gic_ipi_init();
 707 }