drivers/media/dvb-frontends/cxd2841er.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * cxd2841er.c
   4  *
   5  * Sony digital demodulator driver for
   6  *      CXD2841ER - DVB-S/S2/T/T2/C/C2
   7  *      CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
   8  *
   9  * Copyright 2012 Sony Corporation
  10  * Copyright (C) 2014 NetUP Inc.
  11  * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
  12  * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
  13   */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/string.h>
  18 #include <linux/slab.h>
  19 #include <linux/bitops.h>
  20 #include <linux/math64.h>
  21 #include <linux/log2.h>
  22 #include <linux/dynamic_debug.h>
  23 #include <linux/kernel.h>
  24
  25 #include <linux/int_log.h>
  26 #include <media/dvb_frontend.h>
  27 #include "cxd2841er.h"
  28 #include "cxd2841er_priv.h"
  29
  30 #define MAX_WRITE_REGSIZE       16
  31 #define LOG2_E_100X 144
  32
  33 #define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24))
  34
  35 /* DVB-C constellation */
  36 enum sony_dvbc_constellation_t {
  37         SONY_DVBC_CONSTELLATION_16QAM,
  38         SONY_DVBC_CONSTELLATION_32QAM,
  39         SONY_DVBC_CONSTELLATION_64QAM,
  40         SONY_DVBC_CONSTELLATION_128QAM,
  41         SONY_DVBC_CONSTELLATION_256QAM
  42 };
  43
  44 enum cxd2841er_state {
  45         STATE_SHUTDOWN = 0,
  46         STATE_SLEEP_S,
  47         STATE_ACTIVE_S,
  48         STATE_SLEEP_TC,
  49         STATE_ACTIVE_TC
  50 };
  51
  52 struct cxd2841er_priv {
  53         struct dvb_frontend             frontend;
  54         struct i2c_adapter              *i2c;
  55         u8                              i2c_addr_slvx;
  56         u8                              i2c_addr_slvt;
  57         const struct cxd2841er_config   *config;
  58         enum cxd2841er_state            state;
  59         u8                              system;
  60         enum cxd2841er_xtal             xtal;
  61         enum fe_caps caps;
  62         u32                             flags;
  63         unsigned long                   stats_time;
  64 };
  65
  66 static const struct cxd2841er_cnr_data s_cn_data[] = {
  67         { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
  68         { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
  69         { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
  70         { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
  71         { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
  72         { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
  73         { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
  74         { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
  75         { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
  76         { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
  77         { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
  78         { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
  79         { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
  80         { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
  81         { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
  82         { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
  83         { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
  84         { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
  85         { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
  86         { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
  87         { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
  88         { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
  89         { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
  90         { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
  91         { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
  92         { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
  93         { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
  94         { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
  95         { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
  96         { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
  97         { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
  98         { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
  99         { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
 100         { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
 101         { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
 102         { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
 103         { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
 104         { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
 105         { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
 106         { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
 107         { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
 108         { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
 109         { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
 110         { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
 111         { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
 112         { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
 113         { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
 114         { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 115         { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 116         { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
 117         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 118         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 119         { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
 120         { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
 121         { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
 122         { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
 123         { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
 124         { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
 125         { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
 126         { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
 127         { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
 128         { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
 129         { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
 130         { 0x0015, 19900 }, { 0x0014, 20000 },
 131 };
 132
 133 static const struct cxd2841er_cnr_data s2_cn_data[] = {
 134         { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
 135         { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
 136         { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
 137         { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
 138         { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
 139         { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
 140         { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
 141         { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
 142         { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
 143         { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
 144         { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
 145         { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
 146         { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
 147         { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
 148         { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
 149         { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
 150         { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
 151         { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
 152         { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
 153         { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
 154         { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
 155         { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
 156         { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
 157         { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
 158         { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
 159         { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
 160         { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
 161         { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
 162         { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
 163         { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
 164         { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
 165         { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
 166         { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
 167         { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
 168         { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
 169         { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
 170         { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
 171         { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
 172         { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
 173         { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
 174         { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
 175         { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
 176         { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
 177         { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
 178         { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
 179         { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
 180         { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
 181         { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 182         { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 183         { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
 184         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 185         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 186         { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
 187         { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
 188         { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
 189         { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
 190         { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
 191         { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
 192         { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
 193         { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
 194         { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
 195         { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
 196         { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
 197         { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
 198 };
 199
 200 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv);
 201 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv);
 202
 203 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
 204                                 u8 addr, u8 reg, u8 write,
 205                                 const u8 *data, u32 len)
 206 {
 207         dev_dbg(&priv->i2c->dev,
 208                 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d data %*ph\n",
 209                 (write == 0 ? "read" : "write"), addr, reg, len, len, data);
 210 }
 211
 212 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
 213                                 u8 addr, u8 reg, const u8 *data, u32 len)
 214 {
 215         int ret;
 216         u8 buf[MAX_WRITE_REGSIZE + 1];
 217         u8 i2c_addr = (addr == I2C_SLVX ?
 218                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 219         struct i2c_msg msg[1] = {
 220                 {
 221                         .addr = i2c_addr,
 222                         .flags = 0,
 223                         .len = len + 1,
 224                         .buf = buf,
 225                 }
 226         };
 227
 228         if (len + 1 >= sizeof(buf)) {
 229                 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
 230                          reg, len + 1);
 231                 return -E2BIG;
 232         }
 233
 234         cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
 235         buf[0] = reg;
 236         memcpy(&buf[1], data, len);
 237
 238         ret = i2c_transfer(priv->i2c, msg, 1);
 239         if (ret >= 0 && ret != 1)
 240                 ret = -EIO;
 241         if (ret < 0) {
 242                 dev_warn(&priv->i2c->dev,
 243                         "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
 244                         KBUILD_MODNAME, ret, i2c_addr, reg, len);
 245                 return ret;
 246         }
 247         return 0;
 248 }
 249
 250 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
 251                                u8 addr, u8 reg, u8 val)
 252 {
 253         u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
 254
 255         return cxd2841er_write_regs(priv, addr, reg, &tmp, 1);
 256 }
 257
 258 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
 259                                u8 addr, u8 reg, u8 *val, u32 len)
 260 {
 261         int ret;
 262         u8 i2c_addr = (addr == I2C_SLVX ?
 263                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 264         struct i2c_msg msg[2] = {
 265                 {
 266                         .addr = i2c_addr,
 267                         .flags = 0,
 268                         .len = 1,
 269                         .buf = &reg,
 270                 }, {
 271                         .addr = i2c_addr,
 272                         .flags = I2C_M_RD,
 273                         .len = len,
 274                         .buf = val,
 275                 }
 276         };
 277
 278         ret = i2c_transfer(priv->i2c, msg, 2);
 279         if (ret >= 0 && ret != 2)
 280                 ret = -EIO;
 281         if (ret < 0) {
 282                 dev_warn(&priv->i2c->dev,
 283                         "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
 284                         KBUILD_MODNAME, ret, i2c_addr, reg);
 285                 return ret;
 286         }
 287         cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
 288         return 0;
 289 }
 290
 291 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
 292                               u8 addr, u8 reg, u8 *val)
 293 {
 294         return cxd2841er_read_regs(priv, addr, reg, val, 1);
 295 }
 296
 297 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
 298                                   u8 addr, u8 reg, u8 data, u8 mask)
 299 {
 300         int res;
 301         u8 rdata;
 302
 303         if (mask != 0xff) {
 304                 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
 305                 if (res)
 306                         return res;
 307                 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
 308         }
 309         return cxd2841er_write_reg(priv, addr, reg, data);
 310 }
 311
 312 static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz)
 313 {
 314         u64 tmp;
 315
 316         tmp = (u64) ifhz * 16777216;
 317         do_div(tmp, ((xtal == SONY_XTAL_24000) ? 48000000 : 41000000));
 318
 319         return (u32) tmp;
 320 }
 321
 322 static u32 cxd2841er_calc_iffreq(u32 ifhz)
 323 {
 324         return cxd2841er_calc_iffreq_xtal(SONY_XTAL_20500, ifhz);
 325 }
 326
 327 static int cxd2841er_get_if_hz(struct cxd2841er_priv *priv, u32 def_hz)
 328 {
 329         u32 hz;
 330
 331         if (priv->frontend.ops.tuner_ops.get_if_frequency
 332                         && (priv->flags & CXD2841ER_AUTO_IFHZ))
 333                 priv->frontend.ops.tuner_ops.get_if_frequency(
 334                         &priv->frontend, &hz);
 335         else
 336                 hz = def_hz;
 337
 338         return hz;
 339 }
 340
 341 static int cxd2841er_tuner_set(struct dvb_frontend *fe)
 342 {
 343         struct cxd2841er_priv *priv = fe->demodulator_priv;
 344
 345         if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
 346                 fe->ops.i2c_gate_ctrl(fe, 1);
 347         if (fe->ops.tuner_ops.set_params)
 348                 fe->ops.tuner_ops.set_params(fe);
 349         if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
 350                 fe->ops.i2c_gate_ctrl(fe, 0);
 351
 352         return 0;
 353 }
 354
 355 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
 356                                            u32 symbol_rate)
 357 {
 358         u32 reg_value = 0;
 359         u8 data[3] = {0, 0, 0};
 360
 361         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 362         /*
 363          * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
 364          *          = ((symbolRateKSps * 2^14) + 500) / 1000
 365          *          = ((symbolRateKSps * 16384) + 500) / 1000
 366          */
 367         reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
 368         if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
 369                 dev_err(&priv->i2c->dev,
 370                         "%s(): reg_value is out of range\n", __func__);
 371                 return -EINVAL;
 372         }
 373         data[0] = (u8)((reg_value >> 16) & 0x0F);
 374         data[1] = (u8)((reg_value >>  8) & 0xFF);
 375         data[2] = (u8)(reg_value & 0xFF);
 376         /* Set SLV-T Bank : 0xAE */
 377         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 378         cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
 379         return 0;
 380 }
 381
 382 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 383                                         u8 system);
 384
 385 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
 386                                          u8 system, u32 symbol_rate)
 387 {
 388         int ret;
 389         u8 data[4] = { 0, 0, 0, 0 };
 390
 391         if (priv->state != STATE_SLEEP_S) {
 392                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 393                         __func__, (int)priv->state);
 394                 return -EINVAL;
 395         }
 396         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 397         cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
 398         /* Set demod mode */
 399         if (system == SYS_DVBS) {
 400                 data[0] = 0x0A;
 401         } else if (system == SYS_DVBS2) {
 402                 data[0] = 0x0B;
 403         } else {
 404                 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
 405                         __func__, system);
 406                 return -EINVAL;
 407         }
 408         /* Set SLV-X Bank : 0x00 */
 409         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 410         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
 411         /* DVB-S/S2 */
 412         data[0] = 0x00;
 413         /* Set SLV-T Bank : 0x00 */
 414         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 415         /* Enable S/S2 auto detection 1 */
 416         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
 417         /* Set SLV-T Bank : 0xAE */
 418         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 419         /* Enable S/S2 auto detection 2 */
 420         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
 421         /* Set SLV-T Bank : 0x00 */
 422         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 423         /* Enable demod clock */
 424         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
 425         /* Enable ADC clock */
 426         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
 427         /* Enable ADC 1 */
 428         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 429         /* Enable ADC 2 */
 430         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
 431         /* Set SLV-X Bank : 0x00 */
 432         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 433         /* Enable ADC 3 */
 434         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
 435         /* Set SLV-T Bank : 0xA3 */
 436         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
 437         cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
 438         data[0] = 0x07;
 439         data[1] = 0x3B;
 440         data[2] = 0x08;
 441         data[3] = 0xC5;
 442         /* Set SLV-T Bank : 0xAB */
 443         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
 444         cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
 445         data[0] = 0x05;
 446         data[1] = 0x80;
 447         data[2] = 0x0A;
 448         data[3] = 0x80;
 449         cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
 450         data[0] = 0x0C;
 451         data[1] = 0xCC;
 452         cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
 453         /* Set demod parameter */
 454         ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
 455         if (ret != 0)
 456                 return ret;
 457         /* Set SLV-T Bank : 0x00 */
 458         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 459         /* disable Hi-Z setting 1 */
 460         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
 461         /* disable Hi-Z setting 2 */
 462         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
 463         priv->state = STATE_ACTIVE_S;
 464         return 0;
 465 }
 466
 467 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
 468                                                u32 bandwidth);
 469
 470 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
 471                                                 u32 bandwidth);
 472
 473 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
 474                                                u32 bandwidth);
 475
 476 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
 477                 u32 bandwidth);
 478
 479 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
 480
 481 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
 482
 483 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
 484
 485 static int cxd2841er_sleep_tc(struct dvb_frontend *fe);
 486
 487 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
 488                                    struct dtv_frontend_properties *p)
 489 {
 490         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 491         if (priv->state != STATE_ACTIVE_S &&
 492                         priv->state != STATE_ACTIVE_TC) {
 493                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
 494                         __func__, priv->state);
 495                 return -EINVAL;
 496         }
 497         /* Set SLV-T Bank : 0x00 */
 498         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 499         /* disable TS output */
 500         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 501         if (priv->state == STATE_ACTIVE_S)
 502                 return cxd2841er_dvbs2_set_symbol_rate(
 503                                 priv, p->symbol_rate / 1000);
 504         else if (priv->state == STATE_ACTIVE_TC) {
 505                 switch (priv->system) {
 506                 case SYS_DVBT:
 507                         return cxd2841er_sleep_tc_to_active_t_band(
 508                                         priv, p->bandwidth_hz);
 509                 case SYS_DVBT2:
 510                         return cxd2841er_sleep_tc_to_active_t2_band(
 511                                         priv, p->bandwidth_hz);
 512                 case SYS_DVBC_ANNEX_A:
 513                         return cxd2841er_sleep_tc_to_active_c_band(
 514                                         priv, p->bandwidth_hz);
 515                 case SYS_ISDBT:
 516                         cxd2841er_active_i_to_sleep_tc(priv);
 517                         cxd2841er_sleep_tc_to_shutdown(priv);
 518                         cxd2841er_shutdown_to_sleep_tc(priv);
 519                         return cxd2841er_sleep_tc_to_active_i(
 520                                         priv, p->bandwidth_hz);
 521                 }
 522         }
 523         dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
 524                 __func__, priv->system);
 525         return -EINVAL;
 526 }
 527
 528 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
 529 {
 530         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 531         if (priv->state != STATE_ACTIVE_S) {
 532                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 533                         __func__, priv->state);
 534                 return -EINVAL;
 535         }
 536         /* Set SLV-T Bank : 0x00 */
 537         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 538         /* disable TS output */
 539         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 540         /* enable Hi-Z setting 1 */
 541         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
 542         /* enable Hi-Z setting 2 */
 543         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 544         /* Set SLV-X Bank : 0x00 */
 545         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 546         /* disable ADC 1 */
 547         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 548         /* Set SLV-T Bank : 0x00 */
 549         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 550         /* disable ADC clock */
 551         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
 552         /* disable ADC 2 */
 553         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 554         /* disable ADC 3 */
 555         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 556         /* SADC Bias ON */
 557         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 558         /* disable demod clock */
 559         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 560         /* Set SLV-T Bank : 0xAE */
 561         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 562         /* disable S/S2 auto detection1 */
 563         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 564         /* Set SLV-T Bank : 0x00 */
 565         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 566         /* disable S/S2 auto detection2 */
 567         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
 568         priv->state = STATE_SLEEP_S;
 569         return 0;
 570 }
 571
 572 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
 573 {
 574         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 575         if (priv->state != STATE_SLEEP_S) {
 576                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 577                         __func__, priv->state);
 578                 return -EINVAL;
 579         }
 580         /* Set SLV-T Bank : 0x00 */
 581         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 582         /* Disable DSQOUT */
 583         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 584         /* Disable DSQIN */
 585         cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
 586         /* Set SLV-X Bank : 0x00 */
 587         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 588         /* Disable oscillator */
 589         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 590         /* Set demod mode */
 591         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 592         priv->state = STATE_SHUTDOWN;
 593         return 0;
 594 }
 595
 596 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
 597 {
 598         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 599         if (priv->state != STATE_SLEEP_TC) {
 600                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 601                         __func__, priv->state);
 602                 return -EINVAL;
 603         }
 604         /* Set SLV-X Bank : 0x00 */
 605         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 606         /* Disable oscillator */
 607         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 608         /* Set demod mode */
 609         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 610         priv->state = STATE_SHUTDOWN;
 611         return 0;
 612 }
 613
 614 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
 615 {
 616         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 617         if (priv->state != STATE_ACTIVE_TC) {
 618                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 619                         __func__, priv->state);
 620                 return -EINVAL;
 621         }
 622         /* Set SLV-T Bank : 0x00 */
 623         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 624         /* disable TS output */
 625         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 626         /* enable Hi-Z setting 1 */
 627         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 628         /* enable Hi-Z setting 2 */
 629         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 630         /* Set SLV-X Bank : 0x00 */
 631         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 632         /* disable ADC 1 */
 633         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 634         /* Set SLV-T Bank : 0x00 */
 635         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 636         /* Disable ADC 2 */
 637         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 638         /* Disable ADC 3 */
 639         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 640         /* Disable ADC clock */
 641         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 642         /* Disable RF level monitor */
 643         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 644         /* Disable demod clock */
 645         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 646         priv->state = STATE_SLEEP_TC;
 647         return 0;
 648 }
 649
 650 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
 651 {
 652         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 653         if (priv->state != STATE_ACTIVE_TC) {
 654                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 655                         __func__, priv->state);
 656                 return -EINVAL;
 657         }
 658         /* Set SLV-T Bank : 0x00 */
 659         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 660         /* disable TS output */
 661         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 662         /* enable Hi-Z setting 1 */
 663         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 664         /* enable Hi-Z setting 2 */
 665         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 666         /* Cancel DVB-T2 setting */
 667         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
 668         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
 669         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
 670         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
 671         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
 672         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
 673         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
 674         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
 675         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
 676         /* Set SLV-X Bank : 0x00 */
 677         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 678         /* disable ADC 1 */
 679         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 680         /* Set SLV-T Bank : 0x00 */
 681         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 682         /* Disable ADC 2 */
 683         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 684         /* Disable ADC 3 */
 685         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 686         /* Disable ADC clock */
 687         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 688         /* Disable RF level monitor */
 689         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 690         /* Disable demod clock */
 691         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 692         priv->state = STATE_SLEEP_TC;
 693         return 0;
 694 }
 695
 696 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
 697 {
 698         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 699         if (priv->state != STATE_ACTIVE_TC) {
 700                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 701                         __func__, priv->state);
 702                 return -EINVAL;
 703         }
 704         /* Set SLV-T Bank : 0x00 */
 705         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 706         /* disable TS output */
 707         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 708         /* enable Hi-Z setting 1 */
 709         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 710         /* enable Hi-Z setting 2 */
 711         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 712         /* Cancel DVB-C setting */
 713         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
 714         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
 715         /* Set SLV-X Bank : 0x00 */
 716         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 717         /* disable ADC 1 */
 718         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 719         /* Set SLV-T Bank : 0x00 */
 720         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 721         /* Disable ADC 2 */
 722         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 723         /* Disable ADC 3 */
 724         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 725         /* Disable ADC clock */
 726         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 727         /* Disable RF level monitor */
 728         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 729         /* Disable demod clock */
 730         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 731         priv->state = STATE_SLEEP_TC;
 732         return 0;
 733 }
 734
 735 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
 736 {
 737         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 738         if (priv->state != STATE_ACTIVE_TC) {
 739                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 740                                 __func__, priv->state);
 741                 return -EINVAL;
 742         }
 743         /* Set SLV-T Bank : 0x00 */
 744         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 745         /* disable TS output */
 746         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 747         /* enable Hi-Z setting 1 */
 748         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 749         /* enable Hi-Z setting 2 */
 750         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 751
 752         /* TODO: Cancel demod parameter */
 753
 754         /* Set SLV-X Bank : 0x00 */
 755         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 756         /* disable ADC 1 */
 757         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 758         /* Set SLV-T Bank : 0x00 */
 759         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 760         /* Disable ADC 2 */
 761         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 762         /* Disable ADC 3 */
 763         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 764         /* Disable ADC clock */
 765         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 766         /* Disable RF level monitor */
 767         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 768         /* Disable demod clock */
 769         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 770         priv->state = STATE_SLEEP_TC;
 771         return 0;
 772 }
 773
 774 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
 775 {
 776         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 777         if (priv->state != STATE_SHUTDOWN) {
 778                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 779                         __func__, priv->state);
 780                 return -EINVAL;
 781         }
 782         /* Set SLV-X Bank : 0x00 */
 783         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 784         /* Clear all demodulator registers */
 785         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 786         usleep_range(3000, 5000);
 787         /* Set SLV-X Bank : 0x00 */
 788         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 789         /* Set demod SW reset */
 790         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 791
 792         switch (priv->xtal) {
 793         case SONY_XTAL_20500:
 794                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
 795                 break;
 796         case SONY_XTAL_24000:
 797                 /* Select demod frequency */
 798                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 799                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
 800                 break;
 801         case SONY_XTAL_41000:
 802                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
 803                 break;
 804         default:
 805                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
 806                                 __func__, priv->xtal);
 807                 return -EINVAL;
 808         }
 809
 810         /* Set demod mode */
 811         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
 812         /* Clear demod SW reset */
 813         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 814         usleep_range(1000, 2000);
 815         /* Set SLV-T Bank : 0x00 */
 816         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 817         /* enable DSQOUT */
 818         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
 819         /* enable DSQIN */
 820         cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
 821         /* TADC Bias On */
 822         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 823         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 824         /* SADC Bias On */
 825         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 826         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 827         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 828         priv->state = STATE_SLEEP_S;
 829         return 0;
 830 }
 831
 832 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
 833 {
 834         u8 data = 0;
 835
 836         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 837         if (priv->state != STATE_SHUTDOWN) {
 838                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 839                         __func__, priv->state);
 840                 return -EINVAL;
 841         }
 842         /* Set SLV-X Bank : 0x00 */
 843         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 844         /* Clear all demodulator registers */
 845         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 846         usleep_range(3000, 5000);
 847         /* Set SLV-X Bank : 0x00 */
 848         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 849         /* Set demod SW reset */
 850         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 851   /* Select ADC clock mode */
 852         cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
 853
 854         switch (priv->xtal) {
 855         case SONY_XTAL_20500:
 856                 data = 0x0;
 857                 break;
 858         case SONY_XTAL_24000:
 859                 /* Select demod frequency */
 860                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 861                 data = 0x3;
 862                 break;
 863         case SONY_XTAL_41000:
 864                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 865                 data = 0x1;
 866                 break;
 867         }
 868         cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
 869         /* Clear demod SW reset */
 870         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 871         usleep_range(1000, 2000);
 872         /* Set SLV-T Bank : 0x00 */
 873         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 874         /* TADC Bias On */
 875         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 876         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 877         /* SADC Bias On */
 878         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 879         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 880         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 881         priv->state = STATE_SLEEP_TC;
 882         return 0;
 883 }
 884
 885 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
 886 {
 887         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 888         /* Set SLV-T Bank : 0x00 */
 889         cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
 890         /* SW Reset */
 891         cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
 892         /* Enable TS output */
 893         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
 894         return 0;
 895 }
 896
 897 /* Set TS parallel mode */
 898 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 899                                         u8 system)
 900 {
 901         u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
 902
 903         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 904         /* Set SLV-T Bank : 0x00 */
 905         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 906         cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
 907         cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
 908         cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
 909         dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
 910                 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
 911
 912         /*
 913          * slave    Bank    Addr    Bit    default    Name
 914          * <SLV-T>  00h     C4h     [1:0]  2'b??      OSERCKMODE
 915          */
 916         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
 917                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
 918         /*
 919          * slave    Bank    Addr    Bit    default    Name
 920          * <SLV-T>  00h     D1h     [1:0]  2'b??      OSERDUTYMODE
 921          */
 922         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd1,
 923                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
 924         /*
 925          * slave    Bank    Addr    Bit    default    Name
 926          * <SLV-T>  00h     D9h     [7:0]  8'h08      OTSCKPERIOD
 927          */
 928         cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
 929         /*
 930          * Disable TS IF Clock
 931          * slave    Bank    Addr    Bit    default    Name
 932          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 933          */
 934         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
 935         /*
 936          * slave    Bank    Addr    Bit    default    Name
 937          * <SLV-T>  00h     33h     [1:0]  2'b01      OREG_CKSEL_TSIF
 938          */
 939         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33,
 940                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
 941         /*
 942          * Enable TS IF Clock
 943          * slave    Bank    Addr    Bit    default    Name
 944          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 945          */
 946         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
 947
 948         if (system == SYS_DVBT) {
 949                 /* Enable parity period for DVB-T */
 950                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 951                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 952         } else if (system == SYS_DVBC_ANNEX_A) {
 953                 /* Enable parity period for DVB-C */
 954                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 955                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 956         }
 957 }
 958
 959 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
 960 {
 961         u8 chip_id = 0;
 962
 963         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 964         if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
 965                 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
 966         else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
 967                 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
 968
 969         return chip_id;
 970 }
 971
 972 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
 973                                    enum fe_status *status)
 974 {
 975         u8 reg = 0;
 976         struct cxd2841er_priv *priv = fe->demodulator_priv;
 977
 978         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 979         *status = 0;
 980         if (priv->state != STATE_ACTIVE_S) {
 981                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 982                         __func__, priv->state);
 983                 return -EINVAL;
 984         }
 985         /* Set SLV-T Bank : 0xA0 */
 986         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
 987         /*
 988          *  slave     Bank      Addr      Bit      Signal name
 989          * <SLV-T>    A0h       11h       [2]      ITSLOCK
 990          */
 991         cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
 992         if (reg & 0x04) {
 993                 *status = FE_HAS_SIGNAL
 994                         | FE_HAS_CARRIER
 995                         | FE_HAS_VITERBI
 996                         | FE_HAS_SYNC
 997                         | FE_HAS_LOCK;
 998         }
 999         dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
1000         return 0;
1001 }
1002
1003 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
1004                                       u8 *sync, u8 *tslock, u8 *unlock)
1005 {
1006         u8 data = 0;
1007
1008         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1009         if (priv->state != STATE_ACTIVE_TC)
1010                 return -EINVAL;
1011         if (priv->system == SYS_DVBT) {
1012                 /* Set SLV-T Bank : 0x10 */
1013                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1014         } else {
1015                 /* Set SLV-T Bank : 0x20 */
1016                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1017         }
1018         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1019         if ((data & 0x07) == 0x07) {
1020                 dev_dbg(&priv->i2c->dev,
1021                         "%s(): invalid hardware state detected\n", __func__);
1022                 *sync = 0;
1023                 *tslock = 0;
1024                 *unlock = 0;
1025         } else {
1026                 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
1027                 *tslock = ((data & 0x20) ? 1 : 0);
1028                 *unlock = ((data & 0x10) ? 1 : 0);
1029         }
1030         return 0;
1031 }
1032
1033 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
1034 {
1035         u8 data;
1036
1037         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1038         if (priv->state != STATE_ACTIVE_TC)
1039                 return -EINVAL;
1040         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1041         cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
1042         if ((data & 0x01) == 0) {
1043                 *tslock = 0;
1044         } else {
1045                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1046                 *tslock = ((data & 0x20) ? 1 : 0);
1047         }
1048         return 0;
1049 }
1050
1051 static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
1052                 u8 *sync, u8 *tslock, u8 *unlock)
1053 {
1054         u8 data = 0;
1055
1056         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1057         if (priv->state != STATE_ACTIVE_TC)
1058                 return -EINVAL;
1059         /* Set SLV-T Bank : 0x60 */
1060         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1061         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1062         dev_dbg(&priv->i2c->dev,
1063                         "%s(): lock=0x%x\n", __func__, data);
1064         *sync = ((data & 0x02) ? 1 : 0);
1065         *tslock = ((data & 0x01) ? 1 : 0);
1066         *unlock = ((data & 0x10) ? 1 : 0);
1067         return 0;
1068 }
1069
1070 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1071                                     enum fe_status *status)
1072 {
1073         int ret = 0;
1074         u8 sync = 0;
1075         u8 tslock = 0;
1076         u8 unlock = 0;
1077         struct cxd2841er_priv *priv = fe->demodulator_priv;
1078
1079         *status = 0;
1080         if (priv->state == STATE_ACTIVE_TC) {
1081                 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1082                         ret = cxd2841er_read_status_t_t2(
1083                                 priv, &sync, &tslock, &unlock);
1084                         if (ret)
1085                                 goto done;
1086                         if (unlock)
1087                                 goto done;
1088                         if (sync)
1089                                 *status = FE_HAS_SIGNAL |
1090                                         FE_HAS_CARRIER |
1091                                         FE_HAS_VITERBI |
1092                                         FE_HAS_SYNC;
1093                         if (tslock)
1094                                 *status |= FE_HAS_LOCK;
1095                 } else if (priv->system == SYS_ISDBT) {
1096                         ret = cxd2841er_read_status_i(
1097                                         priv, &sync, &tslock, &unlock);
1098                         if (ret)
1099                                 goto done;
1100                         if (unlock)
1101                                 goto done;
1102                         if (sync)
1103                                 *status = FE_HAS_SIGNAL |
1104                                         FE_HAS_CARRIER |
1105                                         FE_HAS_VITERBI |
1106                                         FE_HAS_SYNC;
1107                         if (tslock)
1108                                 *status |= FE_HAS_LOCK;
1109                 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1110                         ret = cxd2841er_read_status_c(priv, &tslock);
1111                         if (ret)
1112                                 goto done;
1113                         if (tslock)
1114                                 *status = FE_HAS_SIGNAL |
1115                                         FE_HAS_CARRIER |
1116                                         FE_HAS_VITERBI |
1117                                         FE_HAS_SYNC |
1118                                         FE_HAS_LOCK;
1119                 }
1120         }
1121 done:
1122         dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1123         return ret;
1124 }
1125
1126 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1127                                              int *offset)
1128 {
1129         u8 data[3];
1130         u8 is_hs_mode;
1131         s32 cfrl_ctrlval;
1132         s32 temp_div, temp_q, temp_r;
1133
1134         if (priv->state != STATE_ACTIVE_S) {
1135                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1136                         __func__, priv->state);
1137                 return -EINVAL;
1138         }
1139         /*
1140          * Get High Sampling Rate mode
1141          *  slave     Bank      Addr      Bit      Signal name
1142          * <SLV-T>    A0h       10h       [0]      ITRL_LOCK
1143          */
1144         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1145         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1146         if (data[0] & 0x01) {
1147                 /*
1148                  *  slave     Bank      Addr      Bit      Signal name
1149                  * <SLV-T>    A0h       50h       [4]      IHSMODE
1150                  */
1151                 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1152                 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1153         } else {
1154                 dev_dbg(&priv->i2c->dev,
1155                         "%s(): unable to detect sampling rate mode\n",
1156                         __func__);
1157                 return -EINVAL;
1158         }
1159         /*
1160          *  slave     Bank      Addr      Bit      Signal name
1161          * <SLV-T>    A0h       45h       [4:0]    ICFRL_CTRLVAL[20:16]
1162          * <SLV-T>    A0h       46h       [7:0]    ICFRL_CTRLVAL[15:8]
1163          * <SLV-T>    A0h       47h       [7:0]    ICFRL_CTRLVAL[7:0]
1164          */
1165         cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1166         cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1167                                 (((u32)data[1] & 0xFF) <<  8) |
1168                                 ((u32)data[2] & 0xFF), 20);
1169         temp_div = (is_hs_mode ? 1048576 : 1572864);
1170         if (cfrl_ctrlval > 0) {
1171                 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1172                         temp_div, &temp_r);
1173         } else {
1174                 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1175                         temp_div, &temp_r);
1176         }
1177         if (temp_r >= temp_div / 2)
1178                 temp_q++;
1179         if (cfrl_ctrlval > 0)
1180                 temp_q *= -1;
1181         *offset = temp_q;
1182         return 0;
1183 }
1184
1185 static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1186                                            u32 bandwidth, int *offset)
1187 {
1188         u8 data[4];
1189
1190         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1191         if (priv->state != STATE_ACTIVE_TC) {
1192                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1193                         __func__, priv->state);
1194                 return -EINVAL;
1195         }
1196         if (priv->system != SYS_ISDBT) {
1197                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1198                         __func__, priv->system);
1199                 return -EINVAL;
1200         }
1201         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1202         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1203         *offset = -1 * sign_extend32(
1204                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1205                 ((u32)data[2] << 8) | (u32)data[3], 29);
1206
1207         switch (bandwidth) {
1208         case 6000000:
1209                 *offset = -1 * ((*offset) * 8/264);
1210                 break;
1211         case 7000000:
1212                 *offset = -1 * ((*offset) * 8/231);
1213                 break;
1214         case 8000000:
1215                 *offset = -1 * ((*offset) * 8/198);
1216                 break;
1217         default:
1218                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1219                                 __func__, bandwidth);
1220                 return -EINVAL;
1221         }
1222
1223         dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1224                         __func__, bandwidth, *offset);
1225
1226         return 0;
1227 }
1228
1229 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1230                                            u32 bandwidth, int *offset)
1231 {
1232         u8 data[4];
1233
1234         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1235         if (priv->state != STATE_ACTIVE_TC) {
1236                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1237                         __func__, priv->state);
1238                 return -EINVAL;
1239         }
1240         if (priv->system != SYS_DVBT) {
1241                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1242                         __func__, priv->system);
1243                 return -EINVAL;
1244         }
1245         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1246         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1247         *offset = -1 * sign_extend32(
1248                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1249                 ((u32)data[2] << 8) | (u32)data[3], 29);
1250         *offset *= (bandwidth / 1000000);
1251         *offset /= 235;
1252         return 0;
1253 }
1254
1255 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1256                                            u32 bandwidth, int *offset)
1257 {
1258         u8 data[4];
1259
1260         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1261         if (priv->state != STATE_ACTIVE_TC) {
1262                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1263                         __func__, priv->state);
1264                 return -EINVAL;
1265         }
1266         if (priv->system != SYS_DVBT2) {
1267                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1268                         __func__, priv->system);
1269                 return -EINVAL;
1270         }
1271         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1272         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1273         *offset = -1 * sign_extend32(
1274                 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1275                 ((u32)data[2] << 8) | (u32)data[3], 27);
1276         switch (bandwidth) {
1277         case 1712000:
1278                 *offset /= 582;
1279                 break;
1280         case 5000000:
1281         case 6000000:
1282         case 7000000:
1283         case 8000000:
1284                 *offset *= (bandwidth / 1000000);
1285                 *offset /= 940;
1286                 break;
1287         default:
1288                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1289                         __func__, bandwidth);
1290                 return -EINVAL;
1291         }
1292         return 0;
1293 }
1294
1295 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1296                                           int *offset)
1297 {
1298         u8 data[2];
1299
1300         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1301         if (priv->state != STATE_ACTIVE_TC) {
1302                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1303                         __func__, priv->state);
1304                 return -EINVAL;
1305         }
1306         if (priv->system != SYS_DVBC_ANNEX_A) {
1307                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1308                         __func__, priv->system);
1309                 return -EINVAL;
1310         }
1311         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1312         cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1313         *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1314                                                 | (u32)data[1], 13), 16384);
1315         return 0;
1316 }
1317
1318 static int cxd2841er_read_packet_errors_c(
1319                 struct cxd2841er_priv *priv, u32 *penum)
1320 {
1321         u8 data[3];
1322
1323         *penum = 0;
1324         if (priv->state != STATE_ACTIVE_TC) {
1325                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1326                                 __func__, priv->state);
1327                 return -EINVAL;
1328         }
1329         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1330         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1331         if (data[2] & 0x01)
1332                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1333         return 0;
1334 }
1335
1336 static int cxd2841er_read_packet_errors_t(
1337                 struct cxd2841er_priv *priv, u32 *penum)
1338 {
1339         u8 data[3];
1340
1341         *penum = 0;
1342         if (priv->state != STATE_ACTIVE_TC) {
1343                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1344                         __func__, priv->state);
1345                 return -EINVAL;
1346         }
1347         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1348         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1349         if (data[2] & 0x01)
1350                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1351         return 0;
1352 }
1353
1354 static int cxd2841er_read_packet_errors_t2(
1355                 struct cxd2841er_priv *priv, u32 *penum)
1356 {
1357         u8 data[3];
1358
1359         *penum = 0;
1360         if (priv->state != STATE_ACTIVE_TC) {
1361                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1362                         __func__, priv->state);
1363                 return -EINVAL;
1364         }
1365         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1366         cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1367         if (data[0] & 0x01)
1368                 *penum = ((u32)data[1] << 8) | (u32)data[2];
1369         return 0;
1370 }
1371
1372 static int cxd2841er_read_packet_errors_i(
1373                 struct cxd2841er_priv *priv, u32 *penum)
1374 {
1375         u8 data[2];
1376
1377         *penum = 0;
1378         if (priv->state != STATE_ACTIVE_TC) {
1379                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1380                                 __func__, priv->state);
1381                 return -EINVAL;
1382         }
1383         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1384         cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1385
1386         if (!(data[0] & 0x01))
1387                 return 0;
1388
1389         /* Layer A */
1390         cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1391         *penum = ((u32)data[0] << 8) | (u32)data[1];
1392
1393         /* Layer B */
1394         cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1395         *penum += ((u32)data[0] << 8) | (u32)data[1];
1396
1397         /* Layer C */
1398         cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1399         *penum += ((u32)data[0] << 8) | (u32)data[1];
1400
1401         return 0;
1402 }
1403
1404 static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
1405                 u32 *bit_error, u32 *bit_count)
1406 {
1407         u8 data[3];
1408         u32 bit_err, period_exp;
1409
1410         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1411         if (priv->state != STATE_ACTIVE_TC) {
1412                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1413                                 __func__, priv->state);
1414                 return -EINVAL;
1415         }
1416         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1417         cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
1418         if (!(data[0] & 0x80)) {
1419                 dev_dbg(&priv->i2c->dev,
1420                                 "%s(): no valid BER data\n", __func__);
1421                 return -EINVAL;
1422         }
1423         bit_err = ((u32)(data[0] & 0x3f) << 16) |
1424                 ((u32)data[1] << 8) |
1425                 (u32)data[2];
1426         cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
1427         period_exp = data[0] & 0x1f;
1428
1429         if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
1430                 dev_dbg(&priv->i2c->dev,
1431                                 "%s(): period_exp(%u) or bit_err(%u)  not in range. no valid BER data\n",
1432                                 __func__, period_exp, bit_err);
1433                 return -EINVAL;
1434         }
1435
1436         dev_dbg(&priv->i2c->dev,
1437                         "%s(): period_exp(%u) or bit_err(%u) count=%d\n",
1438                         __func__, period_exp, bit_err,
1439                         ((1 << period_exp) * 204 * 8));
1440
1441         *bit_error = bit_err;
1442         *bit_count = ((1 << period_exp) * 204 * 8);
1443
1444         return 0;
1445 }
1446
1447 static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv,
1448                 u32 *bit_error, u32 *bit_count)
1449 {
1450         u8 data[3];
1451         u8 pktnum[2];
1452
1453         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1454         if (priv->state != STATE_ACTIVE_TC) {
1455                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1456                                 __func__, priv->state);
1457                 return -EINVAL;
1458         }
1459
1460         cxd2841er_freeze_regs(priv);
1461         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1462         cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum));
1463         cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data));
1464         cxd2841er_unfreeze_regs(priv);
1465
1466         if (!pktnum[0] && !pktnum[1]) {
1467                 dev_dbg(&priv->i2c->dev,
1468                                 "%s(): no valid BER data\n", __func__);
1469                 return -EINVAL;
1470         }
1471
1472         *bit_error = ((u32)(data[0] & 0x7F) << 16) |
1473                 ((u32)data[1] << 8) | data[2];
1474         *bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8);
1475         dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n",
1476                         __func__, *bit_error, *bit_count);
1477
1478         return 0;
1479 }
1480
1481 static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
1482                                     u32 *bit_error, u32 *bit_count)
1483 {
1484         u8 data[11];
1485
1486         /* Set SLV-T Bank : 0xA0 */
1487         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1488         /*
1489          *  slave     Bank      Addr      Bit      Signal name
1490          * <SLV-T>    A0h       35h       [0]      IFVBER_VALID
1491          * <SLV-T>    A0h       36h       [5:0]    IFVBER_BITERR[21:16]
1492          * <SLV-T>    A0h       37h       [7:0]    IFVBER_BITERR[15:8]
1493          * <SLV-T>    A0h       38h       [7:0]    IFVBER_BITERR[7:0]
1494          * <SLV-T>    A0h       3Dh       [5:0]    IFVBER_BITNUM[21:16]
1495          * <SLV-T>    A0h       3Eh       [7:0]    IFVBER_BITNUM[15:8]
1496          * <SLV-T>    A0h       3Fh       [7:0]    IFVBER_BITNUM[7:0]
1497          */
1498         cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1499         if (data[0] & 0x01) {
1500                 *bit_error = ((u32)(data[1]  & 0x3F) << 16) |
1501                              ((u32)(data[2]  & 0xFF) <<  8) |
1502                              (u32)(data[3]  & 0xFF);
1503                 *bit_count = ((u32)(data[8]  & 0x3F) << 16) |
1504                              ((u32)(data[9]  & 0xFF) <<  8) |
1505                              (u32)(data[10] & 0xFF);
1506                 if ((*bit_count == 0) || (*bit_error > *bit_count)) {
1507                         dev_dbg(&priv->i2c->dev,
1508                                 "%s(): invalid bit_error %d, bit_count %d\n",
1509                                 __func__, *bit_error, *bit_count);
1510                         return -EINVAL;
1511                 }
1512                 return 0;
1513         }
1514         dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1515         return -EINVAL;
1516 }
1517
1518
1519 static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
1520                                      u32 *bit_error, u32 *bit_count)
1521 {
1522         u8 data[5];
1523         u32 period;
1524
1525         /* Set SLV-T Bank : 0xB2 */
1526         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1527         /*
1528          *  slave     Bank      Addr      Bit      Signal name
1529          * <SLV-T>    B2h       30h       [0]      IFLBER_VALID
1530          * <SLV-T>    B2h       31h       [3:0]    IFLBER_BITERR[27:24]
1531          * <SLV-T>    B2h       32h       [7:0]    IFLBER_BITERR[23:16]
1532          * <SLV-T>    B2h       33h       [7:0]    IFLBER_BITERR[15:8]
1533          * <SLV-T>    B2h       34h       [7:0]    IFLBER_BITERR[7:0]
1534          */
1535         cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1536         if (data[0] & 0x01) {
1537                 /* Bit error count */
1538                 *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1539                              ((u32)(data[2] & 0xFF) << 16) |
1540                              ((u32)(data[3] & 0xFF) <<  8) |
1541                              (u32)(data[4] & 0xFF);
1542
1543                 /* Set SLV-T Bank : 0xA0 */
1544                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1545                 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1546                 /* Measurement period */
1547                 period = (u32)(1 << (data[0] & 0x0F));
1548                 if (period == 0) {
1549                         dev_dbg(&priv->i2c->dev,
1550                                 "%s(): period is 0\n", __func__);
1551                         return -EINVAL;
1552                 }
1553                 if (*bit_error > (period * 64800)) {
1554                         dev_dbg(&priv->i2c->dev,
1555                                 "%s(): invalid bit_err 0x%x period 0x%x\n",
1556                                 __func__, *bit_error, period);
1557                         return -EINVAL;
1558                 }
1559                 *bit_count = period * 64800;
1560
1561                 return 0;
1562         } else {
1563                 dev_dbg(&priv->i2c->dev,
1564                         "%s(): no data available\n", __func__);
1565         }
1566         return -EINVAL;
1567 }
1568
1569 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
1570                                  u32 *bit_error, u32 *bit_count)
1571 {
1572         u8 data[4];
1573         u32 period_exp, n_ldpc;
1574
1575         if (priv->state != STATE_ACTIVE_TC) {
1576                 dev_dbg(&priv->i2c->dev,
1577                         "%s(): invalid state %d\n", __func__, priv->state);
1578                 return -EINVAL;
1579         }
1580         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1581         cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1582         if (!(data[0] & 0x10)) {
1583                 dev_dbg(&priv->i2c->dev,
1584                         "%s(): no valid BER data\n", __func__);
1585                 return -EINVAL;
1586         }
1587         *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1588                      ((u32)data[1] << 16) |
1589                      ((u32)data[2] << 8) |
1590                      (u32)data[3];
1591         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1592         period_exp = data[0] & 0x0f;
1593         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1594         cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1595         n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1596         if (*bit_error > ((1U << period_exp) * n_ldpc)) {
1597                 dev_dbg(&priv->i2c->dev,
1598                         "%s(): invalid BER value\n", __func__);
1599                 return -EINVAL;
1600         }
1601
1602         /*
1603          * FIXME: the right thing would be to return bit_error untouched,
1604          * but, as we don't know the scale returned by the counters, let's
1605          * at least preserver BER = bit_error/bit_count.
1606          */
1607         if (period_exp >= 4) {
1608                 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
1609                 *bit_error *= 3125ULL;
1610         } else {
1611                 *bit_count = (1U << period_exp) * (n_ldpc / 200);
1612                 *bit_error *= 50000ULL;
1613         }
1614         return 0;
1615 }
1616
1617 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
1618                                 u32 *bit_error, u32 *bit_count)
1619 {
1620         u8 data[2];
1621         u32 period;
1622
1623         if (priv->state != STATE_ACTIVE_TC) {
1624                 dev_dbg(&priv->i2c->dev,
1625                         "%s(): invalid state %d\n", __func__, priv->state);
1626                 return -EINVAL;
1627         }
1628         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1629         cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1630         if (!(data[0] & 0x01)) {
1631                 dev_dbg(&priv->i2c->dev,
1632                         "%s(): no valid BER data\n", __func__);
1633                 return 0;
1634         }
1635         cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1636         *bit_error = ((u32)data[0] << 8) | (u32)data[1];
1637         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1638         period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1639
1640         /*
1641          * FIXME: the right thing would be to return bit_error untouched,
1642          * but, as we don't know the scale returned by the counters, let's
1643          * at least preserver BER = bit_error/bit_count.
1644          */
1645         *bit_count = period / 128;
1646         *bit_error *= 78125ULL;
1647         return 0;
1648 }
1649
1650 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv)
1651 {
1652         /*
1653          * Freeze registers: ensure multiple separate register reads
1654          * are from the same snapshot
1655          */
1656         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1657         return 0;
1658 }
1659
1660 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv)
1661 {
1662         /*
1663          * un-freeze registers
1664          */
1665         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00);
1666         return 0;
1667 }
1668
1669 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
1670                 u8 delsys, u32 *snr)
1671 {
1672         u8 data[3];
1673         u32 res = 0, value;
1674         int min_index, max_index, index;
1675         static const struct cxd2841er_cnr_data *cn_data;
1676
1677         cxd2841er_freeze_regs(priv);
1678         /* Set SLV-T Bank : 0xA1 */
1679         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1680         /*
1681          *  slave     Bank      Addr      Bit     Signal name
1682          * <SLV-T>    A1h       10h       [0]     ICPM_QUICKRDY
1683          * <SLV-T>    A1h       11h       [4:0]   ICPM_QUICKCNDT[12:8]
1684          * <SLV-T>    A1h       12h       [7:0]   ICPM_QUICKCNDT[7:0]
1685          */
1686         cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1687         cxd2841er_unfreeze_regs(priv);
1688
1689         if (data[0] & 0x01) {
1690                 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1691                 min_index = 0;
1692                 if (delsys == SYS_DVBS) {
1693                         cn_data = s_cn_data;
1694                         max_index = ARRAY_SIZE(s_cn_data) - 1;
1695                 } else {
1696                         cn_data = s2_cn_data;
1697                         max_index = ARRAY_SIZE(s2_cn_data) - 1;
1698                 }
1699                 if (value >= cn_data[min_index].value) {
1700                         res = cn_data[min_index].cnr_x1000;
1701                         goto done;
1702                 }
1703                 if (value <= cn_data[max_index].value) {
1704                         res = cn_data[max_index].cnr_x1000;
1705                         goto done;
1706                 }
1707                 while ((max_index - min_index) > 1) {
1708                         index = (max_index + min_index) / 2;
1709                         if (value == cn_data[index].value) {
1710                                 res = cn_data[index].cnr_x1000;
1711                                 goto done;
1712                         } else if (value > cn_data[index].value)
1713                                 max_index = index;
1714                         else
1715                                 min_index = index;
1716                         if ((max_index - min_index) <= 1) {
1717                                 if (value == cn_data[max_index].value) {
1718                                         res = cn_data[max_index].cnr_x1000;
1719                                         goto done;
1720                                 } else {
1721                                         res = cn_data[min_index].cnr_x1000;
1722                                         goto done;
1723                                 }
1724                         }
1725                 }
1726         } else {
1727                 dev_dbg(&priv->i2c->dev,
1728                         "%s(): no data available\n", __func__);
1729                 return -EINVAL;
1730         }
1731 done:
1732         *snr = res;
1733         return 0;
1734 }
1735
1736 static uint32_t sony_log(uint32_t x)
1737 {
1738         return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
1739 }
1740
1741 static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
1742 {
1743         u32 reg;
1744         u8 data[2];
1745         enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
1746
1747         *snr = 0;
1748         if (priv->state != STATE_ACTIVE_TC) {
1749                 dev_dbg(&priv->i2c->dev,
1750                                 "%s(): invalid state %d\n",
1751                                 __func__, priv->state);
1752                 return -EINVAL;
1753         }
1754
1755         cxd2841er_freeze_regs(priv);
1756         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1757         cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
1758         qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
1759         cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
1760         cxd2841er_unfreeze_regs(priv);
1761
1762         reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
1763         if (reg == 0) {
1764                 dev_dbg(&priv->i2c->dev,
1765                                 "%s(): reg value out of range\n", __func__);
1766                 return 0;
1767         }
1768
1769         switch (qam) {
1770         case SONY_DVBC_CONSTELLATION_16QAM:
1771         case SONY_DVBC_CONSTELLATION_64QAM:
1772         case SONY_DVBC_CONSTELLATION_256QAM:
1773                 /* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */
1774                 if (reg < 126)
1775                         reg = 126;
1776                 *snr = -95 * (int32_t)sony_log(reg) + 95941;
1777                 break;
1778         case SONY_DVBC_CONSTELLATION_32QAM:
1779         case SONY_DVBC_CONSTELLATION_128QAM:
1780                 /* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */
1781                 if (reg < 69)
1782                         reg = 69;
1783                 *snr = -88 * (int32_t)sony_log(reg) + 86999;
1784                 break;
1785         default:
1786                 return -EINVAL;
1787         }
1788
1789         return 0;
1790 }
1791
1792 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1793 {
1794         u32 reg;
1795         u8 data[2];
1796
1797         *snr = 0;
1798         if (priv->state != STATE_ACTIVE_TC) {
1799                 dev_dbg(&priv->i2c->dev,
1800                         "%s(): invalid state %d\n", __func__, priv->state);
1801                 return -EINVAL;
1802         }
1803
1804         cxd2841er_freeze_regs(priv);
1805         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1806         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1807         cxd2841er_unfreeze_regs(priv);
1808
1809         reg = ((u32)data[0] << 8) | (u32)data[1];
1810         if (reg == 0) {
1811                 dev_dbg(&priv->i2c->dev,
1812                         "%s(): reg value out of range\n", __func__);
1813                 return 0;
1814         }
1815         if (reg > 4996)
1816                 reg = 4996;
1817         *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(5350 - reg)) + 285);
1818         return 0;
1819 }
1820
1821 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1822 {
1823         u32 reg;
1824         u8 data[2];
1825
1826         *snr = 0;
1827         if (priv->state != STATE_ACTIVE_TC) {
1828                 dev_dbg(&priv->i2c->dev,
1829                         "%s(): invalid state %d\n", __func__, priv->state);
1830                 return -EINVAL;
1831         }
1832
1833         cxd2841er_freeze_regs(priv);
1834         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1835         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1836         cxd2841er_unfreeze_regs(priv);
1837
1838         reg = ((u32)data[0] << 8) | (u32)data[1];
1839         if (reg == 0) {
1840                 dev_dbg(&priv->i2c->dev,
1841                         "%s(): reg value out of range\n", __func__);
1842                 return 0;
1843         }
1844         if (reg > 10876)
1845                 reg = 10876;
1846         *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(12600 - reg)) + 320);
1847         return 0;
1848 }
1849
1850 static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1851 {
1852         u32 reg;
1853         u8 data[2];
1854
1855         *snr = 0;
1856         if (priv->state != STATE_ACTIVE_TC) {
1857                 dev_dbg(&priv->i2c->dev,
1858                                 "%s(): invalid state %d\n", __func__,
1859                                 priv->state);
1860                 return -EINVAL;
1861         }
1862
1863         cxd2841er_freeze_regs(priv);
1864         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1865         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1866         cxd2841er_unfreeze_regs(priv);
1867
1868         reg = ((u32)data[0] << 8) | (u32)data[1];
1869         if (reg == 0) {
1870                 dev_dbg(&priv->i2c->dev,
1871                                 "%s(): reg value out of range\n", __func__);
1872                 return 0;
1873         }
1874         *snr = 10000 * (intlog10(reg) >> 24) - 9031;
1875         return 0;
1876 }
1877
1878 static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1879                                         u8 delsys)
1880 {
1881         u8 data[2];
1882
1883         cxd2841er_write_reg(
1884                 priv, I2C_SLVT, 0x00, 0x40);
1885         cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1886         dev_dbg(&priv->i2c->dev,
1887                         "%s(): AGC value=%u\n",
1888                         __func__, (((u16)data[0] & 0x0F) << 8) |
1889                         (u16)(data[1] & 0xFF));
1890         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1891 }
1892
1893 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1894                                         u8 delsys)
1895 {
1896         u8 data[2];
1897
1898         cxd2841er_write_reg(
1899                 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1900         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1901         dev_dbg(&priv->i2c->dev,
1902                         "%s(): AGC value=%u\n",
1903                         __func__, (((u16)data[0] & 0x0F) << 8) |
1904                         (u16)(data[1] & 0xFF));
1905         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1906 }
1907
1908 static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1909                 u8 delsys)
1910 {
1911         u8 data[2];
1912
1913         cxd2841er_write_reg(
1914                         priv, I2C_SLVT, 0x00, 0x60);
1915         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1916
1917         dev_dbg(&priv->i2c->dev,
1918                         "%s(): AGC value=%u\n",
1919                         __func__, (((u16)data[0] & 0x0F) << 8) |
1920                         (u16)(data[1] & 0xFF));
1921         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1922 }
1923
1924 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1925 {
1926         u8 data[2];
1927
1928         /* Set SLV-T Bank : 0xA0 */
1929         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1930         /*
1931          *  slave     Bank      Addr      Bit       Signal name
1932          * <SLV-T>    A0h       1Fh       [4:0]     IRFAGC_GAIN[12:8]
1933          * <SLV-T>    A0h       20h       [7:0]     IRFAGC_GAIN[7:0]
1934          */
1935         cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1936         return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1937 }
1938
1939 static void cxd2841er_read_ber(struct dvb_frontend *fe)
1940 {
1941         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1942         struct cxd2841er_priv *priv = fe->demodulator_priv;
1943         u32 ret, bit_error = 0, bit_count = 0;
1944
1945         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1946         switch (p->delivery_system) {
1947         case SYS_DVBC_ANNEX_A:
1948         case SYS_DVBC_ANNEX_B:
1949         case SYS_DVBC_ANNEX_C:
1950                 ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
1951                 break;
1952         case SYS_ISDBT:
1953                 ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count);
1954                 break;
1955         case SYS_DVBS:
1956                 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
1957                 break;
1958         case SYS_DVBS2:
1959                 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
1960                 break;
1961         case SYS_DVBT:
1962                 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
1963                 break;
1964         case SYS_DVBT2:
1965                 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
1966                 break;
1967         default:
1968                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1969                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1970                 return;
1971         }
1972
1973         if (!ret) {
1974                 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1975                 p->post_bit_error.stat[0].uvalue += bit_error;
1976                 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1977                 p->post_bit_count.stat[0].uvalue += bit_count;
1978         } else {
1979                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1980                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1981         }
1982 }
1983
1984 static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
1985 {
1986         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1987         struct cxd2841er_priv *priv = fe->demodulator_priv;
1988         s32 strength;
1989
1990         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1991         switch (p->delivery_system) {
1992         case SYS_DVBT:
1993         case SYS_DVBT2:
1994                 strength = cxd2841er_read_agc_gain_t_t2(priv,
1995                                                         p->delivery_system);
1996                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1997                 /* Formula was empirically determinated @ 410 MHz */
1998                 p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
1999                 break;  /* Code moved out of the function */
2000         case SYS_DVBC_ANNEX_A:
2001         case SYS_DVBC_ANNEX_B:
2002         case SYS_DVBC_ANNEX_C:
2003                 strength = cxd2841er_read_agc_gain_c(priv,
2004                                                         p->delivery_system);
2005                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2006                 /*
2007                  * Formula was empirically determinated via linear regression,
2008                  * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
2009                  * stream modulated with QAM64
2010                  */
2011                 p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
2012                 break;
2013         case SYS_ISDBT:
2014                 strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
2015                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2016                 /*
2017                  * Formula was empirically determinated via linear regression,
2018                  * using frequencies: 175 MHz, 410 MHz and 800 MHz.
2019                  */
2020                 p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
2021                 break;
2022         case SYS_DVBS:
2023         case SYS_DVBS2:
2024                 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
2025                 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2026                 p->strength.stat[0].uvalue = strength;
2027                 break;
2028         default:
2029                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2030                 break;
2031         }
2032 }
2033
2034 static void cxd2841er_read_snr(struct dvb_frontend *fe)
2035 {
2036         u32 tmp = 0;
2037         int ret = 0;
2038         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2039         struct cxd2841er_priv *priv = fe->demodulator_priv;
2040
2041         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2042         switch (p->delivery_system) {
2043         case SYS_DVBC_ANNEX_A:
2044         case SYS_DVBC_ANNEX_B:
2045         case SYS_DVBC_ANNEX_C:
2046                 ret = cxd2841er_read_snr_c(priv, &tmp);
2047                 break;
2048         case SYS_DVBT:
2049                 ret = cxd2841er_read_snr_t(priv, &tmp);
2050                 break;
2051         case SYS_DVBT2:
2052                 ret = cxd2841er_read_snr_t2(priv, &tmp);
2053                 break;
2054         case SYS_ISDBT:
2055                 ret = cxd2841er_read_snr_i(priv, &tmp);
2056                 break;
2057         case SYS_DVBS:
2058         case SYS_DVBS2:
2059                 ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
2060                 break;
2061         default:
2062                 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
2063                         __func__, p->delivery_system);
2064                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2065                 return;
2066         }
2067
2068         dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n",
2069                         __func__, (int32_t)tmp);
2070
2071         if (!ret) {
2072                 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2073                 p->cnr.stat[0].svalue = tmp;
2074         } else {
2075                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2076         }
2077 }
2078
2079 static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
2080 {
2081         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2082         struct cxd2841er_priv *priv = fe->demodulator_priv;
2083         u32 ucblocks = 0;
2084
2085         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2086         switch (p->delivery_system) {
2087         case SYS_DVBC_ANNEX_A:
2088         case SYS_DVBC_ANNEX_B:
2089         case SYS_DVBC_ANNEX_C:
2090                 cxd2841er_read_packet_errors_c(priv, &ucblocks);
2091                 break;
2092         case SYS_DVBT:
2093                 cxd2841er_read_packet_errors_t(priv, &ucblocks);
2094                 break;
2095         case SYS_DVBT2:
2096                 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
2097                 break;
2098         case SYS_ISDBT:
2099                 cxd2841er_read_packet_errors_i(priv, &ucblocks);
2100                 break;
2101         default:
2102                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2103                 return;
2104         }
2105         dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks);
2106
2107         p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2108         p->block_error.stat[0].uvalue = ucblocks;
2109 }
2110
2111 static int cxd2841er_dvbt2_set_profile(
2112         struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
2113 {
2114         u8 tune_mode;
2115         u8 seq_not2d_time;
2116
2117         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2118         switch (profile) {
2119         case DVBT2_PROFILE_BASE:
2120                 tune_mode = 0x01;
2121                 /* Set early unlock time */
2122                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
2123                 break;
2124         case DVBT2_PROFILE_LITE:
2125                 tune_mode = 0x05;
2126                 /* Set early unlock time */
2127                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2128                 break;
2129         case DVBT2_PROFILE_ANY:
2130                 tune_mode = 0x00;
2131                 /* Set early unlock time */
2132                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2133                 break;
2134         default:
2135                 return -EINVAL;
2136         }
2137         /* Set SLV-T Bank : 0x2E */
2138         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
2139         /* Set profile and tune mode */
2140         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
2141         /* Set SLV-T Bank : 0x2B */
2142         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2143         /* Set early unlock detection time */
2144         cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
2145         return 0;
2146 }
2147
2148 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
2149                                           u8 is_auto, u8 plp_id)
2150 {
2151         if (is_auto) {
2152                 dev_dbg(&priv->i2c->dev,
2153                         "%s() using auto PLP selection\n", __func__);
2154         } else {
2155                 dev_dbg(&priv->i2c->dev,
2156                         "%s() using manual PLP selection, ID %d\n",
2157                         __func__, plp_id);
2158         }
2159         /* Set SLV-T Bank : 0x23 */
2160         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2161         if (!is_auto) {
2162                 /* Manual PLP selection mode. Set the data PLP Id. */
2163                 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
2164         }
2165         /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
2166         cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
2167         return 0;
2168 }
2169
2170 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
2171                                                 u32 bandwidth)
2172 {
2173         u32 iffreq, ifhz;
2174         u8 data[MAX_WRITE_REGSIZE];
2175
2176         static const uint8_t nominalRate8bw[3][5] = {
2177                 /* TRCG Nominal Rate [37:0] */
2178                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2179                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2180                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2181         };
2182
2183         static const uint8_t nominalRate7bw[3][5] = {
2184                 /* TRCG Nominal Rate [37:0] */
2185                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2186                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2187                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2188         };
2189
2190         static const uint8_t nominalRate6bw[3][5] = {
2191                 /* TRCG Nominal Rate [37:0] */
2192                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2193                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2194                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2195         };
2196
2197         static const uint8_t nominalRate5bw[3][5] = {
2198                 /* TRCG Nominal Rate [37:0] */
2199                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2200                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2201                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2202         };
2203
2204         static const uint8_t nominalRate17bw[3][5] = {
2205                 /* TRCG Nominal Rate [37:0] */
2206                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
2207                 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
2208                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}  /* 41MHz XTal */
2209         };
2210
2211         static const uint8_t itbCoef8bw[3][14] = {
2212                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2213                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2214                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
2215                         0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2216                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2217                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2218         };
2219
2220         static const uint8_t itbCoef7bw[3][14] = {
2221                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2222                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2223                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
2224                         0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2225                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2226                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2227         };
2228
2229         static const uint8_t itbCoef6bw[3][14] = {
2230                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2231                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2232                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2233                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2234                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2235                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2236         };
2237
2238         static const uint8_t itbCoef5bw[3][14] = {
2239                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2240                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2241                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2242                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2243                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2244                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2245         };
2246
2247         static const uint8_t itbCoef17bw[3][14] = {
2248                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2249                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
2250                 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
2251                         0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal   */
2252                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2253                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}  /* 41MHz XTal   */
2254         };
2255
2256         /* Set SLV-T Bank : 0x20 */
2257         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2258
2259         switch (bandwidth) {
2260         case 8000000:
2261                 /* <Timing Recovery setting> */
2262                 cxd2841er_write_regs(priv, I2C_SLVT,
2263                                 0x9F, nominalRate8bw[priv->xtal], 5);
2264
2265                 /* Set SLV-T Bank : 0x27 */
2266                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2267                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2268                                 0x7a, 0x00, 0x0f);
2269
2270                 /* Set SLV-T Bank : 0x10 */
2271                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2272
2273                 /* Group delay equaliser settings for
2274                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2275                  */
2276                 if (priv->flags & CXD2841ER_ASCOT)
2277                         cxd2841er_write_regs(priv, I2C_SLVT,
2278                                 0xA6, itbCoef8bw[priv->xtal], 14);
2279                 /* <IF freq setting> */
2280                 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2281                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2282                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2283                 data[1] = (u8)((iffreq >> 8) & 0xff);
2284                 data[2] = (u8)(iffreq & 0xff);
2285                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2286                 /* System bandwidth setting */
2287                 cxd2841er_set_reg_bits(
2288                                 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2289                 break;
2290         case 7000000:
2291                 /* <Timing Recovery setting> */
2292                 cxd2841er_write_regs(priv, I2C_SLVT,
2293                                 0x9F, nominalRate7bw[priv->xtal], 5);
2294
2295                 /* Set SLV-T Bank : 0x27 */
2296                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2297                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2298                                 0x7a, 0x00, 0x0f);
2299
2300                 /* Set SLV-T Bank : 0x10 */
2301                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2302
2303                 /* Group delay equaliser settings for
2304                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2305                  */
2306                 if (priv->flags & CXD2841ER_ASCOT)
2307                         cxd2841er_write_regs(priv, I2C_SLVT,
2308                                 0xA6, itbCoef7bw[priv->xtal], 14);
2309                 /* <IF freq setting> */
2310                 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2311                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2312                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2313                 data[1] = (u8)((iffreq >> 8) & 0xff);
2314                 data[2] = (u8)(iffreq & 0xff);
2315                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2316                 /* System bandwidth setting */
2317                 cxd2841er_set_reg_bits(
2318                                 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2319                 break;
2320         case 6000000:
2321                 /* <Timing Recovery setting> */
2322                 cxd2841er_write_regs(priv, I2C_SLVT,
2323                                 0x9F, nominalRate6bw[priv->xtal], 5);
2324
2325                 /* Set SLV-T Bank : 0x27 */
2326                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2327                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2328                                 0x7a, 0x00, 0x0f);
2329
2330                 /* Set SLV-T Bank : 0x10 */
2331                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2332
2333                 /* Group delay equaliser settings for
2334                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2335                  */
2336                 if (priv->flags & CXD2841ER_ASCOT)
2337                         cxd2841er_write_regs(priv, I2C_SLVT,
2338                                 0xA6, itbCoef6bw[priv->xtal], 14);
2339                 /* <IF freq setting> */
2340                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2341                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2342                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2343                 data[1] = (u8)((iffreq >> 8) & 0xff);
2344                 data[2] = (u8)(iffreq & 0xff);
2345                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2346                 /* System bandwidth setting */
2347                 cxd2841er_set_reg_bits(
2348                                 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2349                 break;
2350         case 5000000:
2351                 /* <Timing Recovery setting> */
2352                 cxd2841er_write_regs(priv, I2C_SLVT,
2353                                 0x9F, nominalRate5bw[priv->xtal], 5);
2354
2355                 /* Set SLV-T Bank : 0x27 */
2356                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2357                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2358                                 0x7a, 0x00, 0x0f);
2359
2360                 /* Set SLV-T Bank : 0x10 */
2361                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2362
2363                 /* Group delay equaliser settings for
2364                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2365                  */
2366                 if (priv->flags & CXD2841ER_ASCOT)
2367                         cxd2841er_write_regs(priv, I2C_SLVT,
2368                                 0xA6, itbCoef5bw[priv->xtal], 14);
2369                 /* <IF freq setting> */
2370                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2371                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2372                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2373                 data[1] = (u8)((iffreq >> 8) & 0xff);
2374                 data[2] = (u8)(iffreq & 0xff);
2375                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2376                 /* System bandwidth setting */
2377                 cxd2841er_set_reg_bits(
2378                                 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2379                 break;
2380         case 1712000:
2381                 /* <Timing Recovery setting> */
2382                 cxd2841er_write_regs(priv, I2C_SLVT,
2383                                 0x9F, nominalRate17bw[priv->xtal], 5);
2384
2385                 /* Set SLV-T Bank : 0x27 */
2386                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2387                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2388                                 0x7a, 0x03, 0x0f);
2389
2390                 /* Set SLV-T Bank : 0x10 */
2391                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2392
2393                 /* Group delay equaliser settings for
2394                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2395                  */
2396                 if (priv->flags & CXD2841ER_ASCOT)
2397                         cxd2841er_write_regs(priv, I2C_SLVT,
2398                                 0xA6, itbCoef17bw[priv->xtal], 14);
2399                 /* <IF freq setting> */
2400                 ifhz = cxd2841er_get_if_hz(priv, 3500000);
2401                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2402                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2403                 data[1] = (u8)((iffreq >> 8) & 0xff);
2404                 data[2] = (u8)(iffreq & 0xff);
2405                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2406                 /* System bandwidth setting */
2407                 cxd2841er_set_reg_bits(
2408                                 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
2409                 break;
2410         default:
2411                 return -EINVAL;
2412         }
2413         return 0;
2414 }
2415
2416 static int cxd2841er_sleep_tc_to_active_t_band(
2417                 struct cxd2841er_priv *priv, u32 bandwidth)
2418 {
2419         u8 data[MAX_WRITE_REGSIZE];
2420         u32 iffreq, ifhz;
2421         static const u8 nominalRate8bw[3][5] = {
2422                 /* TRCG Nominal Rate [37:0] */
2423                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2424                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2425                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2426         };
2427         static const u8 nominalRate7bw[3][5] = {
2428                 /* TRCG Nominal Rate [37:0] */
2429                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2430                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2431                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2432         };
2433         static const u8 nominalRate6bw[3][5] = {
2434                 /* TRCG Nominal Rate [37:0] */
2435                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2436                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2437                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2438         };
2439         static const u8 nominalRate5bw[3][5] = {
2440                 /* TRCG Nominal Rate [37:0] */
2441                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2442                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2443                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2444         };
2445
2446         static const u8 itbCoef8bw[3][14] = {
2447                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2448                         0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2449                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2450                         0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2451                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2452                         0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2453         };
2454         static const u8 itbCoef7bw[3][14] = {
2455                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2456                         0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2457                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2458                         0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2459                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2460                         0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2461         };
2462         static const u8 itbCoef6bw[3][14] = {
2463                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2464                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2465                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2466                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2467                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2468                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2469         };
2470         static const u8 itbCoef5bw[3][14] = {
2471                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2472                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2473                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2474                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2475                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2476                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2477         };
2478
2479         /* Set SLV-T Bank : 0x13 */
2480         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2481         /* Echo performance optimization setting */
2482         data[0] = 0x01;
2483         data[1] = 0x14;
2484         cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2485
2486         /* Set SLV-T Bank : 0x10 */
2487         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2488
2489         switch (bandwidth) {
2490         case 8000000:
2491                 /* <Timing Recovery setting> */
2492                 cxd2841er_write_regs(priv, I2C_SLVT,
2493                                 0x9F, nominalRate8bw[priv->xtal], 5);
2494                 /* Group delay equaliser settings for
2495                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2496                 */
2497                 if (priv->flags & CXD2841ER_ASCOT)
2498                         cxd2841er_write_regs(priv, I2C_SLVT,
2499                                 0xA6, itbCoef8bw[priv->xtal], 14);
2500                 /* <IF freq setting> */
2501                 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2502                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2503                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2504                 data[1] = (u8)((iffreq >> 8) & 0xff);
2505                 data[2] = (u8)(iffreq & 0xff);
2506                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2507                 /* System bandwidth setting */
2508                 cxd2841er_set_reg_bits(
2509                         priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2510
2511                 /* Demod core latency setting */
2512                 if (priv->xtal == SONY_XTAL_24000) {
2513                         data[0] = 0x15;
2514                         data[1] = 0x28;
2515                 } else {
2516                         data[0] = 0x01;
2517                         data[1] = 0xE0;
2518                 }
2519                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2520
2521                 /* Notch filter setting */
2522                 data[0] = 0x01;
2523                 data[1] = 0x02;
2524                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2525                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2526                 break;
2527         case 7000000:
2528                 /* <Timing Recovery setting> */
2529                 cxd2841er_write_regs(priv, I2C_SLVT,
2530                                 0x9F, nominalRate7bw[priv->xtal], 5);
2531                 /* Group delay equaliser settings for
2532                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2533                 */
2534                 if (priv->flags & CXD2841ER_ASCOT)
2535                         cxd2841er_write_regs(priv, I2C_SLVT,
2536                                 0xA6, itbCoef7bw[priv->xtal], 14);
2537                 /* <IF freq setting> */
2538                 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2539                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2540                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2541                 data[1] = (u8)((iffreq >> 8) & 0xff);
2542                 data[2] = (u8)(iffreq & 0xff);
2543                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2544                 /* System bandwidth setting */
2545                 cxd2841er_set_reg_bits(
2546                         priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2547
2548                 /* Demod core latency setting */
2549                 if (priv->xtal == SONY_XTAL_24000) {
2550                         data[0] = 0x1F;
2551                         data[1] = 0xF8;
2552                 } else {
2553                         data[0] = 0x12;
2554                         data[1] = 0xF8;
2555                 }
2556                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2557
2558                 /* Notch filter setting */
2559                 data[0] = 0x00;
2560                 data[1] = 0x03;
2561                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2562                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2563                 break;
2564         case 6000000:
2565                 /* <Timing Recovery setting> */
2566                 cxd2841er_write_regs(priv, I2C_SLVT,
2567                                 0x9F, nominalRate6bw[priv->xtal], 5);
2568                 /* Group delay equaliser settings for
2569                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2570                 */
2571                 if (priv->flags & CXD2841ER_ASCOT)
2572                         cxd2841er_write_regs(priv, I2C_SLVT,
2573                                 0xA6, itbCoef6bw[priv->xtal], 14);
2574                 /* <IF freq setting> */
2575                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2576                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2577                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2578                 data[1] = (u8)((iffreq >> 8) & 0xff);
2579                 data[2] = (u8)(iffreq & 0xff);
2580                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2581                 /* System bandwidth setting */
2582                 cxd2841er_set_reg_bits(
2583                         priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2584
2585                 /* Demod core latency setting */
2586                 if (priv->xtal == SONY_XTAL_24000) {
2587                         data[0] = 0x25;
2588                         data[1] = 0x4C;
2589                 } else {
2590                         data[0] = 0x1F;
2591                         data[1] = 0xDC;
2592                 }
2593                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2594
2595                 /* Notch filter setting */
2596                 data[0] = 0x00;
2597                 data[1] = 0x03;
2598                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2599                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2600                 break;
2601         case 5000000:
2602                 /* <Timing Recovery setting> */
2603                 cxd2841er_write_regs(priv, I2C_SLVT,
2604                                 0x9F, nominalRate5bw[priv->xtal], 5);
2605                 /* Group delay equaliser settings for
2606                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2607                 */
2608                 if (priv->flags & CXD2841ER_ASCOT)
2609                         cxd2841er_write_regs(priv, I2C_SLVT,
2610                                 0xA6, itbCoef5bw[priv->xtal], 14);
2611                 /* <IF freq setting> */
2612                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2613                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2614                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2615                 data[1] = (u8)((iffreq >> 8) & 0xff);
2616                 data[2] = (u8)(iffreq & 0xff);
2617                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2618                 /* System bandwidth setting */
2619                 cxd2841er_set_reg_bits(
2620                         priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2621
2622                 /* Demod core latency setting */
2623                 if (priv->xtal == SONY_XTAL_24000) {
2624                         data[0] = 0x2C;
2625                         data[1] = 0xC2;
2626                 } else {
2627                         data[0] = 0x26;
2628                         data[1] = 0x3C;
2629                 }
2630                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2631
2632                 /* Notch filter setting */
2633                 data[0] = 0x00;
2634                 data[1] = 0x03;
2635                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2636                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2637                 break;
2638         }
2639
2640         return 0;
2641 }
2642
2643 static int cxd2841er_sleep_tc_to_active_i_band(
2644                 struct cxd2841er_priv *priv, u32 bandwidth)
2645 {
2646         u32 iffreq, ifhz;
2647         u8 data[3];
2648
2649         /* TRCG Nominal Rate */
2650         static const u8 nominalRate8bw[3][5] = {
2651                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2652                 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2653                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2654         };
2655
2656         static const u8 nominalRate7bw[3][5] = {
2657                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2658                 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2659                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2660         };
2661
2662         static const u8 nominalRate6bw[3][5] = {
2663                 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2664                 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2665                 {0x14, 0x2E, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2666         };
2667
2668         static const u8 itbCoef8bw[3][14] = {
2669                 {0x00}, /* 20.5MHz XTal */
2670                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2671                         0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2672                 {0x0}, /* 41MHz XTal   */
2673         };
2674
2675         static const u8 itbCoef7bw[3][14] = {
2676                 {0x00}, /* 20.5MHz XTal */
2677                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2678                         0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2679                 {0x00}, /* 41MHz XTal   */
2680         };
2681
2682         static const u8 itbCoef6bw[3][14] = {
2683                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2684                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2685                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2686                         0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal   */
2687                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2688                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal   */
2689         };
2690
2691         dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2692         /* Set SLV-T Bank : 0x10 */
2693         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2694
2695         /*  20.5/41MHz Xtal support is not available
2696          *  on ISDB-T 7MHzBW and 8MHzBW
2697         */
2698         if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2699                 dev_err(&priv->i2c->dev,
2700                         "%s(): bandwidth %d supported only for 24MHz xtal\n",
2701                         __func__, bandwidth);
2702                 return -EINVAL;
2703         }
2704
2705         switch (bandwidth) {
2706         case 8000000:
2707                 /* TRCG Nominal Rate */
2708                 cxd2841er_write_regs(priv, I2C_SLVT,
2709                                 0x9F, nominalRate8bw[priv->xtal], 5);
2710                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2711                 if (priv->flags & CXD2841ER_ASCOT)
2712                         cxd2841er_write_regs(priv, I2C_SLVT,
2713                                 0xA6, itbCoef8bw[priv->xtal], 14);
2714
2715                 /* IF freq setting */
2716                 ifhz = cxd2841er_get_if_hz(priv, 4750000);
2717                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2718                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2719                 data[1] = (u8)((iffreq >> 8) & 0xff);
2720                 data[2] = (u8)(iffreq & 0xff);
2721                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2722
2723                 /* System bandwidth setting */
2724                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2725
2726                 /* Demod core latency setting */
2727                 data[0] = 0x13;
2728                 data[1] = 0xFC;
2729                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2730
2731                 /* Acquisition optimization setting */
2732                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2733                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2734                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2735                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2736                 break;
2737         case 7000000:
2738                 /* TRCG Nominal Rate */
2739                 cxd2841er_write_regs(priv, I2C_SLVT,
2740                                 0x9F, nominalRate7bw[priv->xtal], 5);
2741                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2742                 if (priv->flags & CXD2841ER_ASCOT)
2743                         cxd2841er_write_regs(priv, I2C_SLVT,
2744                                 0xA6, itbCoef7bw[priv->xtal], 14);
2745
2746                 /* IF freq setting */
2747                 ifhz = cxd2841er_get_if_hz(priv, 4150000);
2748                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2749                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2750                 data[1] = (u8)((iffreq >> 8) & 0xff);
2751                 data[2] = (u8)(iffreq & 0xff);
2752                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2753
2754                 /* System bandwidth setting */
2755                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2756
2757                 /* Demod core latency setting */
2758                 data[0] = 0x1A;
2759                 data[1] = 0xFA;
2760                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2761
2762                 /* Acquisition optimization setting */
2763                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2764                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2765                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2766                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2767                 break;
2768         case 6000000:
2769                 /* TRCG Nominal Rate */
2770                 cxd2841er_write_regs(priv, I2C_SLVT,
2771                                 0x9F, nominalRate6bw[priv->xtal], 5);
2772                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2773                 if (priv->flags & CXD2841ER_ASCOT)
2774                         cxd2841er_write_regs(priv, I2C_SLVT,
2775                                 0xA6, itbCoef6bw[priv->xtal], 14);
2776
2777                 /* IF freq setting */
2778                 ifhz = cxd2841er_get_if_hz(priv, 3550000);
2779                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2780                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2781                 data[1] = (u8)((iffreq >> 8) & 0xff);
2782                 data[2] = (u8)(iffreq & 0xff);
2783                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2784
2785                 /* System bandwidth setting */
2786                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2787
2788                 /* Demod core latency setting */
2789                 if (priv->xtal == SONY_XTAL_24000) {
2790                         data[0] = 0x1F;
2791                         data[1] = 0x79;
2792                 } else {
2793                         data[0] = 0x1A;
2794                         data[1] = 0xE2;
2795                 }
2796                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2797
2798                 /* Acquisition optimization setting */
2799                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2800                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2801                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2802                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2803                 break;
2804         default:
2805                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2806                                 __func__, bandwidth);
2807                 return -EINVAL;
2808         }
2809         return 0;
2810 }
2811
2812 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2813                                                u32 bandwidth)
2814 {
2815         u8 bw7_8mhz_b10_a6[] = {
2816                 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2817                 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2818         u8 bw6mhz_b10_a6[] = {
2819                 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2820                 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2821         u8 b10_b6[3];
2822         u32 iffreq, ifhz;
2823
2824         if (bandwidth != 6000000 &&
2825                         bandwidth != 7000000 &&
2826                         bandwidth != 8000000) {
2827                 dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n",
2828                                 __func__, bandwidth);
2829                 bandwidth = 8000000;
2830         }
2831
2832         dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
2833         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2834         switch (bandwidth) {
2835         case 8000000:
2836         case 7000000:
2837                 if (priv->flags & CXD2841ER_ASCOT)
2838                         cxd2841er_write_regs(
2839                                 priv, I2C_SLVT, 0xa6,
2840                                 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2841                 ifhz = cxd2841er_get_if_hz(priv, 4900000);
2842                 iffreq = cxd2841er_calc_iffreq(ifhz);
2843                 break;
2844         case 6000000:
2845                 if (priv->flags & CXD2841ER_ASCOT)
2846                         cxd2841er_write_regs(
2847                                 priv, I2C_SLVT, 0xa6,
2848                                 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2849                 ifhz = cxd2841er_get_if_hz(priv, 3700000);
2850                 iffreq = cxd2841er_calc_iffreq(ifhz);
2851                 break;
2852         default:
2853                 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2854                         __func__, bandwidth);
2855                 return -EINVAL;
2856         }
2857         /* <IF freq setting> */
2858         b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2859         b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2860         b10_b6[2] = (u8)(iffreq & 0xff);
2861         cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2862         /* Set SLV-T Bank : 0x11 */
2863         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2864         switch (bandwidth) {
2865         case 8000000:
2866         case 7000000:
2867                 cxd2841er_set_reg_bits(
2868                         priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2869                 break;
2870         case 6000000:
2871                 cxd2841er_set_reg_bits(
2872                         priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2873                 break;
2874         }
2875         /* Set SLV-T Bank : 0x40 */
2876         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2877         switch (bandwidth) {
2878         case 8000000:
2879                 cxd2841er_set_reg_bits(
2880                         priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2881                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x3e);
2882                 break;
2883         case 7000000:
2884                 cxd2841er_set_reg_bits(
2885                         priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2886                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0xd6);
2887                 break;
2888         case 6000000:
2889                 cxd2841er_set_reg_bits(
2890                         priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2891                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x6e);
2892                 break;
2893         }
2894         return 0;
2895 }
2896
2897 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2898                                           u32 bandwidth)
2899 {
2900         u8 data[2] = { 0x09, 0x54 };
2901         u8 data24m[3] = {0xDC, 0x6C, 0x00};
2902
2903         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2904         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2905         /* Set SLV-X Bank : 0x00 */
2906         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2907         /* Set demod mode */
2908         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2909         /* Set SLV-T Bank : 0x00 */
2910         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2911         /* Enable demod clock */
2912         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2913         /* Disable RF level monitor */
2914         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2915         /* Enable ADC clock */
2916         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2917         /* Enable ADC 1 */
2918         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2919         /* Enable ADC 2 & 3 */
2920         if (priv->xtal == SONY_XTAL_41000) {
2921                 data[0] = 0x0A;
2922                 data[1] = 0xD4;
2923         }
2924         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2925         /* Enable ADC 4 */
2926         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2927         /* Set SLV-T Bank : 0x10 */
2928         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2929         /* IFAGC gain settings */
2930         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2931         /* Set SLV-T Bank : 0x11 */
2932         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2933         /* BBAGC TARGET level setting */
2934         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2935         /* Set SLV-T Bank : 0x10 */
2936         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2937         /* ASCOT setting */
2938         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
2939                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
2940         /* Set SLV-T Bank : 0x18 */
2941         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2942         /* Pre-RS BER monitor setting */
2943         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2944         /* FEC Auto Recovery setting */
2945         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2946         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2947         /* Set SLV-T Bank : 0x00 */
2948         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2949         /* TSIF setting */
2950         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2951         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2952
2953         if (priv->xtal == SONY_XTAL_24000) {
2954                 /* Set SLV-T Bank : 0x10 */
2955                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2956                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2957                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2958                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2959         }
2960
2961         cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2962         /* Set SLV-T Bank : 0x00 */
2963         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2964         /* Disable HiZ Setting 1 */
2965         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2966         /* Disable HiZ Setting 2 */
2967         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2968         priv->state = STATE_ACTIVE_TC;
2969         return 0;
2970 }
2971
2972 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2973                                            u32 bandwidth)
2974 {
2975         u8 data[MAX_WRITE_REGSIZE];
2976
2977         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2978         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2979         /* Set SLV-X Bank : 0x00 */
2980         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2981         /* Set demod mode */
2982         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2983         /* Set SLV-T Bank : 0x00 */
2984         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2985         /* Enable demod clock */
2986         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2987         /* Disable RF level monitor */
2988         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
2989         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2990         /* Enable ADC clock */
2991         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2992         /* Enable ADC 1 */
2993         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2994
2995         if (priv->xtal == SONY_XTAL_41000) {
2996                 data[0] = 0x0A;
2997                 data[1] = 0xD4;
2998         } else {
2999                 data[0] = 0x09;
3000                 data[1] = 0x54;
3001         }
3002
3003         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3004         /* Enable ADC 4 */
3005         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3006         /* Set SLV-T Bank : 0x10 */
3007         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3008         /* IFAGC gain settings */
3009         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
3010         /* Set SLV-T Bank : 0x11 */
3011         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3012         /* BBAGC TARGET level setting */
3013         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
3014         /* Set SLV-T Bank : 0x10 */
3015         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3016         /* ASCOT setting */
3017         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3018                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3019         /* Set SLV-T Bank : 0x20 */
3020         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3021         /* Acquisition optimization setting */
3022         cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
3023         /* Set SLV-T Bank : 0x2b */
3024         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3025         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
3026         /* Set SLV-T Bank : 0x23 */
3027         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
3028         /* L1 Control setting */
3029         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
3030         /* Set SLV-T Bank : 0x00 */
3031         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3032         /* TSIF setting */
3033         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3034         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3035         /* DVB-T2 initial setting */
3036         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
3037         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
3038         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
3039         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
3040         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
3041         /* Set SLV-T Bank : 0x2a */
3042         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
3043         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
3044         /* Set SLV-T Bank : 0x2b */
3045         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3046         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
3047
3048         /* 24MHz Xtal setting */
3049         if (priv->xtal == SONY_XTAL_24000) {
3050                 /* Set SLV-T Bank : 0x11 */
3051                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3052                 data[0] = 0xEB;
3053                 data[1] = 0x03;
3054                 data[2] = 0x3B;
3055                 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
3056
3057                 /* Set SLV-T Bank : 0x20 */
3058                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3059                 data[0] = 0x5E;
3060                 data[1] = 0x5E;
3061                 data[2] = 0x47;
3062                 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
3063
3064                 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
3065
3066                 data[0] = 0x3F;
3067                 data[1] = 0xFF;
3068                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
3069
3070                 /* Set SLV-T Bank : 0x24 */
3071                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
3072                 data[0] = 0x0B;
3073                 data[1] = 0x72;
3074                 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
3075
3076                 data[0] = 0x93;
3077                 data[1] = 0xF3;
3078                 data[2] = 0x00;
3079                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
3080
3081                 data[0] = 0x05;
3082                 data[1] = 0xB8;
3083                 data[2] = 0xD8;
3084                 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
3085
3086                 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
3087
3088                 /* Set SLV-T Bank : 0x25 */
3089                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
3090                 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
3091
3092                 /* Set SLV-T Bank : 0x27 */
3093                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
3094                 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
3095
3096                 /* Set SLV-T Bank : 0x2B */
3097                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
3098                 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
3099                 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
3100
3101                 /* Set SLV-T Bank : 0x2D */
3102                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
3103                 data[0] = 0x89;
3104                 data[1] = 0x89;
3105                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
3106
3107                 /* Set SLV-T Bank : 0x5E */
3108                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
3109                 data[0] = 0x24;
3110                 data[1] = 0x95;
3111                 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
3112         }
3113
3114         cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
3115
3116         /* Set SLV-T Bank : 0x00 */
3117         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3118         /* Disable HiZ Setting 1 */
3119         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3120         /* Disable HiZ Setting 2 */
3121         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3122         priv->state = STATE_ACTIVE_TC;
3123         return 0;
3124 }
3125
3126 /* ISDB-Tb part */
3127 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
3128                 u32 bandwidth)
3129 {
3130         u8 data[2] = { 0x09, 0x54 };
3131         u8 data24m[2] = {0x60, 0x00};
3132         u8 data24m2[3] = {0xB7, 0x1B, 0x00};
3133
3134         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3135         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
3136         /* Set SLV-X Bank : 0x00 */
3137         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3138         /* Set demod mode */
3139         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
3140         /* Set SLV-T Bank : 0x00 */
3141         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3142         /* Enable demod clock */
3143         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3144         /* Enable RF level monitor */
3145         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
3146         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
3147         /* Enable ADC clock */
3148         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3149         /* Enable ADC 1 */
3150         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3151         /* xtal freq 20.5MHz or 24M */
3152         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3153         /* Enable ADC 4 */
3154         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3155         /* ASCOT setting */
3156         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3157                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3158         /* FEC Auto Recovery setting */
3159         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
3160         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
3161         /* ISDB-T initial setting */
3162         /* Set SLV-T Bank : 0x00 */
3163         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3164         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
3165         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
3166         /* Set SLV-T Bank : 0x10 */
3167         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3168         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
3169         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
3170         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
3171         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
3172         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
3173         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
3174         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
3175         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
3176         /* Set SLV-T Bank : 0x15 */
3177         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
3178         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
3179         /* Set SLV-T Bank : 0x1E */
3180         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
3181         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
3182         /* Set SLV-T Bank : 0x63 */
3183         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
3184         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
3185
3186         /* for xtal 24MHz */
3187         /* Set SLV-T Bank : 0x10 */
3188         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3189         cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
3190         /* Set SLV-T Bank : 0x60 */
3191         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
3192         cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
3193
3194         cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
3195         /* Set SLV-T Bank : 0x00 */
3196         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3197         /* Disable HiZ Setting 1 */
3198         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3199         /* Disable HiZ Setting 2 */
3200         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3201         priv->state = STATE_ACTIVE_TC;
3202         return 0;
3203 }
3204
3205 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
3206                                           u32 bandwidth)
3207 {
3208         u8 data[2] = { 0x09, 0x54 };
3209
3210         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3211         cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
3212         /* Set SLV-X Bank : 0x00 */
3213         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3214         /* Set demod mode */
3215         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
3216         /* Set SLV-T Bank : 0x00 */
3217         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3218         /* Enable demod clock */
3219         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3220         /* Disable RF level monitor */
3221         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
3222         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
3223         /* Enable ADC clock */
3224         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3225         /* Enable ADC 1 */
3226         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3227         /* xtal freq 20.5MHz */
3228         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3229         /* Enable ADC 4 */
3230         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3231         /* Set SLV-T Bank : 0x10 */
3232         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3233         /* IFAGC gain settings */
3234         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
3235         /* Set SLV-T Bank : 0x11 */
3236         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3237         /* BBAGC TARGET level setting */
3238         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
3239         /* Set SLV-T Bank : 0x10 */
3240         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3241         /* ASCOT setting */
3242         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3243                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3244         /* Set SLV-T Bank : 0x40 */
3245         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
3246         /* Demod setting */
3247         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
3248         /* Set SLV-T Bank : 0x00 */
3249         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3250         /* TSIF setting */
3251         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3252         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3253
3254         cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
3255         /* Set SLV-T Bank : 0x00 */
3256         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3257         /* Disable HiZ Setting 1 */
3258         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3259         /* Disable HiZ Setting 2 */
3260         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3261         priv->state = STATE_ACTIVE_TC;
3262         return 0;
3263 }
3264
3265 static int cxd2841er_get_frontend(struct dvb_frontend *fe,
3266                                   struct dtv_frontend_properties *p)
3267 {
3268         enum fe_status status = 0;
3269         struct cxd2841er_priv *priv = fe->demodulator_priv;
3270
3271         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3272         if (priv->state == STATE_ACTIVE_S)
3273                 cxd2841er_read_status_s(fe, &status);
3274         else if (priv->state == STATE_ACTIVE_TC)
3275                 cxd2841er_read_status_tc(fe, &status);
3276
3277         if (priv->state == STATE_ACTIVE_TC || priv->state == STATE_ACTIVE_S)
3278                 cxd2841er_read_signal_strength(fe);
3279         else
3280                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3281
3282         if (status & FE_HAS_LOCK) {
3283                 if (priv->stats_time &&
3284                     (!time_after(jiffies, priv->stats_time)))
3285                         return 0;
3286
3287                 /* Prevent retrieving stats faster than once per second */
3288                 priv->stats_time = jiffies + msecs_to_jiffies(1000);
3289
3290                 cxd2841er_read_snr(fe);
3291                 cxd2841er_read_ucblocks(fe);
3292                 cxd2841er_read_ber(fe);
3293         } else {
3294                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3295                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3296                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3297                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3298         }
3299         return 0;
3300 }
3301
3302 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
3303 {
3304         int ret = 0, i, timeout, carr_offset;
3305         enum fe_status status;
3306         struct cxd2841er_priv *priv = fe->demodulator_priv;
3307         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3308         u32 symbol_rate = p->symbol_rate/1000;
3309
3310         dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
3311                 __func__,
3312                 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
3313                  p->frequency, symbol_rate, priv->xtal);
3314
3315         if (priv->flags & CXD2841ER_EARLY_TUNE)
3316                 cxd2841er_tuner_set(fe);
3317
3318         switch (priv->state) {
3319         case STATE_SLEEP_S:
3320                 ret = cxd2841er_sleep_s_to_active_s(
3321                         priv, p->delivery_system, symbol_rate);
3322                 break;
3323         case STATE_ACTIVE_S:
3324                 ret = cxd2841er_retune_active(priv, p);
3325                 break;
3326         default:
3327                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3328                         __func__, priv->state);
3329                 ret = -EINVAL;
3330                 goto done;
3331         }
3332         if (ret) {
3333                 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3334                 goto done;
3335         }
3336
3337         if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3338                 cxd2841er_tuner_set(fe);
3339
3340         cxd2841er_tune_done(priv);
3341         timeout = DIV_ROUND_UP(3000000, symbol_rate) + 150;
3342
3343         i = 0;
3344         do {
3345                 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3346                         (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3347                 cxd2841er_read_status_s(fe, &status);
3348                 if (status & FE_HAS_LOCK)
3349                         break;
3350                 i++;
3351         } while (i < timeout / CXD2841ER_DVBS_POLLING_INVL);
3352
3353         if (status & FE_HAS_LOCK) {
3354                 if (cxd2841er_get_carrier_offset_s_s2(
3355                                 priv, &carr_offset)) {
3356                         ret = -EINVAL;
3357                         goto done;
3358                 }
3359                 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3360                         __func__, carr_offset);
3361         }
3362 done:
3363         /* Reset stats */
3364         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3365         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3366         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3367         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3368         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3369
3370         /* Reset the wait for jiffies logic */
3371         priv->stats_time = 0;
3372
3373         return ret;
3374 }
3375
3376 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3377 {
3378         int ret = 0, timeout;
3379         enum fe_status status;
3380         struct cxd2841er_priv *priv = fe->demodulator_priv;
3381         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3382
3383         dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3384                  __func__, p->delivery_system, p->bandwidth_hz);
3385
3386         if (priv->flags & CXD2841ER_EARLY_TUNE)
3387                 cxd2841er_tuner_set(fe);
3388
3389         /* deconfigure/put demod to sleep on delsys switch if active */
3390         if (priv->state == STATE_ACTIVE_TC &&
3391             priv->system != p->delivery_system) {
3392                 dev_dbg(&priv->i2c->dev, "%s(): old_delsys=%d, new_delsys=%d -> sleep\n",
3393                          __func__, priv->system, p->delivery_system);
3394                 cxd2841er_sleep_tc(fe);
3395         }
3396
3397         if (p->delivery_system == SYS_DVBT) {
3398                 priv->system = SYS_DVBT;
3399                 switch (priv->state) {
3400                 case STATE_SLEEP_TC:
3401                         ret = cxd2841er_sleep_tc_to_active_t(
3402                                 priv, p->bandwidth_hz);
3403                         break;
3404                 case STATE_ACTIVE_TC:
3405                         ret = cxd2841er_retune_active(priv, p);
3406                         break;
3407                 default:
3408                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3409                                 __func__, priv->state);
3410                         ret = -EINVAL;
3411                 }
3412         } else if (p->delivery_system == SYS_DVBT2) {
3413                 priv->system = SYS_DVBT2;
3414                 cxd2841er_dvbt2_set_plp_config(priv,
3415                         (int)(p->stream_id > 255), p->stream_id);
3416                 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3417                 switch (priv->state) {
3418                 case STATE_SLEEP_TC:
3419                         ret = cxd2841er_sleep_tc_to_active_t2(priv,
3420                                 p->bandwidth_hz);
3421                         break;
3422                 case STATE_ACTIVE_TC:
3423                         ret = cxd2841er_retune_active(priv, p);
3424                         break;
3425                 default:
3426                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3427                                 __func__, priv->state);
3428                         ret = -EINVAL;
3429                 }
3430         } else if (p->delivery_system == SYS_ISDBT) {
3431                 priv->system = SYS_ISDBT;
3432                 switch (priv->state) {
3433                 case STATE_SLEEP_TC:
3434                         ret = cxd2841er_sleep_tc_to_active_i(
3435                                         priv, p->bandwidth_hz);
3436                         break;
3437                 case STATE_ACTIVE_TC:
3438                         ret = cxd2841er_retune_active(priv, p);
3439                         break;
3440                 default:
3441                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3442                                         __func__, priv->state);
3443                         ret = -EINVAL;
3444                 }
3445         } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3446                         p->delivery_system == SYS_DVBC_ANNEX_C) {
3447                 priv->system = SYS_DVBC_ANNEX_A;
3448                 /* correct bandwidth */
3449                 if (p->bandwidth_hz != 6000000 &&
3450                                 p->bandwidth_hz != 7000000 &&
3451                                 p->bandwidth_hz != 8000000) {
3452                         p->bandwidth_hz = 8000000;
3453                         dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3454                                         __func__, p->bandwidth_hz);
3455                 }
3456
3457                 switch (priv->state) {
3458                 case STATE_SLEEP_TC:
3459                         ret = cxd2841er_sleep_tc_to_active_c(
3460                                 priv, p->bandwidth_hz);
3461                         break;
3462                 case STATE_ACTIVE_TC:
3463                         ret = cxd2841er_retune_active(priv, p);
3464                         break;
3465                 default:
3466                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3467                                 __func__, priv->state);
3468                         ret = -EINVAL;
3469                 }
3470         } else {
3471                 dev_dbg(&priv->i2c->dev,
3472                         "%s(): invalid delivery system %d\n",
3473                         __func__, p->delivery_system);
3474                 ret = -EINVAL;
3475         }
3476         if (ret)
3477                 goto done;
3478
3479         if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3480                 cxd2841er_tuner_set(fe);
3481
3482         cxd2841er_tune_done(priv);
3483
3484         if (priv->flags & CXD2841ER_NO_WAIT_LOCK)
3485                 goto done;
3486
3487         timeout = 2500;
3488         while (timeout > 0) {
3489                 ret = cxd2841er_read_status_tc(fe, &status);
3490                 if (ret)
3491                         goto done;
3492                 if (status & FE_HAS_LOCK)
3493                         break;
3494                 msleep(20);
3495                 timeout -= 20;
3496         }
3497         if (timeout < 0)
3498                 dev_dbg(&priv->i2c->dev,
3499                         "%s(): LOCK wait timeout\n", __func__);
3500 done:
3501         return ret;
3502 }
3503
3504 static int cxd2841er_tune_s(struct dvb_frontend *fe,
3505                             bool re_tune,
3506                             unsigned int mode_flags,
3507                             unsigned int *delay,
3508                             enum fe_status *status)
3509 {
3510         int ret, carrier_offset;
3511         struct cxd2841er_priv *priv = fe->demodulator_priv;
3512         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3513
3514         dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3515         if (re_tune) {
3516                 ret = cxd2841er_set_frontend_s(fe);
3517                 if (ret)
3518                         return ret;
3519                 cxd2841er_read_status_s(fe, status);
3520                 if (*status & FE_HAS_LOCK) {
3521                         if (cxd2841er_get_carrier_offset_s_s2(
3522                                         priv, &carrier_offset))
3523                                 return -EINVAL;
3524                         p->frequency += carrier_offset;
3525                         ret = cxd2841er_set_frontend_s(fe);
3526                         if (ret)
3527                                 return ret;
3528                 }
3529         }
3530         *delay = HZ / 5;
3531         return cxd2841er_read_status_s(fe, status);
3532 }
3533
3534 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3535                              bool re_tune,
3536                              unsigned int mode_flags,
3537                              unsigned int *delay,
3538                              enum fe_status *status)
3539 {
3540         int ret, carrier_offset;
3541         struct cxd2841er_priv *priv = fe->demodulator_priv;
3542         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3543
3544         dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3545                         re_tune, p->bandwidth_hz);
3546         if (re_tune) {
3547                 ret = cxd2841er_set_frontend_tc(fe);
3548                 if (ret)
3549                         return ret;
3550                 cxd2841er_read_status_tc(fe, status);
3551                 if (*status & FE_HAS_LOCK) {
3552                         switch (priv->system) {
3553                         case SYS_ISDBT:
3554                                 ret = cxd2841er_get_carrier_offset_i(
3555                                                 priv, p->bandwidth_hz,
3556                                                 &carrier_offset);
3557                                 if (ret)
3558                                         return ret;
3559                                 break;
3560                         case SYS_DVBT:
3561                                 ret = cxd2841er_get_carrier_offset_t(
3562                                         priv, p->bandwidth_hz,
3563                                         &carrier_offset);
3564                                 if (ret)
3565                                         return ret;
3566                                 break;
3567                         case SYS_DVBT2:
3568                                 ret = cxd2841er_get_carrier_offset_t2(
3569                                         priv, p->bandwidth_hz,
3570                                         &carrier_offset);
3571                                 if (ret)
3572                                         return ret;
3573                                 break;
3574                         case SYS_DVBC_ANNEX_A:
3575                                 ret = cxd2841er_get_carrier_offset_c(
3576                                         priv, &carrier_offset);
3577                                 if (ret)
3578                                         return ret;
3579                                 break;
3580                         default:
3581                                 dev_dbg(&priv->i2c->dev,
3582                                         "%s(): invalid delivery system %d\n",
3583                                         __func__, priv->system);
3584                                 return -EINVAL;
3585                         }
3586                         dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3587                                 __func__, carrier_offset);
3588                         p->frequency += carrier_offset;
3589                         ret = cxd2841er_set_frontend_tc(fe);
3590                         if (ret)
3591                                 return ret;
3592                 }
3593         }
3594         *delay = HZ / 5;
3595         return cxd2841er_read_status_tc(fe, status);
3596 }
3597
3598 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3599 {
3600         struct cxd2841er_priv *priv = fe->demodulator_priv;
3601
3602         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3603         cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3604         cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3605         return 0;
3606 }
3607
3608 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3609 {
3610         struct cxd2841er_priv *priv = fe->demodulator_priv;
3611
3612         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3613
3614         if (priv->state == STATE_ACTIVE_TC) {
3615                 switch (priv->system) {
3616                 case SYS_DVBT:
3617                         cxd2841er_active_t_to_sleep_tc(priv);
3618                         break;
3619                 case SYS_DVBT2:
3620                         cxd2841er_active_t2_to_sleep_tc(priv);
3621                         break;
3622                 case SYS_ISDBT:
3623                         cxd2841er_active_i_to_sleep_tc(priv);
3624                         break;
3625                 case SYS_DVBC_ANNEX_A:
3626                         cxd2841er_active_c_to_sleep_tc(priv);
3627                         break;
3628                 default:
3629                         dev_warn(&priv->i2c->dev,
3630                                 "%s(): unknown delivery system %d\n",
3631                                 __func__, priv->system);
3632                 }
3633         }
3634         if (priv->state != STATE_SLEEP_TC) {
3635                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3636                         __func__, priv->state);
3637                 return -EINVAL;
3638         }
3639         return 0;
3640 }
3641
3642 static int cxd2841er_shutdown_tc(struct dvb_frontend *fe)
3643 {
3644         struct cxd2841er_priv *priv = fe->demodulator_priv;
3645
3646         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3647
3648         if (!cxd2841er_sleep_tc(fe))
3649                 cxd2841er_sleep_tc_to_shutdown(priv);
3650         return 0;
3651 }
3652
3653 static int cxd2841er_send_burst(struct dvb_frontend *fe,
3654                                 enum fe_sec_mini_cmd burst)
3655 {
3656         u8 data;
3657         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3658
3659         dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3660                 (burst == SEC_MINI_A ? "A" : "B"));
3661         if (priv->state != STATE_SLEEP_S &&
3662                         priv->state != STATE_ACTIVE_S) {
3663                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3664                         __func__, priv->state);
3665                 return -EINVAL;
3666         }
3667         data = (burst == SEC_MINI_A ? 0 : 1);
3668         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3669         cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3670         cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3671         return 0;
3672 }
3673
3674 static int cxd2841er_set_tone(struct dvb_frontend *fe,
3675                               enum fe_sec_tone_mode tone)
3676 {
3677         u8 data;
3678         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3679
3680         dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3681                 (tone == SEC_TONE_ON ? "On" : "Off"));
3682         if (priv->state != STATE_SLEEP_S &&
3683                         priv->state != STATE_ACTIVE_S) {
3684                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3685                         __func__, priv->state);
3686                 return -EINVAL;
3687         }
3688         data = (tone == SEC_TONE_ON ? 1 : 0);
3689         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3690         cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3691         return 0;
3692 }
3693
3694 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3695                                      struct dvb_diseqc_master_cmd *cmd)
3696 {
3697         int i;
3698         u8 data[12];
3699         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3700
3701         if (priv->state != STATE_SLEEP_S &&
3702                         priv->state != STATE_ACTIVE_S) {
3703                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3704                         __func__, priv->state);
3705                 return -EINVAL;
3706         }
3707         dev_dbg(&priv->i2c->dev,
3708                 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3709         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3710         /* DiDEqC enable */
3711         cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3712         /* cmd1 length & data */
3713         cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3714         memset(data, 0, sizeof(data));
3715         for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3716                 data[i] = cmd->msg[i];
3717         cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3718         /* repeat count for cmd1 */
3719         cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3720         /* repeat count for cmd2: always 0 */
3721         cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3722         /* start transmit */
3723         cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3724         /* wait for 1 sec timeout */
3725         for (i = 0; i < 50; i++) {
3726                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3727                 if (!data[0]) {
3728                         dev_dbg(&priv->i2c->dev,
3729                                 "%s(): DiSEqC cmd has been sent\n", __func__);
3730                         return 0;
3731                 }
3732                 msleep(20);
3733         }
3734         dev_dbg(&priv->i2c->dev,
3735                 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3736         return -ETIMEDOUT;
3737 }
3738
3739 static void cxd2841er_release(struct dvb_frontend *fe)
3740 {
3741         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3742
3743         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3744         kfree(priv);
3745 }
3746
3747 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3748 {
3749         struct cxd2841er_priv *priv = fe->demodulator_priv;
3750
3751         dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3752         cxd2841er_set_reg_bits(
3753                 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3754         return 0;
3755 }
3756
3757 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3758 {
3759         struct cxd2841er_priv *priv = fe->demodulator_priv;
3760
3761         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3762         return DVBFE_ALGO_HW;
3763 }
3764
3765 static void cxd2841er_init_stats(struct dvb_frontend *fe)
3766 {
3767         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3768
3769         p->strength.len = 1;
3770         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3771         p->cnr.len = 1;
3772         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3773         p->block_error.len = 1;
3774         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3775         p->post_bit_error.len = 1;
3776         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3777         p->post_bit_count.len = 1;
3778         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3779 }
3780
3781
3782 static int cxd2841er_init_s(struct dvb_frontend *fe)
3783 {
3784         struct cxd2841er_priv *priv = fe->demodulator_priv;
3785
3786         /* sanity. force demod to SHUTDOWN state */
3787         if (priv->state == STATE_SLEEP_S) {
3788                 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3789                                 __func__);
3790                 cxd2841er_sleep_s_to_shutdown(priv);
3791         } else if (priv->state == STATE_ACTIVE_S) {
3792                 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3793                                 __func__);
3794                 cxd2841er_active_s_to_sleep_s(priv);
3795                 cxd2841er_sleep_s_to_shutdown(priv);
3796         }
3797
3798         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3799         cxd2841er_shutdown_to_sleep_s(priv);
3800         /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3801         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3802         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3803
3804         cxd2841er_init_stats(fe);
3805
3806         return 0;
3807 }
3808
3809 static int cxd2841er_init_tc(struct dvb_frontend *fe)
3810 {
3811         struct cxd2841er_priv *priv = fe->demodulator_priv;
3812         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3813
3814         dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3815                         __func__, p->bandwidth_hz);
3816         cxd2841er_shutdown_to_sleep_tc(priv);
3817         /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 (0 for NO_AGCNEG */
3818         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3819         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb,
3820                 ((priv->flags & CXD2841ER_NO_AGCNEG) ? 0x00 : 0x40), 0x40);
3821         /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3822         cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3823         /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3824         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3825         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
3826                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80);
3827
3828         /* clear TSCFG bits 3+4 */
3829         if (priv->flags & CXD2841ER_TSBITS)
3830                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18);
3831
3832         cxd2841er_init_stats(fe);
3833
3834         return 0;
3835 }
3836
3837 static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3838 static struct dvb_frontend_ops cxd2841er_t_c_ops;
3839
3840 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3841                                              struct i2c_adapter *i2c,
3842                                              u8 system)
3843 {
3844         u8 chip_id = 0;
3845         const char *type;
3846         const char *name;
3847         struct cxd2841er_priv *priv = NULL;
3848
3849         /* allocate memory for the internal state */
3850         priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3851         if (!priv)
3852                 return NULL;
3853         priv->i2c = i2c;
3854         priv->config = cfg;
3855         priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3856         priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
3857         priv->xtal = cfg->xtal;
3858         priv->flags = cfg->flags;
3859         priv->frontend.demodulator_priv = priv;
3860         dev_info(&priv->i2c->dev,
3861                 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3862                 __func__, priv->i2c,
3863                 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3864         chip_id = cxd2841er_chip_id(priv);
3865         switch (chip_id) {
3866         case CXD2837ER_CHIP_ID:
3867                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3868                                 "Sony CXD2837ER DVB-T/T2/C demodulator");
3869                 name = "CXD2837ER";
3870                 type = "C/T/T2";
3871                 break;
3872         case CXD2838ER_CHIP_ID:
3873                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3874                                 "Sony CXD2838ER ISDB-T demodulator");
3875                 cxd2841er_t_c_ops.delsys[0] = SYS_ISDBT;
3876                 cxd2841er_t_c_ops.delsys[1] = SYS_UNDEFINED;
3877                 cxd2841er_t_c_ops.delsys[2] = SYS_UNDEFINED;
3878                 name = "CXD2838ER";
3879                 type = "ISDB-T";
3880                 break;
3881         case CXD2841ER_CHIP_ID:
3882                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3883                                 "Sony CXD2841ER DVB-T/T2/C demodulator");
3884                 name = "CXD2841ER";
3885                 type = "T/T2/C/ISDB-T";
3886                 break;
3887         case CXD2843ER_CHIP_ID:
3888                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3889                                 "Sony CXD2843ER DVB-T/T2/C/C2 demodulator");
3890                 name = "CXD2843ER";
3891                 type = "C/C2/T/T2";
3892                 break;
3893         case CXD2854ER_CHIP_ID:
3894                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3895                                 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3896                 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3897                 name = "CXD2854ER";
3898                 type = "C/C2/T/T2/ISDB-T";
3899                 break;
3900         default:
3901                 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3902                                 __func__, chip_id);
3903                 priv->frontend.demodulator_priv = NULL;
3904                 kfree(priv);
3905                 return NULL;
3906         }
3907
3908         /* create dvb_frontend */
3909         if (system == SYS_DVBS) {
3910                 memcpy(&priv->frontend.ops,
3911                         &cxd2841er_dvbs_s2_ops,
3912                         sizeof(struct dvb_frontend_ops));
3913                 type = "S/S2";
3914         } else {
3915                 memcpy(&priv->frontend.ops,
3916                         &cxd2841er_t_c_ops,
3917                         sizeof(struct dvb_frontend_ops));
3918         }
3919
3920         dev_info(&priv->i2c->dev,
3921                 "%s(): attaching %s DVB-%s frontend\n",
3922                 __func__, name, type);
3923         dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3924                 __func__, chip_id);
3925         return &priv->frontend;
3926 }
3927
3928 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3929                                         struct i2c_adapter *i2c)
3930 {
3931         return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3932 }
3933 EXPORT_SYMBOL(cxd2841er_attach_s);
3934
3935 struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
3936                                         struct i2c_adapter *i2c)
3937 {
3938         return cxd2841er_attach(cfg, i2c, 0);
3939 }
3940 EXPORT_SYMBOL(cxd2841er_attach_t_c);
3941
3942 static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3943         .delsys = { SYS_DVBS, SYS_DVBS2 },
3944         .info = {
3945                 .name           = "Sony CXD2841ER DVB-S/S2 demodulator",
3946                 .frequency_min_hz       =  500 * MHz,
3947                 .frequency_max_hz       = 2500 * MHz,
3948                 .symbol_rate_min = 1000000,
3949                 .symbol_rate_max = 45000000,
3950                 .symbol_rate_tolerance = 500,
3951                 .caps = FE_CAN_INVERSION_AUTO |
3952                         FE_CAN_FEC_AUTO |
3953                         FE_CAN_QPSK,
3954         },
3955         .init = cxd2841er_init_s,
3956         .sleep = cxd2841er_sleep_s,
3957         .release = cxd2841er_release,
3958         .set_frontend = cxd2841er_set_frontend_s,
3959         .get_frontend = cxd2841er_get_frontend,
3960         .read_status = cxd2841er_read_status_s,
3961         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3962         .get_frontend_algo = cxd2841er_get_algo,
3963         .set_tone = cxd2841er_set_tone,
3964         .diseqc_send_burst = cxd2841er_send_burst,
3965         .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3966         .tune = cxd2841er_tune_s
3967 };
3968
3969 static struct dvb_frontend_ops cxd2841er_t_c_ops = {
3970         .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
3971         .info = {
3972                 .name   = "", /* will set in attach function */
3973                 .caps = FE_CAN_FEC_1_2 |
3974                         FE_CAN_FEC_2_3 |
3975                         FE_CAN_FEC_3_4 |
3976                         FE_CAN_FEC_5_6 |
3977                         FE_CAN_FEC_7_8 |
3978                         FE_CAN_FEC_AUTO |
3979                         FE_CAN_QPSK |
3980                         FE_CAN_QAM_16 |
3981                         FE_CAN_QAM_32 |
3982                         FE_CAN_QAM_64 |
3983                         FE_CAN_QAM_128 |
3984                         FE_CAN_QAM_256 |
3985                         FE_CAN_QAM_AUTO |
3986                         FE_CAN_TRANSMISSION_MODE_AUTO |
3987                         FE_CAN_GUARD_INTERVAL_AUTO |
3988                         FE_CAN_HIERARCHY_AUTO |
3989                         FE_CAN_MUTE_TS |
3990                         FE_CAN_2G_MODULATION,
3991                 .frequency_min_hz =   42 * MHz,
3992                 .frequency_max_hz = 1002 * MHz,
3993                 .symbol_rate_min = 870000,
3994                 .symbol_rate_max = 11700000
3995         },
3996         .init = cxd2841er_init_tc,
3997         .sleep = cxd2841er_shutdown_tc,
3998         .release = cxd2841er_release,
3999         .set_frontend = cxd2841er_set_frontend_tc,
4000         .get_frontend = cxd2841er_get_frontend,
4001         .read_status = cxd2841er_read_status_tc,
4002         .tune = cxd2841er_tune_tc,
4003         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
4004         .get_frontend_algo = cxd2841er_get_algo
4005 };
4006
4007 MODULE_DESCRIPTION("Sony CXD2837/38/41/43/54ER DVB-C/C2/T/T2/S/S2 demodulator driver");
4008 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
4009 MODULE_LICENSE("GPL");