1 // SPDX-License-Identifier: GPL-2.0
3 * Tegra20 External Memory Controller driver
5 * Author: Dmitry Osipenko <digetx@gmail.com>
9 #include <linux/clk/tegra.h>
10 #include <linux/completion.h>
11 #include <linux/err.h>
12 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/sort.h>
19 #include <linux/types.h>
21 #include <soc/tegra/fuse.h>
23 #define EMC_INTSTATUS 0x000
24 #define EMC_INTMASK 0x004
26 #define EMC_TIMING_CONTROL 0x028
35 #define EMC_RD_RCD 0x04c
36 #define EMC_WR_RCD 0x050
38 #define EMC_REXT 0x058
40 #define EMC_QUSE 0x060
41 #define EMC_QRST 0x064
42 #define EMC_QSAFE 0x068
44 #define EMC_REFRESH 0x070
45 #define EMC_BURST_REFRESH_NUM 0x074
46 #define EMC_PDEX2WR 0x078
47 #define EMC_PDEX2RD 0x07c
48 #define EMC_PCHG2PDEN 0x080
49 #define EMC_ACT2PDEN 0x084
50 #define EMC_AR2PDEN 0x088
51 #define EMC_RW2PDEN 0x08c
52 #define EMC_TXSR 0x090
53 #define EMC_TCKE 0x094
54 #define EMC_TFAW 0x098
55 #define EMC_TRPAB 0x09c
56 #define EMC_TCLKSTABLE 0x0a0
57 #define EMC_TCLKSTOP 0x0a4
58 #define EMC_TREFBW 0x0a8
59 #define EMC_QUSE_EXTRA 0x0ac
60 #define EMC_ODT_WRITE 0x0b0
61 #define EMC_ODT_READ 0x0b4
62 #define EMC_FBIO_CFG5 0x104
63 #define EMC_FBIO_CFG6 0x114
64 #define EMC_AUTO_CAL_INTERVAL 0x2a8
65 #define EMC_CFG_2 0x2b8
66 #define EMC_CFG_DIG_DLL 0x2bc
67 #define EMC_DLL_XFORM_DQS 0x2c0
68 #define EMC_DLL_XFORM_QUSE 0x2c4
69 #define EMC_ZCAL_REF_CNT 0x2e0
70 #define EMC_ZCAL_WAIT_CNT 0x2e4
71 #define EMC_CFG_CLKTRIM_0 0x2d0
72 #define EMC_CFG_CLKTRIM_1 0x2d4
73 #define EMC_CFG_CLKTRIM_2 0x2d8
75 #define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
76 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
77 #define EMC_CLKCHANGE_SR_ENABLE BIT(2)
79 #define EMC_TIMING_UPDATE BIT(0)
81 #define EMC_REFRESH_OVERFLOW_INT BIT(3)
82 #define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
84 #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
85 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
86 #define EMC_DBG_FORCE_UPDATE BIT(2)
87 #define EMC_DBG_READ_DQM_CTRL BIT(9)
88 #define EMC_DBG_CFG_PRIORITY BIT(24)
90 static const u16 emc_timing_registers[] = {
109 EMC_BURST_REFRESH_NUM,
133 EMC_AUTO_CAL_INTERVAL,
141 u32 data[ARRAY_SIZE(emc_timing_registers)];
146 struct completion clk_handshake_complete;
147 struct notifier_block clk_nb;
151 struct emc_timing *timings;
152 unsigned int num_timings;
155 static irqreturn_t tegra_emc_isr(int irq, void *data)
157 struct tegra_emc *emc = data;
158 u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT;
161 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
165 /* notify about EMC-CAR handshake completion */
166 if (status & EMC_CLKCHANGE_COMPLETE_INT)
167 complete(&emc->clk_handshake_complete);
169 /* notify about HW problem */
170 if (status & EMC_REFRESH_OVERFLOW_INT)
171 dev_err_ratelimited(emc->dev,
172 "refresh request overflow timeout\n");
174 /* clear interrupts */
175 writel_relaxed(status, emc->regs + EMC_INTSTATUS);
180 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
183 struct emc_timing *timing = NULL;
186 for (i = 0; i < emc->num_timings; i++) {
187 if (emc->timings[i].rate >= rate) {
188 timing = &emc->timings[i];
194 dev_err(emc->dev, "no timing for rate %lu\n", rate);
201 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
203 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
209 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
210 __func__, timing->rate, rate);
212 /* program shadow registers */
213 for (i = 0; i < ARRAY_SIZE(timing->data); i++)
214 writel_relaxed(timing->data[i],
215 emc->regs + emc_timing_registers[i]);
217 /* wait until programming has settled */
218 readl_relaxed(emc->regs + emc_timing_registers[i - 1]);
220 reinit_completion(&emc->clk_handshake_complete);
225 static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)
227 unsigned long timeout;
229 dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush);
232 /* manually initiate memory timing update */
233 writel_relaxed(EMC_TIMING_UPDATE,
234 emc->regs + EMC_TIMING_CONTROL);
238 timeout = wait_for_completion_timeout(&emc->clk_handshake_complete,
239 msecs_to_jiffies(100));
241 dev_err(emc->dev, "EMC-CAR handshake failed\n");
248 static int tegra_emc_clk_change_notify(struct notifier_block *nb,
249 unsigned long msg, void *data)
251 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
252 struct clk_notifier_data *cnd = data;
256 case PRE_RATE_CHANGE:
257 err = emc_prepare_timing_change(emc, cnd->new_rate);
260 case ABORT_RATE_CHANGE:
261 err = emc_prepare_timing_change(emc, cnd->old_rate);
265 err = emc_complete_timing_change(emc, true);
268 case POST_RATE_CHANGE:
269 err = emc_complete_timing_change(emc, false);
276 return notifier_from_errno(err);
279 static int load_one_timing_from_dt(struct tegra_emc *emc,
280 struct emc_timing *timing,
281 struct device_node *node)
286 if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) {
287 dev_err(emc->dev, "incompatible DT node: %pOF\n", node);
291 err = of_property_read_u32(node, "clock-frequency", &rate);
293 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
298 err = of_property_read_u32_array(node, "nvidia,emc-registers",
300 ARRAY_SIZE(emc_timing_registers));
303 "timing %pOF: failed to read emc timing data: %d\n",
309 * The EMC clock rate is twice the bus rate, and the bus rate is
312 timing->rate = rate * 2 * 1000;
314 dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n",
315 __func__, node, timing->rate);
320 static int cmp_timings(const void *_a, const void *_b)
322 const struct emc_timing *a = _a;
323 const struct emc_timing *b = _b;
325 if (a->rate < b->rate)
328 if (a->rate > b->rate)
334 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
335 struct device_node *node)
337 struct device_node *child;
338 struct emc_timing *timing;
342 child_count = of_get_child_count(node);
344 dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node);
348 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
353 emc->num_timings = child_count;
354 timing = emc->timings;
356 for_each_child_of_node(node, child) {
357 err = load_one_timing_from_dt(emc, timing++, child);
364 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
368 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
370 tegra_read_ram_code(),
371 emc->timings[0].rate / 1000000,
372 emc->timings[emc->num_timings - 1].rate / 1000000);
377 static struct device_node *
378 tegra_emc_find_node_by_ram_code(struct device *dev)
380 struct device_node *np;
384 if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code"))
385 return of_node_get(dev->of_node);
387 ram_code = tegra_read_ram_code();
389 for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np;
390 np = of_find_node_by_name(np, "emc-tables")) {
391 err = of_property_read_u32(np, "nvidia,ram-code", &value);
392 if (err || value != ram_code) {
400 dev_err(dev, "no memory timings for RAM code %u found in device tree\n",
406 static int emc_setup_hw(struct tegra_emc *emc)
408 u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT;
409 u32 emc_cfg, emc_dbg;
411 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
414 * Depending on a memory type, DRAM should enter either self-refresh
415 * or power-down state on EMC clock change.
417 if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) &&
418 !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) {
420 "bootloader didn't specify DRAM auto-suspend mode\n");
424 /* enable EMC and CAR to handshake on PLL divider/source changes */
425 emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
426 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
428 /* initialize interrupt */
429 writel_relaxed(intmask, emc->regs + EMC_INTMASK);
430 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
432 /* ensure that unwanted debug features are disabled */
433 emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
434 emc_dbg |= EMC_DBG_CFG_PRIORITY;
435 emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
436 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
437 emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
438 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
443 static long emc_round_rate(unsigned long rate,
444 unsigned long min_rate,
445 unsigned long max_rate,
448 struct emc_timing *timing = NULL;
449 struct tegra_emc *emc = arg;
452 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
454 for (i = 0; i < emc->num_timings; i++) {
455 if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
458 if (emc->timings[i].rate > max_rate) {
461 if (emc->timings[i].rate < min_rate)
465 if (emc->timings[i].rate < min_rate)
468 timing = &emc->timings[i];
473 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
474 rate, min_rate, max_rate);
481 static int tegra_emc_probe(struct platform_device *pdev)
483 struct device_node *np;
484 struct tegra_emc *emc;
485 struct resource *res;
488 /* driver has nothing to do in a case of memory timing absence */
489 if (of_get_child_count(pdev->dev.of_node) == 0) {
491 "EMC device tree node doesn't have memory timings\n");
495 irq = platform_get_irq(pdev, 0);
497 dev_err(&pdev->dev, "interrupt not specified\n");
498 dev_err(&pdev->dev, "please update your device tree\n");
502 np = tegra_emc_find_node_by_ram_code(&pdev->dev);
506 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
512 init_completion(&emc->clk_handshake_complete);
513 emc->clk_nb.notifier_call = tegra_emc_clk_change_notify;
514 emc->dev = &pdev->dev;
516 err = tegra_emc_load_timings_from_dt(emc, np);
521 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
522 emc->regs = devm_ioremap_resource(&pdev->dev, res);
523 if (IS_ERR(emc->regs))
524 return PTR_ERR(emc->regs);
526 err = emc_setup_hw(emc);
530 err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0,
531 dev_name(&pdev->dev), emc);
533 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err);
537 tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
539 emc->clk = devm_clk_get(&pdev->dev, "emc");
540 if (IS_ERR(emc->clk)) {
541 err = PTR_ERR(emc->clk);
542 dev_err(&pdev->dev, "failed to get emc clock: %d\n", err);
546 err = clk_notifier_register(emc->clk, &emc->clk_nb);
548 dev_err(&pdev->dev, "failed to register clk notifier: %d\n",
556 tegra20_clk_set_emc_round_callback(NULL, NULL);
561 static const struct of_device_id tegra_emc_of_match[] = {
562 { .compatible = "nvidia,tegra20-emc", },
566 static struct platform_driver tegra_emc_driver = {
567 .probe = tegra_emc_probe,
569 .name = "tegra20-emc",
570 .of_match_table = tegra_emc_of_match,
571 .suppress_bind_attrs = true,
575 static int __init tegra_emc_init(void)
577 return platform_driver_register(&tegra_emc_driver);
579 subsys_initcall(tegra_emc_init);