drivers/misc/mei/pci-me.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
   4  * Intel Management Engine Interface (Intel MEI) Linux driver
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/kernel.h>
   9 #include <linux/device.h>
  10 #include <linux/errno.h>
  11 #include <linux/types.h>
  12 #include <linux/pci.h>
  13 #include <linux/sched.h>
  14 #include <linux/interrupt.h>
  15
  16 #include <linux/pm_domain.h>
  17 #include <linux/pm_runtime.h>
  18
  19 #include <linux/mei.h>
  20
  21 #include "mei_dev.h"
  22 #include "client.h"
  23 #include "hw-me-regs.h"
  24 #include "hw-me.h"
  25
  26 /* mei_pci_tbl - PCI Device ID Table */
  27 static const struct pci_device_id mei_me_pci_tbl[] = {
  28         {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
  29         {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
  30         {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
  31         {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
  32         {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
  33         {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
  34         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
  35         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
  36         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
  37         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
  38         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
  39
  40         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
  41         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
  42         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
  43         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
  44         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
  45         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
  46         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
  47         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
  48         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
  49
  50         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
  51         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
  52         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
  53         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
  54
  55         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
  56         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
  57         {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
  58         {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
  59         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
  60         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
  61         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
  62         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
  63         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
  64         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
  65         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
  66         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
  67         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
  68
  69         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
  70         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
  71         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
  72         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
  73         {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)},
  74
  75         {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
  76         {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
  77
  78         {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
  79
  80         {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
  81
  82         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
  83         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
  84
  85         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
  86         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_CFG)},
  87         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)},
  88         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH8_CFG)},
  89
  90         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
  91         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)},
  92         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
  93         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
  94         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_CFG)},
  95
  96         {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
  97
  98         {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
  99
 100         {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
 101
 102         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
 103         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
 104
 105         {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
 106
 107         /* required last entry */
 108         {0, }
 109 };
 110
 111 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
 112
 113 #ifdef CONFIG_PM
 114 static inline void mei_me_set_pm_domain(struct mei_device *dev);
 115 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
 116 #else
 117 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
 118 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
 119 #endif /* CONFIG_PM */
 120
 121 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
 122 {
 123         struct pci_dev *pdev = to_pci_dev(dev->dev);
 124
 125         return pci_read_config_dword(pdev, where, val);
 126 }
 127
 128 /**
 129  * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 130  *
 131  * @pdev: PCI device structure
 132  * @cfg: per generation config
 133  *
 134  * Return: true if ME Interface is valid, false otherwise
 135  */
 136 static bool mei_me_quirk_probe(struct pci_dev *pdev,
 137                                 const struct mei_cfg *cfg)
 138 {
 139         if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
 140                 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
 141                 return false;
 142         }
 143
 144         return true;
 145 }
 146
 147 /**
 148  * mei_me_probe - Device Initialization Routine
 149  *
 150  * @pdev: PCI device structure
 151  * @ent: entry in kcs_pci_tbl
 152  *
 153  * Return: 0 on success, <0 on failure.
 154  */
 155 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 156 {
 157         const struct mei_cfg *cfg;
 158         struct mei_device *dev;
 159         struct mei_me_hw *hw;
 160         unsigned int irqflags;
 161         int err;
 162
 163         cfg = mei_me_get_cfg(ent->driver_data);
 164         if (!cfg)
 165                 return -ENODEV;
 166
 167         if (!mei_me_quirk_probe(pdev, cfg))
 168                 return -ENODEV;
 169
 170         /* enable pci dev */
 171         err = pcim_enable_device(pdev);
 172         if (err) {
 173                 dev_err(&pdev->dev, "failed to enable pci device.\n");
 174                 goto end;
 175         }
 176         /* set PCI host mastering  */
 177         pci_set_master(pdev);
 178         /* pci request regions and mapping IO device memory for mei driver */
 179         err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
 180         if (err) {
 181                 dev_err(&pdev->dev, "failed to get pci regions.\n");
 182                 goto end;
 183         }
 184
 185         if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
 186             dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
 187
 188                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
 189                 if (err)
 190                         err = dma_set_coherent_mask(&pdev->dev,
 191                                                     DMA_BIT_MASK(32));
 192         }
 193         if (err) {
 194                 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
 195                 goto end;
 196         }
 197
 198         /* allocates and initializes the mei dev structure */
 199         dev = mei_me_dev_init(&pdev->dev, cfg);
 200         if (!dev) {
 201                 err = -ENOMEM;
 202                 goto end;
 203         }
 204         hw = to_me_hw(dev);
 205         hw->mem_addr = pcim_iomap_table(pdev)[0];
 206         hw->irq = pdev->irq;
 207         hw->read_fws = mei_me_read_fws;
 208
 209         pci_enable_msi(pdev);
 210
 211          /* request and enable interrupt */
 212         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 213
 214         err = request_threaded_irq(pdev->irq,
 215                         mei_me_irq_quick_handler,
 216                         mei_me_irq_thread_handler,
 217                         irqflags, KBUILD_MODNAME, dev);
 218         if (err) {
 219                 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
 220                        pdev->irq);
 221                 goto end;
 222         }
 223
 224         if (mei_start(dev)) {
 225                 dev_err(&pdev->dev, "init hw failure.\n");
 226                 err = -ENODEV;
 227                 goto release_irq;
 228         }
 229
 230         pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
 231         pm_runtime_use_autosuspend(&pdev->dev);
 232
 233         err = mei_register(dev, &pdev->dev);
 234         if (err)
 235                 goto stop;
 236
 237         pci_set_drvdata(pdev, dev);
 238
 239         /*
 240          * MEI requires to resume from runtime suspend mode
 241          * in order to perform link reset flow upon system suspend.
 242          */
 243         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
 244
 245         /*
 246          * ME maps runtime suspend/resume to D0i states,
 247          * hence we need to go around native PCI runtime service which
 248          * eventually brings the device into D3cold/hot state,
 249          * but the mei device cannot wake up from D3 unlike from D0i3.
 250          * To get around the PCI device native runtime pm,
 251          * ME uses runtime pm domain handlers which take precedence
 252          * over the driver's pm handlers.
 253          */
 254         mei_me_set_pm_domain(dev);
 255
 256         if (mei_pg_is_enabled(dev)) {
 257                 pm_runtime_put_noidle(&pdev->dev);
 258                 if (hw->d0i3_supported)
 259                         pm_runtime_allow(&pdev->dev);
 260         }
 261
 262         dev_dbg(&pdev->dev, "initialization successful.\n");
 263
 264         return 0;
 265
 266 stop:
 267         mei_stop(dev);
 268 release_irq:
 269         mei_cancel_work(dev);
 270         mei_disable_interrupts(dev);
 271         free_irq(pdev->irq, dev);
 272 end:
 273         dev_err(&pdev->dev, "initialization failed.\n");
 274         return err;
 275 }
 276
 277 /**
 278  * mei_me_shutdown - Device Removal Routine
 279  *
 280  * @pdev: PCI device structure
 281  *
 282  * mei_me_shutdown is called from the reboot notifier
 283  * it's a simplified version of remove so we go down
 284  * faster.
 285  */
 286 static void mei_me_shutdown(struct pci_dev *pdev)
 287 {
 288         struct mei_device *dev;
 289
 290         dev = pci_get_drvdata(pdev);
 291         if (!dev)
 292                 return;
 293
 294         dev_dbg(&pdev->dev, "shutdown\n");
 295         mei_stop(dev);
 296
 297         mei_me_unset_pm_domain(dev);
 298
 299         mei_disable_interrupts(dev);
 300         free_irq(pdev->irq, dev);
 301 }
 302
 303 /**
 304  * mei_me_remove - Device Removal Routine
 305  *
 306  * @pdev: PCI device structure
 307  *
 308  * mei_me_remove is called by the PCI subsystem to alert the driver
 309  * that it should release a PCI device.
 310  */
 311 static void mei_me_remove(struct pci_dev *pdev)
 312 {
 313         struct mei_device *dev;
 314
 315         dev = pci_get_drvdata(pdev);
 316         if (!dev)
 317                 return;
 318
 319         if (mei_pg_is_enabled(dev))
 320                 pm_runtime_get_noresume(&pdev->dev);
 321
 322         dev_dbg(&pdev->dev, "stop\n");
 323         mei_stop(dev);
 324
 325         mei_me_unset_pm_domain(dev);
 326
 327         mei_disable_interrupts(dev);
 328
 329         free_irq(pdev->irq, dev);
 330
 331         mei_deregister(dev);
 332 }
 333
 334 #ifdef CONFIG_PM_SLEEP
 335 static int mei_me_pci_suspend(struct device *device)
 336 {
 337         struct pci_dev *pdev = to_pci_dev(device);
 338         struct mei_device *dev = pci_get_drvdata(pdev);
 339
 340         if (!dev)
 341                 return -ENODEV;
 342
 343         dev_dbg(&pdev->dev, "suspend\n");
 344
 345         mei_stop(dev);
 346
 347         mei_disable_interrupts(dev);
 348
 349         free_irq(pdev->irq, dev);
 350         pci_disable_msi(pdev);
 351
 352         return 0;
 353 }
 354
 355 static int mei_me_pci_resume(struct device *device)
 356 {
 357         struct pci_dev *pdev = to_pci_dev(device);
 358         struct mei_device *dev;
 359         unsigned int irqflags;
 360         int err;
 361
 362         dev = pci_get_drvdata(pdev);
 363         if (!dev)
 364                 return -ENODEV;
 365
 366         pci_enable_msi(pdev);
 367
 368         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 369
 370         /* request and enable interrupt */
 371         err = request_threaded_irq(pdev->irq,
 372                         mei_me_irq_quick_handler,
 373                         mei_me_irq_thread_handler,
 374                         irqflags, KBUILD_MODNAME, dev);
 375
 376         if (err) {
 377                 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
 378                                 pdev->irq);
 379                 return err;
 380         }
 381
 382         err = mei_restart(dev);
 383         if (err)
 384                 return err;
 385
 386         /* Start timer if stopped in suspend */
 387         schedule_delayed_work(&dev->timer_work, HZ);
 388
 389         return 0;
 390 }
 391 #endif /* CONFIG_PM_SLEEP */
 392
 393 #ifdef CONFIG_PM
 394 static int mei_me_pm_runtime_idle(struct device *device)
 395 {
 396         struct mei_device *dev;
 397
 398         dev_dbg(device, "rpm: me: runtime_idle\n");
 399
 400         dev = dev_get_drvdata(device);
 401         if (!dev)
 402                 return -ENODEV;
 403         if (mei_write_is_idle(dev))
 404                 pm_runtime_autosuspend(device);
 405
 406         return -EBUSY;
 407 }
 408
 409 static int mei_me_pm_runtime_suspend(struct device *device)
 410 {
 411         struct mei_device *dev;
 412         int ret;
 413
 414         dev_dbg(device, "rpm: me: runtime suspend\n");
 415
 416         dev = dev_get_drvdata(device);
 417         if (!dev)
 418                 return -ENODEV;
 419
 420         mutex_lock(&dev->device_lock);
 421
 422         if (mei_write_is_idle(dev))
 423                 ret = mei_me_pg_enter_sync(dev);
 424         else
 425                 ret = -EAGAIN;
 426
 427         mutex_unlock(&dev->device_lock);
 428
 429         dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
 430
 431         if (ret && ret != -EAGAIN)
 432                 schedule_work(&dev->reset_work);
 433
 434         return ret;
 435 }
 436
 437 static int mei_me_pm_runtime_resume(struct device *device)
 438 {
 439         struct mei_device *dev;
 440         int ret;
 441
 442         dev_dbg(device, "rpm: me: runtime resume\n");
 443
 444         dev = dev_get_drvdata(device);
 445         if (!dev)
 446                 return -ENODEV;
 447
 448         mutex_lock(&dev->device_lock);
 449
 450         ret = mei_me_pg_exit_sync(dev);
 451
 452         mutex_unlock(&dev->device_lock);
 453
 454         dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
 455
 456         if (ret)
 457                 schedule_work(&dev->reset_work);
 458
 459         return ret;
 460 }
 461
 462 /**
 463  * mei_me_set_pm_domain - fill and set pm domain structure for device
 464  *
 465  * @dev: mei_device
 466  */
 467 static inline void mei_me_set_pm_domain(struct mei_device *dev)
 468 {
 469         struct pci_dev *pdev  = to_pci_dev(dev->dev);
 470
 471         if (pdev->dev.bus && pdev->dev.bus->pm) {
 472                 dev->pg_domain.ops = *pdev->dev.bus->pm;
 473
 474                 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
 475                 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
 476                 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
 477
 478                 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
 479         }
 480 }
 481
 482 /**
 483  * mei_me_unset_pm_domain - clean pm domain structure for device
 484  *
 485  * @dev: mei_device
 486  */
 487 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
 488 {
 489         /* stop using pm callbacks if any */
 490         dev_pm_domain_set(dev->dev, NULL);
 491 }
 492
 493 static const struct dev_pm_ops mei_me_pm_ops = {
 494         SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
 495                                 mei_me_pci_resume)
 496         SET_RUNTIME_PM_OPS(
 497                 mei_me_pm_runtime_suspend,
 498                 mei_me_pm_runtime_resume,
 499                 mei_me_pm_runtime_idle)
 500 };
 501
 502 #define MEI_ME_PM_OPS   (&mei_me_pm_ops)
 503 #else
 504 #define MEI_ME_PM_OPS   NULL
 505 #endif /* CONFIG_PM */
 506 /*
 507  *  PCI driver structure
 508  */
 509 static struct pci_driver mei_me_driver = {
 510         .name = KBUILD_MODNAME,
 511         .id_table = mei_me_pci_tbl,
 512         .probe = mei_me_probe,
 513         .remove = mei_me_remove,
 514         .shutdown = mei_me_shutdown,
 515         .driver.pm = MEI_ME_PM_OPS,
 516         .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 517 };
 518
 519 module_pci_driver(mei_me_driver);
 520
 521 MODULE_AUTHOR("Intel Corporation");
 522 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
 523 MODULE_LICENSE("GPL v2");