2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/highmem.h>
21 #include <linux/log2.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/card.h>
24 #include <linux/amba/bus.h>
25 #include <linux/clk.h>
26 #include <linux/scatterlist.h>
27 #include <linux/gpio.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/amba/mmci.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/types.h>
35 #include <asm/div64.h>
37 #include <asm/sizes.h>
41 #define DRIVER_NAME "mmci-pl18x"
43 static unsigned int fmax = 515633;
46 * struct variant_data - MMCI variant-specific quirks
47 * @clkreg: default value for MCICLOCK register
48 * @clkreg_enable: enable value for MMCICLOCK register
49 * @datalength_bits: number of bits in the MMCIDATALENGTH register
50 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
51 * is asserted (likewise for RX)
52 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
53 * is asserted (likewise for RX)
54 * @sdio: variant supports SDIO
55 * @st_clkdiv: true if using a ST-specific clock divider algorithm
56 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
60 unsigned int clkreg_enable;
61 unsigned int datalength_bits;
62 unsigned int fifosize;
63 unsigned int fifohalfsize;
66 bool blksz_datactrl16;
69 static struct variant_data variant_arm = {
71 .fifohalfsize = 8 * 4,
72 .datalength_bits = 16,
75 static struct variant_data variant_arm_extended_fifo = {
77 .fifohalfsize = 64 * 4,
78 .datalength_bits = 16,
81 static struct variant_data variant_u300 = {
83 .fifohalfsize = 8 * 4,
84 .clkreg_enable = MCI_ST_U300_HWFCEN,
85 .datalength_bits = 16,
89 static struct variant_data variant_ux500 = {
91 .fifohalfsize = 8 * 4,
92 .clkreg = MCI_CLK_ENABLE,
93 .clkreg_enable = MCI_ST_UX500_HWFCEN,
94 .datalength_bits = 24,
99 static struct variant_data variant_ux500v2 = {
101 .fifohalfsize = 8 * 4,
102 .clkreg = MCI_CLK_ENABLE,
103 .clkreg_enable = MCI_ST_UX500_HWFCEN,
104 .datalength_bits = 24,
107 .blksz_datactrl16 = true,
111 * This must be called with host->lock held
113 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
115 struct variant_data *variant = host->variant;
116 u32 clk = variant->clkreg;
119 if (desired >= host->mclk) {
120 clk = MCI_CLK_BYPASS;
121 if (variant->st_clkdiv)
122 clk |= MCI_ST_UX500_NEG_EDGE;
123 host->cclk = host->mclk;
124 } else if (variant->st_clkdiv) {
126 * DB8500 TRM says f = mclk / (clkdiv + 2)
127 * => clkdiv = (mclk / f) - 2
128 * Round the divider up so we don't exceed the max
131 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
134 host->cclk = host->mclk / (clk + 2);
137 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
138 * => clkdiv = mclk / (2 * f) - 1
140 clk = host->mclk / (2 * desired) - 1;
143 host->cclk = host->mclk / (2 * (clk + 1));
146 clk |= variant->clkreg_enable;
147 clk |= MCI_CLK_ENABLE;
148 /* This hasn't proven to be worthwhile */
149 /* clk |= MCI_CLK_PWRSAVE; */
152 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
154 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
155 clk |= MCI_ST_8BIT_BUS;
157 writel(clk, host->base + MMCICLOCK);
161 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
163 writel(0, host->base + MMCICOMMAND);
171 * Need to drop the host lock here; mmc_request_done may call
172 * back into the driver...
174 spin_unlock(&host->lock);
175 pm_runtime_put(mmc_dev(host->mmc));
176 mmc_request_done(host->mmc, mrq);
177 spin_lock(&host->lock);
180 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
182 void __iomem *base = host->base;
184 if (host->singleirq) {
185 unsigned int mask0 = readl(base + MMCIMASK0);
187 mask0 &= ~MCI_IRQ1MASK;
190 writel(mask0, base + MMCIMASK0);
193 writel(mask, base + MMCIMASK1);
196 static void mmci_stop_data(struct mmci_host *host)
198 writel(0, host->base + MMCIDATACTRL);
199 mmci_set_mask1(host, 0);
203 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
205 unsigned int flags = SG_MITER_ATOMIC;
207 if (data->flags & MMC_DATA_READ)
208 flags |= SG_MITER_TO_SG;
210 flags |= SG_MITER_FROM_SG;
212 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
216 * All the DMA operation mode stuff goes inside this ifdef.
217 * This assumes that you have a generic DMA device interface,
218 * no custom DMA interfaces are supported.
220 #ifdef CONFIG_DMA_ENGINE
221 static void __devinit mmci_dma_setup(struct mmci_host *host)
223 struct mmci_platform_data *plat = host->plat;
224 const char *rxname, *txname;
227 if (!plat || !plat->dma_filter) {
228 dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
232 /* initialize pre request cookie */
233 host->next_data.cookie = 1;
235 /* Try to acquire a generic DMA engine slave channel */
237 dma_cap_set(DMA_SLAVE, mask);
240 * If only an RX channel is specified, the driver will
241 * attempt to use it bidirectionally, however if it is
242 * is specified but cannot be located, DMA will be disabled.
244 if (plat->dma_rx_param) {
245 host->dma_rx_channel = dma_request_channel(mask,
248 /* E.g if no DMA hardware is present */
249 if (!host->dma_rx_channel)
250 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
253 if (plat->dma_tx_param) {
254 host->dma_tx_channel = dma_request_channel(mask,
257 if (!host->dma_tx_channel)
258 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
260 host->dma_tx_channel = host->dma_rx_channel;
263 if (host->dma_rx_channel)
264 rxname = dma_chan_name(host->dma_rx_channel);
268 if (host->dma_tx_channel)
269 txname = dma_chan_name(host->dma_tx_channel);
273 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
277 * Limit the maximum segment size in any SG entry according to
278 * the parameters of the DMA engine device.
280 if (host->dma_tx_channel) {
281 struct device *dev = host->dma_tx_channel->device->dev;
282 unsigned int max_seg_size = dma_get_max_seg_size(dev);
284 if (max_seg_size < host->mmc->max_seg_size)
285 host->mmc->max_seg_size = max_seg_size;
287 if (host->dma_rx_channel) {
288 struct device *dev = host->dma_rx_channel->device->dev;
289 unsigned int max_seg_size = dma_get_max_seg_size(dev);
291 if (max_seg_size < host->mmc->max_seg_size)
292 host->mmc->max_seg_size = max_seg_size;
297 * This is used in __devinit or __devexit so inline it
298 * so it can be discarded.
300 static inline void mmci_dma_release(struct mmci_host *host)
302 struct mmci_platform_data *plat = host->plat;
304 if (host->dma_rx_channel)
305 dma_release_channel(host->dma_rx_channel);
306 if (host->dma_tx_channel && plat->dma_tx_param)
307 dma_release_channel(host->dma_tx_channel);
308 host->dma_rx_channel = host->dma_tx_channel = NULL;
311 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
313 struct dma_chan *chan = host->dma_current;
314 enum dma_data_direction dir;
318 /* Wait up to 1ms for the DMA to complete */
320 status = readl(host->base + MMCISTATUS);
321 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
327 * Check to see whether we still have some data left in the FIFO -
328 * this catches DMA controllers which are unable to monitor the
329 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
330 * contiguous buffers. On TX, we'll get a FIFO underrun error.
332 if (status & MCI_RXDATAAVLBLMASK) {
333 dmaengine_terminate_all(chan);
338 if (data->flags & MMC_DATA_WRITE) {
341 dir = DMA_FROM_DEVICE;
344 if (!data->host_cookie)
345 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
348 * Use of DMA with scatter-gather is impossible.
349 * Give up with DMA and switch back to PIO mode.
351 if (status & MCI_RXDATAAVLBLMASK) {
352 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
353 mmci_dma_release(host);
357 static void mmci_dma_data_error(struct mmci_host *host)
359 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
360 dmaengine_terminate_all(host->dma_current);
363 static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
364 struct mmci_host_next *next)
366 struct variant_data *variant = host->variant;
367 struct dma_slave_config conf = {
368 .src_addr = host->phybase + MMCIFIFO,
369 .dst_addr = host->phybase + MMCIFIFO,
370 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
371 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
372 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
373 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
376 struct dma_chan *chan;
377 struct dma_device *device;
378 struct dma_async_tx_descriptor *desc;
379 enum dma_data_direction buffer_dirn;
382 /* Check if next job is already prepared */
383 if (data->host_cookie && !next &&
384 host->dma_current && host->dma_desc_current)
388 host->dma_current = NULL;
389 host->dma_desc_current = NULL;
392 if (data->flags & MMC_DATA_READ) {
393 conf.direction = DMA_DEV_TO_MEM;
394 buffer_dirn = DMA_FROM_DEVICE;
395 chan = host->dma_rx_channel;
397 conf.direction = DMA_MEM_TO_DEV;
398 buffer_dirn = DMA_TO_DEVICE;
399 chan = host->dma_tx_channel;
402 /* If there's no DMA channel, fall back to PIO */
406 /* If less than or equal to the fifo size, don't bother with DMA */
407 if (data->blksz * data->blocks <= variant->fifosize)
410 device = chan->device;
411 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
415 dmaengine_slave_config(chan, &conf);
416 desc = device->device_prep_slave_sg(chan, data->sg, nr_sg,
417 conf.direction, DMA_CTRL_ACK);
422 next->dma_chan = chan;
423 next->dma_desc = desc;
425 host->dma_current = chan;
426 host->dma_desc_current = desc;
433 dmaengine_terminate_all(chan);
434 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
438 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
441 struct mmc_data *data = host->data;
443 ret = mmci_dma_prep_data(host, host->data, NULL);
447 /* Okay, go for it. */
448 dev_vdbg(mmc_dev(host->mmc),
449 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
450 data->sg_len, data->blksz, data->blocks, data->flags);
451 dmaengine_submit(host->dma_desc_current);
452 dma_async_issue_pending(host->dma_current);
454 datactrl |= MCI_DPSM_DMAENABLE;
456 /* Trigger the DMA transfer */
457 writel(datactrl, host->base + MMCIDATACTRL);
460 * Let the MMCI say when the data is ended and it's time
461 * to fire next DMA request. When that happens, MMCI will
462 * call mmci_data_end()
464 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
465 host->base + MMCIMASK0);
469 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
471 struct mmci_host_next *next = &host->next_data;
473 if (data->host_cookie && data->host_cookie != next->cookie) {
474 pr_warning("[%s] invalid cookie: data->host_cookie %d"
475 " host->next_data.cookie %d\n",
476 __func__, data->host_cookie, host->next_data.cookie);
477 data->host_cookie = 0;
480 if (!data->host_cookie)
483 host->dma_desc_current = next->dma_desc;
484 host->dma_current = next->dma_chan;
486 next->dma_desc = NULL;
487 next->dma_chan = NULL;
490 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
493 struct mmci_host *host = mmc_priv(mmc);
494 struct mmc_data *data = mrq->data;
495 struct mmci_host_next *nd = &host->next_data;
500 if (data->host_cookie) {
501 data->host_cookie = 0;
505 /* if config for dma */
506 if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) ||
507 ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) {
508 if (mmci_dma_prep_data(host, data, nd))
509 data->host_cookie = 0;
511 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
515 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
518 struct mmci_host *host = mmc_priv(mmc);
519 struct mmc_data *data = mrq->data;
520 struct dma_chan *chan;
521 enum dma_data_direction dir;
526 if (data->flags & MMC_DATA_READ) {
527 dir = DMA_FROM_DEVICE;
528 chan = host->dma_rx_channel;
531 chan = host->dma_tx_channel;
535 /* if config for dma */
538 dmaengine_terminate_all(chan);
539 if (data->host_cookie)
540 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
542 mrq->data->host_cookie = 0;
547 /* Blank functions if the DMA engine is not available */
548 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
551 static inline void mmci_dma_setup(struct mmci_host *host)
555 static inline void mmci_dma_release(struct mmci_host *host)
559 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
563 static inline void mmci_dma_data_error(struct mmci_host *host)
567 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
572 #define mmci_pre_request NULL
573 #define mmci_post_request NULL
577 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
579 struct variant_data *variant = host->variant;
580 unsigned int datactrl, timeout, irqmask;
581 unsigned long long clks;
585 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
586 data->blksz, data->blocks, data->flags);
589 host->size = data->blksz * data->blocks;
590 data->bytes_xfered = 0;
592 clks = (unsigned long long)data->timeout_ns * host->cclk;
593 do_div(clks, 1000000000UL);
595 timeout = data->timeout_clks + (unsigned int)clks;
598 writel(timeout, base + MMCIDATATIMER);
599 writel(host->size, base + MMCIDATALENGTH);
601 blksz_bits = ffs(data->blksz) - 1;
602 BUG_ON(1 << blksz_bits != data->blksz);
604 if (variant->blksz_datactrl16)
605 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
607 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
609 if (data->flags & MMC_DATA_READ)
610 datactrl |= MCI_DPSM_DIRECTION;
613 * Attempt to use DMA operation mode, if this
614 * should fail, fall back to PIO mode
616 if (!mmci_dma_start_data(host, datactrl))
619 /* IRQ mode, map the SG list for CPU reading/writing */
620 mmci_init_sg(host, data);
622 if (data->flags & MMC_DATA_READ) {
623 irqmask = MCI_RXFIFOHALFFULLMASK;
626 * If we have less than the fifo 'half-full' threshold to
627 * transfer, trigger a PIO interrupt as soon as any data
630 if (host->size < variant->fifohalfsize)
631 irqmask |= MCI_RXDATAAVLBLMASK;
634 * We don't actually need to include "FIFO empty" here
635 * since its implicit in "FIFO half empty".
637 irqmask = MCI_TXFIFOHALFEMPTYMASK;
640 /* The ST Micro variants has a special bit to enable SDIO */
641 if (variant->sdio && host->mmc->card)
642 if (mmc_card_sdio(host->mmc->card))
643 datactrl |= MCI_ST_DPSM_SDIOEN;
645 writel(datactrl, base + MMCIDATACTRL);
646 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
647 mmci_set_mask1(host, irqmask);
651 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
653 void __iomem *base = host->base;
655 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
656 cmd->opcode, cmd->arg, cmd->flags);
658 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
659 writel(0, base + MMCICOMMAND);
663 c |= cmd->opcode | MCI_CPSM_ENABLE;
664 if (cmd->flags & MMC_RSP_PRESENT) {
665 if (cmd->flags & MMC_RSP_136)
666 c |= MCI_CPSM_LONGRSP;
667 c |= MCI_CPSM_RESPONSE;
670 c |= MCI_CPSM_INTERRUPT;
674 writel(cmd->arg, base + MMCIARGUMENT);
675 writel(c, base + MMCICOMMAND);
679 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
682 /* First check for errors */
683 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
684 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
687 /* Terminate the DMA transfer */
688 if (dma_inprogress(host))
689 mmci_dma_data_error(host);
692 * Calculate how far we are into the transfer. Note that
693 * the data counter gives the number of bytes transferred
694 * on the MMC bus, not on the host side. On reads, this
695 * can be as much as a FIFO-worth of data ahead. This
696 * matters for FIFO overruns only.
698 remain = readl(host->base + MMCIDATACNT);
699 success = data->blksz * data->blocks - remain;
701 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
703 if (status & MCI_DATACRCFAIL) {
704 /* Last block was not successful */
706 data->error = -EILSEQ;
707 } else if (status & MCI_DATATIMEOUT) {
708 data->error = -ETIMEDOUT;
709 } else if (status & MCI_STARTBITERR) {
710 data->error = -ECOMM;
711 } else if (status & MCI_TXUNDERRUN) {
713 } else if (status & MCI_RXOVERRUN) {
714 if (success > host->variant->fifosize)
715 success -= host->variant->fifosize;
720 data->bytes_xfered = round_down(success, data->blksz);
723 if (status & MCI_DATABLOCKEND)
724 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
726 if (status & MCI_DATAEND || data->error) {
727 if (dma_inprogress(host))
728 mmci_dma_unmap(host, data);
729 mmci_stop_data(host);
732 /* The error clause is handled above, success! */
733 data->bytes_xfered = data->blksz * data->blocks;
736 mmci_request_end(host, data->mrq);
738 mmci_start_command(host, data->stop, 0);
744 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
747 void __iomem *base = host->base;
751 if (status & MCI_CMDTIMEOUT) {
752 cmd->error = -ETIMEDOUT;
753 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
754 cmd->error = -EILSEQ;
756 cmd->resp[0] = readl(base + MMCIRESPONSE0);
757 cmd->resp[1] = readl(base + MMCIRESPONSE1);
758 cmd->resp[2] = readl(base + MMCIRESPONSE2);
759 cmd->resp[3] = readl(base + MMCIRESPONSE3);
762 if (!cmd->data || cmd->error) {
764 /* Terminate the DMA transfer */
765 if (dma_inprogress(host))
766 mmci_dma_data_error(host);
767 mmci_stop_data(host);
769 mmci_request_end(host, cmd->mrq);
770 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
771 mmci_start_data(host, cmd->data);
775 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
777 void __iomem *base = host->base;
780 int host_remain = host->size;
783 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
791 readsl(base + MMCIFIFO, ptr, count >> 2);
795 host_remain -= count;
800 status = readl(base + MMCISTATUS);
801 } while (status & MCI_RXDATAAVLBL);
806 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
808 struct variant_data *variant = host->variant;
809 void __iomem *base = host->base;
813 unsigned int count, maxcnt;
815 maxcnt = status & MCI_TXFIFOEMPTY ?
816 variant->fifosize : variant->fifohalfsize;
817 count = min(remain, maxcnt);
820 * The ST Micro variant for SDIO transfer sizes
821 * less then 8 bytes should have clock H/W flow
825 mmc_card_sdio(host->mmc->card)) {
827 writel(readl(host->base + MMCICLOCK) &
828 ~variant->clkreg_enable,
829 host->base + MMCICLOCK);
831 writel(readl(host->base + MMCICLOCK) |
832 variant->clkreg_enable,
833 host->base + MMCICLOCK);
837 * SDIO especially may want to send something that is
838 * not divisible by 4 (as opposed to card sectors
839 * etc), and the FIFO only accept full 32-bit writes.
840 * So compensate by adding +3 on the count, a single
841 * byte become a 32bit write, 7 bytes will be two
844 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2);
852 status = readl(base + MMCISTATUS);
853 } while (status & MCI_TXFIFOHALFEMPTY);
859 * PIO data transfer IRQ handler.
861 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
863 struct mmci_host *host = dev_id;
864 struct sg_mapping_iter *sg_miter = &host->sg_miter;
865 struct variant_data *variant = host->variant;
866 void __iomem *base = host->base;
870 status = readl(base + MMCISTATUS);
872 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
874 local_irq_save(flags);
877 unsigned int remain, len;
881 * For write, we only need to test the half-empty flag
882 * here - if the FIFO is completely empty, then by
883 * definition it is more than half empty.
885 * For read, check for data available.
887 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
890 if (!sg_miter_next(sg_miter))
893 buffer = sg_miter->addr;
894 remain = sg_miter->length;
897 if (status & MCI_RXACTIVE)
898 len = mmci_pio_read(host, buffer, remain);
899 if (status & MCI_TXACTIVE)
900 len = mmci_pio_write(host, buffer, remain, status);
902 sg_miter->consumed = len;
910 status = readl(base + MMCISTATUS);
913 sg_miter_stop(sg_miter);
915 local_irq_restore(flags);
918 * If we have less than the fifo 'half-full' threshold to transfer,
919 * trigger a PIO interrupt as soon as any data is available.
921 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
922 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
925 * If we run out of data, disable the data IRQs; this
926 * prevents a race where the FIFO becomes empty before
927 * the chip itself has disabled the data path, and
928 * stops us racing with our data end IRQ.
930 if (host->size == 0) {
931 mmci_set_mask1(host, 0);
932 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
939 * Handle completion of command and data transfers.
941 static irqreturn_t mmci_irq(int irq, void *dev_id)
943 struct mmci_host *host = dev_id;
947 spin_lock(&host->lock);
950 struct mmc_command *cmd;
951 struct mmc_data *data;
953 status = readl(host->base + MMCISTATUS);
955 if (host->singleirq) {
956 if (status & readl(host->base + MMCIMASK1))
957 mmci_pio_irq(irq, dev_id);
959 status &= ~MCI_IRQ1MASK;
962 status &= readl(host->base + MMCIMASK0);
963 writel(status, host->base + MMCICLEAR);
965 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
968 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
969 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
970 MCI_DATABLOCKEND) && data)
971 mmci_data_irq(host, data, status);
974 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
975 mmci_cmd_irq(host, cmd, status);
980 spin_unlock(&host->lock);
982 return IRQ_RETVAL(ret);
985 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
987 struct mmci_host *host = mmc_priv(mmc);
990 WARN_ON(host->mrq != NULL);
992 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
993 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
995 mrq->cmd->error = -EINVAL;
996 mmc_request_done(mmc, mrq);
1000 pm_runtime_get_sync(mmc_dev(mmc));
1002 spin_lock_irqsave(&host->lock, flags);
1007 mmci_get_next_data(host, mrq->data);
1009 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1010 mmci_start_data(host, mrq->data);
1012 mmci_start_command(host, mrq->cmd, 0);
1014 spin_unlock_irqrestore(&host->lock, flags);
1017 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1019 struct mmci_host *host = mmc_priv(mmc);
1021 unsigned long flags;
1024 switch (ios->power_mode) {
1027 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0);
1031 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd);
1033 dev_err(mmc_dev(mmc), "unable to set OCR\n");
1035 * The .set_ios() function in the mmc_host_ops
1036 * struct return void, and failing to set the
1037 * power should be rare so we print an error
1043 if (host->plat->vdd_handler)
1044 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
1046 /* The ST version does not have this, fall through to POWER_ON */
1047 if (host->hw_designer != AMBA_VENDOR_ST) {
1056 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1057 if (host->hw_designer != AMBA_VENDOR_ST)
1061 * The ST Micro variant use the ROD bit for something
1062 * else and only has OD (Open Drain).
1068 spin_lock_irqsave(&host->lock, flags);
1070 mmci_set_clkreg(host, ios->clock);
1072 if (host->pwr != pwr) {
1074 writel(pwr, host->base + MMCIPOWER);
1077 spin_unlock_irqrestore(&host->lock, flags);
1080 static int mmci_get_ro(struct mmc_host *mmc)
1082 struct mmci_host *host = mmc_priv(mmc);
1084 if (host->gpio_wp == -ENOSYS)
1087 return gpio_get_value_cansleep(host->gpio_wp);
1090 static int mmci_get_cd(struct mmc_host *mmc)
1092 struct mmci_host *host = mmc_priv(mmc);
1093 struct mmci_platform_data *plat = host->plat;
1094 unsigned int status;
1096 if (host->gpio_cd == -ENOSYS) {
1098 return 1; /* Assume always present */
1100 status = plat->status(mmc_dev(host->mmc));
1102 status = !!gpio_get_value_cansleep(host->gpio_cd)
1106 * Use positive logic throughout - status is zero for no card,
1107 * non-zero for card inserted.
1112 static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
1114 struct mmci_host *host = dev_id;
1116 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1121 static const struct mmc_host_ops mmci_ops = {
1122 .request = mmci_request,
1123 .pre_req = mmci_pre_request,
1124 .post_req = mmci_post_request,
1125 .set_ios = mmci_set_ios,
1126 .get_ro = mmci_get_ro,
1127 .get_cd = mmci_get_cd,
1130 static int __devinit mmci_probe(struct amba_device *dev,
1131 const struct amba_id *id)
1133 struct mmci_platform_data *plat = dev->dev.platform_data;
1134 struct variant_data *variant = id->data;
1135 struct mmci_host *host;
1136 struct mmc_host *mmc;
1139 /* must have platform data */
1145 ret = amba_request_regions(dev, DRIVER_NAME);
1149 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1155 host = mmc_priv(mmc);
1158 host->gpio_wp = -ENOSYS;
1159 host->gpio_cd = -ENOSYS;
1160 host->gpio_cd_irq = -1;
1162 host->hw_designer = amba_manf(dev);
1163 host->hw_revision = amba_rev(dev);
1164 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1165 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1167 host->clk = clk_get(&dev->dev, NULL);
1168 if (IS_ERR(host->clk)) {
1169 ret = PTR_ERR(host->clk);
1174 ret = clk_prepare(host->clk);
1178 ret = clk_enable(host->clk);
1183 host->variant = variant;
1184 host->mclk = clk_get_rate(host->clk);
1186 * According to the spec, mclk is max 100 MHz,
1187 * so we try to adjust the clock down to this,
1190 if (host->mclk > 100000000) {
1191 ret = clk_set_rate(host->clk, 100000000);
1194 host->mclk = clk_get_rate(host->clk);
1195 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1198 host->phybase = dev->res.start;
1199 host->base = ioremap(dev->res.start, resource_size(&dev->res));
1205 mmc->ops = &mmci_ops;
1207 * The ARM and ST versions of the block have slightly different
1208 * clock divider equations which means that the minimum divider
1211 if (variant->st_clkdiv)
1212 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1214 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1216 * If the platform data supplies a maximum operating
1217 * frequency, this takes precedence. Else, we fall back
1218 * to using the module parameter, which has a (low)
1219 * default value in case it is not specified. Either
1220 * value must not exceed the clock rate into the block,
1224 mmc->f_max = min(host->mclk, plat->f_max);
1226 mmc->f_max = min(host->mclk, fmax);
1227 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1229 #ifdef CONFIG_REGULATOR
1230 /* If we're using the regulator framework, try to fetch a regulator */
1231 host->vcc = regulator_get(&dev->dev, "vmmc");
1232 if (IS_ERR(host->vcc))
1235 int mask = mmc_regulator_get_ocrmask(host->vcc);
1238 dev_err(&dev->dev, "error getting OCR mask (%d)\n",
1241 host->mmc->ocr_avail = (u32) mask;
1244 "Provided ocr_mask/setpower will not be used "
1245 "(using regulator instead)\n");
1249 /* Fall back to platform data if no regulator is found */
1250 if (host->vcc == NULL)
1251 mmc->ocr_avail = plat->ocr_mask;
1252 mmc->caps = plat->capabilities;
1253 mmc->caps2 = plat->capabilities2;
1258 mmc->max_segs = NR_SG;
1261 * Since only a certain number of bits are valid in the data length
1262 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1265 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1268 * Set the maximum segment size. Since we aren't doing DMA
1269 * (yet) we are only limited by the data length register.
1271 mmc->max_seg_size = mmc->max_req_size;
1274 * Block size can be up to 2048 bytes, but must be a power of two.
1276 mmc->max_blk_size = 2048;
1279 * No limit on the number of blocks transferred.
1281 mmc->max_blk_count = mmc->max_req_size;
1283 spin_lock_init(&host->lock);
1285 writel(0, host->base + MMCIMASK0);
1286 writel(0, host->base + MMCIMASK1);
1287 writel(0xfff, host->base + MMCICLEAR);
1289 if (gpio_is_valid(plat->gpio_cd)) {
1290 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1292 ret = gpio_direction_input(plat->gpio_cd);
1294 host->gpio_cd = plat->gpio_cd;
1295 else if (ret != -ENOSYS)
1299 * A gpio pin that will detect cards when inserted and removed
1300 * will most likely want to trigger on the edges if it is
1301 * 0 when ejected and 1 when inserted (or mutatis mutandis
1302 * for the inverted case) so we request triggers on both
1305 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
1307 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1308 DRIVER_NAME " (cd)", host);
1310 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
1312 if (gpio_is_valid(plat->gpio_wp)) {
1313 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1315 ret = gpio_direction_input(plat->gpio_wp);
1317 host->gpio_wp = plat->gpio_wp;
1318 else if (ret != -ENOSYS)
1322 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1323 && host->gpio_cd_irq < 0)
1324 mmc->caps |= MMC_CAP_NEEDS_POLL;
1326 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
1330 if (dev->irq[1] == NO_IRQ)
1331 host->singleirq = true;
1333 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1334 DRIVER_NAME " (pio)", host);
1339 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1341 amba_set_drvdata(dev, mmc);
1343 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1344 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1345 amba_rev(dev), (unsigned long long)dev->res.start,
1346 dev->irq[0], dev->irq[1]);
1348 mmci_dma_setup(host);
1350 pm_runtime_put(&dev->dev);
1357 free_irq(dev->irq[0], host);
1359 if (host->gpio_wp != -ENOSYS)
1360 gpio_free(host->gpio_wp);
1362 if (host->gpio_cd_irq >= 0)
1363 free_irq(host->gpio_cd_irq, host);
1364 if (host->gpio_cd != -ENOSYS)
1365 gpio_free(host->gpio_cd);
1367 iounmap(host->base);
1369 clk_disable(host->clk);
1371 clk_unprepare(host->clk);
1377 amba_release_regions(dev);
1382 static int __devexit mmci_remove(struct amba_device *dev)
1384 struct mmc_host *mmc = amba_get_drvdata(dev);
1386 amba_set_drvdata(dev, NULL);
1389 struct mmci_host *host = mmc_priv(mmc);
1392 * Undo pm_runtime_put() in probe. We use the _sync
1393 * version here so that we can access the primecell.
1395 pm_runtime_get_sync(&dev->dev);
1397 mmc_remove_host(mmc);
1399 writel(0, host->base + MMCIMASK0);
1400 writel(0, host->base + MMCIMASK1);
1402 writel(0, host->base + MMCICOMMAND);
1403 writel(0, host->base + MMCIDATACTRL);
1405 mmci_dma_release(host);
1406 free_irq(dev->irq[0], host);
1407 if (!host->singleirq)
1408 free_irq(dev->irq[1], host);
1410 if (host->gpio_wp != -ENOSYS)
1411 gpio_free(host->gpio_wp);
1412 if (host->gpio_cd_irq >= 0)
1413 free_irq(host->gpio_cd_irq, host);
1414 if (host->gpio_cd != -ENOSYS)
1415 gpio_free(host->gpio_cd);
1417 iounmap(host->base);
1418 clk_disable(host->clk);
1419 clk_unprepare(host->clk);
1423 mmc_regulator_set_ocr(mmc, host->vcc, 0);
1424 regulator_put(host->vcc);
1428 amba_release_regions(dev);
1435 static int mmci_suspend(struct amba_device *dev, pm_message_t state)
1437 struct mmc_host *mmc = amba_get_drvdata(dev);
1441 struct mmci_host *host = mmc_priv(mmc);
1443 ret = mmc_suspend_host(mmc);
1445 writel(0, host->base + MMCIMASK0);
1451 static int mmci_resume(struct amba_device *dev)
1453 struct mmc_host *mmc = amba_get_drvdata(dev);
1457 struct mmci_host *host = mmc_priv(mmc);
1459 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1461 ret = mmc_resume_host(mmc);
1467 #define mmci_suspend NULL
1468 #define mmci_resume NULL
1471 static struct amba_id mmci_ids[] = {
1475 .data = &variant_arm,
1480 .data = &variant_arm_extended_fifo,
1485 .data = &variant_arm,
1487 /* ST Micro variants */
1491 .data = &variant_u300,
1496 .data = &variant_u300,
1501 .data = &variant_ux500,
1506 .data = &variant_ux500v2,
1511 MODULE_DEVICE_TABLE(amba, mmci_ids);
1513 static struct amba_driver mmci_driver = {
1515 .name = DRIVER_NAME,
1517 .probe = mmci_probe,
1518 .remove = __devexit_p(mmci_remove),
1519 .suspend = mmci_suspend,
1520 .resume = mmci_resume,
1521 .id_table = mmci_ids,
1524 static int __init mmci_init(void)
1526 return amba_driver_register(&mmci_driver);
1529 static void __exit mmci_exit(void)
1531 amba_driver_unregister(&mmci_driver);
1534 module_init(mmci_init);
1535 module_exit(mmci_exit);
1536 module_param(fmax, uint, 0444);
1538 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1539 MODULE_LICENSE("GPL");