drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/timer.h>
  29 #include <linux/clk.h>
  30 #include <linux/of.h>
  31 #include <linux/of_gpio.h>
  32 #include <linux/of_device.h>
  33 #include <linux/omap-dma.h>
  34 #include <linux/mmc/host.h>
  35 #include <linux/mmc/core.h>
  36 #include <linux/mmc/mmc.h>
  37 #include <linux/io.h>
  38 #include <linux/gpio.h>
  39 #include <linux/regulator/consumer.h>
  40 #include <linux/pm_runtime.h>
  41 #include <mach/hardware.h>
  42 #include <plat/mmc.h>
  43 #include <plat/cpu.h>
  44
  45 /* OMAP HSMMC Host Controller Registers */
  46 #define OMAP_HSMMC_SYSSTATUS    0x0014
  47 #define OMAP_HSMMC_CON          0x002C
  48 #define OMAP_HSMMC_BLK          0x0104
  49 #define OMAP_HSMMC_ARG          0x0108
  50 #define OMAP_HSMMC_CMD          0x010C
  51 #define OMAP_HSMMC_RSP10        0x0110
  52 #define OMAP_HSMMC_RSP32        0x0114
  53 #define OMAP_HSMMC_RSP54        0x0118
  54 #define OMAP_HSMMC_RSP76        0x011C
  55 #define OMAP_HSMMC_DATA         0x0120
  56 #define OMAP_HSMMC_HCTL         0x0128
  57 #define OMAP_HSMMC_SYSCTL       0x012C
  58 #define OMAP_HSMMC_STAT         0x0130
  59 #define OMAP_HSMMC_IE           0x0134
  60 #define OMAP_HSMMC_ISE          0x0138
  61 #define OMAP_HSMMC_CAPA         0x0140
  62
  63 #define VS18                    (1 << 26)
  64 #define VS30                    (1 << 25)
  65 #define SDVS18                  (0x5 << 9)
  66 #define SDVS30                  (0x6 << 9)
  67 #define SDVS33                  (0x7 << 9)
  68 #define SDVS_MASK               0x00000E00
  69 #define SDVSCLR                 0xFFFFF1FF
  70 #define SDVSDET                 0x00000400
  71 #define AUTOIDLE                0x1
  72 #define SDBP                    (1 << 8)
  73 #define DTO                     0xe
  74 #define ICE                     0x1
  75 #define ICS                     0x2
  76 #define CEN                     (1 << 2)
  77 #define CLKD_MASK               0x0000FFC0
  78 #define CLKD_SHIFT              6
  79 #define DTO_MASK                0x000F0000
  80 #define DTO_SHIFT               16
  81 #define INT_EN_MASK             0x307F0033
  82 #define BWR_ENABLE              (1 << 4)
  83 #define BRR_ENABLE              (1 << 5)
  84 #define DTO_ENABLE              (1 << 20)
  85 #define INIT_STREAM             (1 << 1)
  86 #define DP_SELECT               (1 << 21)
  87 #define DDIR                    (1 << 4)
  88 #define DMA_EN                  0x1
  89 #define MSBS                    (1 << 5)
  90 #define BCE                     (1 << 1)
  91 #define FOUR_BIT                (1 << 1)
  92 #define DDR                     (1 << 19)
  93 #define DW8                     (1 << 5)
  94 #define CC                      0x1
  95 #define TC                      0x02
  96 #define OD                      0x1
  97 #define ERR                     (1 << 15)
  98 #define CMD_TIMEOUT             (1 << 16)
  99 #define DATA_TIMEOUT            (1 << 20)
 100 #define CMD_CRC                 (1 << 17)
 101 #define DATA_CRC                (1 << 21)
 102 #define CARD_ERR                (1 << 28)
 103 #define STAT_CLEAR              0xFFFFFFFF
 104 #define INIT_STREAM_CMD         0x00000000
 105 #define DUAL_VOLT_OCR_BIT       7
 106 #define SRC                     (1 << 25)
 107 #define SRD                     (1 << 26)
 108 #define SOFTRESET               (1 << 1)
 109 #define RESETDONE               (1 << 0)
 110
 111 #define MMC_AUTOSUSPEND_DELAY   100
 112 #define MMC_TIMEOUT_MS          20
 113 #define OMAP_MMC_MIN_CLOCK      400000
 114 #define OMAP_MMC_MAX_CLOCK      52000000
 115 #define DRIVER_NAME             "omap_hsmmc"
 116
 117 /*
 118  * One controller can have multiple slots, like on some omap boards using
 119  * omap.c controller driver. Luckily this is not currently done on any known
 120  * omap_hsmmc.c device.
 121  */
 122 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 123
 124 /*
 125  * MMC Host controller read/write API's
 126  */
 127 #define OMAP_HSMMC_READ(base, reg)      \
 128         __raw_readl((base) + OMAP_HSMMC_##reg)
 129
 130 #define OMAP_HSMMC_WRITE(base, reg, val) \
 131         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 132
 133 struct omap_hsmmc_next {
 134         unsigned int    dma_len;
 135         s32             cookie;
 136 };
 137
 138 struct omap_hsmmc_host {
 139         struct  device          *dev;
 140         struct  mmc_host        *mmc;
 141         struct  mmc_request     *mrq;
 142         struct  mmc_command     *cmd;
 143         struct  mmc_data        *data;
 144         struct  clk             *fclk;
 145         struct  clk             *dbclk;
 146         /*
 147          * vcc == configured supply
 148          * vcc_aux == optional
 149          *   -  MMC1, supply for DAT4..DAT7
 150          *   -  MMC2/MMC2, external level shifter voltage supply, for
 151          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 152          */
 153         struct  regulator       *vcc;
 154         struct  regulator       *vcc_aux;
 155         void    __iomem         *base;
 156         resource_size_t         mapbase;
 157         spinlock_t              irq_lock; /* Prevent races with irq handler */
 158         unsigned int            dma_len;
 159         unsigned int            dma_sg_idx;
 160         unsigned char           bus_mode;
 161         unsigned char           power_mode;
 162         int                     suspended;
 163         int                     irq;
 164         int                     use_dma, dma_ch;
 165         struct dma_chan         *tx_chan;
 166         struct dma_chan         *rx_chan;
 167         int                     slot_id;
 168         int                     response_busy;
 169         int                     context_loss;
 170         int                     protect_card;
 171         int                     reqs_blocked;
 172         int                     use_reg;
 173         int                     req_in_progress;
 174         struct omap_hsmmc_next  next_data;
 175
 176         struct  omap_mmc_platform_data  *pdata;
 177 };
 178
 179 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 180 {
 181         struct omap_mmc_platform_data *mmc = dev->platform_data;
 182
 183         /* NOTE: assumes card detect signal is active-low */
 184         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 185 }
 186
 187 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 188 {
 189         struct omap_mmc_platform_data *mmc = dev->platform_data;
 190
 191         /* NOTE: assumes write protect signal is active-high */
 192         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 193 }
 194
 195 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 196 {
 197         struct omap_mmc_platform_data *mmc = dev->platform_data;
 198
 199         /* NOTE: assumes card detect signal is active-low */
 200         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 201 }
 202
 203 #ifdef CONFIG_PM
 204
 205 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 206 {
 207         struct omap_mmc_platform_data *mmc = dev->platform_data;
 208
 209         disable_irq(mmc->slots[0].card_detect_irq);
 210         return 0;
 211 }
 212
 213 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 214 {
 215         struct omap_mmc_platform_data *mmc = dev->platform_data;
 216
 217         enable_irq(mmc->slots[0].card_detect_irq);
 218         return 0;
 219 }
 220
 221 #else
 222
 223 #define omap_hsmmc_suspend_cdirq        NULL
 224 #define omap_hsmmc_resume_cdirq         NULL
 225
 226 #endif
 227
 228 #ifdef CONFIG_REGULATOR
 229
 230 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
 231                                    int vdd)
 232 {
 233         struct omap_hsmmc_host *host =
 234                 platform_get_drvdata(to_platform_device(dev));
 235         int ret = 0;
 236
 237         /*
 238          * If we don't see a Vcc regulator, assume it's a fixed
 239          * voltage always-on regulator.
 240          */
 241         if (!host->vcc)
 242                 return 0;
 243         /*
 244          * With DT, never turn OFF the regulator. This is because
 245          * the pbias cell programming support is still missing when
 246          * booting with Device tree
 247          */
 248         if (dev->of_node && !vdd)
 249                 return 0;
 250
 251         if (mmc_slot(host).before_set_reg)
 252                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 253
 254         /*
 255          * Assume Vcc regulator is used only to power the card ... OMAP
 256          * VDDS is used to power the pins, optionally with a transceiver to
 257          * support cards using voltages other than VDDS (1.8V nominal).  When a
 258          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 259          *
 260          * In some cases this regulator won't support enable/disable;
 261          * e.g. it's a fixed rail for a WLAN chip.
 262          *
 263          * In other cases vcc_aux switches interface power.  Example, for
 264          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 265          * chips/cards need an interface voltage rail too.
 266          */
 267         if (power_on) {
 268                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 269                 /* Enable interface voltage rail, if needed */
 270                 if (ret == 0 && host->vcc_aux) {
 271                         ret = regulator_enable(host->vcc_aux);
 272                         if (ret < 0)
 273                                 ret = mmc_regulator_set_ocr(host->mmc,
 274                                                         host->vcc, 0);
 275                 }
 276         } else {
 277                 /* Shut down the rail */
 278                 if (host->vcc_aux)
 279                         ret = regulator_disable(host->vcc_aux);
 280                 if (!ret) {
 281                         /* Then proceed to shut down the local regulator */
 282                         ret = mmc_regulator_set_ocr(host->mmc,
 283                                                 host->vcc, 0);
 284                 }
 285         }
 286
 287         if (mmc_slot(host).after_set_reg)
 288                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 289
 290         return ret;
 291 }
 292
 293 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 294 {
 295         struct regulator *reg;
 296         int ocr_value = 0;
 297
 298         reg = regulator_get(host->dev, "vmmc");
 299         if (IS_ERR(reg)) {
 300                 dev_dbg(host->dev, "vmmc regulator missing\n");
 301                 return PTR_ERR(reg);
 302         } else {
 303                 mmc_slot(host).set_power = omap_hsmmc_set_power;
 304                 host->vcc = reg;
 305                 ocr_value = mmc_regulator_get_ocrmask(reg);
 306                 if (!mmc_slot(host).ocr_mask) {
 307                         mmc_slot(host).ocr_mask = ocr_value;
 308                 } else {
 309                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 310                                 dev_err(host->dev, "ocrmask %x is not supported\n",
 311                                         mmc_slot(host).ocr_mask);
 312                                 mmc_slot(host).ocr_mask = 0;
 313                                 return -EINVAL;
 314                         }
 315                 }
 316
 317                 /* Allow an aux regulator */
 318                 reg = regulator_get(host->dev, "vmmc_aux");
 319                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 320
 321                 /* For eMMC do not power off when not in sleep state */
 322                 if (mmc_slot(host).no_regulator_off_init)
 323                         return 0;
 324                 /*
 325                 * UGLY HACK:  workaround regulator framework bugs.
 326                 * When the bootloader leaves a supply active, it's
 327                 * initialized with zero usecount ... and we can't
 328                 * disable it without first enabling it.  Until the
 329                 * framework is fixed, we need a workaround like this
 330                 * (which is safe for MMC, but not in general).
 331                 */
 332                 if (regulator_is_enabled(host->vcc) > 0 ||
 333                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 334                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
 335
 336                         mmc_slot(host).set_power(host->dev, host->slot_id,
 337                                                  1, vdd);
 338                         mmc_slot(host).set_power(host->dev, host->slot_id,
 339                                                  0, 0);
 340                 }
 341         }
 342
 343         return 0;
 344 }
 345
 346 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 347 {
 348         regulator_put(host->vcc);
 349         regulator_put(host->vcc_aux);
 350         mmc_slot(host).set_power = NULL;
 351 }
 352
 353 static inline int omap_hsmmc_have_reg(void)
 354 {
 355         return 1;
 356 }
 357
 358 #else
 359
 360 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 361 {
 362         return -EINVAL;
 363 }
 364
 365 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 366 {
 367 }
 368
 369 static inline int omap_hsmmc_have_reg(void)
 370 {
 371         return 0;
 372 }
 373
 374 #endif
 375
 376 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 377 {
 378         int ret;
 379
 380         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 381                 if (pdata->slots[0].cover)
 382                         pdata->slots[0].get_cover_state =
 383                                         omap_hsmmc_get_cover_state;
 384                 else
 385                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 386                 pdata->slots[0].card_detect_irq =
 387                                 gpio_to_irq(pdata->slots[0].switch_pin);
 388                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 389                 if (ret)
 390                         return ret;
 391                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 392                 if (ret)
 393                         goto err_free_sp;
 394         } else
 395                 pdata->slots[0].switch_pin = -EINVAL;
 396
 397         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 398                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 399                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 400                 if (ret)
 401                         goto err_free_cd;
 402                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 403                 if (ret)
 404                         goto err_free_wp;
 405         } else
 406                 pdata->slots[0].gpio_wp = -EINVAL;
 407
 408         return 0;
 409
 410 err_free_wp:
 411         gpio_free(pdata->slots[0].gpio_wp);
 412 err_free_cd:
 413         if (gpio_is_valid(pdata->slots[0].switch_pin))
 414 err_free_sp:
 415                 gpio_free(pdata->slots[0].switch_pin);
 416         return ret;
 417 }
 418
 419 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 420 {
 421         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 422                 gpio_free(pdata->slots[0].gpio_wp);
 423         if (gpio_is_valid(pdata->slots[0].switch_pin))
 424                 gpio_free(pdata->slots[0].switch_pin);
 425 }
 426
 427 /*
 428  * Start clock to the card
 429  */
 430 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 431 {
 432         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 433                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 434 }
 435
 436 /*
 437  * Stop clock to the card
 438  */
 439 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 440 {
 441         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 442                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 443         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 444                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
 445 }
 446
 447 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 448                                   struct mmc_command *cmd)
 449 {
 450         unsigned int irq_mask;
 451
 452         if (host->use_dma)
 453                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
 454         else
 455                 irq_mask = INT_EN_MASK;
 456
 457         /* Disable timeout for erases */
 458         if (cmd->opcode == MMC_ERASE)
 459                 irq_mask &= ~DTO_ENABLE;
 460
 461         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 462         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 463         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 464 }
 465
 466 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 467 {
 468         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 469         OMAP_HSMMC_WRITE(host->base, IE, 0);
 470         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 471 }
 472
 473 /* Calculate divisor for the given clock frequency */
 474 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 475 {
 476         u16 dsor = 0;
 477
 478         if (ios->clock) {
 479                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 480                 if (dsor > 250)
 481                         dsor = 250;
 482         }
 483
 484         return dsor;
 485 }
 486
 487 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 488 {
 489         struct mmc_ios *ios = &host->mmc->ios;
 490         unsigned long regval;
 491         unsigned long timeout;
 492
 493         dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 494
 495         omap_hsmmc_stop_clock(host);
 496
 497         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 498         regval = regval & ~(CLKD_MASK | DTO_MASK);
 499         regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
 500         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 501         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 502                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 503
 504         /* Wait till the ICS bit is set */
 505         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 506         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 507                 && time_before(jiffies, timeout))
 508                 cpu_relax();
 509
 510         omap_hsmmc_start_clock(host);
 511 }
 512
 513 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 514 {
 515         struct mmc_ios *ios = &host->mmc->ios;
 516         u32 con;
 517
 518         con = OMAP_HSMMC_READ(host->base, CON);
 519         if (ios->timing == MMC_TIMING_UHS_DDR50)
 520                 con |= DDR;     /* configure in DDR mode */
 521         else
 522                 con &= ~DDR;
 523         switch (ios->bus_width) {
 524         case MMC_BUS_WIDTH_8:
 525                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 526                 break;
 527         case MMC_BUS_WIDTH_4:
 528                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 529                 OMAP_HSMMC_WRITE(host->base, HCTL,
 530                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 531                 break;
 532         case MMC_BUS_WIDTH_1:
 533                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 534                 OMAP_HSMMC_WRITE(host->base, HCTL,
 535                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 536                 break;
 537         }
 538 }
 539
 540 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 541 {
 542         struct mmc_ios *ios = &host->mmc->ios;
 543         u32 con;
 544
 545         con = OMAP_HSMMC_READ(host->base, CON);
 546         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 547                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 548         else
 549                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 550 }
 551
 552 #ifdef CONFIG_PM
 553
 554 /*
 555  * Restore the MMC host context, if it was lost as result of a
 556  * power state change.
 557  */
 558 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 559 {
 560         struct mmc_ios *ios = &host->mmc->ios;
 561         struct omap_mmc_platform_data *pdata = host->pdata;
 562         int context_loss = 0;
 563         u32 hctl, capa;
 564         unsigned long timeout;
 565
 566         if (pdata->get_context_loss_count) {
 567                 context_loss = pdata->get_context_loss_count(host->dev);
 568                 if (context_loss < 0)
 569                         return 1;
 570         }
 571
 572         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 573                 context_loss == host->context_loss ? "not " : "");
 574         if (host->context_loss == context_loss)
 575                 return 1;
 576
 577         if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
 578                 return 1;
 579
 580         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 581                 if (host->power_mode != MMC_POWER_OFF &&
 582                     (1 << ios->vdd) <= MMC_VDD_23_24)
 583                         hctl = SDVS18;
 584                 else
 585                         hctl = SDVS30;
 586                 capa = VS30 | VS18;
 587         } else {
 588                 hctl = SDVS18;
 589                 capa = VS18;
 590         }
 591
 592         OMAP_HSMMC_WRITE(host->base, HCTL,
 593                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 594
 595         OMAP_HSMMC_WRITE(host->base, CAPA,
 596                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 597
 598         OMAP_HSMMC_WRITE(host->base, HCTL,
 599                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 600
 601         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 602         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 603                 && time_before(jiffies, timeout))
 604                 ;
 605
 606         omap_hsmmc_disable_irq(host);
 607
 608         /* Do not initialize card-specific things if the power is off */
 609         if (host->power_mode == MMC_POWER_OFF)
 610                 goto out;
 611
 612         omap_hsmmc_set_bus_width(host);
 613
 614         omap_hsmmc_set_clock(host);
 615
 616         omap_hsmmc_set_bus_mode(host);
 617
 618 out:
 619         host->context_loss = context_loss;
 620
 621         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 622         return 0;
 623 }
 624
 625 /*
 626  * Save the MMC host context (store the number of power state changes so far).
 627  */
 628 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 629 {
 630         struct omap_mmc_platform_data *pdata = host->pdata;
 631         int context_loss;
 632
 633         if (pdata->get_context_loss_count) {
 634                 context_loss = pdata->get_context_loss_count(host->dev);
 635                 if (context_loss < 0)
 636                         return;
 637                 host->context_loss = context_loss;
 638         }
 639 }
 640
 641 #else
 642
 643 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 644 {
 645         return 0;
 646 }
 647
 648 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 649 {
 650 }
 651
 652 #endif
 653
 654 /*
 655  * Send init stream sequence to card
 656  * before sending IDLE command
 657  */
 658 static void send_init_stream(struct omap_hsmmc_host *host)
 659 {
 660         int reg = 0;
 661         unsigned long timeout;
 662
 663         if (host->protect_card)
 664                 return;
 665
 666         disable_irq(host->irq);
 667
 668         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 669         OMAP_HSMMC_WRITE(host->base, CON,
 670                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 671         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 672
 673         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 674         while ((reg != CC) && time_before(jiffies, timeout))
 675                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 676
 677         OMAP_HSMMC_WRITE(host->base, CON,
 678                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 679
 680         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 681         OMAP_HSMMC_READ(host->base, STAT);
 682
 683         enable_irq(host->irq);
 684 }
 685
 686 static inline
 687 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 688 {
 689         int r = 1;
 690
 691         if (mmc_slot(host).get_cover_state)
 692                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 693         return r;
 694 }
 695
 696 static ssize_t
 697 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 698                            char *buf)
 699 {
 700         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 701         struct omap_hsmmc_host *host = mmc_priv(mmc);
 702
 703         return sprintf(buf, "%s\n",
 704                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 705 }
 706
 707 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 708
 709 static ssize_t
 710 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 711                         char *buf)
 712 {
 713         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 714         struct omap_hsmmc_host *host = mmc_priv(mmc);
 715
 716         return sprintf(buf, "%s\n", mmc_slot(host).name);
 717 }
 718
 719 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 720
 721 /*
 722  * Configure the response type and send the cmd.
 723  */
 724 static void
 725 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 726         struct mmc_data *data)
 727 {
 728         int cmdreg = 0, resptype = 0, cmdtype = 0;
 729
 730         dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 731                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 732         host->cmd = cmd;
 733
 734         omap_hsmmc_enable_irq(host, cmd);
 735
 736         host->response_busy = 0;
 737         if (cmd->flags & MMC_RSP_PRESENT) {
 738                 if (cmd->flags & MMC_RSP_136)
 739                         resptype = 1;
 740                 else if (cmd->flags & MMC_RSP_BUSY) {
 741                         resptype = 3;
 742                         host->response_busy = 1;
 743                 } else
 744                         resptype = 2;
 745         }
 746
 747         /*
 748          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 749          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 750          * a val of 0x3, rest 0x0.
 751          */
 752         if (cmd == host->mrq->stop)
 753                 cmdtype = 0x3;
 754
 755         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 756
 757         if (data) {
 758                 cmdreg |= DP_SELECT | MSBS | BCE;
 759                 if (data->flags & MMC_DATA_READ)
 760                         cmdreg |= DDIR;
 761                 else
 762                         cmdreg &= ~(DDIR);
 763         }
 764
 765         if (host->use_dma)
 766                 cmdreg |= DMA_EN;
 767
 768         host->req_in_progress = 1;
 769
 770         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 771         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 772 }
 773
 774 static int
 775 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 776 {
 777         if (data->flags & MMC_DATA_WRITE)
 778                 return DMA_TO_DEVICE;
 779         else
 780                 return DMA_FROM_DEVICE;
 781 }
 782
 783 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
 784         struct mmc_data *data)
 785 {
 786         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
 787 }
 788
 789 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 790 {
 791         int dma_ch;
 792         unsigned long flags;
 793
 794         spin_lock_irqsave(&host->irq_lock, flags);
 795         host->req_in_progress = 0;
 796         dma_ch = host->dma_ch;
 797         spin_unlock_irqrestore(&host->irq_lock, flags);
 798
 799         omap_hsmmc_disable_irq(host);
 800         /* Do not complete the request if DMA is still in progress */
 801         if (mrq->data && host->use_dma && dma_ch != -1)
 802                 return;
 803         host->mrq = NULL;
 804         mmc_request_done(host->mmc, mrq);
 805 }
 806
 807 /*
 808  * Notify the transfer complete to MMC core
 809  */
 810 static void
 811 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 812 {
 813         if (!data) {
 814                 struct mmc_request *mrq = host->mrq;
 815
 816                 /* TC before CC from CMD6 - don't know why, but it happens */
 817                 if (host->cmd && host->cmd->opcode == 6 &&
 818                     host->response_busy) {
 819                         host->response_busy = 0;
 820                         return;
 821                 }
 822
 823                 omap_hsmmc_request_done(host, mrq);
 824                 return;
 825         }
 826
 827         host->data = NULL;
 828
 829         if (!data->error)
 830                 data->bytes_xfered += data->blocks * (data->blksz);
 831         else
 832                 data->bytes_xfered = 0;
 833
 834         if (!data->stop) {
 835                 omap_hsmmc_request_done(host, data->mrq);
 836                 return;
 837         }
 838         omap_hsmmc_start_command(host, data->stop, NULL);
 839 }
 840
 841 /*
 842  * Notify the core about command completion
 843  */
 844 static void
 845 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 846 {
 847         host->cmd = NULL;
 848
 849         if (cmd->flags & MMC_RSP_PRESENT) {
 850                 if (cmd->flags & MMC_RSP_136) {
 851                         /* response type 2 */
 852                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 853                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 854                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 855                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 856                 } else {
 857                         /* response types 1, 1b, 3, 4, 5, 6 */
 858                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 859                 }
 860         }
 861         if ((host->data == NULL && !host->response_busy) || cmd->error)
 862                 omap_hsmmc_request_done(host, cmd->mrq);
 863 }
 864
 865 /*
 866  * DMA clean up for command errors
 867  */
 868 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 869 {
 870         int dma_ch;
 871         unsigned long flags;
 872
 873         host->data->error = errno;
 874
 875         spin_lock_irqsave(&host->irq_lock, flags);
 876         dma_ch = host->dma_ch;
 877         host->dma_ch = -1;
 878         spin_unlock_irqrestore(&host->irq_lock, flags);
 879
 880         if (host->use_dma && dma_ch != -1) {
 881                 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
 882
 883                 dmaengine_terminate_all(chan);
 884                 dma_unmap_sg(chan->device->dev,
 885                         host->data->sg, host->data->sg_len,
 886                         omap_hsmmc_get_dma_dir(host, host->data));
 887
 888                 host->data->host_cookie = 0;
 889         }
 890         host->data = NULL;
 891 }
 892
 893 /*
 894  * Readable error output
 895  */
 896 #ifdef CONFIG_MMC_DEBUG
 897 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
 898 {
 899         /* --- means reserved bit without definition at documentation */
 900         static const char *omap_hsmmc_status_bits[] = {
 901                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
 902                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
 903                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
 904                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
 905         };
 906         char res[256];
 907         char *buf = res;
 908         int len, i;
 909
 910         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 911         buf += len;
 912
 913         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 914                 if (status & (1 << i)) {
 915                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 916                         buf += len;
 917                 }
 918
 919         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
 920 }
 921 #else
 922 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
 923                                              u32 status)
 924 {
 925 }
 926 #endif  /* CONFIG_MMC_DEBUG */
 927
 928 /*
 929  * MMC controller internal state machines reset
 930  *
 931  * Used to reset command or data internal state machines, using respectively
 932  *  SRC or SRD bit of SYSCTL register
 933  * Can be called from interrupt context
 934  */
 935 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 936                                                    unsigned long bit)
 937 {
 938         unsigned long i = 0;
 939         unsigned long limit = (loops_per_jiffy *
 940                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 941
 942         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 943                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 944
 945         /*
 946          * OMAP4 ES2 and greater has an updated reset logic.
 947          * Monitor a 0->1 transition first
 948          */
 949         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
 950                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
 951                                         && (i++ < limit))
 952                         cpu_relax();
 953         }
 954         i = 0;
 955
 956         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 957                 (i++ < limit))
 958                 cpu_relax();
 959
 960         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 961                 dev_err(mmc_dev(host->mmc),
 962                         "Timeout waiting on controller reset in %s\n",
 963                         __func__);
 964 }
 965
 966 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, int err)
 967 {
 968         omap_hsmmc_reset_controller_fsm(host, SRC);
 969         host->cmd->error = err;
 970
 971         if (host->data) {
 972                 omap_hsmmc_reset_controller_fsm(host, SRD);
 973                 omap_hsmmc_dma_cleanup(host, err);
 974         }
 975
 976 }
 977
 978 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
 979 {
 980         struct mmc_data *data;
 981         int end_cmd = 0, end_trans = 0;
 982
 983         data = host->data;
 984         dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 985
 986         if (status & ERR) {
 987                 omap_hsmmc_dbg_report_irq(host, status);
 988                 if (status & (CMD_TIMEOUT | DATA_TIMEOUT))
 989                         hsmmc_command_incomplete(host, -ETIMEDOUT);
 990                 else if (status & (CMD_CRC | DATA_CRC))
 991                         hsmmc_command_incomplete(host, -EILSEQ);
 992
 993                 end_cmd = 1;
 994                 if (host->data || host->response_busy) {
 995                         end_trans = 1;
 996                         host->response_busy = 0;
 997                 }
 998         }
 999
1000         if (end_cmd || ((status & CC) && host->cmd))
1001                 omap_hsmmc_cmd_done(host, host->cmd);
1002         if ((end_trans || (status & TC)) && host->mrq)
1003                 omap_hsmmc_xfer_done(host, data);
1004 }
1005
1006 /*
1007  * MMC controller IRQ handler
1008  */
1009 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1010 {
1011         struct omap_hsmmc_host *host = dev_id;
1012         int status;
1013
1014         status = OMAP_HSMMC_READ(host->base, STAT);
1015         while (status & INT_EN_MASK && host->req_in_progress) {
1016                 omap_hsmmc_do_irq(host, status);
1017
1018                 /* Flush posted write */
1019                 OMAP_HSMMC_WRITE(host->base, STAT, status);
1020                 status = OMAP_HSMMC_READ(host->base, STAT);
1021         }
1022
1023         return IRQ_HANDLED;
1024 }
1025
1026 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1027 {
1028         unsigned long i;
1029
1030         OMAP_HSMMC_WRITE(host->base, HCTL,
1031                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1032         for (i = 0; i < loops_per_jiffy; i++) {
1033                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1034                         break;
1035                 cpu_relax();
1036         }
1037 }
1038
1039 /*
1040  * Switch MMC interface voltage ... only relevant for MMC1.
1041  *
1042  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1043  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1044  * Some chips, like eMMC ones, use internal transceivers.
1045  */
1046 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1047 {
1048         u32 reg_val = 0;
1049         int ret;
1050
1051         /* Disable the clocks */
1052         pm_runtime_put_sync(host->dev);
1053         if (host->dbclk)
1054                 clk_disable_unprepare(host->dbclk);
1055
1056         /* Turn the power off */
1057         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1058
1059         /* Turn the power ON with given VDD 1.8 or 3.0v */
1060         if (!ret)
1061                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1062                                                vdd);
1063         pm_runtime_get_sync(host->dev);
1064         if (host->dbclk)
1065                 clk_prepare_enable(host->dbclk);
1066
1067         if (ret != 0)
1068                 goto err;
1069
1070         OMAP_HSMMC_WRITE(host->base, HCTL,
1071                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1072         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1073
1074         /*
1075          * If a MMC dual voltage card is detected, the set_ios fn calls
1076          * this fn with VDD bit set for 1.8V. Upon card removal from the
1077          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1078          *
1079          * Cope with a bit of slop in the range ... per data sheets:
1080          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1081          *    but recommended values are 1.71V to 1.89V
1082          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1083          *    but recommended values are 2.7V to 3.3V
1084          *
1085          * Board setup code shouldn't permit anything very out-of-range.
1086          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1087          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1088          */
1089         if ((1 << vdd) <= MMC_VDD_23_24)
1090                 reg_val |= SDVS18;
1091         else
1092                 reg_val |= SDVS30;
1093
1094         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1095         set_sd_bus_power(host);
1096
1097         return 0;
1098 err:
1099         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1100         return ret;
1101 }
1102
1103 /* Protect the card while the cover is open */
1104 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1105 {
1106         if (!mmc_slot(host).get_cover_state)
1107                 return;
1108
1109         host->reqs_blocked = 0;
1110         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1111                 if (host->protect_card) {
1112                         dev_info(host->dev, "%s: cover is closed, "
1113                                          "card is now accessible\n",
1114                                          mmc_hostname(host->mmc));
1115                         host->protect_card = 0;
1116                 }
1117         } else {
1118                 if (!host->protect_card) {
1119                         dev_info(host->dev, "%s: cover is open, "
1120                                          "card is now inaccessible\n",
1121                                          mmc_hostname(host->mmc));
1122                         host->protect_card = 1;
1123                 }
1124         }
1125 }
1126
1127 /*
1128  * irq handler to notify the core about card insertion/removal
1129  */
1130 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1131 {
1132         struct omap_hsmmc_host *host = dev_id;
1133         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1134         int carddetect;
1135
1136         if (host->suspended)
1137                 return IRQ_HANDLED;
1138
1139         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1140
1141         if (slot->card_detect)
1142                 carddetect = slot->card_detect(host->dev, host->slot_id);
1143         else {
1144                 omap_hsmmc_protect_card(host);
1145                 carddetect = -ENOSYS;
1146         }
1147
1148         if (carddetect)
1149                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1150         else
1151                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1152         return IRQ_HANDLED;
1153 }
1154
1155 static void omap_hsmmc_dma_callback(void *param)
1156 {
1157         struct omap_hsmmc_host *host = param;
1158         struct dma_chan *chan;
1159         struct mmc_data *data;
1160         int req_in_progress;
1161
1162         spin_lock_irq(&host->irq_lock);
1163         if (host->dma_ch < 0) {
1164                 spin_unlock_irq(&host->irq_lock);
1165                 return;
1166         }
1167
1168         data = host->mrq->data;
1169         chan = omap_hsmmc_get_dma_chan(host, data);
1170         if (!data->host_cookie)
1171                 dma_unmap_sg(chan->device->dev,
1172                              data->sg, data->sg_len,
1173                              omap_hsmmc_get_dma_dir(host, data));
1174
1175         req_in_progress = host->req_in_progress;
1176         host->dma_ch = -1;
1177         spin_unlock_irq(&host->irq_lock);
1178
1179         /* If DMA has finished after TC, complete the request */
1180         if (!req_in_progress) {
1181                 struct mmc_request *mrq = host->mrq;
1182
1183                 host->mrq = NULL;
1184                 mmc_request_done(host->mmc, mrq);
1185         }
1186 }
1187
1188 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1189                                        struct mmc_data *data,
1190                                        struct omap_hsmmc_next *next,
1191                                        struct dma_chan *chan)
1192 {
1193         int dma_len;
1194
1195         if (!next && data->host_cookie &&
1196             data->host_cookie != host->next_data.cookie) {
1197                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1198                        " host->next_data.cookie %d\n",
1199                        __func__, data->host_cookie, host->next_data.cookie);
1200                 data->host_cookie = 0;
1201         }
1202
1203         /* Check if next job is already prepared */
1204         if (next ||
1205             (!next && data->host_cookie != host->next_data.cookie)) {
1206                 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1207                                      omap_hsmmc_get_dma_dir(host, data));
1208
1209         } else {
1210                 dma_len = host->next_data.dma_len;
1211                 host->next_data.dma_len = 0;
1212         }
1213
1214
1215         if (dma_len == 0)
1216                 return -EINVAL;
1217
1218         if (next) {
1219                 next->dma_len = dma_len;
1220                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1221         } else
1222                 host->dma_len = dma_len;
1223
1224         return 0;
1225 }
1226
1227 /*
1228  * Routine to configure and start DMA for the MMC card
1229  */
1230 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1231                                         struct mmc_request *req)
1232 {
1233         struct dma_slave_config cfg;
1234         struct dma_async_tx_descriptor *tx;
1235         int ret = 0, i;
1236         struct mmc_data *data = req->data;
1237         struct dma_chan *chan;
1238
1239         /* Sanity check: all the SG entries must be aligned by block size. */
1240         for (i = 0; i < data->sg_len; i++) {
1241                 struct scatterlist *sgl;
1242
1243                 sgl = data->sg + i;
1244                 if (sgl->length % data->blksz)
1245                         return -EINVAL;
1246         }
1247         if ((data->blksz % 4) != 0)
1248                 /* REVISIT: The MMC buffer increments only when MSB is written.
1249                  * Return error for blksz which is non multiple of four.
1250                  */
1251                 return -EINVAL;
1252
1253         BUG_ON(host->dma_ch != -1);
1254
1255         chan = omap_hsmmc_get_dma_chan(host, data);
1256
1257         cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1258         cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1259         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1260         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1261         cfg.src_maxburst = data->blksz / 4;
1262         cfg.dst_maxburst = data->blksz / 4;
1263
1264         ret = dmaengine_slave_config(chan, &cfg);
1265         if (ret)
1266                 return ret;
1267
1268         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1269         if (ret)
1270                 return ret;
1271
1272         tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1273                 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1274                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1275         if (!tx) {
1276                 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1277                 /* FIXME: cleanup */
1278                 return -1;
1279         }
1280
1281         tx->callback = omap_hsmmc_dma_callback;
1282         tx->callback_param = host;
1283
1284         /* Does not fail */
1285         dmaengine_submit(tx);
1286
1287         host->dma_ch = 1;
1288
1289         dma_async_issue_pending(chan);
1290
1291         return 0;
1292 }
1293
1294 static void set_data_timeout(struct omap_hsmmc_host *host,
1295                              unsigned int timeout_ns,
1296                              unsigned int timeout_clks)
1297 {
1298         unsigned int timeout, cycle_ns;
1299         uint32_t reg, clkd, dto = 0;
1300
1301         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1302         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1303         if (clkd == 0)
1304                 clkd = 1;
1305
1306         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1307         timeout = timeout_ns / cycle_ns;
1308         timeout += timeout_clks;
1309         if (timeout) {
1310                 while ((timeout & 0x80000000) == 0) {
1311                         dto += 1;
1312                         timeout <<= 1;
1313                 }
1314                 dto = 31 - dto;
1315                 timeout <<= 1;
1316                 if (timeout && dto)
1317                         dto += 1;
1318                 if (dto >= 13)
1319                         dto -= 13;
1320                 else
1321                         dto = 0;
1322                 if (dto > 14)
1323                         dto = 14;
1324         }
1325
1326         reg &= ~DTO_MASK;
1327         reg |= dto << DTO_SHIFT;
1328         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1329 }
1330
1331 /*
1332  * Configure block length for MMC/SD cards and initiate the transfer.
1333  */
1334 static int
1335 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1336 {
1337         int ret;
1338         host->data = req->data;
1339
1340         if (req->data == NULL) {
1341                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1342                 /*
1343                  * Set an arbitrary 100ms data timeout for commands with
1344                  * busy signal.
1345                  */
1346                 if (req->cmd->flags & MMC_RSP_BUSY)
1347                         set_data_timeout(host, 100000000U, 0);
1348                 return 0;
1349         }
1350
1351         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1352                                         | (req->data->blocks << 16));
1353         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1354
1355         if (host->use_dma) {
1356                 ret = omap_hsmmc_start_dma_transfer(host, req);
1357                 if (ret != 0) {
1358                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1359                         return ret;
1360                 }
1361         }
1362         return 0;
1363 }
1364
1365 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1366                                 int err)
1367 {
1368         struct omap_hsmmc_host *host = mmc_priv(mmc);
1369         struct mmc_data *data = mrq->data;
1370
1371         if (host->use_dma && data->host_cookie) {
1372                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1373
1374                 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1375                              omap_hsmmc_get_dma_dir(host, data));
1376                 data->host_cookie = 0;
1377         }
1378 }
1379
1380 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1381                                bool is_first_req)
1382 {
1383         struct omap_hsmmc_host *host = mmc_priv(mmc);
1384
1385         if (mrq->data->host_cookie) {
1386                 mrq->data->host_cookie = 0;
1387                 return ;
1388         }
1389
1390         if (host->use_dma) {
1391                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1392
1393                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1394                                                 &host->next_data, c))
1395                         mrq->data->host_cookie = 0;
1396         }
1397 }
1398
1399 /*
1400  * Request function. for read/write operation
1401  */
1402 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1403 {
1404         struct omap_hsmmc_host *host = mmc_priv(mmc);
1405         int err;
1406
1407         BUG_ON(host->req_in_progress);
1408         BUG_ON(host->dma_ch != -1);
1409         if (host->protect_card) {
1410                 if (host->reqs_blocked < 3) {
1411                         /*
1412                          * Ensure the controller is left in a consistent
1413                          * state by resetting the command and data state
1414                          * machines.
1415                          */
1416                         omap_hsmmc_reset_controller_fsm(host, SRD);
1417                         omap_hsmmc_reset_controller_fsm(host, SRC);
1418                         host->reqs_blocked += 1;
1419                 }
1420                 req->cmd->error = -EBADF;
1421                 if (req->data)
1422                         req->data->error = -EBADF;
1423                 req->cmd->retries = 0;
1424                 mmc_request_done(mmc, req);
1425                 return;
1426         } else if (host->reqs_blocked)
1427                 host->reqs_blocked = 0;
1428         WARN_ON(host->mrq != NULL);
1429         host->mrq = req;
1430         err = omap_hsmmc_prepare_data(host, req);
1431         if (err) {
1432                 req->cmd->error = err;
1433                 if (req->data)
1434                         req->data->error = err;
1435                 host->mrq = NULL;
1436                 mmc_request_done(mmc, req);
1437                 return;
1438         }
1439
1440         omap_hsmmc_start_command(host, req->cmd, req->data);
1441 }
1442
1443 /* Routine to configure clock values. Exposed API to core */
1444 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1445 {
1446         struct omap_hsmmc_host *host = mmc_priv(mmc);
1447         int do_send_init_stream = 0;
1448
1449         pm_runtime_get_sync(host->dev);
1450
1451         if (ios->power_mode != host->power_mode) {
1452                 switch (ios->power_mode) {
1453                 case MMC_POWER_OFF:
1454                         mmc_slot(host).set_power(host->dev, host->slot_id,
1455                                                  0, 0);
1456                         break;
1457                 case MMC_POWER_UP:
1458                         mmc_slot(host).set_power(host->dev, host->slot_id,
1459                                                  1, ios->vdd);
1460                         break;
1461                 case MMC_POWER_ON:
1462                         do_send_init_stream = 1;
1463                         break;
1464                 }
1465                 host->power_mode = ios->power_mode;
1466         }
1467
1468         /* FIXME: set registers based only on changes to ios */
1469
1470         omap_hsmmc_set_bus_width(host);
1471
1472         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1473                 /* Only MMC1 can interface at 3V without some flavor
1474                  * of external transceiver; but they all handle 1.8V.
1475                  */
1476                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1477                         (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1478                         /*
1479                          * With pbias cell programming missing, this
1480                          * can't be allowed when booting with device
1481                          * tree.
1482                          */
1483                         !host->dev->of_node) {
1484                                 /*
1485                                  * The mmc_select_voltage fn of the core does
1486                                  * not seem to set the power_mode to
1487                                  * MMC_POWER_UP upon recalculating the voltage.
1488                                  * vdd 1.8v.
1489                                  */
1490                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1491                                 dev_dbg(mmc_dev(host->mmc),
1492                                                 "Switch operation failed\n");
1493                 }
1494         }
1495
1496         omap_hsmmc_set_clock(host);
1497
1498         if (do_send_init_stream)
1499                 send_init_stream(host);
1500
1501         omap_hsmmc_set_bus_mode(host);
1502
1503         pm_runtime_put_autosuspend(host->dev);
1504 }
1505
1506 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1507 {
1508         struct omap_hsmmc_host *host = mmc_priv(mmc);
1509
1510         if (!mmc_slot(host).card_detect)
1511                 return -ENOSYS;
1512         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1513 }
1514
1515 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1516 {
1517         struct omap_hsmmc_host *host = mmc_priv(mmc);
1518
1519         if (!mmc_slot(host).get_ro)
1520                 return -ENOSYS;
1521         return mmc_slot(host).get_ro(host->dev, 0);
1522 }
1523
1524 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1525 {
1526         struct omap_hsmmc_host *host = mmc_priv(mmc);
1527
1528         if (mmc_slot(host).init_card)
1529                 mmc_slot(host).init_card(card);
1530 }
1531
1532 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1533 {
1534         u32 hctl, capa, value;
1535
1536         /* Only MMC1 supports 3.0V */
1537         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1538                 hctl = SDVS30;
1539                 capa = VS30 | VS18;
1540         } else {
1541                 hctl = SDVS18;
1542                 capa = VS18;
1543         }
1544
1545         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1546         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1547
1548         value = OMAP_HSMMC_READ(host->base, CAPA);
1549         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1550
1551         /* Set SD bus power bit */
1552         set_sd_bus_power(host);
1553 }
1554
1555 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1556 {
1557         struct omap_hsmmc_host *host = mmc_priv(mmc);
1558
1559         pm_runtime_get_sync(host->dev);
1560
1561         return 0;
1562 }
1563
1564 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1565 {
1566         struct omap_hsmmc_host *host = mmc_priv(mmc);
1567
1568         pm_runtime_mark_last_busy(host->dev);
1569         pm_runtime_put_autosuspend(host->dev);
1570
1571         return 0;
1572 }
1573
1574 static const struct mmc_host_ops omap_hsmmc_ops = {
1575         .enable = omap_hsmmc_enable_fclk,
1576         .disable = omap_hsmmc_disable_fclk,
1577         .post_req = omap_hsmmc_post_req,
1578         .pre_req = omap_hsmmc_pre_req,
1579         .request = omap_hsmmc_request,
1580         .set_ios = omap_hsmmc_set_ios,
1581         .get_cd = omap_hsmmc_get_cd,
1582         .get_ro = omap_hsmmc_get_ro,
1583         .init_card = omap_hsmmc_init_card,
1584         /* NYET -- enable_sdio_irq */
1585 };
1586
1587 #ifdef CONFIG_DEBUG_FS
1588
1589 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1590 {
1591         struct mmc_host *mmc = s->private;
1592         struct omap_hsmmc_host *host = mmc_priv(mmc);
1593         int context_loss = 0;
1594
1595         if (host->pdata->get_context_loss_count)
1596                 context_loss = host->pdata->get_context_loss_count(host->dev);
1597
1598         seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1599                         mmc->index, host->context_loss, context_loss);
1600
1601         if (host->suspended) {
1602                 seq_printf(s, "host suspended, can't read registers\n");
1603                 return 0;
1604         }
1605
1606         pm_runtime_get_sync(host->dev);
1607
1608         seq_printf(s, "CON:\t\t0x%08x\n",
1609                         OMAP_HSMMC_READ(host->base, CON));
1610         seq_printf(s, "HCTL:\t\t0x%08x\n",
1611                         OMAP_HSMMC_READ(host->base, HCTL));
1612         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1613                         OMAP_HSMMC_READ(host->base, SYSCTL));
1614         seq_printf(s, "IE:\t\t0x%08x\n",
1615                         OMAP_HSMMC_READ(host->base, IE));
1616         seq_printf(s, "ISE:\t\t0x%08x\n",
1617                         OMAP_HSMMC_READ(host->base, ISE));
1618         seq_printf(s, "CAPA:\t\t0x%08x\n",
1619                         OMAP_HSMMC_READ(host->base, CAPA));
1620
1621         pm_runtime_mark_last_busy(host->dev);
1622         pm_runtime_put_autosuspend(host->dev);
1623
1624         return 0;
1625 }
1626
1627 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1628 {
1629         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1630 }
1631
1632 static const struct file_operations mmc_regs_fops = {
1633         .open           = omap_hsmmc_regs_open,
1634         .read           = seq_read,
1635         .llseek         = seq_lseek,
1636         .release        = single_release,
1637 };
1638
1639 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1640 {
1641         if (mmc->debugfs_root)
1642                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1643                         mmc, &mmc_regs_fops);
1644 }
1645
1646 #else
1647
1648 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1649 {
1650 }
1651
1652 #endif
1653
1654 #ifdef CONFIG_OF
1655 static u16 omap4_reg_offset = 0x100;
1656
1657 static const struct of_device_id omap_mmc_of_match[] = {
1658         {
1659                 .compatible = "ti,omap2-hsmmc",
1660         },
1661         {
1662                 .compatible = "ti,omap3-hsmmc",
1663         },
1664         {
1665                 .compatible = "ti,omap4-hsmmc",
1666                 .data = &omap4_reg_offset,
1667         },
1668         {},
1669 };
1670 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1671
1672 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1673 {
1674         struct omap_mmc_platform_data *pdata;
1675         struct device_node *np = dev->of_node;
1676         u32 bus_width;
1677
1678         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1679         if (!pdata)
1680                 return NULL; /* out of memory */
1681
1682         if (of_find_property(np, "ti,dual-volt", NULL))
1683                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1684
1685         /* This driver only supports 1 slot */
1686         pdata->nr_slots = 1;
1687         pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1688         pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1689
1690         if (of_find_property(np, "ti,non-removable", NULL)) {
1691                 pdata->slots[0].nonremovable = true;
1692                 pdata->slots[0].no_regulator_off_init = true;
1693         }
1694         of_property_read_u32(np, "bus-width", &bus_width);
1695         if (bus_width == 4)
1696                 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1697         else if (bus_width == 8)
1698                 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1699
1700         if (of_find_property(np, "ti,needs-special-reset", NULL))
1701                 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1702
1703         return pdata;
1704 }
1705 #else
1706 static inline struct omap_mmc_platform_data
1707                         *of_get_hsmmc_pdata(struct device *dev)
1708 {
1709         return NULL;
1710 }
1711 #endif
1712
1713 static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
1714 {
1715         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1716         struct mmc_host *mmc;
1717         struct omap_hsmmc_host *host = NULL;
1718         struct resource *res;
1719         int ret, irq;
1720         const struct of_device_id *match;
1721         dma_cap_mask_t mask;
1722         unsigned tx_req, rx_req;
1723
1724         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1725         if (match) {
1726                 pdata = of_get_hsmmc_pdata(&pdev->dev);
1727                 if (match->data) {
1728                         const u16 *offsetp = match->data;
1729                         pdata->reg_offset = *offsetp;
1730                 }
1731         }
1732
1733         if (pdata == NULL) {
1734                 dev_err(&pdev->dev, "Platform Data is missing\n");
1735                 return -ENXIO;
1736         }
1737
1738         if (pdata->nr_slots == 0) {
1739                 dev_err(&pdev->dev, "No Slots\n");
1740                 return -ENXIO;
1741         }
1742
1743         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1744         irq = platform_get_irq(pdev, 0);
1745         if (res == NULL || irq < 0)
1746                 return -ENXIO;
1747
1748         res = request_mem_region(res->start, resource_size(res), pdev->name);
1749         if (res == NULL)
1750                 return -EBUSY;
1751
1752         ret = omap_hsmmc_gpio_init(pdata);
1753         if (ret)
1754                 goto err;
1755
1756         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1757         if (!mmc) {
1758                 ret = -ENOMEM;
1759                 goto err_alloc;
1760         }
1761
1762         host            = mmc_priv(mmc);
1763         host->mmc       = mmc;
1764         host->pdata     = pdata;
1765         host->dev       = &pdev->dev;
1766         host->use_dma   = 1;
1767         host->dma_ch    = -1;
1768         host->irq       = irq;
1769         host->slot_id   = 0;
1770         host->mapbase   = res->start + pdata->reg_offset;
1771         host->base      = ioremap(host->mapbase, SZ_4K);
1772         host->power_mode = MMC_POWER_OFF;
1773         host->next_data.cookie = 1;
1774
1775         platform_set_drvdata(pdev, host);
1776
1777         mmc->ops        = &omap_hsmmc_ops;
1778
1779         /*
1780          * If regulator_disable can only put vcc_aux to sleep then there is
1781          * no off state.
1782          */
1783         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1784                 mmc_slot(host).no_off = 1;
1785
1786         mmc->f_min = OMAP_MMC_MIN_CLOCK;
1787
1788         if (pdata->max_freq > 0)
1789                 mmc->f_max = pdata->max_freq;
1790         else
1791                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1792
1793         spin_lock_init(&host->irq_lock);
1794
1795         host->fclk = clk_get(&pdev->dev, "fck");
1796         if (IS_ERR(host->fclk)) {
1797                 ret = PTR_ERR(host->fclk);
1798                 host->fclk = NULL;
1799                 goto err1;
1800         }
1801
1802         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1803                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1804                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1805         }
1806
1807         pm_runtime_enable(host->dev);
1808         pm_runtime_get_sync(host->dev);
1809         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1810         pm_runtime_use_autosuspend(host->dev);
1811
1812         omap_hsmmc_context_save(host);
1813
1814         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1815         /*
1816          * MMC can still work without debounce clock.
1817          */
1818         if (IS_ERR(host->dbclk)) {
1819                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n");
1820                 host->dbclk = NULL;
1821         } else if (clk_prepare_enable(host->dbclk) != 0) {
1822                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1823                 clk_put(host->dbclk);
1824                 host->dbclk = NULL;
1825         }
1826
1827         /* Since we do only SG emulation, we can have as many segs
1828          * as we want. */
1829         mmc->max_segs = 1024;
1830
1831         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1832         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1833         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1834         mmc->max_seg_size = mmc->max_req_size;
1835
1836         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1837                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1838
1839         mmc->caps |= mmc_slot(host).caps;
1840         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1841                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1842
1843         if (mmc_slot(host).nonremovable)
1844                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1845
1846         mmc->pm_caps = mmc_slot(host).pm_caps;
1847
1848         omap_hsmmc_conf_bus_power(host);
1849
1850         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1851         if (!res) {
1852                 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1853                 ret = -ENXIO;
1854                 goto err_irq;
1855         }
1856         tx_req = res->start;
1857
1858         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1859         if (!res) {
1860                 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1861                 ret = -ENXIO;
1862                 goto err_irq;
1863         }
1864         rx_req = res->start;
1865
1866         dma_cap_zero(mask);
1867         dma_cap_set(DMA_SLAVE, mask);
1868
1869         host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
1870         if (!host->rx_chan) {
1871                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
1872                 ret = -ENXIO;
1873                 goto err_irq;
1874         }
1875
1876         host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
1877         if (!host->tx_chan) {
1878                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
1879                 ret = -ENXIO;
1880                 goto err_irq;
1881         }
1882
1883         /* Request IRQ for MMC operations */
1884         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1885                         mmc_hostname(mmc), host);
1886         if (ret) {
1887                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1888                 goto err_irq;
1889         }
1890
1891         if (pdata->init != NULL) {
1892                 if (pdata->init(&pdev->dev) != 0) {
1893                         dev_dbg(mmc_dev(host->mmc),
1894                                 "Unable to configure MMC IRQs\n");
1895                         goto err_irq_cd_init;
1896                 }
1897         }
1898
1899         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1900                 ret = omap_hsmmc_reg_get(host);
1901                 if (ret)
1902                         goto err_reg;
1903                 host->use_reg = 1;
1904         }
1905
1906         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1907
1908         /* Request IRQ for card detect */
1909         if ((mmc_slot(host).card_detect_irq)) {
1910                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1911                                            NULL,
1912                                            omap_hsmmc_detect,
1913                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1914                                            mmc_hostname(mmc), host);
1915                 if (ret) {
1916                         dev_dbg(mmc_dev(host->mmc),
1917                                 "Unable to grab MMC CD IRQ\n");
1918                         goto err_irq_cd;
1919                 }
1920                 pdata->suspend = omap_hsmmc_suspend_cdirq;
1921                 pdata->resume = omap_hsmmc_resume_cdirq;
1922         }
1923
1924         omap_hsmmc_disable_irq(host);
1925
1926         omap_hsmmc_protect_card(host);
1927
1928         mmc_add_host(mmc);
1929
1930         if (mmc_slot(host).name != NULL) {
1931                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1932                 if (ret < 0)
1933                         goto err_slot_name;
1934         }
1935         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1936                 ret = device_create_file(&mmc->class_dev,
1937                                         &dev_attr_cover_switch);
1938                 if (ret < 0)
1939                         goto err_slot_name;
1940         }
1941
1942         omap_hsmmc_debugfs(mmc);
1943         pm_runtime_mark_last_busy(host->dev);
1944         pm_runtime_put_autosuspend(host->dev);
1945
1946         return 0;
1947
1948 err_slot_name:
1949         mmc_remove_host(mmc);
1950         free_irq(mmc_slot(host).card_detect_irq, host);
1951 err_irq_cd:
1952         if (host->use_reg)
1953                 omap_hsmmc_reg_put(host);
1954 err_reg:
1955         if (host->pdata->cleanup)
1956                 host->pdata->cleanup(&pdev->dev);
1957 err_irq_cd_init:
1958         free_irq(host->irq, host);
1959 err_irq:
1960         if (host->tx_chan)
1961                 dma_release_channel(host->tx_chan);
1962         if (host->rx_chan)
1963                 dma_release_channel(host->rx_chan);
1964         pm_runtime_put_sync(host->dev);
1965         pm_runtime_disable(host->dev);
1966         clk_put(host->fclk);
1967         if (host->dbclk) {
1968                 clk_disable_unprepare(host->dbclk);
1969                 clk_put(host->dbclk);
1970         }
1971 err1:
1972         iounmap(host->base);
1973         platform_set_drvdata(pdev, NULL);
1974         mmc_free_host(mmc);
1975 err_alloc:
1976         omap_hsmmc_gpio_free(pdata);
1977 err:
1978         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1979         if (res)
1980                 release_mem_region(res->start, resource_size(res));
1981         return ret;
1982 }
1983
1984 static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
1985 {
1986         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1987         struct resource *res;
1988
1989         pm_runtime_get_sync(host->dev);
1990         mmc_remove_host(host->mmc);
1991         if (host->use_reg)
1992                 omap_hsmmc_reg_put(host);
1993         if (host->pdata->cleanup)
1994                 host->pdata->cleanup(&pdev->dev);
1995         free_irq(host->irq, host);
1996         if (mmc_slot(host).card_detect_irq)
1997                 free_irq(mmc_slot(host).card_detect_irq, host);
1998
1999         if (host->tx_chan)
2000                 dma_release_channel(host->tx_chan);
2001         if (host->rx_chan)
2002                 dma_release_channel(host->rx_chan);
2003
2004         pm_runtime_put_sync(host->dev);
2005         pm_runtime_disable(host->dev);
2006         clk_put(host->fclk);
2007         if (host->dbclk) {
2008                 clk_disable_unprepare(host->dbclk);
2009                 clk_put(host->dbclk);
2010         }
2011
2012         mmc_free_host(host->mmc);
2013         iounmap(host->base);
2014         omap_hsmmc_gpio_free(pdev->dev.platform_data);
2015
2016         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2017         if (res)
2018                 release_mem_region(res->start, resource_size(res));
2019         platform_set_drvdata(pdev, NULL);
2020
2021         return 0;
2022 }
2023
2024 #ifdef CONFIG_PM
2025 static int omap_hsmmc_suspend(struct device *dev)
2026 {
2027         int ret = 0;
2028         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2029
2030         if (!host)
2031                 return 0;
2032
2033         if (host && host->suspended)
2034                 return 0;
2035
2036         pm_runtime_get_sync(host->dev);
2037         host->suspended = 1;
2038         if (host->pdata->suspend) {
2039                 ret = host->pdata->suspend(dev, host->slot_id);
2040                 if (ret) {
2041                         dev_dbg(dev, "Unable to handle MMC board"
2042                                         " level suspend\n");
2043                         host->suspended = 0;
2044                         return ret;
2045                 }
2046         }
2047         ret = mmc_suspend_host(host->mmc);
2048
2049         if (ret) {
2050                 host->suspended = 0;
2051                 if (host->pdata->resume) {
2052                         if (host->pdata->resume(dev, host->slot_id))
2053                                 dev_dbg(dev, "Unmask interrupt failed\n");
2054                 }
2055                 goto err;
2056         }
2057
2058         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2059                 omap_hsmmc_disable_irq(host);
2060                 OMAP_HSMMC_WRITE(host->base, HCTL,
2061                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2062         }
2063
2064         if (host->dbclk)
2065                 clk_disable_unprepare(host->dbclk);
2066 err:
2067         pm_runtime_put_sync(host->dev);
2068         return ret;
2069 }
2070
2071 /* Routine to resume the MMC device */
2072 static int omap_hsmmc_resume(struct device *dev)
2073 {
2074         int ret = 0;
2075         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2076
2077         if (!host)
2078                 return 0;
2079
2080         if (host && !host->suspended)
2081                 return 0;
2082
2083         pm_runtime_get_sync(host->dev);
2084
2085         if (host->dbclk)
2086                 clk_prepare_enable(host->dbclk);
2087
2088         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2089                 omap_hsmmc_conf_bus_power(host);
2090
2091         if (host->pdata->resume) {
2092                 ret = host->pdata->resume(dev, host->slot_id);
2093                 if (ret)
2094                         dev_dbg(dev, "Unmask interrupt failed\n");
2095         }
2096
2097         omap_hsmmc_protect_card(host);
2098
2099         /* Notify the core to resume the host */
2100         ret = mmc_resume_host(host->mmc);
2101         if (ret == 0)
2102                 host->suspended = 0;
2103
2104         pm_runtime_mark_last_busy(host->dev);
2105         pm_runtime_put_autosuspend(host->dev);
2106
2107         return ret;
2108
2109 }
2110
2111 #else
2112 #define omap_hsmmc_suspend      NULL
2113 #define omap_hsmmc_resume               NULL
2114 #endif
2115
2116 static int omap_hsmmc_runtime_suspend(struct device *dev)
2117 {
2118         struct omap_hsmmc_host *host;
2119
2120         host = platform_get_drvdata(to_platform_device(dev));
2121         omap_hsmmc_context_save(host);
2122         dev_dbg(dev, "disabled\n");
2123
2124         return 0;
2125 }
2126
2127 static int omap_hsmmc_runtime_resume(struct device *dev)
2128 {
2129         struct omap_hsmmc_host *host;
2130
2131         host = platform_get_drvdata(to_platform_device(dev));
2132         omap_hsmmc_context_restore(host);
2133         dev_dbg(dev, "enabled\n");
2134
2135         return 0;
2136 }
2137
2138 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2139         .suspend        = omap_hsmmc_suspend,
2140         .resume         = omap_hsmmc_resume,
2141         .runtime_suspend = omap_hsmmc_runtime_suspend,
2142         .runtime_resume = omap_hsmmc_runtime_resume,
2143 };
2144
2145 static struct platform_driver omap_hsmmc_driver = {
2146         .probe          = omap_hsmmc_probe,
2147         .remove         = __devexit_p(omap_hsmmc_remove),
2148         .driver         = {
2149                 .name = DRIVER_NAME,
2150                 .owner = THIS_MODULE,
2151                 .pm = &omap_hsmmc_dev_pm_ops,
2152                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2153         },
2154 };
2155
2156 module_platform_driver(omap_hsmmc_driver);
2157 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2158 MODULE_LICENSE("GPL");
2159 MODULE_ALIAS("platform:" DRIVER_NAME);
2160 MODULE_AUTHOR("Texas Instruments Inc");