drivers/mmc/host/sdhci-omap.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /**
   3  * SDHCI Controller driver for TI's OMAP SoCs
   4  *
   5  * Copyright (C) 2017 Texas Instruments
   6  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/mmc/mmc.h>
  11 #include <linux/mmc/slot-gpio.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/sys_soc.h>
  20 #include <linux/thermal.h>
  21
  22 #include "sdhci-pltfm.h"
  23
  24 #define SDHCI_OMAP_CON          0x12c
  25 #define CON_DW8                 BIT(5)
  26 #define CON_DMA_MASTER          BIT(20)
  27 #define CON_DDR                 BIT(19)
  28 #define CON_CLKEXTFREE          BIT(16)
  29 #define CON_PADEN               BIT(15)
  30 #define CON_CTPL                BIT(11)
  31 #define CON_INIT                BIT(1)
  32 #define CON_OD                  BIT(0)
  33
  34 #define SDHCI_OMAP_DLL          0x0134
  35 #define DLL_SWT                 BIT(20)
  36 #define DLL_FORCE_SR_C_SHIFT    13
  37 #define DLL_FORCE_SR_C_MASK     (0x7f << DLL_FORCE_SR_C_SHIFT)
  38 #define DLL_FORCE_VALUE         BIT(12)
  39 #define DLL_CALIB               BIT(1)
  40
  41 #define SDHCI_OMAP_CMD          0x20c
  42
  43 #define SDHCI_OMAP_PSTATE       0x0224
  44 #define PSTATE_DLEV_DAT0        BIT(20)
  45 #define PSTATE_DATI             BIT(1)
  46
  47 #define SDHCI_OMAP_HCTL         0x228
  48 #define HCTL_SDBP               BIT(8)
  49 #define HCTL_SDVS_SHIFT         9
  50 #define HCTL_SDVS_MASK          (0x7 << HCTL_SDVS_SHIFT)
  51 #define HCTL_SDVS_33            (0x7 << HCTL_SDVS_SHIFT)
  52 #define HCTL_SDVS_30            (0x6 << HCTL_SDVS_SHIFT)
  53 #define HCTL_SDVS_18            (0x5 << HCTL_SDVS_SHIFT)
  54
  55 #define SDHCI_OMAP_SYSCTL       0x22c
  56 #define SYSCTL_CEN              BIT(2)
  57 #define SYSCTL_CLKD_SHIFT       6
  58 #define SYSCTL_CLKD_MASK        0x3ff
  59
  60 #define SDHCI_OMAP_STAT         0x230
  61
  62 #define SDHCI_OMAP_IE           0x234
  63 #define INT_CC_EN               BIT(0)
  64
  65 #define SDHCI_OMAP_AC12         0x23c
  66 #define AC12_V1V8_SIGEN         BIT(19)
  67 #define AC12_SCLK_SEL           BIT(23)
  68
  69 #define SDHCI_OMAP_CAPA         0x240
  70 #define CAPA_VS33               BIT(24)
  71 #define CAPA_VS30               BIT(25)
  72 #define CAPA_VS18               BIT(26)
  73
  74 #define SDHCI_OMAP_CAPA2        0x0244
  75 #define CAPA2_TSDR50            BIT(13)
  76
  77 #define SDHCI_OMAP_TIMEOUT      1               /* 1 msec */
  78
  79 #define SYSCTL_CLKD_MAX         0x3FF
  80
  81 #define IOV_1V8                 1800000         /* 180000 uV */
  82 #define IOV_3V0                 3000000         /* 300000 uV */
  83 #define IOV_3V3                 3300000         /* 330000 uV */
  84
  85 #define MAX_PHASE_DELAY         0x7C
  86
  87 /* sdhci-omap controller flags */
  88 #define SDHCI_OMAP_REQUIRE_IODELAY      BIT(0)
  89 #define SDHCI_OMAP_SPECIAL_RESET        BIT(1)
  90
  91 struct sdhci_omap_data {
  92         u32 offset;
  93         u8 flags;
  94 };
  95
  96 struct sdhci_omap_host {
  97         char                    *version;
  98         void __iomem            *base;
  99         struct device           *dev;
 100         struct  regulator       *pbias;
 101         bool                    pbias_enabled;
 102         struct sdhci_host       *host;
 103         u8                      bus_mode;
 104         u8                      power_mode;
 105         u8                      timing;
 106         u8                      flags;
 107
 108         struct pinctrl          *pinctrl;
 109         struct pinctrl_state    **pinctrl_state;
 110         bool                    is_tuning;
 111 };
 112
 113 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
 114 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
 115
 116 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
 117                                    unsigned int offset)
 118 {
 119         return readl(host->base + offset);
 120 }
 121
 122 static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
 123                                      unsigned int offset, u32 data)
 124 {
 125         writel(data, host->base + offset);
 126 }
 127
 128 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
 129                                 bool power_on, unsigned int iov)
 130 {
 131         int ret;
 132         struct device *dev = omap_host->dev;
 133
 134         if (IS_ERR(omap_host->pbias))
 135                 return 0;
 136
 137         if (power_on) {
 138                 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
 139                 if (ret) {
 140                         dev_err(dev, "pbias set voltage failed\n");
 141                         return ret;
 142                 }
 143
 144                 if (omap_host->pbias_enabled)
 145                         return 0;
 146
 147                 ret = regulator_enable(omap_host->pbias);
 148                 if (ret) {
 149                         dev_err(dev, "pbias reg enable fail\n");
 150                         return ret;
 151                 }
 152
 153                 omap_host->pbias_enabled = true;
 154         } else {
 155                 if (!omap_host->pbias_enabled)
 156                         return 0;
 157
 158                 ret = regulator_disable(omap_host->pbias);
 159                 if (ret) {
 160                         dev_err(dev, "pbias reg disable fail\n");
 161                         return ret;
 162                 }
 163                 omap_host->pbias_enabled = false;
 164         }
 165
 166         return 0;
 167 }
 168
 169 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
 170                                  unsigned int iov)
 171 {
 172         int ret;
 173         struct sdhci_host *host = omap_host->host;
 174         struct mmc_host *mmc = host->mmc;
 175
 176         ret = sdhci_omap_set_pbias(omap_host, false, 0);
 177         if (ret)
 178                 return ret;
 179
 180         if (!IS_ERR(mmc->supply.vqmmc)) {
 181                 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
 182                 if (ret) {
 183                         dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
 184                         return ret;
 185                 }
 186         }
 187
 188         ret = sdhci_omap_set_pbias(omap_host, true, iov);
 189         if (ret)
 190                 return ret;
 191
 192         return 0;
 193 }
 194
 195 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
 196                                       unsigned char signal_voltage)
 197 {
 198         u32 reg;
 199         ktime_t timeout;
 200
 201         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
 202         reg &= ~HCTL_SDVS_MASK;
 203
 204         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 205                 reg |= HCTL_SDVS_33;
 206         else
 207                 reg |= HCTL_SDVS_18;
 208
 209         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 210
 211         reg |= HCTL_SDBP;
 212         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 213
 214         /* wait 1ms */
 215         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 216         while (1) {
 217                 bool timedout = ktime_after(ktime_get(), timeout);
 218
 219                 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)
 220                         break;
 221                 if (WARN_ON(timedout))
 222                         return;
 223                 usleep_range(5, 10);
 224         }
 225 }
 226
 227 static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
 228 {
 229         struct sdhci_host *host = mmc_priv(mmc);
 230         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 231         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 232         u32 reg;
 233
 234         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 235         if (enable)
 236                 reg |= (CON_CTPL | CON_CLKEXTFREE);
 237         else
 238                 reg &= ~(CON_CTPL | CON_CLKEXTFREE);
 239         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 240
 241         sdhci_enable_sdio_irq(mmc, enable);
 242 }
 243
 244 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
 245                                       int count)
 246 {
 247         int i;
 248         u32 reg;
 249
 250         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 251         reg |= DLL_FORCE_VALUE;
 252         reg &= ~DLL_FORCE_SR_C_MASK;
 253         reg |= (count << DLL_FORCE_SR_C_SHIFT);
 254         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 255
 256         reg |= DLL_CALIB;
 257         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 258         for (i = 0; i < 1000; i++) {
 259                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 260                 if (reg & DLL_CALIB)
 261                         break;
 262         }
 263         reg &= ~DLL_CALIB;
 264         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 265 }
 266
 267 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
 268 {
 269         u32 reg;
 270
 271         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 272         reg &= ~AC12_SCLK_SEL;
 273         sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 274
 275         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 276         reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
 277         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 278 }
 279
 280 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
 281 {
 282         struct sdhci_host *host = mmc_priv(mmc);
 283         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 284         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 285         struct thermal_zone_device *thermal_dev;
 286         struct device *dev = omap_host->dev;
 287         struct mmc_ios *ios = &mmc->ios;
 288         u32 start_window = 0, max_window = 0;
 289         bool single_point_failure = false;
 290         bool dcrc_was_enabled = false;
 291         u8 cur_match, prev_match = 0;
 292         u32 length = 0, max_len = 0;
 293         u32 phase_delay = 0;
 294         int temperature;
 295         int ret = 0;
 296         u32 reg;
 297         int i;
 298
 299         /* clock tuning is not needed for upto 52MHz */
 300         if (ios->clock <= 52000000)
 301                 return 0;
 302
 303         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
 304         if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
 305                 return 0;
 306
 307         thermal_dev = thermal_zone_get_zone_by_name("cpu_thermal");
 308         if (IS_ERR(thermal_dev)) {
 309                 dev_err(dev, "Unable to get thermal zone for tuning\n");
 310                 return PTR_ERR(thermal_dev);
 311         }
 312
 313         ret = thermal_zone_get_temp(thermal_dev, &temperature);
 314         if (ret)
 315                 return ret;
 316
 317         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 318         reg |= DLL_SWT;
 319         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 320
 321         /*
 322          * OMAP5/DRA74X/DRA72x Errata i802:
 323          * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
 324          * during the tuning procedure. So disable it during the
 325          * tuning procedure.
 326          */
 327         if (host->ier & SDHCI_INT_DATA_CRC) {
 328                 host->ier &= ~SDHCI_INT_DATA_CRC;
 329                 dcrc_was_enabled = true;
 330         }
 331
 332         omap_host->is_tuning = true;
 333
 334         /*
 335          * Stage 1: Search for a maximum pass window ignoring any
 336          * any single point failures. If the tuning value ends up
 337          * near it, move away from it in stage 2 below
 338          */
 339         while (phase_delay <= MAX_PHASE_DELAY) {
 340                 sdhci_omap_set_dll(omap_host, phase_delay);
 341
 342                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 343                 if (cur_match) {
 344                         if (prev_match) {
 345                                 length++;
 346                         } else if (single_point_failure) {
 347                                 /* ignore single point failure */
 348                                 length++;
 349                         } else {
 350                                 start_window = phase_delay;
 351                                 length = 1;
 352                         }
 353                 } else {
 354                         single_point_failure = prev_match;
 355                 }
 356
 357                 if (length > max_len) {
 358                         max_window = start_window;
 359                         max_len = length;
 360                 }
 361
 362                 prev_match = cur_match;
 363                 phase_delay += 4;
 364         }
 365
 366         if (!max_len) {
 367                 dev_err(dev, "Unable to find match\n");
 368                 ret = -EIO;
 369                 goto tuning_error;
 370         }
 371
 372         /*
 373          * Assign tuning value as a ratio of maximum pass window based
 374          * on temperature
 375          */
 376         if (temperature < -20000)
 377                 phase_delay = min(max_window + 4 * (max_len - 1) - 24,
 378                                   max_window +
 379                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 380         else if (temperature < 20000)
 381                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 382         else if (temperature < 40000)
 383                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 384         else if (temperature < 70000)
 385                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 386         else if (temperature < 90000)
 387                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 388         else if (temperature < 120000)
 389                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 390         else
 391                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 392
 393         /*
 394          * Stage 2: Search for a single point failure near the chosen tuning
 395          * value in two steps. First in the +3 to +10 range and then in the
 396          * +2 to -10 range. If found, move away from it in the appropriate
 397          * direction by the appropriate amount depending on the temperature.
 398          */
 399         for (i = 3; i <= 10; i++) {
 400                 sdhci_omap_set_dll(omap_host, phase_delay + i);
 401
 402                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 403                         if (temperature < 10000)
 404                                 phase_delay += i + 6;
 405                         else if (temperature < 20000)
 406                                 phase_delay += i - 12;
 407                         else if (temperature < 70000)
 408                                 phase_delay += i - 8;
 409                         else
 410                                 phase_delay += i - 6;
 411
 412                         goto single_failure_found;
 413                 }
 414         }
 415
 416         for (i = 2; i >= -10; i--) {
 417                 sdhci_omap_set_dll(omap_host, phase_delay + i);
 418
 419                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 420                         if (temperature < 10000)
 421                                 phase_delay += i + 12;
 422                         else if (temperature < 20000)
 423                                 phase_delay += i + 8;
 424                         else if (temperature < 70000)
 425                                 phase_delay += i + 8;
 426                         else if (temperature < 90000)
 427                                 phase_delay += i + 10;
 428                         else
 429                                 phase_delay += i + 12;
 430
 431                         goto single_failure_found;
 432                 }
 433         }
 434
 435 single_failure_found:
 436         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 437         if (!(reg & AC12_SCLK_SEL)) {
 438                 ret = -EIO;
 439                 goto tuning_error;
 440         }
 441
 442         sdhci_omap_set_dll(omap_host, phase_delay);
 443
 444         omap_host->is_tuning = false;
 445
 446         goto ret;
 447
 448 tuning_error:
 449         omap_host->is_tuning = false;
 450         dev_err(dev, "Tuning failed\n");
 451         sdhci_omap_disable_tuning(omap_host);
 452
 453 ret:
 454         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 455         /* Reenable forbidden interrupt */
 456         if (dcrc_was_enabled)
 457                 host->ier |= SDHCI_INT_DATA_CRC;
 458         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 459         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 460         return ret;
 461 }
 462
 463 static int sdhci_omap_card_busy(struct mmc_host *mmc)
 464 {
 465         u32 reg, ac12;
 466         int ret = false;
 467         struct sdhci_host *host = mmc_priv(mmc);
 468         struct sdhci_pltfm_host *pltfm_host;
 469         struct sdhci_omap_host *omap_host;
 470         u32 ier = host->ier;
 471
 472         pltfm_host = sdhci_priv(host);
 473         omap_host = sdhci_pltfm_priv(pltfm_host);
 474
 475         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 476         ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 477         reg &= ~CON_CLKEXTFREE;
 478         if (ac12 & AC12_V1V8_SIGEN)
 479                 reg |= CON_CLKEXTFREE;
 480         reg |= CON_PADEN;
 481         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 482
 483         disable_irq(host->irq);
 484         ier |= SDHCI_INT_CARD_INT;
 485         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 486         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 487
 488         /*
 489          * Delay is required for PSTATE to correctly reflect
 490          * DLEV/CLEV values after PADEN is set.
 491          */
 492         usleep_range(50, 100);
 493         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
 494         if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
 495                 ret = true;
 496
 497         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 498         reg &= ~(CON_CLKEXTFREE | CON_PADEN);
 499         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 500
 501         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 502         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 503         enable_irq(host->irq);
 504
 505         return ret;
 506 }
 507
 508 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
 509                                                   struct mmc_ios *ios)
 510 {
 511         u32 reg;
 512         int ret;
 513         unsigned int iov;
 514         struct sdhci_host *host = mmc_priv(mmc);
 515         struct sdhci_pltfm_host *pltfm_host;
 516         struct sdhci_omap_host *omap_host;
 517         struct device *dev;
 518
 519         pltfm_host = sdhci_priv(host);
 520         omap_host = sdhci_pltfm_priv(pltfm_host);
 521         dev = omap_host->dev;
 522
 523         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 524                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 525                 if (!(reg & CAPA_VS33))
 526                         return -EOPNOTSUPP;
 527
 528                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 529
 530                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 531                 reg &= ~AC12_V1V8_SIGEN;
 532                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 533
 534                 iov = IOV_3V3;
 535         } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 536                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 537                 if (!(reg & CAPA_VS18))
 538                         return -EOPNOTSUPP;
 539
 540                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 541
 542                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 543                 reg |= AC12_V1V8_SIGEN;
 544                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 545
 546                 iov = IOV_1V8;
 547         } else {
 548                 return -EOPNOTSUPP;
 549         }
 550
 551         ret = sdhci_omap_enable_iov(omap_host, iov);
 552         if (ret) {
 553                 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
 554                 return ret;
 555         }
 556
 557         dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
 558         return 0;
 559 }
 560
 561 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
 562 {
 563         int ret;
 564         struct pinctrl_state *pinctrl_state;
 565         struct device *dev = omap_host->dev;
 566
 567         if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
 568                 return;
 569
 570         if (omap_host->timing == timing)
 571                 return;
 572
 573         sdhci_omap_stop_clock(omap_host);
 574
 575         pinctrl_state = omap_host->pinctrl_state[timing];
 576         ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
 577         if (ret) {
 578                 dev_err(dev, "failed to select pinctrl state\n");
 579                 return;
 580         }
 581
 582         sdhci_omap_start_clock(omap_host);
 583         omap_host->timing = timing;
 584 }
 585
 586 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
 587                                       u8 power_mode)
 588 {
 589         if (omap_host->bus_mode == MMC_POWER_OFF)
 590                 sdhci_omap_disable_tuning(omap_host);
 591         omap_host->power_mode = power_mode;
 592 }
 593
 594 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
 595                                     unsigned int mode)
 596 {
 597         u32 reg;
 598
 599         if (omap_host->bus_mode == mode)
 600                 return;
 601
 602         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 603         if (mode == MMC_BUSMODE_OPENDRAIN)
 604                 reg |= CON_OD;
 605         else
 606                 reg &= ~CON_OD;
 607         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 608
 609         omap_host->bus_mode = mode;
 610 }
 611
 612 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 613 {
 614         struct sdhci_host *host = mmc_priv(mmc);
 615         struct sdhci_pltfm_host *pltfm_host;
 616         struct sdhci_omap_host *omap_host;
 617
 618         pltfm_host = sdhci_priv(host);
 619         omap_host = sdhci_pltfm_priv(pltfm_host);
 620
 621         sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
 622         sdhci_omap_set_timing(omap_host, ios->timing);
 623         sdhci_set_ios(mmc, ios);
 624         sdhci_omap_set_power_mode(omap_host, ios->power_mode);
 625 }
 626
 627 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
 628                                    unsigned int clock)
 629 {
 630         u16 dsor;
 631
 632         dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
 633         if (dsor > SYSCTL_CLKD_MAX)
 634                 dsor = SYSCTL_CLKD_MAX;
 635
 636         return dsor;
 637 }
 638
 639 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
 640 {
 641         u32 reg;
 642
 643         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 644         reg |= SYSCTL_CEN;
 645         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 646 }
 647
 648 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
 649 {
 650         u32 reg;
 651
 652         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 653         reg &= ~SYSCTL_CEN;
 654         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 655 }
 656
 657 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
 658 {
 659         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 660         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 661         unsigned long clkdiv;
 662
 663         sdhci_omap_stop_clock(omap_host);
 664
 665         if (!clock)
 666                 return;
 667
 668         clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
 669         clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
 670         sdhci_enable_clk(host, clkdiv);
 671
 672         sdhci_omap_start_clock(omap_host);
 673 }
 674
 675 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
 676                           unsigned short vdd)
 677 {
 678         struct mmc_host *mmc = host->mmc;
 679
 680         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 681 }
 682
 683 static int sdhci_omap_enable_dma(struct sdhci_host *host)
 684 {
 685         u32 reg;
 686         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 687         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 688
 689         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 690         reg &= ~CON_DMA_MASTER;
 691         /* Switch to DMA slave mode when using external DMA */
 692         if (!host->use_external_dma)
 693                 reg |= CON_DMA_MASTER;
 694
 695         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 696
 697         return 0;
 698 }
 699
 700 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
 701 {
 702         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 703
 704         return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
 705 }
 706
 707 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
 708 {
 709         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 710         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 711         u32 reg;
 712
 713         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 714         if (width == MMC_BUS_WIDTH_8)
 715                 reg |= CON_DW8;
 716         else
 717                 reg &= ~CON_DW8;
 718         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 719
 720         sdhci_set_bus_width(host, width);
 721 }
 722
 723 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 724 {
 725         u32 reg;
 726         ktime_t timeout;
 727         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 728         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 729
 730         if (omap_host->power_mode == power_mode)
 731                 return;
 732
 733         if (power_mode != MMC_POWER_ON)
 734                 return;
 735
 736         disable_irq(host->irq);
 737
 738         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 739         reg |= CON_INIT;
 740         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 741         sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
 742
 743         /* wait 1ms */
 744         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 745         while (1) {
 746                 bool timedout = ktime_after(ktime_get(), timeout);
 747
 748                 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)
 749                         break;
 750                 if (WARN_ON(timedout))
 751                         return;
 752                 usleep_range(5, 10);
 753         }
 754
 755         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 756         reg &= ~CON_INIT;
 757         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 758         sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
 759
 760         enable_irq(host->irq);
 761 }
 762
 763 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
 764                                          unsigned int timing)
 765 {
 766         u32 reg;
 767         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 768         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 769
 770         sdhci_omap_stop_clock(omap_host);
 771
 772         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 773         if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
 774                 reg |= CON_DDR;
 775         else
 776                 reg &= ~CON_DDR;
 777         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 778
 779         sdhci_set_uhs_signaling(host, timing);
 780         sdhci_omap_start_clock(omap_host);
 781 }
 782
 783 #define MMC_TIMEOUT_US          20000           /* 20000 micro Sec */
 784 static void sdhci_omap_reset(struct sdhci_host *host, u8 mask)
 785 {
 786         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 787         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 788         unsigned long limit = MMC_TIMEOUT_US;
 789         unsigned long i = 0;
 790
 791         /* Don't reset data lines during tuning operation */
 792         if (omap_host->is_tuning)
 793                 mask &= ~SDHCI_RESET_DATA;
 794
 795         if (omap_host->flags & SDHCI_OMAP_SPECIAL_RESET) {
 796                 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 797                 while ((!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) &&
 798                        (i++ < limit))
 799                         udelay(1);
 800                 i = 0;
 801                 while ((sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) &&
 802                        (i++ < limit))
 803                         udelay(1);
 804
 805                 if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)
 806                         dev_err(mmc_dev(host->mmc),
 807                                 "Timeout waiting on controller reset in %s\n",
 808                                 __func__);
 809                 return;
 810         }
 811
 812         sdhci_reset(host, mask);
 813 }
 814
 815 #define CMD_ERR_MASK (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX |\
 816                       SDHCI_INT_TIMEOUT)
 817 #define CMD_MASK (CMD_ERR_MASK | SDHCI_INT_RESPONSE)
 818
 819 static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask)
 820 {
 821         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 822         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 823
 824         if (omap_host->is_tuning && host->cmd && !host->data_early &&
 825             (intmask & CMD_ERR_MASK)) {
 826
 827                 /*
 828                  * Since we are not resetting data lines during tuning
 829                  * operation, data error or data complete interrupts
 830                  * might still arrive. Mark this request as a failure
 831                  * but still wait for the data interrupt
 832                  */
 833                 if (intmask & SDHCI_INT_TIMEOUT)
 834                         host->cmd->error = -ETIMEDOUT;
 835                 else
 836                         host->cmd->error = -EILSEQ;
 837
 838                 host->cmd = NULL;
 839
 840                 /*
 841                  * Sometimes command error interrupts and command complete
 842                  * interrupt will arrive together. Clear all command related
 843                  * interrupts here.
 844                  */
 845                 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS);
 846                 intmask &= ~CMD_MASK;
 847         }
 848
 849         return intmask;
 850 }
 851
 852 static void sdhci_omap_set_timeout(struct sdhci_host *host,
 853                                    struct mmc_command *cmd)
 854 {
 855         if (cmd->opcode == MMC_ERASE)
 856                 sdhci_set_data_timeout_irq(host, false);
 857
 858         __sdhci_set_timeout(host, cmd);
 859 }
 860
 861 static struct sdhci_ops sdhci_omap_ops = {
 862         .set_clock = sdhci_omap_set_clock,
 863         .set_power = sdhci_omap_set_power,
 864         .enable_dma = sdhci_omap_enable_dma,
 865         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 866         .get_min_clock = sdhci_omap_get_min_clock,
 867         .set_bus_width = sdhci_omap_set_bus_width,
 868         .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
 869         .reset = sdhci_omap_reset,
 870         .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
 871         .irq = sdhci_omap_irq,
 872         .set_timeout = sdhci_omap_set_timeout,
 873 };
 874
 875 static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
 876 {
 877         u32 reg;
 878         int ret = 0;
 879         struct device *dev = omap_host->dev;
 880         struct regulator *vqmmc;
 881
 882         vqmmc = regulator_get(dev, "vqmmc");
 883         if (IS_ERR(vqmmc)) {
 884                 ret = PTR_ERR(vqmmc);
 885                 goto reg_put;
 886         }
 887
 888         /* voltage capabilities might be set by boot loader, clear it */
 889         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 890         reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
 891
 892         if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
 893                 reg |= CAPA_VS33;
 894         if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
 895                 reg |= CAPA_VS18;
 896
 897         sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
 898
 899 reg_put:
 900         regulator_put(vqmmc);
 901
 902         return ret;
 903 }
 904
 905 static const struct sdhci_pltfm_data sdhci_omap_pdata = {
 906         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 907                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 908                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
 909                   SDHCI_QUIRK_NO_HISPD_BIT |
 910                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
 911         .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
 912                    SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 913                    SDHCI_QUIRK2_RSP_136_HAS_CRC |
 914                    SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
 915         .ops = &sdhci_omap_ops,
 916 };
 917
 918 static const struct sdhci_omap_data k2g_data = {
 919         .offset = 0x200,
 920 };
 921
 922 static const struct sdhci_omap_data am335_data = {
 923         .offset = 0x200,
 924         .flags = SDHCI_OMAP_SPECIAL_RESET,
 925 };
 926
 927 static const struct sdhci_omap_data am437_data = {
 928         .offset = 0x200,
 929         .flags = SDHCI_OMAP_SPECIAL_RESET,
 930 };
 931
 932 static const struct sdhci_omap_data dra7_data = {
 933         .offset = 0x200,
 934         .flags  = SDHCI_OMAP_REQUIRE_IODELAY,
 935 };
 936
 937 static const struct of_device_id omap_sdhci_match[] = {
 938         { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
 939         { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
 940         { .compatible = "ti,am335-sdhci", .data = &am335_data },
 941         { .compatible = "ti,am437-sdhci", .data = &am437_data },
 942         {},
 943 };
 944 MODULE_DEVICE_TABLE(of, omap_sdhci_match);
 945
 946 static struct pinctrl_state
 947 *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
 948                                   u32 *caps, u32 capmask)
 949 {
 950         struct device *dev = omap_host->dev;
 951         char *version = omap_host->version;
 952         struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
 953         char str[20];
 954
 955         if (!(*caps & capmask))
 956                 goto ret;
 957
 958         if (version) {
 959                 snprintf(str, 20, "%s-%s", mode, version);
 960                 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
 961         }
 962
 963         if (IS_ERR(pinctrl_state))
 964                 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
 965
 966         if (IS_ERR(pinctrl_state)) {
 967                 dev_err(dev, "no pinctrl state for %s mode", mode);
 968                 *caps &= ~capmask;
 969         }
 970
 971 ret:
 972         return pinctrl_state;
 973 }
 974
 975 static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
 976                                                    *omap_host)
 977 {
 978         struct device *dev = omap_host->dev;
 979         struct sdhci_host *host = omap_host->host;
 980         struct mmc_host *mmc = host->mmc;
 981         u32 *caps = &mmc->caps;
 982         u32 *caps2 = &mmc->caps2;
 983         struct pinctrl_state *state;
 984         struct pinctrl_state **pinctrl_state;
 985
 986         if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
 987                 return 0;
 988
 989         pinctrl_state = devm_kcalloc(dev,
 990                                      MMC_TIMING_MMC_HS200 + 1,
 991                                      sizeof(*pinctrl_state),
 992                                      GFP_KERNEL);
 993         if (!pinctrl_state)
 994                 return -ENOMEM;
 995
 996         omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
 997         if (IS_ERR(omap_host->pinctrl)) {
 998                 dev_err(dev, "Cannot get pinctrl\n");
 999                 return PTR_ERR(omap_host->pinctrl);
1000         }
1001
1002         state = pinctrl_lookup_state(omap_host->pinctrl, "default");
1003         if (IS_ERR(state)) {
1004                 dev_err(dev, "no pinctrl state for default mode\n");
1005                 return PTR_ERR(state);
1006         }
1007         pinctrl_state[MMC_TIMING_LEGACY] = state;
1008
1009         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
1010                                                  MMC_CAP_UHS_SDR104);
1011         if (!IS_ERR(state))
1012                 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
1013
1014         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
1015                                                  MMC_CAP_UHS_DDR50);
1016         if (!IS_ERR(state))
1017                 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
1018
1019         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
1020                                                  MMC_CAP_UHS_SDR50);
1021         if (!IS_ERR(state))
1022                 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
1023
1024         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
1025                                                  MMC_CAP_UHS_SDR25);
1026         if (!IS_ERR(state))
1027                 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
1028
1029         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
1030                                                  MMC_CAP_UHS_SDR12);
1031         if (!IS_ERR(state))
1032                 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
1033
1034         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
1035                                                  MMC_CAP_1_8V_DDR);
1036         if (!IS_ERR(state)) {
1037                 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1038         } else {
1039                 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
1040                                                          caps,
1041                                                          MMC_CAP_3_3V_DDR);
1042                 if (!IS_ERR(state))
1043                         pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1044         }
1045
1046         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1047                                                  MMC_CAP_SD_HIGHSPEED);
1048         if (!IS_ERR(state))
1049                 pinctrl_state[MMC_TIMING_SD_HS] = state;
1050
1051         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1052                                                  MMC_CAP_MMC_HIGHSPEED);
1053         if (!IS_ERR(state))
1054                 pinctrl_state[MMC_TIMING_MMC_HS] = state;
1055
1056         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
1057                                                  MMC_CAP2_HS200_1_8V_SDR);
1058         if (!IS_ERR(state))
1059                 pinctrl_state[MMC_TIMING_MMC_HS200] = state;
1060
1061         omap_host->pinctrl_state = pinctrl_state;
1062
1063         return 0;
1064 }
1065
1066 static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
1067         {
1068                 .machine = "DRA7[45]*",
1069                 .revision = "ES1.[01]",
1070         },
1071         {
1072                 /* sentinel */
1073         }
1074 };
1075
1076 static int sdhci_omap_probe(struct platform_device *pdev)
1077 {
1078         int ret;
1079         u32 offset;
1080         struct device *dev = &pdev->dev;
1081         struct sdhci_host *host;
1082         struct sdhci_pltfm_host *pltfm_host;
1083         struct sdhci_omap_host *omap_host;
1084         struct mmc_host *mmc;
1085         const struct of_device_id *match;
1086         struct sdhci_omap_data *data;
1087         const struct soc_device_attribute *soc;
1088         struct resource *regs;
1089
1090         match = of_match_device(omap_sdhci_match, dev);
1091         if (!match)
1092                 return -EINVAL;
1093
1094         data = (struct sdhci_omap_data *)match->data;
1095         if (!data) {
1096                 dev_err(dev, "no sdhci omap data\n");
1097                 return -EINVAL;
1098         }
1099         offset = data->offset;
1100
1101         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1102         if (!regs)
1103                 return -ENXIO;
1104
1105         host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
1106                                 sizeof(*omap_host));
1107         if (IS_ERR(host)) {
1108                 dev_err(dev, "Failed sdhci_pltfm_init\n");
1109                 return PTR_ERR(host);
1110         }
1111
1112         pltfm_host = sdhci_priv(host);
1113         omap_host = sdhci_pltfm_priv(pltfm_host);
1114         omap_host->host = host;
1115         omap_host->base = host->ioaddr;
1116         omap_host->dev = dev;
1117         omap_host->power_mode = MMC_POWER_UNDEFINED;
1118         omap_host->timing = MMC_TIMING_LEGACY;
1119         omap_host->flags = data->flags;
1120         host->ioaddr += offset;
1121         host->mapbase = regs->start + offset;
1122
1123         mmc = host->mmc;
1124         sdhci_get_of_property(pdev);
1125         ret = mmc_of_parse(mmc);
1126         if (ret)
1127                 goto err_pltfm_free;
1128
1129         soc = soc_device_match(sdhci_omap_soc_devices);
1130         if (soc) {
1131                 omap_host->version = "rev11";
1132                 if (!strcmp(dev_name(dev), "4809c000.mmc"))
1133                         mmc->f_max = 96000000;
1134                 if (!strcmp(dev_name(dev), "480b4000.mmc"))
1135                         mmc->f_max = 48000000;
1136                 if (!strcmp(dev_name(dev), "480ad000.mmc"))
1137                         mmc->f_max = 48000000;
1138         }
1139
1140         if (!mmc_can_gpio_ro(mmc))
1141                 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1142
1143         pltfm_host->clk = devm_clk_get(dev, "fck");
1144         if (IS_ERR(pltfm_host->clk)) {
1145                 ret = PTR_ERR(pltfm_host->clk);
1146                 goto err_pltfm_free;
1147         }
1148
1149         ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
1150         if (ret) {
1151                 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
1152                 goto err_pltfm_free;
1153         }
1154
1155         omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
1156         if (IS_ERR(omap_host->pbias)) {
1157                 ret = PTR_ERR(omap_host->pbias);
1158                 if (ret != -ENODEV)
1159                         goto err_pltfm_free;
1160                 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
1161         }
1162         omap_host->pbias_enabled = false;
1163
1164         /*
1165          * omap_device_pm_domain has callbacks to enable the main
1166          * functional clock, interface clock and also configure the
1167          * SYSCONFIG register of omap devices. The callback will be invoked
1168          * as part of pm_runtime_get_sync.
1169          */
1170         pm_runtime_enable(dev);
1171         ret = pm_runtime_get_sync(dev);
1172         if (ret < 0) {
1173                 dev_err(dev, "pm_runtime_get_sync failed\n");
1174                 pm_runtime_put_noidle(dev);
1175                 goto err_rpm_disable;
1176         }
1177
1178         ret = sdhci_omap_set_capabilities(omap_host);
1179         if (ret) {
1180                 dev_err(dev, "failed to set system capabilities\n");
1181                 goto err_put_sync;
1182         }
1183
1184         host->mmc_host_ops.start_signal_voltage_switch =
1185                                         sdhci_omap_start_signal_voltage_switch;
1186         host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
1187         host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
1188         host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
1189         host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
1190
1191         /* Switch to external DMA only if there is the "dmas" property */
1192         if (of_find_property(dev->of_node, "dmas", NULL))
1193                 sdhci_switch_external_dma(host, true);
1194
1195         /* R1B responses is required to properly manage HW busy detection. */
1196         mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
1197
1198         ret = sdhci_setup_host(host);
1199         if (ret)
1200                 goto err_put_sync;
1201
1202         ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
1203         if (ret)
1204                 goto err_cleanup_host;
1205
1206         ret = __sdhci_add_host(host);
1207         if (ret)
1208                 goto err_cleanup_host;
1209
1210         return 0;
1211
1212 err_cleanup_host:
1213         sdhci_cleanup_host(host);
1214
1215 err_put_sync:
1216         pm_runtime_put_sync(dev);
1217
1218 err_rpm_disable:
1219         pm_runtime_disable(dev);
1220
1221 err_pltfm_free:
1222         sdhci_pltfm_free(pdev);
1223         return ret;
1224 }
1225
1226 static int sdhci_omap_remove(struct platform_device *pdev)
1227 {
1228         struct device *dev = &pdev->dev;
1229         struct sdhci_host *host = platform_get_drvdata(pdev);
1230
1231         sdhci_remove_host(host, true);
1232         pm_runtime_put_sync(dev);
1233         pm_runtime_disable(dev);
1234         sdhci_pltfm_free(pdev);
1235
1236         return 0;
1237 }
1238
1239 static struct platform_driver sdhci_omap_driver = {
1240         .probe = sdhci_omap_probe,
1241         .remove = sdhci_omap_remove,
1242         .driver = {
1243                    .name = "sdhci-omap",
1244                    .of_match_table = omap_sdhci_match,
1245                   },
1246 };
1247
1248 module_platform_driver(sdhci_omap_driver);
1249
1250 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
1251 MODULE_AUTHOR("Texas Instruments Inc.");
1252 MODULE_LICENSE("GPL v2");
1253 MODULE_ALIAS("platform:sdhci_omap");