2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
36 #include <mach/hardware.h>
38 #define DRIVER_NAME "mxc_nand"
40 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
41 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27())
43 /* Addresses for NFC registers */
44 #define NFC_BUF_SIZE 0xE00
45 #define NFC_BUF_ADDR 0xE04
46 #define NFC_FLASH_ADDR 0xE06
47 #define NFC_FLASH_CMD 0xE08
48 #define NFC_CONFIG 0xE0A
49 #define NFC_ECC_STATUS_RESULT 0xE0C
50 #define NFC_RSLTMAIN_AREA 0xE0E
51 #define NFC_RSLTSPARE_AREA 0xE10
52 #define NFC_WRPROT 0xE12
53 #define NFC_V1_UNLOCKSTART_BLKADDR 0xe14
54 #define NFC_V1_UNLOCKEND_BLKADDR 0xe16
55 #define NFC_V21_UNLOCKSTART_BLKADDR 0xe20
56 #define NFC_V21_UNLOCKEND_BLKADDR 0xe22
57 #define NFC_NF_WRPRST 0xE18
58 #define NFC_CONFIG1 0xE1A
59 #define NFC_CONFIG2 0xE1C
61 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
62 * for Command operation */
65 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
66 * for Address operation */
69 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
70 * for Input operation */
73 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
74 * for Data Output operation */
75 #define NFC_OUTPUT 0x8
77 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
78 * for Read ID operation */
81 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
82 * for Read Status operation */
83 #define NFC_STATUS 0x20
85 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
87 #define NFC_INT 0x8000
89 #define NFC_SP_EN (1 << 2)
90 #define NFC_ECC_EN (1 << 3)
91 #define NFC_INT_MSK (1 << 4)
92 #define NFC_BIG (1 << 5)
93 #define NFC_RST (1 << 6)
94 #define NFC_CE (1 << 7)
95 #define NFC_ONE_CYCLE (1 << 8)
97 struct mxc_nand_host {
99 struct nand_chip nand;
100 struct mtd_partition *parts;
114 wait_queue_head_t irq_waitq;
117 unsigned int buf_start;
121 /* OOB placement block for use with hardware ecc generation */
122 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
124 .eccpos = {6, 7, 8, 9, 10},
125 .oobfree = {{0, 5}, {12, 4}, }
128 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
130 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
131 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
132 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
135 /* OOB description for 512 byte pages with 16 byte OOB */
136 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
139 7, 8, 9, 10, 11, 12, 13, 14, 15
142 {.offset = 0, .length = 5}
146 /* OOB description for 2048 byte pages with 64 byte OOB */
147 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
150 7, 8, 9, 10, 11, 12, 13, 14, 15,
151 23, 24, 25, 26, 27, 28, 29, 30, 31,
152 39, 40, 41, 42, 43, 44, 45, 46, 47,
153 55, 56, 57, 58, 59, 60, 61, 62, 63
156 {.offset = 2, .length = 4},
157 {.offset = 16, .length = 7},
158 {.offset = 32, .length = 7},
159 {.offset = 48, .length = 7}
163 #ifdef CONFIG_MTD_PARTITIONS
164 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
167 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
169 struct mxc_nand_host *host = dev_id;
173 tmp = readw(host->regs + NFC_CONFIG1);
174 tmp |= NFC_INT_MSK; /* Disable interrupt */
175 writew(tmp, host->regs + NFC_CONFIG1);
177 wake_up(&host->irq_waitq);
182 /* This function polls the NANDFC to wait for the basic operation to
183 * complete by checking the INT bit of config2 register.
185 static void wait_op_done(struct mxc_nand_host *host, int useirq)
188 int max_retries = 2000;
191 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
193 tmp = readw(host->regs + NFC_CONFIG1);
194 tmp &= ~NFC_INT_MSK; /* Enable interrupt */
195 writew(tmp, host->regs + NFC_CONFIG1);
197 wait_event(host->irq_waitq,
198 readw(host->regs + NFC_CONFIG2) & NFC_INT);
200 tmp = readw(host->regs + NFC_CONFIG2);
202 writew(tmp, host->regs + NFC_CONFIG2);
205 while (max_retries-- > 0) {
206 if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
207 tmp = readw(host->regs + NFC_CONFIG2);
209 writew(tmp, host->regs + NFC_CONFIG2);
215 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
220 /* This function issues the specified command to the NAND device and
221 * waits for completion. */
222 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
224 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
226 writew(cmd, host->regs + NFC_FLASH_CMD);
227 writew(NFC_CMD, host->regs + NFC_CONFIG2);
229 /* Wait for operation to complete */
230 wait_op_done(host, useirq);
233 /* This function sends an address (or partial address) to the
234 * NAND device. The address is used to select the source/destination for
236 static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
238 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
240 writew(addr, host->regs + NFC_FLASH_ADDR);
241 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
243 /* Wait for operation to complete */
244 wait_op_done(host, islast);
247 static void send_page(struct mtd_info *mtd, unsigned int ops)
249 struct nand_chip *nand_chip = mtd->priv;
250 struct mxc_nand_host *host = nand_chip->priv;
253 if (nfc_is_v1() && mtd->writesize > 512)
258 for (i = 0; i < bufs; i++) {
260 /* NANDFC buffer 0 is used for page read/write */
261 writew(i, host->regs + NFC_BUF_ADDR);
263 writew(ops, host->regs + NFC_CONFIG2);
265 /* Wait for operation to complete */
266 wait_op_done(host, true);
270 /* Request the NANDFC to perform a read of the NAND device ID. */
271 static void send_read_id(struct mxc_nand_host *host)
273 struct nand_chip *this = &host->nand;
275 /* NANDFC buffer 0 is used for device ID output */
276 writew(0x0, host->regs + NFC_BUF_ADDR);
278 writew(NFC_ID, host->regs + NFC_CONFIG2);
280 /* Wait for operation to complete */
281 wait_op_done(host, true);
283 if (this->options & NAND_BUSWIDTH_16) {
284 void __iomem *main_buf = host->main_area0;
285 /* compress the ID info */
286 writeb(readb(main_buf + 2), main_buf + 1);
287 writeb(readb(main_buf + 4), main_buf + 2);
288 writeb(readb(main_buf + 6), main_buf + 3);
289 writeb(readb(main_buf + 8), main_buf + 4);
290 writeb(readb(main_buf + 10), main_buf + 5);
292 memcpy(host->data_buf, host->main_area0, 16);
295 /* This function requests the NANDFC to perform a read of the
296 * NAND device status and returns the current status. */
297 static uint16_t get_dev_status(struct mxc_nand_host *host)
299 void __iomem *main_buf = host->main_area1;
302 /* Issue status request to NAND device */
304 /* store the main area1 first word, later do recovery */
305 store = readl(main_buf);
306 /* NANDFC buffer 1 is used for device status to prevent
307 * corruption of read/write buffer on status requests. */
308 writew(1, host->regs + NFC_BUF_ADDR);
310 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
312 /* Wait for operation to complete */
313 wait_op_done(host, true);
315 /* Status is placed in first word of main buffer */
316 /* get status, then recovery area 1 data */
317 ret = readw(main_buf);
318 writel(store, main_buf);
323 /* This functions is used by upper layer to checks if device is ready */
324 static int mxc_nand_dev_ready(struct mtd_info *mtd)
327 * NFC handles R/B internally. Therefore, this function
328 * always returns status as ready.
333 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
336 * If HW ECC is enabled, we turn it on during init. There is
337 * no need to enable again here.
341 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
342 u_char *read_ecc, u_char *calc_ecc)
344 struct nand_chip *nand_chip = mtd->priv;
345 struct mxc_nand_host *host = nand_chip->priv;
348 * 1-Bit errors are automatically corrected in HW. No need for
349 * additional correction. 2-Bit errors cannot be corrected by
350 * HW ECC, so we need to return failure
352 uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
354 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
355 DEBUG(MTD_DEBUG_LEVEL0,
356 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
363 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
369 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
371 struct nand_chip *nand_chip = mtd->priv;
372 struct mxc_nand_host *host = nand_chip->priv;
375 /* Check for status request */
376 if (host->status_request)
377 return get_dev_status(host) & 0xFF;
379 ret = *(uint8_t *)(host->data_buf + host->buf_start);
385 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
387 struct nand_chip *nand_chip = mtd->priv;
388 struct mxc_nand_host *host = nand_chip->priv;
391 ret = *(uint16_t *)(host->data_buf + host->buf_start);
392 host->buf_start += 2;
397 /* Write data of length len to buffer buf. The data to be
398 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
399 * Operation by the NFC, the data is written to NAND Flash */
400 static void mxc_nand_write_buf(struct mtd_info *mtd,
401 const u_char *buf, int len)
403 struct nand_chip *nand_chip = mtd->priv;
404 struct mxc_nand_host *host = nand_chip->priv;
405 u16 col = host->buf_start;
406 int n = mtd->oobsize + mtd->writesize - col;
410 memcpy(host->data_buf + col, buf, n);
412 host->buf_start += n;
415 /* Read the data buffer from the NAND Flash. To read the data from NAND
416 * Flash first the data output cycle is initiated by the NFC, which copies
417 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
419 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
421 struct nand_chip *nand_chip = mtd->priv;
422 struct mxc_nand_host *host = nand_chip->priv;
423 u16 col = host->buf_start;
424 int n = mtd->oobsize + mtd->writesize - col;
428 memcpy(buf, host->data_buf + col, len);
430 host->buf_start += len;
433 /* Used by the upper layer to verify the data in NAND Flash
434 * with the data in the buf. */
435 static int mxc_nand_verify_buf(struct mtd_info *mtd,
436 const u_char *buf, int len)
441 /* This function is used by upper layer for select and
442 * deselect of the NAND chip */
443 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
445 struct nand_chip *nand_chip = mtd->priv;
446 struct mxc_nand_host *host = nand_chip->priv;
450 /* Disable the NFC clock */
452 clk_disable(host->clk);
457 /* Enable the NFC clock */
458 if (!host->clk_act) {
459 clk_enable(host->clk);
470 * Function to transfer data to/from spare area.
472 static void copy_spare(struct mtd_info *mtd, bool bfrom)
474 struct nand_chip *this = mtd->priv;
475 struct mxc_nand_host *host = this->priv;
477 u16 n = mtd->writesize >> 9;
478 u8 *d = host->data_buf + mtd->writesize;
479 u8 *s = host->spare0;
480 u16 t = host->spare_len;
482 j = (mtd->oobsize / n >> 1) << 1;
485 for (i = 0; i < n - 1; i++)
486 memcpy(d + i * j, s + i * t, j);
488 /* the last section */
489 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
491 for (i = 0; i < n - 1; i++)
492 memcpy(&s[i * t], &d[i * j], j);
494 /* the last section */
495 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
499 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
501 struct nand_chip *nand_chip = mtd->priv;
502 struct mxc_nand_host *host = nand_chip->priv;
504 /* Write out column address, if necessary */
507 * MXC NANDFC can only perform full page+spare or
508 * spare-only read/write. When the upper layers
509 * layers perform a read/write buf operation,
510 * we will used the saved column address to index into
513 send_addr(host, 0, page_addr == -1);
514 if (mtd->writesize > 512)
515 /* another col addr cycle for 2k page */
516 send_addr(host, 0, false);
519 /* Write out page address, if necessary */
520 if (page_addr != -1) {
521 /* paddr_0 - p_addr_7 */
522 send_addr(host, (page_addr & 0xff), false);
524 if (mtd->writesize > 512) {
525 if (mtd->size >= 0x10000000) {
526 /* paddr_8 - paddr_15 */
527 send_addr(host, (page_addr >> 8) & 0xff, false);
528 send_addr(host, (page_addr >> 16) & 0xff, true);
530 /* paddr_8 - paddr_15 */
531 send_addr(host, (page_addr >> 8) & 0xff, true);
533 /* One more address cycle for higher density devices */
534 if (mtd->size >= 0x4000000) {
535 /* paddr_8 - paddr_15 */
536 send_addr(host, (page_addr >> 8) & 0xff, false);
537 send_addr(host, (page_addr >> 16) & 0xff, true);
539 /* paddr_8 - paddr_15 */
540 send_addr(host, (page_addr >> 8) & 0xff, true);
545 static void preset(struct mtd_info *mtd)
547 struct nand_chip *nand_chip = mtd->priv;
548 struct mxc_nand_host *host = nand_chip->priv;
551 /* disable interrupt, disable spare enable */
552 tmp = readw(host->regs + NFC_CONFIG1);
555 if (nand_chip->ecc.mode == NAND_ECC_HW) {
560 writew(tmp, host->regs + NFC_CONFIG1);
561 /* preset operation */
563 /* Unlock the internal RAM Buffer */
564 writew(0x2, host->regs + NFC_CONFIG);
566 /* Blocks to be unlocked */
568 writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
569 writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
570 } else if (nfc_is_v1()) {
571 writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
572 writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
576 /* Unlock Block Command for given address range */
577 writew(0x4, host->regs + NFC_WRPROT);
580 /* Used by the upper layer to write command to NAND Flash for
581 * different operations to be carried out on NAND Flash */
582 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
583 int column, int page_addr)
585 struct nand_chip *nand_chip = mtd->priv;
586 struct mxc_nand_host *host = nand_chip->priv;
588 DEBUG(MTD_DEBUG_LEVEL3,
589 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
590 command, column, page_addr);
592 /* Reset command state information */
593 host->status_request = false;
595 /* Command pre-processing step */
598 send_cmd(host, command, false);
602 case NAND_CMD_STATUS:
604 host->status_request = true;
606 send_cmd(host, command, true);
607 mxc_do_addr_cycle(mtd, column, page_addr);
611 case NAND_CMD_READOOB:
612 if (command == NAND_CMD_READ0)
613 host->buf_start = column;
615 host->buf_start = column + mtd->writesize;
617 if (mtd->writesize > 512)
618 command = NAND_CMD_READ0; /* only READ0 is valid */
620 send_cmd(host, command, false);
621 mxc_do_addr_cycle(mtd, column, page_addr);
623 if (mtd->writesize > 512)
624 send_cmd(host, NAND_CMD_READSTART, true);
626 send_page(mtd, NFC_OUTPUT);
628 memcpy(host->data_buf, host->main_area0, mtd->writesize);
629 copy_spare(mtd, true);
633 if (column >= mtd->writesize) {
635 * FIXME: before send SEQIN command for write OOB,
636 * We must read one page out.
637 * For K9F1GXX has no READ1 command to set current HW
638 * pointer to spare area, we must write the whole page
639 * including OOB together.
641 if (mtd->writesize > 512)
642 /* call ourself to read a page */
643 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
646 host->buf_start = column;
648 /* Set program pointer to spare region */
649 if (mtd->writesize == 512)
650 send_cmd(host, NAND_CMD_READOOB, false);
652 host->buf_start = column;
654 /* Set program pointer to page start */
655 if (mtd->writesize == 512)
656 send_cmd(host, NAND_CMD_READ0, false);
659 send_cmd(host, command, false);
660 mxc_do_addr_cycle(mtd, column, page_addr);
663 case NAND_CMD_PAGEPROG:
664 memcpy(host->main_area0, host->data_buf, mtd->writesize);
665 copy_spare(mtd, false);
666 send_page(mtd, NFC_INPUT);
667 send_cmd(host, command, true);
668 mxc_do_addr_cycle(mtd, column, page_addr);
671 case NAND_CMD_READID:
672 send_cmd(host, command, true);
673 mxc_do_addr_cycle(mtd, column, page_addr);
675 host->buf_start = column;
678 case NAND_CMD_ERASE1:
679 case NAND_CMD_ERASE2:
680 send_cmd(host, command, false);
681 mxc_do_addr_cycle(mtd, column, page_addr);
688 * The generic flash bbt decriptors overlap with our ecc
689 * hardware, so define some i.MX specific ones.
691 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
692 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
694 static struct nand_bbt_descr bbt_main_descr = {
695 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
696 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
701 .pattern = bbt_pattern,
704 static struct nand_bbt_descr bbt_mirror_descr = {
705 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
706 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
711 .pattern = mirror_pattern,
714 static int __init mxcnd_probe(struct platform_device *pdev)
716 struct nand_chip *this;
717 struct mtd_info *mtd;
718 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
719 struct mxc_nand_host *host;
720 struct resource *res;
721 int err = 0, nr_parts = 0;
722 struct nand_ecclayout *oob_smallpage, *oob_largepage;
724 /* Allocate memory for MTD device structure and private data */
725 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
726 NAND_MAX_OOBSIZE, GFP_KERNEL);
730 host->data_buf = (uint8_t *)(host + 1);
732 host->dev = &pdev->dev;
733 /* structures must be linked */
737 mtd->owner = THIS_MODULE;
738 mtd->dev.parent = &pdev->dev;
739 mtd->name = DRIVER_NAME;
741 /* 50 us command delay time */
742 this->chip_delay = 5;
745 this->dev_ready = mxc_nand_dev_ready;
746 this->cmdfunc = mxc_nand_command;
747 this->select_chip = mxc_nand_select_chip;
748 this->read_byte = mxc_nand_read_byte;
749 this->read_word = mxc_nand_read_word;
750 this->write_buf = mxc_nand_write_buf;
751 this->read_buf = mxc_nand_read_buf;
752 this->verify_buf = mxc_nand_verify_buf;
754 host->clk = clk_get(&pdev->dev, "nfc");
755 if (IS_ERR(host->clk)) {
756 err = PTR_ERR(host->clk);
760 clk_enable(host->clk);
763 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
769 host->base = ioremap(res->start, resource_size(res));
775 host->main_area0 = host->base;
776 host->main_area1 = host->base + 0x200;
779 host->regs = host->base + 0x1000;
780 host->spare0 = host->base + 0x1000;
781 host->spare_len = 64;
782 oob_smallpage = &nandv2_hw_eccoob_smallpage;
783 oob_largepage = &nandv2_hw_eccoob_largepage;
785 } else if (nfc_is_v1()) {
786 host->regs = host->base;
787 host->spare0 = host->base + 0x800;
788 host->spare_len = 16;
789 oob_smallpage = &nandv1_hw_eccoob_smallpage;
790 oob_largepage = &nandv1_hw_eccoob_largepage;
795 this->ecc.size = 512;
796 this->ecc.layout = oob_smallpage;
799 this->ecc.calculate = mxc_nand_calculate_ecc;
800 this->ecc.hwctl = mxc_nand_enable_hwecc;
801 this->ecc.correct = mxc_nand_correct_data;
802 this->ecc.mode = NAND_ECC_HW;
804 this->ecc.mode = NAND_ECC_SOFT;
807 /* NAND bus width determines access funtions used by upper layer */
808 if (pdata->width == 2)
809 this->options |= NAND_BUSWIDTH_16;
811 if (pdata->flash_bbt) {
812 this->bbt_td = &bbt_main_descr;
813 this->bbt_md = &bbt_mirror_descr;
814 /* update flash based bbt */
815 this->options |= NAND_USE_FLASH_BBT;
818 init_waitqueue_head(&host->irq_waitq);
820 host->irq = platform_get_irq(pdev, 0);
822 err = request_irq(host->irq, mxc_nfc_irq, 0, DRIVER_NAME, host);
826 /* first scan to find the device and get the page size */
827 if (nand_scan_ident(mtd, 1)) {
832 if (mtd->writesize == 2048)
833 this->ecc.layout = oob_largepage;
835 /* second phase scan */
836 if (nand_scan_tail(mtd)) {
841 /* Register the partitions */
842 #ifdef CONFIG_MTD_PARTITIONS
844 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
846 add_mtd_partitions(mtd, host->parts, nr_parts);
850 pr_info("Registering %s as whole device\n", mtd->name);
854 platform_set_drvdata(pdev, host);
859 free_irq(host->irq, host);
870 static int __devexit mxcnd_remove(struct platform_device *pdev)
872 struct mxc_nand_host *host = platform_get_drvdata(pdev);
876 platform_set_drvdata(pdev, NULL);
878 nand_release(&host->mtd);
879 free_irq(host->irq, host);
887 static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
889 struct mtd_info *mtd = platform_get_drvdata(pdev);
890 struct nand_chip *nand_chip = mtd->priv;
891 struct mxc_nand_host *host = nand_chip->priv;
894 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
896 ret = mtd->suspend(mtd);
897 /* Disable the NFC clock */
898 clk_disable(host->clk);
904 static int mxcnd_resume(struct platform_device *pdev)
906 struct mtd_info *mtd = platform_get_drvdata(pdev);
907 struct nand_chip *nand_chip = mtd->priv;
908 struct mxc_nand_host *host = nand_chip->priv;
911 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
914 /* Enable the NFC clock */
915 clk_enable(host->clk);
923 # define mxcnd_suspend NULL
924 # define mxcnd_resume NULL
925 #endif /* CONFIG_PM */
927 static struct platform_driver mxcnd_driver = {
931 .remove = __devexit_p(mxcnd_remove),
932 .suspend = mxcnd_suspend,
933 .resume = mxcnd_resume,
936 static int __init mxc_nd_init(void)
938 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
941 static void __exit mxc_nd_cleanup(void)
943 /* Unregister the device structure */
944 platform_driver_unregister(&mxcnd_driver);
947 module_init(mxc_nd_init);
948 module_exit(mxc_nd_cleanup);
950 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
951 MODULE_DESCRIPTION("MXC NAND MTD driver");
952 MODULE_LICENSE("GPL");