2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
36 #include <asm/mach/flash.h>
37 #include <mach/mxc_nand.h>
38 #include <mach/hardware.h>
40 #define DRIVER_NAME "mxc_nand"
42 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
43 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
44 #define nfc_is_v3_2() (cpu_is_mx51() || cpu_is_mx53())
45 #define nfc_is_v3() nfc_is_v3_2()
47 /* Addresses for NFC registers */
48 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
49 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
50 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
51 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
52 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
53 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
54 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
55 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
56 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
57 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
58 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
59 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
60 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
61 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
62 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
63 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
64 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
65 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
66 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
67 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
68 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
69 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
71 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
72 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
73 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
74 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
75 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
76 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
77 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
78 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
79 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
80 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
82 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
85 * Operation modes for the NFC. Valid for v1, v2 and v3
88 #define NFC_CMD (1 << 0)
89 #define NFC_ADDR (1 << 1)
90 #define NFC_INPUT (1 << 2)
91 #define NFC_OUTPUT (1 << 3)
92 #define NFC_ID (1 << 4)
93 #define NFC_STATUS (1 << 5)
95 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
96 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
98 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
99 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
100 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
102 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
104 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
106 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
107 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
108 #define NFC_V3_WRPROT_LOCK (1 << 1)
109 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
110 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
112 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
114 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
115 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
116 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
117 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
118 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
119 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
120 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
121 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
122 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
123 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
124 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
125 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
126 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
127 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
129 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
130 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
131 #define NFC_V3_CONFIG3_FW8 (1 << 3)
132 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
133 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
134 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
135 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
137 #define NFC_V3_IPC (host->regs_ip + 0x2C)
138 #define NFC_V3_IPC_CREQ (1 << 0)
139 #define NFC_V3_IPC_INT (1 << 31)
141 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
143 struct mxc_nand_host {
145 struct nand_chip nand;
153 void __iomem *regs_axi;
154 void __iomem *regs_ip;
162 struct completion op_completion;
165 unsigned int buf_start;
168 void (*preset)(struct mtd_info *);
169 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
170 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
171 void (*send_page)(struct mtd_info *, unsigned int);
172 void (*send_read_id)(struct mxc_nand_host *);
173 uint16_t (*get_dev_status)(struct mxc_nand_host *);
174 int (*check_int)(struct mxc_nand_host *);
175 void (*irq_control)(struct mxc_nand_host *, int);
178 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
179 * (CONFIG1:INT_MSK is set). To handle this the driver uses
180 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
182 int irqpending_quirk;
185 /* OOB placement block for use with hardware ecc generation */
186 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
188 .eccpos = {6, 7, 8, 9, 10},
189 .oobfree = {{0, 5}, {12, 4}, }
192 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
194 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
195 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
196 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
199 /* OOB description for 512 byte pages with 16 byte OOB */
200 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
203 7, 8, 9, 10, 11, 12, 13, 14, 15
206 {.offset = 0, .length = 5}
210 /* OOB description for 2048 byte pages with 64 byte OOB */
211 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
214 7, 8, 9, 10, 11, 12, 13, 14, 15,
215 23, 24, 25, 26, 27, 28, 29, 30, 31,
216 39, 40, 41, 42, 43, 44, 45, 46, 47,
217 55, 56, 57, 58, 59, 60, 61, 62, 63
220 {.offset = 2, .length = 4},
221 {.offset = 16, .length = 7},
222 {.offset = 32, .length = 7},
223 {.offset = 48, .length = 7}
227 /* OOB description for 4096 byte pages with 128 byte OOB */
228 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
231 7, 8, 9, 10, 11, 12, 13, 14, 15,
232 23, 24, 25, 26, 27, 28, 29, 30, 31,
233 39, 40, 41, 42, 43, 44, 45, 46, 47,
234 55, 56, 57, 58, 59, 60, 61, 62, 63,
235 71, 72, 73, 74, 75, 76, 77, 78, 79,
236 87, 88, 89, 90, 91, 92, 93, 94, 95,
237 103, 104, 105, 106, 107, 108, 109, 110, 111,
238 119, 120, 121, 122, 123, 124, 125, 126, 127,
241 {.offset = 2, .length = 4},
242 {.offset = 16, .length = 7},
243 {.offset = 32, .length = 7},
244 {.offset = 48, .length = 7},
245 {.offset = 64, .length = 7},
246 {.offset = 80, .length = 7},
247 {.offset = 96, .length = 7},
248 {.offset = 112, .length = 7},
252 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
254 static int check_int_v3(struct mxc_nand_host *host)
258 tmp = readl(NFC_V3_IPC);
259 if (!(tmp & NFC_V3_IPC_INT))
262 tmp &= ~NFC_V3_IPC_INT;
263 writel(tmp, NFC_V3_IPC);
268 static int check_int_v1_v2(struct mxc_nand_host *host)
272 tmp = readw(NFC_V1_V2_CONFIG2);
273 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
276 if (!host->irqpending_quirk)
277 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
282 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
286 tmp = readw(NFC_V1_V2_CONFIG1);
289 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
291 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
293 writew(tmp, NFC_V1_V2_CONFIG1);
296 static void irq_control_v3(struct mxc_nand_host *host, int activate)
300 tmp = readl(NFC_V3_CONFIG2);
303 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
305 tmp |= NFC_V3_CONFIG2_INT_MSK;
307 writel(tmp, NFC_V3_CONFIG2);
310 static void irq_control(struct mxc_nand_host *host, int activate)
312 if (host->irqpending_quirk) {
314 enable_irq(host->irq);
316 disable_irq_nosync(host->irq);
318 host->irq_control(host, activate);
322 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
324 struct mxc_nand_host *host = dev_id;
326 if (!host->check_int(host))
329 irq_control(host, 0);
331 complete(&host->op_completion);
336 /* This function polls the NANDFC to wait for the basic operation to
337 * complete by checking the INT bit of config2 register.
339 static void wait_op_done(struct mxc_nand_host *host, int useirq)
341 int max_retries = 8000;
344 if (!host->check_int(host)) {
345 INIT_COMPLETION(host->op_completion);
346 irq_control(host, 1);
347 wait_for_completion(&host->op_completion);
350 while (max_retries-- > 0) {
351 if (host->check_int(host))
357 pr_debug("%s: INT not set\n", __func__);
361 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
364 writel(cmd, NFC_V3_FLASH_CMD);
366 /* send out command */
367 writel(NFC_CMD, NFC_V3_LAUNCH);
369 /* Wait for operation to complete */
370 wait_op_done(host, useirq);
373 /* This function issues the specified command to the NAND device and
374 * waits for completion. */
375 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
377 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
379 writew(cmd, NFC_V1_V2_FLASH_CMD);
380 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
382 if (host->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
383 int max_retries = 100;
384 /* Reset completion is indicated by NFC_CONFIG2 */
386 while (max_retries-- > 0) {
387 if (readw(NFC_V1_V2_CONFIG2) == 0) {
393 pr_debug("%s: RESET failed\n", __func__);
395 /* Wait for operation to complete */
396 wait_op_done(host, useirq);
400 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
403 writel(addr, NFC_V3_FLASH_ADDR0);
405 /* send out address */
406 writel(NFC_ADDR, NFC_V3_LAUNCH);
408 wait_op_done(host, 0);
411 /* This function sends an address (or partial address) to the
412 * NAND device. The address is used to select the source/destination for
414 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
416 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
418 writew(addr, NFC_V1_V2_FLASH_ADDR);
419 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
421 /* Wait for operation to complete */
422 wait_op_done(host, islast);
425 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
427 struct nand_chip *nand_chip = mtd->priv;
428 struct mxc_nand_host *host = nand_chip->priv;
431 tmp = readl(NFC_V3_CONFIG1);
433 writel(tmp, NFC_V3_CONFIG1);
435 /* transfer data from NFC ram to nand */
436 writel(ops, NFC_V3_LAUNCH);
438 wait_op_done(host, false);
441 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
443 struct nand_chip *nand_chip = mtd->priv;
444 struct mxc_nand_host *host = nand_chip->priv;
447 if (nfc_is_v1() && mtd->writesize > 512)
452 for (i = 0; i < bufs; i++) {
454 /* NANDFC buffer 0 is used for page read/write */
455 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
457 writew(ops, NFC_V1_V2_CONFIG2);
459 /* Wait for operation to complete */
460 wait_op_done(host, true);
464 static void send_read_id_v3(struct mxc_nand_host *host)
466 /* Read ID into main buffer */
467 writel(NFC_ID, NFC_V3_LAUNCH);
469 wait_op_done(host, true);
471 memcpy(host->data_buf, host->main_area0, 16);
474 /* Request the NANDFC to perform a read of the NAND device ID. */
475 static void send_read_id_v1_v2(struct mxc_nand_host *host)
477 struct nand_chip *this = &host->nand;
479 /* NANDFC buffer 0 is used for device ID output */
480 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
482 writew(NFC_ID, NFC_V1_V2_CONFIG2);
484 /* Wait for operation to complete */
485 wait_op_done(host, true);
487 memcpy(host->data_buf, host->main_area0, 16);
489 if (this->options & NAND_BUSWIDTH_16) {
490 /* compress the ID info */
491 host->data_buf[1] = host->data_buf[2];
492 host->data_buf[2] = host->data_buf[4];
493 host->data_buf[3] = host->data_buf[6];
494 host->data_buf[4] = host->data_buf[8];
495 host->data_buf[5] = host->data_buf[10];
499 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
501 writew(NFC_STATUS, NFC_V3_LAUNCH);
502 wait_op_done(host, true);
504 return readl(NFC_V3_CONFIG1) >> 16;
507 /* This function requests the NANDFC to perform a read of the
508 * NAND device status and returns the current status. */
509 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
511 void __iomem *main_buf = host->main_area0;
515 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
518 * The device status is stored in main_area0. To
519 * prevent corruption of the buffer save the value
520 * and restore it afterwards.
522 store = readl(main_buf);
524 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
525 wait_op_done(host, true);
527 ret = readw(main_buf);
529 writel(store, main_buf);
534 /* This functions is used by upper layer to checks if device is ready */
535 static int mxc_nand_dev_ready(struct mtd_info *mtd)
538 * NFC handles R/B internally. Therefore, this function
539 * always returns status as ready.
544 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
547 * If HW ECC is enabled, we turn it on during init. There is
548 * no need to enable again here.
552 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
553 u_char *read_ecc, u_char *calc_ecc)
555 struct nand_chip *nand_chip = mtd->priv;
556 struct mxc_nand_host *host = nand_chip->priv;
559 * 1-Bit errors are automatically corrected in HW. No need for
560 * additional correction. 2-Bit errors cannot be corrected by
561 * HW ECC, so we need to return failure
563 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
565 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
566 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
573 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
574 u_char *read_ecc, u_char *calc_ecc)
576 struct nand_chip *nand_chip = mtd->priv;
577 struct mxc_nand_host *host = nand_chip->priv;
581 u8 ecc_bit_mask, err_limit;
583 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
584 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
586 no_subpages = mtd->writesize >> 9;
589 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
591 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
594 err = ecc_stat & ecc_bit_mask;
595 if (err > err_limit) {
596 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
602 } while (--no_subpages);
604 mtd->ecc_stats.corrected += ret;
605 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
610 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
616 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
618 struct nand_chip *nand_chip = mtd->priv;
619 struct mxc_nand_host *host = nand_chip->priv;
622 /* Check for status request */
623 if (host->status_request)
624 return host->get_dev_status(host) & 0xFF;
626 ret = *(uint8_t *)(host->data_buf + host->buf_start);
632 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
634 struct nand_chip *nand_chip = mtd->priv;
635 struct mxc_nand_host *host = nand_chip->priv;
638 ret = *(uint16_t *)(host->data_buf + host->buf_start);
639 host->buf_start += 2;
644 /* Write data of length len to buffer buf. The data to be
645 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
646 * Operation by the NFC, the data is written to NAND Flash */
647 static void mxc_nand_write_buf(struct mtd_info *mtd,
648 const u_char *buf, int len)
650 struct nand_chip *nand_chip = mtd->priv;
651 struct mxc_nand_host *host = nand_chip->priv;
652 u16 col = host->buf_start;
653 int n = mtd->oobsize + mtd->writesize - col;
657 memcpy(host->data_buf + col, buf, n);
659 host->buf_start += n;
662 /* Read the data buffer from the NAND Flash. To read the data from NAND
663 * Flash first the data output cycle is initiated by the NFC, which copies
664 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
666 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
668 struct nand_chip *nand_chip = mtd->priv;
669 struct mxc_nand_host *host = nand_chip->priv;
670 u16 col = host->buf_start;
671 int n = mtd->oobsize + mtd->writesize - col;
675 memcpy(buf, host->data_buf + col, n);
677 host->buf_start += n;
680 /* Used by the upper layer to verify the data in NAND Flash
681 * with the data in the buf. */
682 static int mxc_nand_verify_buf(struct mtd_info *mtd,
683 const u_char *buf, int len)
688 /* This function is used by upper layer for select and
689 * deselect of the NAND chip */
690 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
692 struct nand_chip *nand_chip = mtd->priv;
693 struct mxc_nand_host *host = nand_chip->priv;
696 /* Disable the NFC clock */
698 clk_disable(host->clk);
704 if (!host->clk_act) {
705 /* Enable the NFC clock */
706 clk_enable(host->clk);
711 host->active_cs = chip;
712 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
717 * Function to transfer data to/from spare area.
719 static void copy_spare(struct mtd_info *mtd, bool bfrom)
721 struct nand_chip *this = mtd->priv;
722 struct mxc_nand_host *host = this->priv;
724 u16 n = mtd->writesize >> 9;
725 u8 *d = host->data_buf + mtd->writesize;
726 u8 *s = host->spare0;
727 u16 t = host->spare_len;
729 j = (mtd->oobsize / n >> 1) << 1;
732 for (i = 0; i < n - 1; i++)
733 memcpy(d + i * j, s + i * t, j);
735 /* the last section */
736 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
738 for (i = 0; i < n - 1; i++)
739 memcpy(&s[i * t], &d[i * j], j);
741 /* the last section */
742 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
746 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
748 struct nand_chip *nand_chip = mtd->priv;
749 struct mxc_nand_host *host = nand_chip->priv;
751 /* Write out column address, if necessary */
754 * MXC NANDFC can only perform full page+spare or
755 * spare-only read/write. When the upper layers
756 * perform a read/write buf operation, the saved column
757 * address is used to index into the full page.
759 host->send_addr(host, 0, page_addr == -1);
760 if (mtd->writesize > 512)
761 /* another col addr cycle for 2k page */
762 host->send_addr(host, 0, false);
765 /* Write out page address, if necessary */
766 if (page_addr != -1) {
767 /* paddr_0 - p_addr_7 */
768 host->send_addr(host, (page_addr & 0xff), false);
770 if (mtd->writesize > 512) {
771 if (mtd->size >= 0x10000000) {
772 /* paddr_8 - paddr_15 */
773 host->send_addr(host, (page_addr >> 8) & 0xff, false);
774 host->send_addr(host, (page_addr >> 16) & 0xff, true);
776 /* paddr_8 - paddr_15 */
777 host->send_addr(host, (page_addr >> 8) & 0xff, true);
779 /* One more address cycle for higher density devices */
780 if (mtd->size >= 0x4000000) {
781 /* paddr_8 - paddr_15 */
782 host->send_addr(host, (page_addr >> 8) & 0xff, false);
783 host->send_addr(host, (page_addr >> 16) & 0xff, true);
785 /* paddr_8 - paddr_15 */
786 host->send_addr(host, (page_addr >> 8) & 0xff, true);
792 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
793 * on how much oob the nand chip has. For 8bit ecc we need at least
794 * 26 bytes of oob data per 512 byte block.
796 static int get_eccsize(struct mtd_info *mtd)
798 int oobbytes_per_512 = 0;
800 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
802 if (oobbytes_per_512 < 26)
808 static void preset_v1_v2(struct mtd_info *mtd)
810 struct nand_chip *nand_chip = mtd->priv;
811 struct mxc_nand_host *host = nand_chip->priv;
812 uint16_t config1 = 0;
814 if (nand_chip->ecc.mode == NAND_ECC_HW)
815 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
818 config1 |= NFC_V2_CONFIG1_FP_INT;
820 if (!host->irqpending_quirk)
821 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
823 if (nfc_is_v21() && mtd->writesize) {
824 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
826 host->eccsize = get_eccsize(mtd);
827 if (host->eccsize == 4)
828 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
830 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
835 writew(config1, NFC_V1_V2_CONFIG1);
836 /* preset operation */
838 /* Unlock the internal RAM Buffer */
839 writew(0x2, NFC_V1_V2_CONFIG);
841 /* Blocks to be unlocked */
843 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
844 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
845 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
846 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
847 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
848 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
849 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
850 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
851 } else if (nfc_is_v1()) {
852 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
853 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
857 /* Unlock Block Command for given address range */
858 writew(0x4, NFC_V1_V2_WRPROT);
861 static void preset_v3(struct mtd_info *mtd)
863 struct nand_chip *chip = mtd->priv;
864 struct mxc_nand_host *host = chip->priv;
865 uint32_t config2, config3;
868 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
869 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
871 /* Unlock the internal RAM Buffer */
872 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
875 /* Blocks to be unlocked */
876 for (i = 0; i < NAND_MAX_CHIPS; i++)
877 writel(0x0 | (0xffff << 16),
878 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
880 writel(0, NFC_V3_IPC);
882 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
883 NFC_V3_CONFIG2_2CMD_PHASES |
884 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
885 NFC_V3_CONFIG2_ST_CMD(0x70) |
886 NFC_V3_CONFIG2_INT_MSK |
887 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
889 if (chip->ecc.mode == NAND_ECC_HW)
890 config2 |= NFC_V3_CONFIG2_ECC_EN;
892 addr_phases = fls(chip->pagemask) >> 3;
894 if (mtd->writesize == 2048) {
895 config2 |= NFC_V3_CONFIG2_PS_2048;
896 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
897 } else if (mtd->writesize == 4096) {
898 config2 |= NFC_V3_CONFIG2_PS_4096;
899 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
901 config2 |= NFC_V3_CONFIG2_PS_512;
902 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
905 if (mtd->writesize) {
906 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
907 host->eccsize = get_eccsize(mtd);
908 if (host->eccsize == 8)
909 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
912 writel(config2, NFC_V3_CONFIG2);
914 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
915 NFC_V3_CONFIG3_NO_SDMA |
916 NFC_V3_CONFIG3_RBB_MODE |
917 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
918 NFC_V3_CONFIG3_ADD_OP(0);
920 if (!(chip->options & NAND_BUSWIDTH_16))
921 config3 |= NFC_V3_CONFIG3_FW8;
923 writel(config3, NFC_V3_CONFIG3);
925 writel(0, NFC_V3_DELAY_LINE);
928 /* Used by the upper layer to write command to NAND Flash for
929 * different operations to be carried out on NAND Flash */
930 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
931 int column, int page_addr)
933 struct nand_chip *nand_chip = mtd->priv;
934 struct mxc_nand_host *host = nand_chip->priv;
936 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
937 command, column, page_addr);
939 /* Reset command state information */
940 host->status_request = false;
942 /* Command pre-processing step */
946 host->send_cmd(host, command, false);
949 case NAND_CMD_STATUS:
951 host->status_request = true;
953 host->send_cmd(host, command, true);
954 mxc_do_addr_cycle(mtd, column, page_addr);
958 case NAND_CMD_READOOB:
959 if (command == NAND_CMD_READ0)
960 host->buf_start = column;
962 host->buf_start = column + mtd->writesize;
964 command = NAND_CMD_READ0; /* only READ0 is valid */
966 host->send_cmd(host, command, false);
967 mxc_do_addr_cycle(mtd, column, page_addr);
969 if (mtd->writesize > 512)
970 host->send_cmd(host, NAND_CMD_READSTART, true);
972 host->send_page(mtd, NFC_OUTPUT);
974 memcpy(host->data_buf, host->main_area0, mtd->writesize);
975 copy_spare(mtd, true);
979 if (column >= mtd->writesize)
980 /* call ourself to read a page */
981 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
983 host->buf_start = column;
985 host->send_cmd(host, command, false);
986 mxc_do_addr_cycle(mtd, column, page_addr);
989 case NAND_CMD_PAGEPROG:
990 memcpy(host->main_area0, host->data_buf, mtd->writesize);
991 copy_spare(mtd, false);
992 host->send_page(mtd, NFC_INPUT);
993 host->send_cmd(host, command, true);
994 mxc_do_addr_cycle(mtd, column, page_addr);
997 case NAND_CMD_READID:
998 host->send_cmd(host, command, true);
999 mxc_do_addr_cycle(mtd, column, page_addr);
1000 host->send_read_id(host);
1001 host->buf_start = column;
1004 case NAND_CMD_ERASE1:
1005 case NAND_CMD_ERASE2:
1006 host->send_cmd(host, command, false);
1007 mxc_do_addr_cycle(mtd, column, page_addr);
1014 * The generic flash bbt decriptors overlap with our ecc
1015 * hardware, so define some i.MX specific ones.
1017 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1018 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1020 static struct nand_bbt_descr bbt_main_descr = {
1021 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1022 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1027 .pattern = bbt_pattern,
1030 static struct nand_bbt_descr bbt_mirror_descr = {
1031 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1032 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1037 .pattern = mirror_pattern,
1040 static int __init mxcnd_probe(struct platform_device *pdev)
1042 struct nand_chip *this;
1043 struct mtd_info *mtd;
1044 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
1045 struct mxc_nand_host *host;
1046 struct resource *res;
1048 struct nand_ecclayout *oob_smallpage, *oob_largepage;
1050 /* Allocate memory for MTD device structure and private data */
1051 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
1052 NAND_MAX_OOBSIZE, GFP_KERNEL);
1056 host->data_buf = (uint8_t *)(host + 1);
1058 host->dev = &pdev->dev;
1059 /* structures must be linked */
1063 mtd->owner = THIS_MODULE;
1064 mtd->dev.parent = &pdev->dev;
1065 mtd->name = DRIVER_NAME;
1067 /* 50 us command delay time */
1068 this->chip_delay = 5;
1071 this->dev_ready = mxc_nand_dev_ready;
1072 this->cmdfunc = mxc_nand_command;
1073 this->select_chip = mxc_nand_select_chip;
1074 this->read_byte = mxc_nand_read_byte;
1075 this->read_word = mxc_nand_read_word;
1076 this->write_buf = mxc_nand_write_buf;
1077 this->read_buf = mxc_nand_read_buf;
1078 this->verify_buf = mxc_nand_verify_buf;
1080 host->clk = clk_get(&pdev->dev, "nfc");
1081 if (IS_ERR(host->clk)) {
1082 err = PTR_ERR(host->clk);
1086 clk_enable(host->clk);
1089 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1095 host->base = ioremap(res->start, resource_size(res));
1101 host->main_area0 = host->base;
1103 if (nfc_is_v1() || nfc_is_v21()) {
1104 host->preset = preset_v1_v2;
1105 host->send_cmd = send_cmd_v1_v2;
1106 host->send_addr = send_addr_v1_v2;
1107 host->send_page = send_page_v1_v2;
1108 host->send_read_id = send_read_id_v1_v2;
1109 host->get_dev_status = get_dev_status_v1_v2;
1110 host->check_int = check_int_v1_v2;
1111 host->irq_control = irq_control_v1_v2;
1113 host->irqpending_quirk = 1;
1117 host->regs = host->base + 0x1e00;
1118 host->spare0 = host->base + 0x1000;
1119 host->spare_len = 64;
1120 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1121 oob_largepage = &nandv2_hw_eccoob_largepage;
1122 this->ecc.bytes = 9;
1123 } else if (nfc_is_v1()) {
1124 host->regs = host->base + 0xe00;
1125 host->spare0 = host->base + 0x800;
1126 host->spare_len = 16;
1127 oob_smallpage = &nandv1_hw_eccoob_smallpage;
1128 oob_largepage = &nandv1_hw_eccoob_largepage;
1129 this->ecc.bytes = 3;
1131 } else if (nfc_is_v3_2()) {
1132 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1137 host->regs_ip = ioremap(res->start, resource_size(res));
1138 if (!host->regs_ip) {
1142 host->regs_axi = host->base + 0x1e00;
1143 host->spare0 = host->base + 0x1000;
1144 host->spare_len = 64;
1145 host->preset = preset_v3;
1146 host->send_cmd = send_cmd_v3;
1147 host->send_addr = send_addr_v3;
1148 host->send_page = send_page_v3;
1149 host->send_read_id = send_read_id_v3;
1150 host->check_int = check_int_v3;
1151 host->get_dev_status = get_dev_status_v3;
1152 host->irq_control = irq_control_v3;
1153 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1154 oob_largepage = &nandv2_hw_eccoob_largepage;
1158 this->ecc.size = 512;
1159 this->ecc.layout = oob_smallpage;
1161 if (pdata->hw_ecc) {
1162 this->ecc.calculate = mxc_nand_calculate_ecc;
1163 this->ecc.hwctl = mxc_nand_enable_hwecc;
1165 this->ecc.correct = mxc_nand_correct_data_v1;
1167 this->ecc.correct = mxc_nand_correct_data_v2_v3;
1168 this->ecc.mode = NAND_ECC_HW;
1170 this->ecc.mode = NAND_ECC_SOFT;
1173 /* NAND bus width determines access funtions used by upper layer */
1174 if (pdata->width == 2)
1175 this->options |= NAND_BUSWIDTH_16;
1177 if (pdata->flash_bbt) {
1178 this->bbt_td = &bbt_main_descr;
1179 this->bbt_md = &bbt_mirror_descr;
1180 /* update flash based bbt */
1181 this->bbt_options |= NAND_BBT_USE_FLASH;
1184 init_completion(&host->op_completion);
1186 host->irq = platform_get_irq(pdev, 0);
1189 * Use host->irq_control here instead of irq_control because we must not
1190 * disable_irq_nosync without having requested the irq
1192 host->irq_control(host, 0);
1194 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
1199 * Now that we "own" the interrupt make sure the interrupt mask bit is
1200 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1203 if (host->irqpending_quirk) {
1204 disable_irq_nosync(host->irq);
1205 host->irq_control(host, 1);
1208 /* first scan to find the device and get the page size */
1209 if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
1214 /* Call preset again, with correct writesize this time */
1217 if (mtd->writesize == 2048)
1218 this->ecc.layout = oob_largepage;
1219 if (nfc_is_v21() && mtd->writesize == 4096)
1220 this->ecc.layout = &nandv2_hw_eccoob_4k;
1222 /* second phase scan */
1223 if (nand_scan_tail(mtd)) {
1228 if (this->ecc.mode == NAND_ECC_HW) {
1230 this->ecc.strength = 1;
1232 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1235 /* Register the partitions */
1236 mtd_device_parse_register(mtd, part_probes, NULL, pdata->parts,
1239 platform_set_drvdata(pdev, host);
1244 free_irq(host->irq, host);
1247 iounmap(host->regs_ip);
1248 iounmap(host->base);
1257 static int __devexit mxcnd_remove(struct platform_device *pdev)
1259 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1263 platform_set_drvdata(pdev, NULL);
1265 nand_release(&host->mtd);
1266 free_irq(host->irq, host);
1268 iounmap(host->regs_ip);
1269 iounmap(host->base);
1275 static struct platform_driver mxcnd_driver = {
1277 .name = DRIVER_NAME,
1278 .owner = THIS_MODULE,
1280 .remove = __devexit_p(mxcnd_remove),
1283 static int __init mxc_nd_init(void)
1285 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1288 static void __exit mxc_nd_cleanup(void)
1290 /* Unregister the device structure */
1291 platform_driver_unregister(&mxcnd_driver);
1294 module_init(mxc_nd_init);
1295 module_exit(mxc_nd_cleanup);
1297 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1298 MODULE_DESCRIPTION("MXC NAND MTD driver");
1299 MODULE_LICENSE("GPL");