1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018
4 * Author: Christophe Kerello <christophe.kerello@st.com>
7 #include <linux/bitfield.h>
9 #include <linux/dmaengine.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/errno.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
14 #include <linux/iopoll.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/mtd/rawnand.h>
18 #include <linux/of_address.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
24 /* Bad block marker length */
25 #define FMC2_BBM_LEN 2
28 #define FMC2_ECC_STEP_SIZE 512
30 /* BCHDSRx registers length */
31 #define FMC2_BCHDSRS_LEN 20
34 #define FMC2_HECCR_LEN 4
36 /* Max requests done for a 8k nand page size */
37 #define FMC2_MAX_SG 16
42 /* Max ECC buffer length */
43 #define FMC2_MAX_ECC_BUF_LEN (FMC2_BCHDSRS_LEN * FMC2_MAX_SG)
45 #define FMC2_TIMEOUT_MS 5000
50 #define FMC2_TSYNC 3000
51 #define FMC2_PCR_TIMING_MASK 0xf
52 #define FMC2_PMEM_PATT_TIMING_MASK 0xff
54 /* FMC2 Controller Registers */
58 #define FMC2_PMEM 0x88
59 #define FMC2_PATT 0x8c
60 #define FMC2_HECCR 0x94
61 #define FMC2_ISR 0x184
62 #define FMC2_ICR 0x188
63 #define FMC2_CSQCR 0x200
64 #define FMC2_CSQCFGR1 0x204
65 #define FMC2_CSQCFGR2 0x208
66 #define FMC2_CSQCFGR3 0x20c
67 #define FMC2_CSQAR1 0x210
68 #define FMC2_CSQAR2 0x214
69 #define FMC2_CSQIER 0x220
70 #define FMC2_CSQISR 0x224
71 #define FMC2_CSQICR 0x228
72 #define FMC2_CSQEMSR 0x230
73 #define FMC2_BCHIER 0x250
74 #define FMC2_BCHISR 0x254
75 #define FMC2_BCHICR 0x258
76 #define FMC2_BCHPBR1 0x260
77 #define FMC2_BCHPBR2 0x264
78 #define FMC2_BCHPBR3 0x268
79 #define FMC2_BCHPBR4 0x26c
80 #define FMC2_BCHDSR0 0x27c
81 #define FMC2_BCHDSR1 0x280
82 #define FMC2_BCHDSR2 0x284
83 #define FMC2_BCHDSR3 0x288
84 #define FMC2_BCHDSR4 0x28c
86 /* Register: FMC2_BCR1 */
87 #define FMC2_BCR1_FMC2EN BIT(31)
89 /* Register: FMC2_PCR */
90 #define FMC2_PCR_PWAITEN BIT(1)
91 #define FMC2_PCR_PBKEN BIT(2)
92 #define FMC2_PCR_PWID GENMASK(5, 4)
93 #define FMC2_PCR_PWID_BUSWIDTH_8 0
94 #define FMC2_PCR_PWID_BUSWIDTH_16 1
95 #define FMC2_PCR_ECCEN BIT(6)
96 #define FMC2_PCR_ECCALG BIT(8)
97 #define FMC2_PCR_TCLR GENMASK(12, 9)
98 #define FMC2_PCR_TCLR_DEFAULT 0xf
99 #define FMC2_PCR_TAR GENMASK(16, 13)
100 #define FMC2_PCR_TAR_DEFAULT 0xf
101 #define FMC2_PCR_ECCSS GENMASK(19, 17)
102 #define FMC2_PCR_ECCSS_512 1
103 #define FMC2_PCR_ECCSS_2048 3
104 #define FMC2_PCR_BCHECC BIT(24)
105 #define FMC2_PCR_WEN BIT(25)
107 /* Register: FMC2_SR */
108 #define FMC2_SR_NWRF BIT(6)
110 /* Register: FMC2_PMEM */
111 #define FMC2_PMEM_MEMSET GENMASK(7, 0)
112 #define FMC2_PMEM_MEMWAIT GENMASK(15, 8)
113 #define FMC2_PMEM_MEMHOLD GENMASK(23, 16)
114 #define FMC2_PMEM_MEMHIZ GENMASK(31, 24)
115 #define FMC2_PMEM_DEFAULT 0x0a0a0a0a
117 /* Register: FMC2_PATT */
118 #define FMC2_PATT_ATTSET GENMASK(7, 0)
119 #define FMC2_PATT_ATTWAIT GENMASK(15, 8)
120 #define FMC2_PATT_ATTHOLD GENMASK(23, 16)
121 #define FMC2_PATT_ATTHIZ GENMASK(31, 24)
122 #define FMC2_PATT_DEFAULT 0x0a0a0a0a
124 /* Register: FMC2_ISR */
125 #define FMC2_ISR_IHLF BIT(1)
127 /* Register: FMC2_ICR */
128 #define FMC2_ICR_CIHLF BIT(1)
130 /* Register: FMC2_CSQCR */
131 #define FMC2_CSQCR_CSQSTART BIT(0)
133 /* Register: FMC2_CSQCFGR1 */
134 #define FMC2_CSQCFGR1_CMD2EN BIT(1)
135 #define FMC2_CSQCFGR1_DMADEN BIT(2)
136 #define FMC2_CSQCFGR1_ACYNBR GENMASK(6, 4)
137 #define FMC2_CSQCFGR1_CMD1 GENMASK(15, 8)
138 #define FMC2_CSQCFGR1_CMD2 GENMASK(23, 16)
139 #define FMC2_CSQCFGR1_CMD1T BIT(24)
140 #define FMC2_CSQCFGR1_CMD2T BIT(25)
142 /* Register: FMC2_CSQCFGR2 */
143 #define FMC2_CSQCFGR2_SQSDTEN BIT(0)
144 #define FMC2_CSQCFGR2_RCMD2EN BIT(1)
145 #define FMC2_CSQCFGR2_DMASEN BIT(2)
146 #define FMC2_CSQCFGR2_RCMD1 GENMASK(15, 8)
147 #define FMC2_CSQCFGR2_RCMD2 GENMASK(23, 16)
148 #define FMC2_CSQCFGR2_RCMD1T BIT(24)
149 #define FMC2_CSQCFGR2_RCMD2T BIT(25)
151 /* Register: FMC2_CSQCFGR3 */
152 #define FMC2_CSQCFGR3_SNBR GENMASK(13, 8)
153 #define FMC2_CSQCFGR3_AC1T BIT(16)
154 #define FMC2_CSQCFGR3_AC2T BIT(17)
155 #define FMC2_CSQCFGR3_AC3T BIT(18)
156 #define FMC2_CSQCFGR3_AC4T BIT(19)
157 #define FMC2_CSQCFGR3_AC5T BIT(20)
158 #define FMC2_CSQCFGR3_SDT BIT(21)
159 #define FMC2_CSQCFGR3_RAC1T BIT(22)
160 #define FMC2_CSQCFGR3_RAC2T BIT(23)
162 /* Register: FMC2_CSQCAR1 */
163 #define FMC2_CSQCAR1_ADDC1 GENMASK(7, 0)
164 #define FMC2_CSQCAR1_ADDC2 GENMASK(15, 8)
165 #define FMC2_CSQCAR1_ADDC3 GENMASK(23, 16)
166 #define FMC2_CSQCAR1_ADDC4 GENMASK(31, 24)
168 /* Register: FMC2_CSQCAR2 */
169 #define FMC2_CSQCAR2_ADDC5 GENMASK(7, 0)
170 #define FMC2_CSQCAR2_NANDCEN GENMASK(11, 10)
171 #define FMC2_CSQCAR2_SAO GENMASK(31, 16)
173 /* Register: FMC2_CSQIER */
174 #define FMC2_CSQIER_TCIE BIT(0)
176 /* Register: FMC2_CSQICR */
177 #define FMC2_CSQICR_CLEAR_IRQ GENMASK(4, 0)
179 /* Register: FMC2_CSQEMSR */
180 #define FMC2_CSQEMSR_SEM GENMASK(15, 0)
182 /* Register: FMC2_BCHIER */
183 #define FMC2_BCHIER_DERIE BIT(1)
184 #define FMC2_BCHIER_EPBRIE BIT(4)
186 /* Register: FMC2_BCHICR */
187 #define FMC2_BCHICR_CLEAR_IRQ GENMASK(4, 0)
189 /* Register: FMC2_BCHDSR0 */
190 #define FMC2_BCHDSR0_DUE BIT(0)
191 #define FMC2_BCHDSR0_DEF BIT(1)
192 #define FMC2_BCHDSR0_DEN GENMASK(7, 4)
194 /* Register: FMC2_BCHDSR1 */
195 #define FMC2_BCHDSR1_EBP1 GENMASK(12, 0)
196 #define FMC2_BCHDSR1_EBP2 GENMASK(28, 16)
198 /* Register: FMC2_BCHDSR2 */
199 #define FMC2_BCHDSR2_EBP3 GENMASK(12, 0)
200 #define FMC2_BCHDSR2_EBP4 GENMASK(28, 16)
202 /* Register: FMC2_BCHDSR3 */
203 #define FMC2_BCHDSR3_EBP5 GENMASK(12, 0)
204 #define FMC2_BCHDSR3_EBP6 GENMASK(28, 16)
206 /* Register: FMC2_BCHDSR4 */
207 #define FMC2_BCHDSR4_EBP7 GENMASK(12, 0)
208 #define FMC2_BCHDSR4_EBP8 GENMASK(28, 16)
210 enum stm32_fmc2_ecc {
216 enum stm32_fmc2_irq_state {
217 FMC2_IRQ_UNKNOWN = 0,
222 struct stm32_fmc2_timings {
233 struct stm32_fmc2_nand {
234 struct nand_chip chip;
235 struct gpio_desc *wp_gpio;
236 struct stm32_fmc2_timings timings;
238 int cs_used[FMC2_MAX_CE];
241 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
243 return container_of(chip, struct stm32_fmc2_nand, chip);
246 struct stm32_fmc2_nfc {
247 struct nand_controller base;
248 struct stm32_fmc2_nand nand;
251 struct regmap *regmap;
252 void __iomem *data_base[FMC2_MAX_CE];
253 void __iomem *cmd_base[FMC2_MAX_CE];
254 void __iomem *addr_base[FMC2_MAX_CE];
255 phys_addr_t io_phys_addr;
256 phys_addr_t data_phys_addr[FMC2_MAX_CE];
260 struct dma_chan *dma_tx_ch;
261 struct dma_chan *dma_rx_ch;
262 struct dma_chan *dma_ecc_ch;
263 struct sg_table dma_data_sg;
264 struct sg_table dma_ecc_sg;
268 struct completion complete;
269 struct completion dma_data_complete;
270 struct completion dma_ecc_complete;
276 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_controller *base)
278 return container_of(base, struct stm32_fmc2_nfc, base);
281 static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip)
283 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
284 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
285 struct stm32_fmc2_timings *timings = &nand->timings;
288 /* Set tclr/tar timings */
289 regmap_update_bits(nfc->regmap, FMC2_PCR,
290 FMC2_PCR_TCLR | FMC2_PCR_TAR,
291 FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) |
292 FIELD_PREP(FMC2_PCR_TAR, timings->tar));
294 /* Set tset/twait/thold/thiz timings in common bank */
295 pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
296 pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
297 pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
298 pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
299 regmap_write(nfc->regmap, FMC2_PMEM, pmem);
301 /* Set tset/twait/thold/thiz timings in attribut bank */
302 patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
303 patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
304 patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
305 patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
306 regmap_write(nfc->regmap, FMC2_PATT, patt);
309 static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
311 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
312 u32 pcr = 0, pcr_mask;
314 /* Configure ECC algorithm (default configuration is Hamming) */
315 pcr_mask = FMC2_PCR_ECCALG;
316 pcr_mask |= FMC2_PCR_BCHECC;
317 if (chip->ecc.strength == FMC2_ECC_BCH8) {
318 pcr |= FMC2_PCR_ECCALG;
319 pcr |= FMC2_PCR_BCHECC;
320 } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
321 pcr |= FMC2_PCR_ECCALG;
325 pcr_mask |= FMC2_PCR_PWID;
326 if (chip->options & NAND_BUSWIDTH_16)
327 pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
329 /* Set ECC sector size */
330 pcr_mask |= FMC2_PCR_ECCSS;
331 pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
333 regmap_update_bits(nfc->regmap, FMC2_PCR, pcr_mask, pcr);
336 static int stm32_fmc2_nfc_select_chip(struct nand_chip *chip, int chipnr)
338 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
339 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
340 struct dma_slave_config dma_cfg;
343 if (nand->cs_used[chipnr] == nfc->cs_sel)
346 nfc->cs_sel = nand->cs_used[chipnr];
347 stm32_fmc2_nfc_setup(chip);
348 stm32_fmc2_nfc_timings_init(chip);
350 if (nfc->dma_tx_ch && nfc->dma_rx_ch) {
351 memset(&dma_cfg, 0, sizeof(dma_cfg));
352 dma_cfg.src_addr = nfc->data_phys_addr[nfc->cs_sel];
353 dma_cfg.dst_addr = nfc->data_phys_addr[nfc->cs_sel];
354 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
355 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
356 dma_cfg.src_maxburst = 32;
357 dma_cfg.dst_maxburst = 32;
359 ret = dmaengine_slave_config(nfc->dma_tx_ch, &dma_cfg);
361 dev_err(nfc->dev, "tx DMA engine slave config failed\n");
365 ret = dmaengine_slave_config(nfc->dma_rx_ch, &dma_cfg);
367 dev_err(nfc->dev, "rx DMA engine slave config failed\n");
372 if (nfc->dma_ecc_ch) {
374 * Hamming: we read HECCR register
375 * BCH4/BCH8: we read BCHDSRSx registers
377 memset(&dma_cfg, 0, sizeof(dma_cfg));
378 dma_cfg.src_addr = nfc->io_phys_addr;
379 dma_cfg.src_addr += chip->ecc.strength == FMC2_ECC_HAM ?
380 FMC2_HECCR : FMC2_BCHDSR0;
381 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
383 ret = dmaengine_slave_config(nfc->dma_ecc_ch, &dma_cfg);
385 dev_err(nfc->dev, "ECC DMA engine slave config failed\n");
389 /* Calculate ECC length needed for one sector */
390 nfc->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ?
391 FMC2_HECCR_LEN : FMC2_BCHDSRS_LEN;
397 static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc, bool set)
401 pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) :
402 FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8);
404 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_PWID, pcr);
407 static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
409 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_ECCEN,
410 enable ? FMC2_PCR_ECCEN : 0);
413 static void stm32_fmc2_nfc_enable_seq_irq(struct stm32_fmc2_nfc *nfc)
415 nfc->irq_state = FMC2_IRQ_SEQ;
417 regmap_update_bits(nfc->regmap, FMC2_CSQIER,
418 FMC2_CSQIER_TCIE, FMC2_CSQIER_TCIE);
421 static void stm32_fmc2_nfc_disable_seq_irq(struct stm32_fmc2_nfc *nfc)
423 regmap_update_bits(nfc->regmap, FMC2_CSQIER, FMC2_CSQIER_TCIE, 0);
425 nfc->irq_state = FMC2_IRQ_UNKNOWN;
428 static void stm32_fmc2_nfc_clear_seq_irq(struct stm32_fmc2_nfc *nfc)
430 regmap_write(nfc->regmap, FMC2_CSQICR, FMC2_CSQICR_CLEAR_IRQ);
433 static void stm32_fmc2_nfc_enable_bch_irq(struct stm32_fmc2_nfc *nfc, int mode)
435 nfc->irq_state = FMC2_IRQ_BCH;
437 if (mode == NAND_ECC_WRITE)
438 regmap_update_bits(nfc->regmap, FMC2_BCHIER,
439 FMC2_BCHIER_EPBRIE, FMC2_BCHIER_EPBRIE);
441 regmap_update_bits(nfc->regmap, FMC2_BCHIER,
442 FMC2_BCHIER_DERIE, FMC2_BCHIER_DERIE);
445 static void stm32_fmc2_nfc_disable_bch_irq(struct stm32_fmc2_nfc *nfc)
447 regmap_update_bits(nfc->regmap, FMC2_BCHIER,
448 FMC2_BCHIER_DERIE | FMC2_BCHIER_EPBRIE, 0);
450 nfc->irq_state = FMC2_IRQ_UNKNOWN;
453 static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
455 regmap_write(nfc->regmap, FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ);
459 * Enable ECC logic and reset syndrome/parity bits previously calculated
460 * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
462 static void stm32_fmc2_nfc_hwctl(struct nand_chip *chip, int mode)
464 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
466 stm32_fmc2_nfc_set_ecc(nfc, false);
468 if (chip->ecc.strength != FMC2_ECC_HAM) {
469 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
470 mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0);
472 reinit_completion(&nfc->complete);
473 stm32_fmc2_nfc_clear_bch_irq(nfc);
474 stm32_fmc2_nfc_enable_bch_irq(nfc, mode);
477 stm32_fmc2_nfc_set_ecc(nfc, true);
481 * ECC Hamming calculation
482 * ECC is 3 bytes for 512 bytes of data (supports error correction up to
485 static void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc)
488 ecc[1] = ecc_sta >> 8;
489 ecc[2] = ecc_sta >> 16;
492 static int stm32_fmc2_nfc_ham_calculate(struct nand_chip *chip, const u8 *data,
495 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
499 ret = regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
500 sr & FMC2_SR_NWRF, 1,
501 1000 * FMC2_TIMEOUT_MS);
503 dev_err(nfc->dev, "ham timeout\n");
507 regmap_read(nfc->regmap, FMC2_HECCR, &heccr);
508 stm32_fmc2_nfc_ham_set_ecc(heccr, ecc);
509 stm32_fmc2_nfc_set_ecc(nfc, false);
514 static int stm32_fmc2_nfc_ham_correct(struct nand_chip *chip, u8 *dat,
515 u8 *read_ecc, u8 *calc_ecc)
517 u8 bit_position = 0, b0, b1, b2;
518 u32 byte_addr = 0, b;
521 /* Indicate which bit and byte is faulty (if any) */
522 b0 = read_ecc[0] ^ calc_ecc[0];
523 b1 = read_ecc[1] ^ calc_ecc[1];
524 b2 = read_ecc[2] ^ calc_ecc[2];
525 b = b0 | (b1 << 8) | (b2 << 16);
531 /* Calculate bit position */
532 for (i = 0; i < 3; i++) {
535 bit_position += shifting;
546 /* Calculate byte position */
548 for (i = 0; i < 9; i++) {
551 byte_addr += shifting;
563 dat[byte_addr] ^= (1 << bit_position);
569 * ECC BCH calculation and correction
570 * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
571 * max of 4-bit/8-bit)
573 static int stm32_fmc2_nfc_bch_calculate(struct nand_chip *chip, const u8 *data,
576 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
579 /* Wait until the BCH code is ready */
580 if (!wait_for_completion_timeout(&nfc->complete,
581 msecs_to_jiffies(FMC2_TIMEOUT_MS))) {
582 dev_err(nfc->dev, "bch timeout\n");
583 stm32_fmc2_nfc_disable_bch_irq(nfc);
587 /* Read parity bits */
588 regmap_read(nfc->regmap, FMC2_BCHPBR1, &bchpbr);
590 ecc[1] = bchpbr >> 8;
591 ecc[2] = bchpbr >> 16;
592 ecc[3] = bchpbr >> 24;
594 regmap_read(nfc->regmap, FMC2_BCHPBR2, &bchpbr);
596 ecc[5] = bchpbr >> 8;
597 ecc[6] = bchpbr >> 16;
599 if (chip->ecc.strength == FMC2_ECC_BCH8) {
600 ecc[7] = bchpbr >> 24;
602 regmap_read(nfc->regmap, FMC2_BCHPBR3, &bchpbr);
604 ecc[9] = bchpbr >> 8;
605 ecc[10] = bchpbr >> 16;
606 ecc[11] = bchpbr >> 24;
608 regmap_read(nfc->regmap, FMC2_BCHPBR4, &bchpbr);
612 stm32_fmc2_nfc_set_ecc(nfc, false);
617 static int stm32_fmc2_nfc_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta)
619 u32 bchdsr0 = ecc_sta[0];
620 u32 bchdsr1 = ecc_sta[1];
621 u32 bchdsr2 = ecc_sta[2];
622 u32 bchdsr3 = ecc_sta[3];
623 u32 bchdsr4 = ecc_sta[4];
626 unsigned int nb_errs = 0;
628 /* No errors found */
629 if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
632 /* Too many errors detected */
633 if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
636 pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1);
637 pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1);
638 pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2);
639 pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2);
640 pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3);
641 pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3);
642 pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4);
643 pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4);
645 den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0);
646 for (i = 0; i < den; i++) {
647 if (pos[i] < eccsize * 8) {
648 change_bit(pos[i], (unsigned long *)dat);
656 static int stm32_fmc2_nfc_bch_correct(struct nand_chip *chip, u8 *dat,
657 u8 *read_ecc, u8 *calc_ecc)
659 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
662 /* Wait until the decoding error is ready */
663 if (!wait_for_completion_timeout(&nfc->complete,
664 msecs_to_jiffies(FMC2_TIMEOUT_MS))) {
665 dev_err(nfc->dev, "bch timeout\n");
666 stm32_fmc2_nfc_disable_bch_irq(nfc);
670 regmap_bulk_read(nfc->regmap, FMC2_BCHDSR0, ecc_sta, 5);
672 stm32_fmc2_nfc_set_ecc(nfc, false);
674 return stm32_fmc2_nfc_bch_decode(chip->ecc.size, dat, ecc_sta);
677 static int stm32_fmc2_nfc_read_page(struct nand_chip *chip, u8 *buf,
678 int oob_required, int page)
680 struct mtd_info *mtd = nand_to_mtd(chip);
681 int ret, i, s, stat, eccsize = chip->ecc.size;
682 int eccbytes = chip->ecc.bytes;
683 int eccsteps = chip->ecc.steps;
684 int eccstrength = chip->ecc.strength;
686 u8 *ecc_calc = chip->ecc.calc_buf;
687 u8 *ecc_code = chip->ecc.code_buf;
688 unsigned int max_bitflips = 0;
690 ret = nand_read_page_op(chip, page, 0, NULL, 0);
694 for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
695 s++, i += eccbytes, p += eccsize) {
696 chip->ecc.hwctl(chip, NAND_ECC_READ);
698 /* Read the nand page sector (512 bytes) */
699 ret = nand_change_read_column_op(chip, s * eccsize, p,
704 /* Read the corresponding ECC bytes */
705 ret = nand_change_read_column_op(chip, i, ecc_code,
710 /* Correct the data */
711 stat = chip->ecc.correct(chip, p, ecc_code, ecc_calc);
712 if (stat == -EBADMSG)
713 /* Check for empty pages with bitflips */
714 stat = nand_check_erased_ecc_chunk(p, eccsize,
720 mtd->ecc_stats.failed++;
722 mtd->ecc_stats.corrected += stat;
723 max_bitflips = max_t(unsigned int, max_bitflips, stat);
729 ret = nand_change_read_column_op(chip, mtd->writesize,
730 chip->oob_poi, mtd->oobsize,
739 /* Sequencer read/write configuration */
740 static void stm32_fmc2_nfc_rw_page_init(struct nand_chip *chip, int page,
741 int raw, bool write_data)
743 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
744 struct mtd_info *mtd = nand_to_mtd(chip);
745 u32 ecc_offset = mtd->writesize + FMC2_BBM_LEN;
747 * cfg[0] => csqcfgr1, cfg[1] => csqcfgr2, cfg[2] => csqcfgr3
748 * cfg[3] => csqar1, cfg[4] => csqar2
752 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
753 write_data ? FMC2_PCR_WEN : 0);
756 * - Set Program Page/Page Read command
757 * - Enable DMA request data
760 cfg[0] = FMC2_CSQCFGR1_DMADEN | FMC2_CSQCFGR1_CMD1T;
762 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_SEQIN);
764 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_READ0) |
765 FMC2_CSQCFGR1_CMD2EN |
766 FIELD_PREP(FMC2_CSQCFGR1_CMD2, NAND_CMD_READSTART) |
770 * - Set Random Data Input/Random Data Read command
771 * - Enable the sequencer to access the Spare data area
772 * - Enable DMA request status decoding for read
776 cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDIN);
778 cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDOUT) |
779 FMC2_CSQCFGR2_RCMD2EN |
780 FIELD_PREP(FMC2_CSQCFGR2_RCMD2, NAND_CMD_RNDOUTSTART) |
781 FMC2_CSQCFGR2_RCMD1T |
782 FMC2_CSQCFGR2_RCMD2T;
784 cfg[1] |= write_data ? 0 : FMC2_CSQCFGR2_DMASEN;
785 cfg[1] |= FMC2_CSQCFGR2_SQSDTEN;
789 * - Set the number of sectors to be written
792 cfg[2] = FIELD_PREP(FMC2_CSQCFGR3_SNBR, chip->ecc.steps - 1);
794 cfg[2] |= FMC2_CSQCFGR3_RAC2T;
795 if (chip->options & NAND_ROW_ADDR_3)
796 cfg[2] |= FMC2_CSQCFGR3_AC5T;
798 cfg[2] |= FMC2_CSQCFGR3_AC4T;
802 * Set the fourth first address cycles
803 * Byte 1 and byte 2 => column, we start at 0x0
804 * Byte 3 and byte 4 => page
806 cfg[3] = FIELD_PREP(FMC2_CSQCAR1_ADDC3, page);
807 cfg[3] |= FIELD_PREP(FMC2_CSQCAR1_ADDC4, page >> 8);
810 * - Set chip enable number
811 * - Set ECC byte offset in the spare area
812 * - Calculate the number of address cycles to be issued
813 * - Set byte 5 of address cycle if needed
815 cfg[4] = FIELD_PREP(FMC2_CSQCAR2_NANDCEN, nfc->cs_sel);
816 if (chip->options & NAND_BUSWIDTH_16)
817 cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset >> 1);
819 cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset);
820 if (chip->options & NAND_ROW_ADDR_3) {
821 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 5);
822 cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_ADDC5, page >> 16);
824 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 4);
827 regmap_bulk_write(nfc->regmap, FMC2_CSQCFGR1, cfg, 5);
830 static void stm32_fmc2_nfc_dma_callback(void *arg)
832 complete((struct completion *)arg);
835 /* Read/write data from/to a page */
836 static int stm32_fmc2_nfc_xfer(struct nand_chip *chip, const u8 *buf,
837 int raw, bool write_data)
839 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
840 struct dma_async_tx_descriptor *desc_data, *desc_ecc;
841 struct scatterlist *sg;
842 struct dma_chan *dma_ch = nfc->dma_rx_ch;
843 enum dma_data_direction dma_data_dir = DMA_FROM_DEVICE;
844 enum dma_transfer_direction dma_transfer_dir = DMA_DEV_TO_MEM;
845 int eccsteps = chip->ecc.steps;
846 int eccsize = chip->ecc.size;
847 unsigned long timeout = msecs_to_jiffies(FMC2_TIMEOUT_MS);
851 /* Configure DMA data */
853 dma_data_dir = DMA_TO_DEVICE;
854 dma_transfer_dir = DMA_MEM_TO_DEV;
855 dma_ch = nfc->dma_tx_ch;
858 for_each_sg(nfc->dma_data_sg.sgl, sg, eccsteps, s) {
859 sg_set_buf(sg, p, eccsize);
863 ret = dma_map_sg(nfc->dev, nfc->dma_data_sg.sgl,
864 eccsteps, dma_data_dir);
868 desc_data = dmaengine_prep_slave_sg(dma_ch, nfc->dma_data_sg.sgl,
869 eccsteps, dma_transfer_dir,
876 reinit_completion(&nfc->dma_data_complete);
877 reinit_completion(&nfc->complete);
878 desc_data->callback = stm32_fmc2_nfc_dma_callback;
879 desc_data->callback_param = &nfc->dma_data_complete;
880 ret = dma_submit_error(dmaengine_submit(desc_data));
884 dma_async_issue_pending(dma_ch);
886 if (!write_data && !raw) {
887 /* Configure DMA ECC status */
889 for_each_sg(nfc->dma_ecc_sg.sgl, sg, eccsteps, s) {
890 sg_set_buf(sg, p, nfc->dma_ecc_len);
891 p += nfc->dma_ecc_len;
894 ret = dma_map_sg(nfc->dev, nfc->dma_ecc_sg.sgl,
895 eccsteps, dma_data_dir);
901 desc_ecc = dmaengine_prep_slave_sg(nfc->dma_ecc_ch,
903 eccsteps, dma_transfer_dir,
910 reinit_completion(&nfc->dma_ecc_complete);
911 desc_ecc->callback = stm32_fmc2_nfc_dma_callback;
912 desc_ecc->callback_param = &nfc->dma_ecc_complete;
913 ret = dma_submit_error(dmaengine_submit(desc_ecc));
917 dma_async_issue_pending(nfc->dma_ecc_ch);
920 stm32_fmc2_nfc_clear_seq_irq(nfc);
921 stm32_fmc2_nfc_enable_seq_irq(nfc);
923 /* Start the transfer */
924 regmap_update_bits(nfc->regmap, FMC2_CSQCR,
925 FMC2_CSQCR_CSQSTART, FMC2_CSQCR_CSQSTART);
927 /* Wait end of sequencer transfer */
928 if (!wait_for_completion_timeout(&nfc->complete, timeout)) {
929 dev_err(nfc->dev, "seq timeout\n");
930 stm32_fmc2_nfc_disable_seq_irq(nfc);
931 dmaengine_terminate_all(dma_ch);
932 if (!write_data && !raw)
933 dmaengine_terminate_all(nfc->dma_ecc_ch);
938 /* Wait DMA data transfer completion */
939 if (!wait_for_completion_timeout(&nfc->dma_data_complete, timeout)) {
940 dev_err(nfc->dev, "data DMA timeout\n");
941 dmaengine_terminate_all(dma_ch);
945 /* Wait DMA ECC transfer completion */
946 if (!write_data && !raw) {
947 if (!wait_for_completion_timeout(&nfc->dma_ecc_complete,
949 dev_err(nfc->dev, "ECC DMA timeout\n");
950 dmaengine_terminate_all(nfc->dma_ecc_ch);
956 if (!write_data && !raw)
957 dma_unmap_sg(nfc->dev, nfc->dma_ecc_sg.sgl,
958 eccsteps, dma_data_dir);
961 dma_unmap_sg(nfc->dev, nfc->dma_data_sg.sgl, eccsteps, dma_data_dir);
966 static int stm32_fmc2_nfc_seq_write(struct nand_chip *chip, const u8 *buf,
967 int oob_required, int page, int raw)
969 struct mtd_info *mtd = nand_to_mtd(chip);
972 /* Configure the sequencer */
973 stm32_fmc2_nfc_rw_page_init(chip, page, raw, true);
976 ret = stm32_fmc2_nfc_xfer(chip, buf, raw, true);
982 ret = nand_change_write_column_op(chip, mtd->writesize,
983 chip->oob_poi, mtd->oobsize,
989 return nand_prog_page_end_op(chip);
992 static int stm32_fmc2_nfc_seq_write_page(struct nand_chip *chip, const u8 *buf,
993 int oob_required, int page)
997 ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1001 return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, false);
1004 static int stm32_fmc2_nfc_seq_write_page_raw(struct nand_chip *chip,
1005 const u8 *buf, int oob_required,
1010 ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1014 return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, true);
1017 /* Get a status indicating which sectors have errors */
1018 static u16 stm32_fmc2_nfc_get_mapping_status(struct stm32_fmc2_nfc *nfc)
1022 regmap_read(nfc->regmap, FMC2_CSQEMSR, &csqemsr);
1024 return FIELD_GET(FMC2_CSQEMSR_SEM, csqemsr);
1027 static int stm32_fmc2_nfc_seq_correct(struct nand_chip *chip, u8 *dat,
1028 u8 *read_ecc, u8 *calc_ecc)
1030 struct mtd_info *mtd = nand_to_mtd(chip);
1031 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1032 int eccbytes = chip->ecc.bytes;
1033 int eccsteps = chip->ecc.steps;
1034 int eccstrength = chip->ecc.strength;
1035 int i, s, eccsize = chip->ecc.size;
1036 u32 *ecc_sta = (u32 *)nfc->ecc_buf;
1037 u16 sta_map = stm32_fmc2_nfc_get_mapping_status(nfc);
1038 unsigned int max_bitflips = 0;
1040 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, dat += eccsize) {
1043 if (eccstrength == FMC2_ECC_HAM) {
1044 /* Ecc_sta = FMC2_HECCR */
1045 if (sta_map & BIT(s)) {
1046 stm32_fmc2_nfc_ham_set_ecc(*ecc_sta,
1048 stat = stm32_fmc2_nfc_ham_correct(chip, dat,
1055 * Ecc_sta[0] = FMC2_BCHDSR0
1056 * Ecc_sta[1] = FMC2_BCHDSR1
1057 * Ecc_sta[2] = FMC2_BCHDSR2
1058 * Ecc_sta[3] = FMC2_BCHDSR3
1059 * Ecc_sta[4] = FMC2_BCHDSR4
1061 if (sta_map & BIT(s))
1062 stat = stm32_fmc2_nfc_bch_decode(eccsize, dat,
1067 if (stat == -EBADMSG)
1068 /* Check for empty pages with bitflips */
1069 stat = nand_check_erased_ecc_chunk(dat, eccsize,
1076 mtd->ecc_stats.failed++;
1078 mtd->ecc_stats.corrected += stat;
1079 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1083 return max_bitflips;
1086 static int stm32_fmc2_nfc_seq_read_page(struct nand_chip *chip, u8 *buf,
1087 int oob_required, int page)
1089 struct mtd_info *mtd = nand_to_mtd(chip);
1090 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1091 u8 *ecc_calc = chip->ecc.calc_buf;
1092 u8 *ecc_code = chip->ecc.code_buf;
1096 ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1100 /* Configure the sequencer */
1101 stm32_fmc2_nfc_rw_page_init(chip, page, 0, false);
1104 ret = stm32_fmc2_nfc_xfer(chip, buf, 0, false);
1108 sta_map = stm32_fmc2_nfc_get_mapping_status(nfc);
1110 /* Check if errors happen */
1111 if (likely(!sta_map)) {
1113 return nand_change_read_column_op(chip, mtd->writesize,
1115 mtd->oobsize, false);
1121 ret = nand_change_read_column_op(chip, mtd->writesize,
1122 chip->oob_poi, mtd->oobsize, false);
1126 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1132 return chip->ecc.correct(chip, buf, ecc_code, ecc_calc);
1135 static int stm32_fmc2_nfc_seq_read_page_raw(struct nand_chip *chip, u8 *buf,
1136 int oob_required, int page)
1138 struct mtd_info *mtd = nand_to_mtd(chip);
1141 ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1145 /* Configure the sequencer */
1146 stm32_fmc2_nfc_rw_page_init(chip, page, 1, false);
1149 ret = stm32_fmc2_nfc_xfer(chip, buf, 1, false);
1155 return nand_change_read_column_op(chip, mtd->writesize,
1156 chip->oob_poi, mtd->oobsize,
1162 static irqreturn_t stm32_fmc2_nfc_irq(int irq, void *dev_id)
1164 struct stm32_fmc2_nfc *nfc = (struct stm32_fmc2_nfc *)dev_id;
1166 if (nfc->irq_state == FMC2_IRQ_SEQ)
1167 /* Sequencer is used */
1168 stm32_fmc2_nfc_disable_seq_irq(nfc);
1169 else if (nfc->irq_state == FMC2_IRQ_BCH)
1171 stm32_fmc2_nfc_disable_bch_irq(nfc);
1173 complete(&nfc->complete);
1178 static void stm32_fmc2_nfc_read_data(struct nand_chip *chip, void *buf,
1179 unsigned int len, bool force_8bit)
1181 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1182 void __iomem *io_addr_r = nfc->data_base[nfc->cs_sel];
1184 if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1185 /* Reconfigure bus width to 8-bit */
1186 stm32_fmc2_nfc_set_buswidth_16(nfc, false);
1188 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
1189 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
1190 *(u8 *)buf = readb_relaxed(io_addr_r);
1195 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
1196 len >= sizeof(u16)) {
1197 *(u16 *)buf = readw_relaxed(io_addr_r);
1203 /* Buf is aligned */
1204 while (len >= sizeof(u32)) {
1205 *(u32 *)buf = readl_relaxed(io_addr_r);
1210 /* Read remaining bytes */
1211 if (len >= sizeof(u16)) {
1212 *(u16 *)buf = readw_relaxed(io_addr_r);
1218 *(u8 *)buf = readb_relaxed(io_addr_r);
1220 if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1221 /* Reconfigure bus width to 16-bit */
1222 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1225 static void stm32_fmc2_nfc_write_data(struct nand_chip *chip, const void *buf,
1226 unsigned int len, bool force_8bit)
1228 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1229 void __iomem *io_addr_w = nfc->data_base[nfc->cs_sel];
1231 if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1232 /* Reconfigure bus width to 8-bit */
1233 stm32_fmc2_nfc_set_buswidth_16(nfc, false);
1235 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
1236 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
1237 writeb_relaxed(*(u8 *)buf, io_addr_w);
1242 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
1243 len >= sizeof(u16)) {
1244 writew_relaxed(*(u16 *)buf, io_addr_w);
1250 /* Buf is aligned */
1251 while (len >= sizeof(u32)) {
1252 writel_relaxed(*(u32 *)buf, io_addr_w);
1257 /* Write remaining bytes */
1258 if (len >= sizeof(u16)) {
1259 writew_relaxed(*(u16 *)buf, io_addr_w);
1265 writeb_relaxed(*(u8 *)buf, io_addr_w);
1267 if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1268 /* Reconfigure bus width to 16-bit */
1269 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1272 static int stm32_fmc2_nfc_waitrdy(struct nand_chip *chip,
1273 unsigned long timeout_ms)
1275 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1276 const struct nand_sdr_timings *timings;
1279 /* Check if there is no pending requests to the NAND flash */
1280 if (regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
1281 sr & FMC2_SR_NWRF, 1,
1282 1000 * FMC2_TIMEOUT_MS))
1283 dev_warn(nfc->dev, "Waitrdy timeout\n");
1285 /* Wait tWB before R/B# signal is low */
1286 timings = nand_get_sdr_timings(nand_get_interface_config(chip));
1287 ndelay(PSEC_TO_NSEC(timings->tWB_max));
1289 /* R/B# signal is low, clear high level flag */
1290 regmap_write(nfc->regmap, FMC2_ICR, FMC2_ICR_CIHLF);
1292 /* Wait R/B# signal is high */
1293 return regmap_read_poll_timeout(nfc->regmap, FMC2_ISR, isr,
1294 isr & FMC2_ISR_IHLF, 5,
1295 1000 * FMC2_TIMEOUT_MS);
1298 static int stm32_fmc2_nfc_exec_op(struct nand_chip *chip,
1299 const struct nand_operation *op,
1302 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1303 const struct nand_op_instr *instr = NULL;
1304 unsigned int op_id, i, timeout;
1310 ret = stm32_fmc2_nfc_select_chip(chip, op->cs);
1314 for (op_id = 0; op_id < op->ninstrs; op_id++) {
1315 instr = &op->instrs[op_id];
1317 switch (instr->type) {
1318 case NAND_OP_CMD_INSTR:
1319 writeb_relaxed(instr->ctx.cmd.opcode,
1320 nfc->cmd_base[nfc->cs_sel]);
1323 case NAND_OP_ADDR_INSTR:
1324 for (i = 0; i < instr->ctx.addr.naddrs; i++)
1325 writeb_relaxed(instr->ctx.addr.addrs[i],
1326 nfc->addr_base[nfc->cs_sel]);
1329 case NAND_OP_DATA_IN_INSTR:
1330 stm32_fmc2_nfc_read_data(chip, instr->ctx.data.buf.in,
1331 instr->ctx.data.len,
1332 instr->ctx.data.force_8bit);
1335 case NAND_OP_DATA_OUT_INSTR:
1336 stm32_fmc2_nfc_write_data(chip, instr->ctx.data.buf.out,
1337 instr->ctx.data.len,
1338 instr->ctx.data.force_8bit);
1341 case NAND_OP_WAITRDY_INSTR:
1342 timeout = instr->ctx.waitrdy.timeout_ms;
1343 ret = stm32_fmc2_nfc_waitrdy(chip, timeout);
1351 static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc)
1355 regmap_read(nfc->regmap, FMC2_PCR, &pcr);
1357 /* Set CS used to undefined */
1360 /* Enable wait feature and nand flash memory bank */
1361 pcr |= FMC2_PCR_PWAITEN;
1362 pcr |= FMC2_PCR_PBKEN;
1364 /* Set buswidth to 8 bits mode for identification */
1365 pcr &= ~FMC2_PCR_PWID;
1367 /* ECC logic is disabled */
1368 pcr &= ~FMC2_PCR_ECCEN;
1371 pcr &= ~FMC2_PCR_ECCALG;
1372 pcr &= ~FMC2_PCR_BCHECC;
1373 pcr &= ~FMC2_PCR_WEN;
1375 /* Set default ECC sector size */
1376 pcr &= ~FMC2_PCR_ECCSS;
1377 pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048);
1379 /* Set default tclr/tar timings */
1380 pcr &= ~FMC2_PCR_TCLR;
1381 pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT);
1382 pcr &= ~FMC2_PCR_TAR;
1383 pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
1385 /* Enable FMC2 controller */
1386 if (nfc->dev == nfc->cdev)
1387 regmap_update_bits(nfc->regmap, FMC2_BCR1,
1388 FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
1390 regmap_write(nfc->regmap, FMC2_PCR, pcr);
1391 regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT);
1392 regmap_write(nfc->regmap, FMC2_PATT, FMC2_PATT_DEFAULT);
1395 static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
1396 const struct nand_sdr_timings *sdrt)
1398 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1399 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
1400 struct stm32_fmc2_timings *tims = &nand->timings;
1401 unsigned long hclk = clk_get_rate(nfc->clk);
1402 unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
1403 unsigned long timing, tar, tclr, thiz, twait;
1404 unsigned long tset_mem, tset_att, thold_mem, thold_att;
1406 tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
1407 timing = DIV_ROUND_UP(tar, hclkp) - 1;
1408 tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
1410 tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
1411 timing = DIV_ROUND_UP(tclr, hclkp) - 1;
1412 tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
1414 tims->thiz = FMC2_THIZ;
1415 thiz = (tims->thiz + 1) * hclkp;
1420 * tWAIT > tREA + tIO
1422 twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
1423 twait = max_t(unsigned long, twait, sdrt->tWP_min);
1424 twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
1425 timing = DIV_ROUND_UP(twait, hclkp);
1426 tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1429 * tSETUP_MEM > tCS - tWAIT
1430 * tSETUP_MEM > tALS - tWAIT
1431 * tSETUP_MEM > tDS - (tWAIT - tHIZ)
1434 if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
1435 tset_mem = sdrt->tCS_min - twait;
1436 if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
1437 tset_mem = sdrt->tALS_min - twait;
1438 if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
1439 (tset_mem < sdrt->tDS_min - (twait - thiz)))
1440 tset_mem = sdrt->tDS_min - (twait - thiz);
1441 timing = DIV_ROUND_UP(tset_mem, hclkp);
1442 tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1446 * tHOLD_MEM > tREH - tSETUP_MEM
1447 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
1449 thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
1450 if (sdrt->tREH_min > tset_mem &&
1451 (thold_mem < sdrt->tREH_min - tset_mem))
1452 thold_mem = sdrt->tREH_min - tset_mem;
1453 if ((sdrt->tRC_min > tset_mem + twait) &&
1454 (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
1455 thold_mem = sdrt->tRC_min - (tset_mem + twait);
1456 if ((sdrt->tWC_min > tset_mem + twait) &&
1457 (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
1458 thold_mem = sdrt->tWC_min - (tset_mem + twait);
1459 timing = DIV_ROUND_UP(thold_mem, hclkp);
1460 tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1463 * tSETUP_ATT > tCS - tWAIT
1464 * tSETUP_ATT > tCLS - tWAIT
1465 * tSETUP_ATT > tALS - tWAIT
1466 * tSETUP_ATT > tRHW - tHOLD_MEM
1467 * tSETUP_ATT > tDS - (tWAIT - tHIZ)
1470 if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
1471 tset_att = sdrt->tCS_min - twait;
1472 if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
1473 tset_att = sdrt->tCLS_min - twait;
1474 if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
1475 tset_att = sdrt->tALS_min - twait;
1476 if (sdrt->tRHW_min > thold_mem &&
1477 (tset_att < sdrt->tRHW_min - thold_mem))
1478 tset_att = sdrt->tRHW_min - thold_mem;
1479 if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
1480 (tset_att < sdrt->tDS_min - (twait - thiz)))
1481 tset_att = sdrt->tDS_min - (twait - thiz);
1482 timing = DIV_ROUND_UP(tset_att, hclkp);
1483 tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1491 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
1492 * tHOLD_ATT > tADL - tSETUP_MEM
1493 * tHOLD_ATT > tWH - tSETUP_MEM
1494 * tHOLD_ATT > tWHR - tSETUP_MEM
1495 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
1496 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
1498 thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
1499 thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
1500 thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
1501 thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
1502 thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
1503 if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
1504 (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
1505 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
1506 if (sdrt->tADL_min > tset_mem &&
1507 (thold_att < sdrt->tADL_min - tset_mem))
1508 thold_att = sdrt->tADL_min - tset_mem;
1509 if (sdrt->tWH_min > tset_mem &&
1510 (thold_att < sdrt->tWH_min - tset_mem))
1511 thold_att = sdrt->tWH_min - tset_mem;
1512 if (sdrt->tWHR_min > tset_mem &&
1513 (thold_att < sdrt->tWHR_min - tset_mem))
1514 thold_att = sdrt->tWHR_min - tset_mem;
1515 if ((sdrt->tRC_min > tset_att + twait) &&
1516 (thold_att < sdrt->tRC_min - (tset_att + twait)))
1517 thold_att = sdrt->tRC_min - (tset_att + twait);
1518 if ((sdrt->tWC_min > tset_att + twait) &&
1519 (thold_att < sdrt->tWC_min - (tset_att + twait)))
1520 thold_att = sdrt->tWC_min - (tset_att + twait);
1521 timing = DIV_ROUND_UP(thold_att, hclkp);
1522 tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1525 static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr,
1526 const struct nand_interface_config *conf)
1528 const struct nand_sdr_timings *sdrt;
1530 sdrt = nand_get_sdr_timings(conf);
1532 return PTR_ERR(sdrt);
1534 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
1537 stm32_fmc2_nfc_calc_timings(chip, sdrt);
1538 stm32_fmc2_nfc_timings_init(chip);
1543 static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc)
1547 nfc->dma_tx_ch = dma_request_chan(nfc->dev, "tx");
1548 if (IS_ERR(nfc->dma_tx_ch)) {
1549 ret = PTR_ERR(nfc->dma_tx_ch);
1550 if (ret != -ENODEV && ret != -EPROBE_DEFER)
1552 "failed to request tx DMA channel: %d\n", ret);
1553 nfc->dma_tx_ch = NULL;
1557 nfc->dma_rx_ch = dma_request_chan(nfc->dev, "rx");
1558 if (IS_ERR(nfc->dma_rx_ch)) {
1559 ret = PTR_ERR(nfc->dma_rx_ch);
1560 if (ret != -ENODEV && ret != -EPROBE_DEFER)
1562 "failed to request rx DMA channel: %d\n", ret);
1563 nfc->dma_rx_ch = NULL;
1567 nfc->dma_ecc_ch = dma_request_chan(nfc->dev, "ecc");
1568 if (IS_ERR(nfc->dma_ecc_ch)) {
1569 ret = PTR_ERR(nfc->dma_ecc_ch);
1570 if (ret != -ENODEV && ret != -EPROBE_DEFER)
1572 "failed to request ecc DMA channel: %d\n", ret);
1573 nfc->dma_ecc_ch = NULL;
1577 ret = sg_alloc_table(&nfc->dma_ecc_sg, FMC2_MAX_SG, GFP_KERNEL);
1581 /* Allocate a buffer to store ECC status registers */
1582 nfc->ecc_buf = devm_kzalloc(nfc->dev, FMC2_MAX_ECC_BUF_LEN, GFP_KERNEL);
1586 ret = sg_alloc_table(&nfc->dma_data_sg, FMC2_MAX_SG, GFP_KERNEL);
1590 init_completion(&nfc->dma_data_complete);
1591 init_completion(&nfc->dma_ecc_complete);
1596 if (ret == -ENODEV) {
1598 "DMAs not defined in the DT, polling mode is used\n");
1605 static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip)
1607 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1610 * Specific callbacks to read/write a page depending on
1611 * the mode (polling/sequencer) and the algo used (Hamming, BCH).
1613 if (nfc->dma_tx_ch && nfc->dma_rx_ch && nfc->dma_ecc_ch) {
1614 /* DMA => use sequencer mode callbacks */
1615 chip->ecc.correct = stm32_fmc2_nfc_seq_correct;
1616 chip->ecc.write_page = stm32_fmc2_nfc_seq_write_page;
1617 chip->ecc.read_page = stm32_fmc2_nfc_seq_read_page;
1618 chip->ecc.write_page_raw = stm32_fmc2_nfc_seq_write_page_raw;
1619 chip->ecc.read_page_raw = stm32_fmc2_nfc_seq_read_page_raw;
1621 /* No DMA => use polling mode callbacks */
1622 chip->ecc.hwctl = stm32_fmc2_nfc_hwctl;
1623 if (chip->ecc.strength == FMC2_ECC_HAM) {
1624 /* Hamming is used */
1625 chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate;
1626 chip->ecc.correct = stm32_fmc2_nfc_ham_correct;
1627 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
1630 chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate;
1631 chip->ecc.correct = stm32_fmc2_nfc_bch_correct;
1632 chip->ecc.read_page = stm32_fmc2_nfc_read_page;
1636 /* Specific configurations depending on the algo used */
1637 if (chip->ecc.strength == FMC2_ECC_HAM)
1638 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
1639 else if (chip->ecc.strength == FMC2_ECC_BCH8)
1640 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
1642 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
1645 static int stm32_fmc2_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
1646 struct mtd_oob_region *oobregion)
1648 struct nand_chip *chip = mtd_to_nand(mtd);
1649 struct nand_ecc_ctrl *ecc = &chip->ecc;
1654 oobregion->length = ecc->total;
1655 oobregion->offset = FMC2_BBM_LEN;
1660 static int stm32_fmc2_nfc_ooblayout_free(struct mtd_info *mtd, int section,
1661 struct mtd_oob_region *oobregion)
1663 struct nand_chip *chip = mtd_to_nand(mtd);
1664 struct nand_ecc_ctrl *ecc = &chip->ecc;
1669 oobregion->length = mtd->oobsize - ecc->total - FMC2_BBM_LEN;
1670 oobregion->offset = ecc->total + FMC2_BBM_LEN;
1675 static const struct mtd_ooblayout_ops stm32_fmc2_nfc_ooblayout_ops = {
1676 .ecc = stm32_fmc2_nfc_ooblayout_ecc,
1677 .free = stm32_fmc2_nfc_ooblayout_free,
1680 static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength)
1683 if (strength == FMC2_ECC_HAM)
1687 if (strength == FMC2_ECC_BCH8)
1694 NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes,
1696 FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
1698 static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip)
1700 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1701 struct mtd_info *mtd = nand_to_mtd(chip);
1705 * Only NAND_ECC_ENGINE_TYPE_ON_HOST mode is actually supported
1706 * Hamming => ecc.strength = 1
1707 * BCH4 => ecc.strength = 4
1708 * BCH8 => ecc.strength = 8
1709 * ECC sector size = 512
1711 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) {
1713 "nand_ecc_engine_type is not well defined in the DT\n");
1717 /* Default ECC settings in case they are not set in the device tree */
1718 if (!chip->ecc.size)
1719 chip->ecc.size = FMC2_ECC_STEP_SIZE;
1721 if (!chip->ecc.strength)
1722 chip->ecc.strength = FMC2_ECC_BCH8;
1724 ret = nand_ecc_choose_conf(chip, &stm32_fmc2_nfc_ecc_caps,
1725 mtd->oobsize - FMC2_BBM_LEN);
1727 dev_err(nfc->dev, "no valid ECC settings set\n");
1731 if (mtd->writesize / chip->ecc.size > FMC2_MAX_SG) {
1732 dev_err(nfc->dev, "nand page size is not supported\n");
1736 if (chip->bbt_options & NAND_BBT_USE_FLASH)
1737 chip->bbt_options |= NAND_BBT_NO_OOB;
1739 stm32_fmc2_nfc_nand_callbacks_setup(chip);
1741 mtd_set_ooblayout(mtd, &stm32_fmc2_nfc_ooblayout_ops);
1743 stm32_fmc2_nfc_setup(chip);
1748 static const struct nand_controller_ops stm32_fmc2_nfc_controller_ops = {
1749 .attach_chip = stm32_fmc2_nfc_attach_chip,
1750 .exec_op = stm32_fmc2_nfc_exec_op,
1751 .setup_interface = stm32_fmc2_nfc_setup_interface,
1754 static void stm32_fmc2_nfc_wp_enable(struct stm32_fmc2_nand *nand)
1757 gpiod_set_value(nand->wp_gpio, 1);
1760 static void stm32_fmc2_nfc_wp_disable(struct stm32_fmc2_nand *nand)
1763 gpiod_set_value(nand->wp_gpio, 0);
1766 static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc,
1767 struct device_node *dn)
1769 struct stm32_fmc2_nand *nand = &nfc->nand;
1773 if (!of_get_property(dn, "reg", &nand->ncs))
1776 nand->ncs /= sizeof(u32);
1778 dev_err(nfc->dev, "invalid reg property size\n");
1782 for (i = 0; i < nand->ncs; i++) {
1783 ret = of_property_read_u32_index(dn, "reg", i, &cs);
1785 dev_err(nfc->dev, "could not retrieve reg property: %d\n",
1790 if (cs >= FMC2_MAX_CE) {
1791 dev_err(nfc->dev, "invalid reg value: %d\n", cs);
1795 if (nfc->cs_assigned & BIT(cs)) {
1796 dev_err(nfc->dev, "cs already assigned: %d\n", cs);
1800 nfc->cs_assigned |= BIT(cs);
1801 nand->cs_used[i] = cs;
1804 nand->wp_gpio = devm_gpiod_get_from_of_node(nfc->dev, dn,
1806 GPIOD_OUT_HIGH, "wp");
1807 if (IS_ERR(nand->wp_gpio)) {
1808 ret = PTR_ERR(nand->wp_gpio);
1810 return dev_err_probe(nfc->dev, ret,
1811 "failed to request WP GPIO\n");
1813 nand->wp_gpio = NULL;
1816 nand_set_flash_node(&nand->chip, dn);
1821 static int stm32_fmc2_nfc_parse_dt(struct stm32_fmc2_nfc *nfc)
1823 struct device_node *dn = nfc->dev->of_node;
1824 struct device_node *child;
1825 int nchips = of_get_child_count(dn);
1829 dev_err(nfc->dev, "NAND chip not defined\n");
1834 dev_err(nfc->dev, "too many NAND chips defined\n");
1838 for_each_child_of_node(dn, child) {
1839 ret = stm32_fmc2_nfc_parse_child(nfc, child);
1849 static int stm32_fmc2_nfc_set_cdev(struct stm32_fmc2_nfc *nfc)
1851 struct device *dev = nfc->dev;
1852 bool ebi_found = false;
1854 if (dev->parent && of_device_is_compatible(dev->parent->of_node,
1855 "st,stm32mp1-fmc2-ebi"))
1858 if (of_device_is_compatible(dev->of_node, "st,stm32mp1-fmc2-nfc")) {
1860 nfc->cdev = dev->parent;
1876 static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
1878 struct device *dev = &pdev->dev;
1879 struct reset_control *rstc;
1880 struct stm32_fmc2_nfc *nfc;
1881 struct stm32_fmc2_nand *nand;
1882 struct resource *res;
1883 struct mtd_info *mtd;
1884 struct nand_chip *chip;
1885 struct resource cres;
1886 int chip_cs, mem_region, ret, irq;
1887 int start_region = 0;
1889 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1894 nand_controller_init(&nfc->base);
1895 nfc->base.ops = &stm32_fmc2_nfc_controller_ops;
1897 ret = stm32_fmc2_nfc_set_cdev(nfc);
1901 ret = stm32_fmc2_nfc_parse_dt(nfc);
1905 ret = of_address_to_resource(nfc->cdev->of_node, 0, &cres);
1909 nfc->io_phys_addr = cres.start;
1911 nfc->regmap = device_node_to_regmap(nfc->cdev->of_node);
1912 if (IS_ERR(nfc->regmap))
1913 return PTR_ERR(nfc->regmap);
1915 if (nfc->dev == nfc->cdev)
1918 for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE;
1919 chip_cs++, mem_region += 3) {
1920 if (!(nfc->cs_assigned & BIT(chip_cs)))
1923 res = platform_get_resource(pdev, IORESOURCE_MEM, mem_region);
1924 nfc->data_base[chip_cs] = devm_ioremap_resource(dev, res);
1925 if (IS_ERR(nfc->data_base[chip_cs]))
1926 return PTR_ERR(nfc->data_base[chip_cs]);
1928 nfc->data_phys_addr[chip_cs] = res->start;
1930 nfc->cmd_base[chip_cs] = devm_platform_ioremap_resource(pdev, mem_region + 1);
1931 if (IS_ERR(nfc->cmd_base[chip_cs]))
1932 return PTR_ERR(nfc->cmd_base[chip_cs]);
1934 nfc->addr_base[chip_cs] = devm_platform_ioremap_resource(pdev, mem_region + 2);
1935 if (IS_ERR(nfc->addr_base[chip_cs]))
1936 return PTR_ERR(nfc->addr_base[chip_cs]);
1939 irq = platform_get_irq(pdev, 0);
1943 ret = devm_request_irq(dev, irq, stm32_fmc2_nfc_irq, 0,
1944 dev_name(dev), nfc);
1946 dev_err(dev, "failed to request irq\n");
1950 init_completion(&nfc->complete);
1952 nfc->clk = devm_clk_get(nfc->cdev, NULL);
1953 if (IS_ERR(nfc->clk))
1954 return PTR_ERR(nfc->clk);
1956 ret = clk_prepare_enable(nfc->clk);
1958 dev_err(dev, "can not enable the clock\n");
1962 rstc = devm_reset_control_get(dev, NULL);
1964 ret = PTR_ERR(rstc);
1965 if (ret == -EPROBE_DEFER)
1966 goto err_clk_disable;
1968 reset_control_assert(rstc);
1969 reset_control_deassert(rstc);
1972 ret = stm32_fmc2_nfc_dma_setup(nfc);
1974 goto err_release_dma;
1976 stm32_fmc2_nfc_init(nfc);
1980 mtd = nand_to_mtd(chip);
1981 mtd->dev.parent = dev;
1983 chip->controller = &nfc->base;
1984 chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
1987 stm32_fmc2_nfc_wp_disable(nand);
1989 /* Scan to find existence of the device */
1990 ret = nand_scan(chip, nand->ncs);
1994 ret = mtd_device_register(mtd, NULL, 0);
1996 goto err_nand_cleanup;
1998 platform_set_drvdata(pdev, nfc);
2006 stm32_fmc2_nfc_wp_enable(nand);
2009 if (nfc->dma_ecc_ch)
2010 dma_release_channel(nfc->dma_ecc_ch);
2012 dma_release_channel(nfc->dma_tx_ch);
2014 dma_release_channel(nfc->dma_rx_ch);
2016 sg_free_table(&nfc->dma_data_sg);
2017 sg_free_table(&nfc->dma_ecc_sg);
2020 clk_disable_unprepare(nfc->clk);
2025 static int stm32_fmc2_nfc_remove(struct platform_device *pdev)
2027 struct stm32_fmc2_nfc *nfc = platform_get_drvdata(pdev);
2028 struct stm32_fmc2_nand *nand = &nfc->nand;
2029 struct nand_chip *chip = &nand->chip;
2032 ret = mtd_device_unregister(nand_to_mtd(chip));
2036 if (nfc->dma_ecc_ch)
2037 dma_release_channel(nfc->dma_ecc_ch);
2039 dma_release_channel(nfc->dma_tx_ch);
2041 dma_release_channel(nfc->dma_rx_ch);
2043 sg_free_table(&nfc->dma_data_sg);
2044 sg_free_table(&nfc->dma_ecc_sg);
2046 clk_disable_unprepare(nfc->clk);
2048 stm32_fmc2_nfc_wp_enable(nand);
2053 static int __maybe_unused stm32_fmc2_nfc_suspend(struct device *dev)
2055 struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev);
2056 struct stm32_fmc2_nand *nand = &nfc->nand;
2058 clk_disable_unprepare(nfc->clk);
2060 stm32_fmc2_nfc_wp_enable(nand);
2062 pinctrl_pm_select_sleep_state(dev);
2067 static int __maybe_unused stm32_fmc2_nfc_resume(struct device *dev)
2069 struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev);
2070 struct stm32_fmc2_nand *nand = &nfc->nand;
2073 pinctrl_pm_select_default_state(dev);
2075 ret = clk_prepare_enable(nfc->clk);
2077 dev_err(dev, "can not enable the clock\n");
2081 stm32_fmc2_nfc_init(nfc);
2083 stm32_fmc2_nfc_wp_disable(nand);
2085 for (chip_cs = 0; chip_cs < FMC2_MAX_CE; chip_cs++) {
2086 if (!(nfc->cs_assigned & BIT(chip_cs)))
2089 nand_reset(&nand->chip, chip_cs);
2095 static SIMPLE_DEV_PM_OPS(stm32_fmc2_nfc_pm_ops, stm32_fmc2_nfc_suspend,
2096 stm32_fmc2_nfc_resume);
2098 static const struct of_device_id stm32_fmc2_nfc_match[] = {
2099 {.compatible = "st,stm32mp15-fmc2"},
2100 {.compatible = "st,stm32mp1-fmc2-nfc"},
2103 MODULE_DEVICE_TABLE(of, stm32_fmc2_nfc_match);
2105 static struct platform_driver stm32_fmc2_nfc_driver = {
2106 .probe = stm32_fmc2_nfc_probe,
2107 .remove = stm32_fmc2_nfc_remove,
2109 .name = "stm32_fmc2_nfc",
2110 .of_match_table = stm32_fmc2_nfc_match,
2111 .pm = &stm32_fmc2_nfc_pm_ops,
2114 module_platform_driver(stm32_fmc2_nfc_driver);
2116 MODULE_ALIAS("platform:stm32_fmc2_nfc");
2117 MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>");
2118 MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 NFC driver");
2119 MODULE_LICENSE("GPL v2");