drivers/mtd/nand/sunxi_nand.c

   1 /*
   2  * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
   3  *
   4  * Derived from:
   5  *      https://github.com/yuq/sunxi-nfc-mtd
   6  *      Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
   7  *
   8  *      https://github.com/hno/Allwinner-Info
   9  *      Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
  10  *
  11  *      Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
  12  *      Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_gpio.h>
  33 #include <linux/of_mtd.h>
  34 #include <linux/mtd/mtd.h>
  35 #include <linux/mtd/nand.h>
  36 #include <linux/mtd/partitions.h>
  37 #include <linux/clk.h>
  38 #include <linux/delay.h>
  39 #include <linux/dmaengine.h>
  40 #include <linux/gpio.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/io.h>
  43
  44 #define NFC_REG_CTL             0x0000
  45 #define NFC_REG_ST              0x0004
  46 #define NFC_REG_INT             0x0008
  47 #define NFC_REG_TIMING_CTL      0x000C
  48 #define NFC_REG_TIMING_CFG      0x0010
  49 #define NFC_REG_ADDR_LOW        0x0014
  50 #define NFC_REG_ADDR_HIGH       0x0018
  51 #define NFC_REG_SECTOR_NUM      0x001C
  52 #define NFC_REG_CNT             0x0020
  53 #define NFC_REG_CMD             0x0024
  54 #define NFC_REG_RCMD_SET        0x0028
  55 #define NFC_REG_WCMD_SET        0x002C
  56 #define NFC_REG_IO_DATA         0x0030
  57 #define NFC_REG_ECC_CTL         0x0034
  58 #define NFC_REG_ECC_ST          0x0038
  59 #define NFC_REG_DEBUG           0x003C
  60 #define NFC_REG_ECC_ERR_CNT(x)  ((0x0040 + (x)) & ~0x3)
  61 #define NFC_REG_USER_DATA(x)    (0x0050 + ((x) * 4))
  62 #define NFC_REG_SPARE_AREA      0x00A0
  63 #define NFC_RAM0_BASE           0x0400
  64 #define NFC_RAM1_BASE           0x0800
  65
  66 /* define bit use in NFC_CTL */
  67 #define NFC_EN                  BIT(0)
  68 #define NFC_RESET               BIT(1)
  69 #define NFC_BUS_WIDTH_MSK       BIT(2)
  70 #define NFC_BUS_WIDTH_8         (0 << 2)
  71 #define NFC_BUS_WIDTH_16        (1 << 2)
  72 #define NFC_RB_SEL_MSK          BIT(3)
  73 #define NFC_RB_SEL(x)           ((x) << 3)
  74 #define NFC_CE_SEL_MSK          GENMASK(26, 24)
  75 #define NFC_CE_SEL(x)           ((x) << 24)
  76 #define NFC_CE_CTL              BIT(6)
  77 #define NFC_PAGE_SHIFT_MSK      GENMASK(11, 8)
  78 #define NFC_PAGE_SHIFT(x)       (((x) < 10 ? 0 : (x) - 10) << 8)
  79 #define NFC_SAM                 BIT(12)
  80 #define NFC_RAM_METHOD          BIT(14)
  81 #define NFC_DEBUG_CTL           BIT(31)
  82
  83 /* define bit use in NFC_ST */
  84 #define NFC_RB_B2R              BIT(0)
  85 #define NFC_CMD_INT_FLAG        BIT(1)
  86 #define NFC_DMA_INT_FLAG        BIT(2)
  87 #define NFC_CMD_FIFO_STATUS     BIT(3)
  88 #define NFC_STA                 BIT(4)
  89 #define NFC_NATCH_INT_FLAG      BIT(5)
  90 #define NFC_RB_STATE(x)         BIT(x + 8)
  91
  92 /* define bit use in NFC_INT */
  93 #define NFC_B2R_INT_ENABLE      BIT(0)
  94 #define NFC_CMD_INT_ENABLE      BIT(1)
  95 #define NFC_DMA_INT_ENABLE      BIT(2)
  96 #define NFC_INT_MASK            (NFC_B2R_INT_ENABLE | \
  97                                  NFC_CMD_INT_ENABLE | \
  98                                  NFC_DMA_INT_ENABLE)
  99
 100 /* define bit use in NFC_TIMING_CTL */
 101 #define NFC_TIMING_CTL_EDO      BIT(8)
 102
 103 /* define NFC_TIMING_CFG register layout */
 104 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD)             \
 105         (((tWB) & 0x3) | (((tADL) & 0x3) << 2) |                \
 106         (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) |         \
 107         (((tCAD) & 0x7) << 8))
 108
 109 /* define bit use in NFC_CMD */
 110 #define NFC_CMD_LOW_BYTE_MSK    GENMASK(7, 0)
 111 #define NFC_CMD_HIGH_BYTE_MSK   GENMASK(15, 8)
 112 #define NFC_CMD(x)              (x)
 113 #define NFC_ADR_NUM_MSK         GENMASK(18, 16)
 114 #define NFC_ADR_NUM(x)          (((x) - 1) << 16)
 115 #define NFC_SEND_ADR            BIT(19)
 116 #define NFC_ACCESS_DIR          BIT(20)
 117 #define NFC_DATA_TRANS          BIT(21)
 118 #define NFC_SEND_CMD1           BIT(22)
 119 #define NFC_WAIT_FLAG           BIT(23)
 120 #define NFC_SEND_CMD2           BIT(24)
 121 #define NFC_SEQ                 BIT(25)
 122 #define NFC_DATA_SWAP_METHOD    BIT(26)
 123 #define NFC_ROW_AUTO_INC        BIT(27)
 124 #define NFC_SEND_CMD3           BIT(28)
 125 #define NFC_SEND_CMD4           BIT(29)
 126 #define NFC_CMD_TYPE_MSK        GENMASK(31, 30)
 127 #define NFC_NORMAL_OP           (0 << 30)
 128 #define NFC_ECC_OP              (1 << 30)
 129 #define NFC_PAGE_OP             (2 << 30)
 130
 131 /* define bit use in NFC_RCMD_SET */
 132 #define NFC_READ_CMD_MSK        GENMASK(7, 0)
 133 #define NFC_RND_READ_CMD0_MSK   GENMASK(15, 8)
 134 #define NFC_RND_READ_CMD1_MSK   GENMASK(23, 16)
 135
 136 /* define bit use in NFC_WCMD_SET */
 137 #define NFC_PROGRAM_CMD_MSK     GENMASK(7, 0)
 138 #define NFC_RND_WRITE_CMD_MSK   GENMASK(15, 8)
 139 #define NFC_READ_CMD0_MSK       GENMASK(23, 16)
 140 #define NFC_READ_CMD1_MSK       GENMASK(31, 24)
 141
 142 /* define bit use in NFC_ECC_CTL */
 143 #define NFC_ECC_EN              BIT(0)
 144 #define NFC_ECC_PIPELINE        BIT(3)
 145 #define NFC_ECC_EXCEPTION       BIT(4)
 146 #define NFC_ECC_BLOCK_SIZE_MSK  BIT(5)
 147 #define NFC_RANDOM_EN           BIT(9)
 148 #define NFC_RANDOM_DIRECTION    BIT(10)
 149 #define NFC_ECC_MODE_MSK        GENMASK(15, 12)
 150 #define NFC_ECC_MODE(x)         ((x) << 12)
 151 #define NFC_RANDOM_SEED_MSK     GENMASK(30, 16)
 152 #define NFC_RANDOM_SEED(x)      ((x) << 16)
 153
 154 /* define bit use in NFC_ECC_ST */
 155 #define NFC_ECC_ERR(x)          BIT(x)
 156 #define NFC_ECC_PAT_FOUND(x)    BIT(x + 16)
 157 #define NFC_ECC_ERR_CNT(b, x)   (((x) >> ((b) * 8)) & 0xff)
 158
 159 /* NFC_USER_DATA helper macros */
 160 #define NFC_BUF_TO_USER_DATA(buf)       ((buf)[0] | ((buf)[1] << 8) | \
 161                                         ((buf)[2] << 16) | ((buf)[3] << 24))
 162
 163 #define NFC_DEFAULT_TIMEOUT_MS  1000
 164
 165 #define NFC_SRAM_SIZE           1024
 166
 167 #define NFC_MAX_CS              7
 168
 169 /*
 170  * Ready/Busy detection type: describes the Ready/Busy detection modes
 171  *
 172  * @RB_NONE:    no external detection available, rely on STATUS command
 173  *              and software timeouts
 174  * @RB_NATIVE:  use sunxi NAND controller Ready/Busy support. The Ready/Busy
 175  *              pin of the NAND flash chip must be connected to one of the
 176  *              native NAND R/B pins (those which can be muxed to the NAND
 177  *              Controller)
 178  * @RB_GPIO:    use a simple GPIO to handle Ready/Busy status. The Ready/Busy
 179  *              pin of the NAND flash chip must be connected to a GPIO capable
 180  *              pin.
 181  */
 182 enum sunxi_nand_rb_type {
 183         RB_NONE,
 184         RB_NATIVE,
 185         RB_GPIO,
 186 };
 187
 188 /*
 189  * Ready/Busy structure: stores information related to Ready/Busy detection
 190  *
 191  * @type:       the Ready/Busy detection mode
 192  * @info:       information related to the R/B detection mode. Either a gpio
 193  *              id or a native R/B id (those supported by the NAND controller).
 194  */
 195 struct sunxi_nand_rb {
 196         enum sunxi_nand_rb_type type;
 197         union {
 198                 int gpio;
 199                 int nativeid;
 200         } info;
 201 };
 202
 203 /*
 204  * Chip Select structure: stores information related to NAND Chip Select
 205  *
 206  * @cs:         the NAND CS id used to communicate with a NAND Chip
 207  * @rb:         the Ready/Busy description
 208  */
 209 struct sunxi_nand_chip_sel {
 210         u8 cs;
 211         struct sunxi_nand_rb rb;
 212 };
 213
 214 /*
 215  * sunxi HW ECC infos: stores information related to HW ECC support
 216  *
 217  * @mode:       the sunxi ECC mode field deduced from ECC requirements
 218  * @layout:     the OOB layout depending on the ECC requirements and the
 219  *              selected ECC mode
 220  */
 221 struct sunxi_nand_hw_ecc {
 222         int mode;
 223         struct nand_ecclayout layout;
 224 };
 225
 226 /*
 227  * NAND chip structure: stores NAND chip device related information
 228  *
 229  * @node:               used to store NAND chips into a list
 230  * @nand:               base NAND chip structure
 231  * @mtd:                base MTD structure
 232  * @clk_rate:           clk_rate required for this NAND chip
 233  * @timing_cfg          TIMING_CFG register value for this NAND chip
 234  * @selected:           current active CS
 235  * @nsels:              number of CS lines required by the NAND chip
 236  * @sels:               array of CS lines descriptions
 237  */
 238 struct sunxi_nand_chip {
 239         struct list_head node;
 240         struct nand_chip nand;
 241         struct mtd_info mtd;
 242         unsigned long clk_rate;
 243         u32 timing_cfg;
 244         u32 timing_ctl;
 245         int selected;
 246         int nsels;
 247         struct sunxi_nand_chip_sel sels[0];
 248 };
 249
 250 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
 251 {
 252         return container_of(nand, struct sunxi_nand_chip, nand);
 253 }
 254
 255 /*
 256  * NAND Controller structure: stores sunxi NAND controller information
 257  *
 258  * @controller:         base controller structure
 259  * @dev:                parent device (used to print error messages)
 260  * @regs:               NAND controller registers
 261  * @ahb_clk:            NAND Controller AHB clock
 262  * @mod_clk:            NAND Controller mod clock
 263  * @assigned_cs:        bitmask describing already assigned CS lines
 264  * @clk_rate:           NAND controller current clock rate
 265  * @chips:              a list containing all the NAND chips attached to
 266  *                      this NAND controller
 267  * @complete:           a completion object used to wait for NAND
 268  *                      controller events
 269  */
 270 struct sunxi_nfc {
 271         struct nand_hw_control controller;
 272         struct device *dev;
 273         void __iomem *regs;
 274         struct clk *ahb_clk;
 275         struct clk *mod_clk;
 276         unsigned long assigned_cs;
 277         unsigned long clk_rate;
 278         struct list_head chips;
 279         struct completion complete;
 280 };
 281
 282 static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
 283 {
 284         return container_of(ctrl, struct sunxi_nfc, controller);
 285 }
 286
 287 static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
 288 {
 289         struct sunxi_nfc *nfc = dev_id;
 290         u32 st = readl(nfc->regs + NFC_REG_ST);
 291         u32 ien = readl(nfc->regs + NFC_REG_INT);
 292
 293         if (!(ien & st))
 294                 return IRQ_NONE;
 295
 296         if ((ien & st) == ien)
 297                 complete(&nfc->complete);
 298
 299         writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
 300         writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
 301
 302         return IRQ_HANDLED;
 303 }
 304
 305 static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
 306                               unsigned int timeout_ms)
 307 {
 308         init_completion(&nfc->complete);
 309
 310         writel(flags, nfc->regs + NFC_REG_INT);
 311
 312         if (!timeout_ms)
 313                 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
 314
 315         if (!wait_for_completion_timeout(&nfc->complete,
 316                                          msecs_to_jiffies(timeout_ms))) {
 317                 dev_err(nfc->dev, "wait interrupt timedout\n");
 318                 return -ETIMEDOUT;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
 325 {
 326         unsigned long timeout = jiffies +
 327                                 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
 328
 329         do {
 330                 if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
 331                         return 0;
 332         } while (time_before(jiffies, timeout));
 333
 334         dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
 335         return -ETIMEDOUT;
 336 }
 337
 338 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
 339 {
 340         unsigned long timeout = jiffies +
 341                                 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
 342
 343         writel(0, nfc->regs + NFC_REG_ECC_CTL);
 344         writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
 345
 346         do {
 347                 if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
 348                         return 0;
 349         } while (time_before(jiffies, timeout));
 350
 351         dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
 352         return -ETIMEDOUT;
 353 }
 354
 355 static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
 356 {
 357         struct nand_chip *nand = mtd->priv;
 358         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 359         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 360         struct sunxi_nand_rb *rb;
 361         unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
 362         int ret;
 363
 364         if (sunxi_nand->selected < 0)
 365                 return 0;
 366
 367         rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
 368
 369         switch (rb->type) {
 370         case RB_NATIVE:
 371                 ret = !!(readl(nfc->regs + NFC_REG_ST) &
 372                          NFC_RB_STATE(rb->info.nativeid));
 373                 if (ret)
 374                         break;
 375
 376                 sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
 377                 ret = !!(readl(nfc->regs + NFC_REG_ST) &
 378                          NFC_RB_STATE(rb->info.nativeid));
 379                 break;
 380         case RB_GPIO:
 381                 ret = gpio_get_value(rb->info.gpio);
 382                 break;
 383         case RB_NONE:
 384         default:
 385                 ret = 0;
 386                 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
 387                 break;
 388         }
 389
 390         return ret;
 391 }
 392
 393 static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
 394 {
 395         struct nand_chip *nand = mtd->priv;
 396         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 397         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 398         struct sunxi_nand_chip_sel *sel;
 399         u32 ctl;
 400
 401         if (chip > 0 && chip >= sunxi_nand->nsels)
 402                 return;
 403
 404         if (chip == sunxi_nand->selected)
 405                 return;
 406
 407         ctl = readl(nfc->regs + NFC_REG_CTL) &
 408               ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
 409
 410         if (chip >= 0) {
 411                 sel = &sunxi_nand->sels[chip];
 412
 413                 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
 414                        NFC_PAGE_SHIFT(nand->page_shift - 10);
 415                 if (sel->rb.type == RB_NONE) {
 416                         nand->dev_ready = NULL;
 417                 } else {
 418                         nand->dev_ready = sunxi_nfc_dev_ready;
 419                         if (sel->rb.type == RB_NATIVE)
 420                                 ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
 421                 }
 422
 423                 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
 424
 425                 if (nfc->clk_rate != sunxi_nand->clk_rate) {
 426                         clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
 427                         nfc->clk_rate = sunxi_nand->clk_rate;
 428                 }
 429         }
 430
 431         writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
 432         writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
 433         writel(ctl, nfc->regs + NFC_REG_CTL);
 434
 435         sunxi_nand->selected = chip;
 436 }
 437
 438 static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 439 {
 440         struct nand_chip *nand = mtd->priv;
 441         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 442         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 443         int ret;
 444         int cnt;
 445         int offs = 0;
 446         u32 tmp;
 447
 448         while (len > offs) {
 449                 cnt = min(len - offs, NFC_SRAM_SIZE);
 450
 451                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 452                 if (ret)
 453                         break;
 454
 455                 writel(cnt, nfc->regs + NFC_REG_CNT);
 456                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
 457                 writel(tmp, nfc->regs + NFC_REG_CMD);
 458
 459                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 460                 if (ret)
 461                         break;
 462
 463                 if (buf)
 464                         memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
 465                                       cnt);
 466                 offs += cnt;
 467         }
 468 }
 469
 470 static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 471                                 int len)
 472 {
 473         struct nand_chip *nand = mtd->priv;
 474         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 475         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 476         int ret;
 477         int cnt;
 478         int offs = 0;
 479         u32 tmp;
 480
 481         while (len > offs) {
 482                 cnt = min(len - offs, NFC_SRAM_SIZE);
 483
 484                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 485                 if (ret)
 486                         break;
 487
 488                 writel(cnt, nfc->regs + NFC_REG_CNT);
 489                 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
 490                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
 491                       NFC_ACCESS_DIR;
 492                 writel(tmp, nfc->regs + NFC_REG_CMD);
 493
 494                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 495                 if (ret)
 496                         break;
 497
 498                 offs += cnt;
 499         }
 500 }
 501
 502 static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
 503 {
 504         uint8_t ret;
 505
 506         sunxi_nfc_read_buf(mtd, &ret, 1);
 507
 508         return ret;
 509 }
 510
 511 static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
 512                                unsigned int ctrl)
 513 {
 514         struct nand_chip *nand = mtd->priv;
 515         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 516         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 517         int ret;
 518         u32 tmp;
 519
 520         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 521         if (ret)
 522                 return;
 523
 524         if (ctrl & NAND_CTRL_CHANGE) {
 525                 tmp = readl(nfc->regs + NFC_REG_CTL);
 526                 if (ctrl & NAND_NCE)
 527                         tmp |= NFC_CE_CTL;
 528                 else
 529                         tmp &= ~NFC_CE_CTL;
 530                 writel(tmp, nfc->regs + NFC_REG_CTL);
 531         }
 532
 533         if (dat == NAND_CMD_NONE)
 534                 return;
 535
 536         if (ctrl & NAND_CLE) {
 537                 writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD);
 538         } else {
 539                 writel(dat, nfc->regs + NFC_REG_ADDR_LOW);
 540                 writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD);
 541         }
 542
 543         sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 544 }
 545
 546 static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
 547 {
 548         struct nand_chip *nand = mtd->priv;
 549         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 550         struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
 551         u32 ecc_ctl;
 552
 553         ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
 554         ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
 555                      NFC_ECC_BLOCK_SIZE_MSK);
 556         ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION;
 557
 558         writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
 559 }
 560
 561 static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
 562 {
 563         struct nand_chip *nand = mtd->priv;
 564         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 565
 566         writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
 567                nfc->regs + NFC_REG_ECC_CTL);
 568 }
 569
 570 static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
 571 {
 572         buf[0] = user_data;
 573         buf[1] = user_data >> 8;
 574         buf[2] = user_data >> 16;
 575         buf[3] = user_data >> 24;
 576 }
 577
 578 static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
 579                                        u8 *data, int data_off,
 580                                        u8 *oob, int oob_off,
 581                                        int *cur_off,
 582                                        unsigned int *max_bitflips)
 583 {
 584         struct nand_chip *nand = mtd->priv;
 585         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 586         struct nand_ecc_ctrl *ecc = &nand->ecc;
 587         u32 status;
 588         int ret;
 589
 590         if (*cur_off != data_off)
 591                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
 592
 593         sunxi_nfc_read_buf(mtd, data, ecc->size);
 594
 595         if (data_off + ecc->bytes != oob_off)
 596                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 597
 598         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 599         if (ret)
 600                 return ret;
 601
 602         writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
 603                nfc->regs + NFC_REG_CMD);
 604
 605         ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 606         if (ret)
 607                 return ret;
 608
 609         status = readl(nfc->regs + NFC_REG_ECC_ST);
 610         ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0)));
 611
 612         memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
 613
 614         nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 615         sunxi_nfc_read_buf(mtd, oob, ecc->bytes + 4);
 616
 617         if (status & NFC_ECC_ERR(0)) {
 618                 ret = -EIO;
 619         } else {
 620                 /*
 621                  * The engine protects 4 bytes of OOB data per chunk.
 622                  * Retrieve the corrected OOB bytes.
 623                  */
 624                 sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(0)),
 625                                            oob);
 626         }
 627
 628         if (ret < 0) {
 629                 mtd->ecc_stats.failed++;
 630         } else {
 631                 mtd->ecc_stats.corrected += ret;
 632                 *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
 633         }
 634
 635         *cur_off = oob_off + ecc->bytes + 4;
 636
 637         return 0;
 638 }
 639
 640 static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
 641                                             u8 *oob, int *cur_off)
 642 {
 643         struct nand_chip *nand = mtd->priv;
 644         struct nand_ecc_ctrl *ecc = &nand->ecc;
 645         int offset = ((ecc->bytes + 4) * ecc->steps);
 646         int len = mtd->oobsize - offset;
 647
 648         if (len <= 0)
 649                 return;
 650
 651         if (*cur_off != offset)
 652                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
 653                               offset + mtd->writesize, -1);
 654
 655         sunxi_nfc_read_buf(mtd, oob + offset, len);
 656
 657         *cur_off = mtd->oobsize + mtd->writesize;
 658 }
 659
 660 static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
 661                                         const u8 *data, int data_off,
 662                                         const u8 *oob, int oob_off,
 663                                         int *cur_off)
 664 {
 665         struct nand_chip *nand = mtd->priv;
 666         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 667         struct nand_ecc_ctrl *ecc = &nand->ecc;
 668         int ret;
 669
 670         if (data_off != *cur_off)
 671                 nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
 672
 673         sunxi_nfc_write_buf(mtd, data, ecc->size);
 674
 675         /* Fill OOB data in */
 676         writel(NFC_BUF_TO_USER_DATA(oob), nfc->regs + NFC_REG_USER_DATA(0));
 677
 678         if (data_off + ecc->bytes != oob_off)
 679                 nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
 680
 681         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 682         if (ret)
 683                 return ret;
 684
 685         writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
 686                NFC_ACCESS_DIR | NFC_ECC_OP,
 687                nfc->regs + NFC_REG_CMD);
 688
 689         ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 690         if (ret)
 691                 return ret;
 692
 693         *cur_off = oob_off + ecc->bytes + 4;
 694
 695         return 0;
 696 }
 697
 698 static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
 699                                              u8 *oob, int *cur_off)
 700 {
 701         struct nand_chip *nand = mtd->priv;
 702         struct nand_ecc_ctrl *ecc = &nand->ecc;
 703         int offset = ((ecc->bytes + 4) * ecc->steps);
 704         int len = mtd->oobsize - offset;
 705
 706         if (len <= 0)
 707                 return;
 708
 709         if (*cur_off != offset)
 710                 nand->cmdfunc(mtd, NAND_CMD_RNDIN,
 711                               offset + mtd->writesize, -1);
 712
 713         sunxi_nfc_write_buf(mtd, oob + offset, len);
 714
 715         *cur_off = mtd->oobsize + mtd->writesize;
 716 }
 717
 718 static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
 719                                       struct nand_chip *chip, uint8_t *buf,
 720                                       int oob_required, int page)
 721 {
 722         struct nand_ecc_ctrl *ecc = &chip->ecc;
 723         unsigned int max_bitflips = 0;
 724         int ret, i, cur_off = 0;
 725
 726         sunxi_nfc_hw_ecc_enable(mtd);
 727
 728         for (i = 0; i < ecc->steps; i++) {
 729                 int data_off = i * ecc->size;
 730                 int oob_off = i * (ecc->bytes + 4);
 731                 u8 *data = buf + data_off;
 732                 u8 *oob = chip->oob_poi + oob_off;
 733
 734                 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
 735                                                   oob_off + mtd->writesize,
 736                                                   &cur_off, &max_bitflips);
 737                 if (ret)
 738                         return ret;
 739         }
 740
 741         if (oob_required)
 742                 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off);
 743
 744         sunxi_nfc_hw_ecc_disable(mtd);
 745
 746         return max_bitflips;
 747 }
 748
 749 static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
 750                                        struct nand_chip *chip,
 751                                        const uint8_t *buf, int oob_required)
 752 {
 753         struct nand_ecc_ctrl *ecc = &chip->ecc;
 754         int ret, i, cur_off = 0;
 755
 756         sunxi_nfc_hw_ecc_enable(mtd);
 757
 758         for (i = 0; i < ecc->steps; i++) {
 759                 int data_off = i * ecc->size;
 760                 int oob_off = i * (ecc->bytes + 4);
 761                 const u8 *data = buf + data_off;
 762                 const u8 *oob = chip->oob_poi + oob_off;
 763
 764                 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
 765                                                    oob_off + mtd->writesize,
 766                                                    &cur_off);
 767                 if (ret)
 768                         return ret;
 769         }
 770
 771         if (oob_required)
 772                 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi, &cur_off);
 773
 774         sunxi_nfc_hw_ecc_disable(mtd);
 775
 776         return 0;
 777 }
 778
 779 static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
 780                                                struct nand_chip *chip,
 781                                                uint8_t *buf, int oob_required,
 782                                                int page)
 783 {
 784         struct nand_ecc_ctrl *ecc = &chip->ecc;
 785         unsigned int max_bitflips = 0;
 786         int ret, i, cur_off = 0;
 787
 788         sunxi_nfc_hw_ecc_enable(mtd);
 789
 790         for (i = 0; i < ecc->steps; i++) {
 791                 int data_off = i * (ecc->size + ecc->bytes + 4);
 792                 int oob_off = data_off + ecc->size;
 793                 u8 *data = buf + (i * ecc->size);
 794                 u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
 795
 796                 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
 797                                                   oob_off, &cur_off,
 798                                                   &max_bitflips);
 799                 if (ret)
 800                         return ret;
 801         }
 802
 803         if (oob_required)
 804                 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off);
 805
 806         sunxi_nfc_hw_ecc_disable(mtd);
 807
 808         return max_bitflips;
 809 }
 810
 811 static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
 812                                                 struct nand_chip *chip,
 813                                                 const uint8_t *buf,
 814                                                 int oob_required)
 815 {
 816         struct nand_ecc_ctrl *ecc = &chip->ecc;
 817         int ret, i, cur_off = 0;
 818
 819         sunxi_nfc_hw_ecc_enable(mtd);
 820
 821         for (i = 0; i < ecc->steps; i++) {
 822                 int data_off = i * (ecc->size + ecc->bytes + 4);
 823                 int oob_off = data_off + ecc->size;
 824                 const u8 *data = buf + (i * ecc->size);
 825                 const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
 826
 827                 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
 828                                                    oob, oob_off, &cur_off);
 829                 if (ret)
 830                         return ret;
 831         }
 832
 833         if (oob_required)
 834                 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi, &cur_off);
 835
 836         sunxi_nfc_hw_ecc_disable(mtd);
 837
 838         return 0;
 839 }
 840
 841 static const s32 tWB_lut[] = {6, 12, 16, 20};
 842 static const s32 tRHW_lut[] = {4, 8, 12, 20};
 843
 844 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
 845                 u32 clk_period)
 846 {
 847         u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
 848         int i;
 849
 850         for (i = 0; i < lut_size; i++) {
 851                 if (clk_cycles <= lut[i])
 852                         return i;
 853         }
 854
 855         /* Doesn't fit */
 856         return -EINVAL;
 857 }
 858
 859 #define sunxi_nand_lookup_timing(l, p, c) \
 860                         _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
 861
 862 static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
 863                                        const struct nand_sdr_timings *timings)
 864 {
 865         struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
 866         u32 min_clk_period = 0;
 867         s32 tWB, tADL, tWHR, tRHW, tCAD;
 868
 869         /* T1 <=> tCLS */
 870         if (timings->tCLS_min > min_clk_period)
 871                 min_clk_period = timings->tCLS_min;
 872
 873         /* T2 <=> tCLH */
 874         if (timings->tCLH_min > min_clk_period)
 875                 min_clk_period = timings->tCLH_min;
 876
 877         /* T3 <=> tCS */
 878         if (timings->tCS_min > min_clk_period)
 879                 min_clk_period = timings->tCS_min;
 880
 881         /* T4 <=> tCH */
 882         if (timings->tCH_min > min_clk_period)
 883                 min_clk_period = timings->tCH_min;
 884
 885         /* T5 <=> tWP */
 886         if (timings->tWP_min > min_clk_period)
 887                 min_clk_period = timings->tWP_min;
 888
 889         /* T6 <=> tWH */
 890         if (timings->tWH_min > min_clk_period)
 891                 min_clk_period = timings->tWH_min;
 892
 893         /* T7 <=> tALS */
 894         if (timings->tALS_min > min_clk_period)
 895                 min_clk_period = timings->tALS_min;
 896
 897         /* T8 <=> tDS */
 898         if (timings->tDS_min > min_clk_period)
 899                 min_clk_period = timings->tDS_min;
 900
 901         /* T9 <=> tDH */
 902         if (timings->tDH_min > min_clk_period)
 903                 min_clk_period = timings->tDH_min;
 904
 905         /* T10 <=> tRR */
 906         if (timings->tRR_min > (min_clk_period * 3))
 907                 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
 908
 909         /* T11 <=> tALH */
 910         if (timings->tALH_min > min_clk_period)
 911                 min_clk_period = timings->tALH_min;
 912
 913         /* T12 <=> tRP */
 914         if (timings->tRP_min > min_clk_period)
 915                 min_clk_period = timings->tRP_min;
 916
 917         /* T13 <=> tREH */
 918         if (timings->tREH_min > min_clk_period)
 919                 min_clk_period = timings->tREH_min;
 920
 921         /* T14 <=> tRC */
 922         if (timings->tRC_min > (min_clk_period * 2))
 923                 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
 924
 925         /* T15 <=> tWC */
 926         if (timings->tWC_min > (min_clk_period * 2))
 927                 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
 928
 929         /* T16 - T19 + tCAD */
 930         tWB  = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
 931                                         min_clk_period);
 932         if (tWB < 0) {
 933                 dev_err(nfc->dev, "unsupported tWB\n");
 934                 return tWB;
 935         }
 936
 937         tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
 938         if (tADL > 3) {
 939                 dev_err(nfc->dev, "unsupported tADL\n");
 940                 return -EINVAL;
 941         }
 942
 943         tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
 944         if (tWHR > 3) {
 945                 dev_err(nfc->dev, "unsupported tWHR\n");
 946                 return -EINVAL;
 947         }
 948
 949         tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
 950                                         min_clk_period);
 951         if (tRHW < 0) {
 952                 dev_err(nfc->dev, "unsupported tRHW\n");
 953                 return tRHW;
 954         }
 955
 956         /*
 957          * TODO: according to ONFI specs this value only applies for DDR NAND,
 958          * but Allwinner seems to set this to 0x7. Mimic them for now.
 959          */
 960         tCAD = 0x7;
 961
 962         /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
 963         chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
 964
 965         /*
 966          * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
 967          * output cycle timings shall be used if the host drives tRC less than
 968          * 30 ns.
 969          */
 970         chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
 971
 972         /* Convert min_clk_period from picoseconds to nanoseconds */
 973         min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
 974
 975         /*
 976          * Convert min_clk_period into a clk frequency, then get the
 977          * appropriate rate for the NAND controller IP given this formula
 978          * (specified in the datasheet):
 979          * nand clk_rate = 2 * min_clk_rate
 980          */
 981         chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;
 982
 983         return 0;
 984 }
 985
 986 static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
 987                                         struct device_node *np)
 988 {
 989         const struct nand_sdr_timings *timings;
 990         int ret;
 991         int mode;
 992
 993         mode = onfi_get_async_timing_mode(&chip->nand);
 994         if (mode == ONFI_TIMING_MODE_UNKNOWN) {
 995                 mode = chip->nand.onfi_timing_mode_default;
 996         } else {
 997                 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
 998                 int i;
 999
1000                 mode = fls(mode) - 1;
1001                 if (mode < 0)
1002                         mode = 0;
1003
1004                 feature[0] = mode;
1005                 for (i = 0; i < chip->nsels; i++) {
1006                         chip->nand.select_chip(&chip->mtd, i);
1007                         ret = chip->nand.onfi_set_features(&chip->mtd,
1008                                                 &chip->nand,
1009                                                 ONFI_FEATURE_ADDR_TIMING_MODE,
1010                                                 feature);
1011                         chip->nand.select_chip(&chip->mtd, -1);
1012                         if (ret)
1013                                 return ret;
1014                 }
1015         }
1016
1017         timings = onfi_async_timing_mode_to_sdr_timings(mode);
1018         if (IS_ERR(timings))
1019                 return PTR_ERR(timings);
1020
1021         return sunxi_nand_chip_set_timings(chip, timings);
1022 }
1023
1024 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1025                                               struct nand_ecc_ctrl *ecc,
1026                                               struct device_node *np)
1027 {
1028         static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1029         struct nand_chip *nand = mtd->priv;
1030         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1031         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1032         struct sunxi_nand_hw_ecc *data;
1033         struct nand_ecclayout *layout;
1034         int nsectors;
1035         int ret;
1036         int i;
1037
1038         data = kzalloc(sizeof(*data), GFP_KERNEL);
1039         if (!data)
1040                 return -ENOMEM;
1041
1042         /* Add ECC info retrieval from DT */
1043         for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1044                 if (ecc->strength <= strengths[i])
1045                         break;
1046         }
1047
1048         if (i >= ARRAY_SIZE(strengths)) {
1049                 dev_err(nfc->dev, "unsupported strength\n");
1050                 ret = -ENOTSUPP;
1051                 goto err;
1052         }
1053
1054         data->mode = i;
1055
1056         /* HW ECC always request ECC bytes for 1024 bytes blocks */
1057         ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1058
1059         /* HW ECC always work with even numbers of ECC bytes */
1060         ecc->bytes = ALIGN(ecc->bytes, 2);
1061
1062         layout = &data->layout;
1063         nsectors = mtd->writesize / ecc->size;
1064
1065         if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1066                 ret = -EINVAL;
1067                 goto err;
1068         }
1069
1070         layout->eccbytes = (ecc->bytes * nsectors);
1071
1072         ecc->layout = layout;
1073         ecc->priv = data;
1074
1075         return 0;
1076
1077 err:
1078         kfree(data);
1079
1080         return ret;
1081 }
1082
1083 static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1084 {
1085         kfree(ecc->priv);
1086 }
1087
1088 static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1089                                        struct nand_ecc_ctrl *ecc,
1090                                        struct device_node *np)
1091 {
1092         struct nand_ecclayout *layout;
1093         int nsectors;
1094         int i, j;
1095         int ret;
1096
1097         ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1098         if (ret)
1099                 return ret;
1100
1101         ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1102         ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1103         layout = ecc->layout;
1104         nsectors = mtd->writesize / ecc->size;
1105
1106         for (i = 0; i < nsectors; i++) {
1107                 if (i) {
1108                         layout->oobfree[i].offset =
1109                                 layout->oobfree[i - 1].offset +
1110                                 layout->oobfree[i - 1].length +
1111                                 ecc->bytes;
1112                         layout->oobfree[i].length = 4;
1113                 } else {
1114                         /*
1115                          * The first 2 bytes are used for BB markers, hence we
1116                          * only have 2 bytes available in the first user data
1117                          * section.
1118                          */
1119                         layout->oobfree[i].length = 2;
1120                         layout->oobfree[i].offset = 2;
1121                 }
1122
1123                 for (j = 0; j < ecc->bytes; j++)
1124                         layout->eccpos[(ecc->bytes * i) + j] =
1125                                         layout->oobfree[i].offset +
1126                                         layout->oobfree[i].length + j;
1127         }
1128
1129         if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
1130                 layout->oobfree[nsectors].offset =
1131                                 layout->oobfree[nsectors - 1].offset +
1132                                 layout->oobfree[nsectors - 1].length +
1133                                 ecc->bytes;
1134                 layout->oobfree[nsectors].length = mtd->oobsize -
1135                                 ((ecc->bytes + 4) * nsectors);
1136         }
1137
1138         return 0;
1139 }
1140
1141 static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1142                                                 struct nand_ecc_ctrl *ecc,
1143                                                 struct device_node *np)
1144 {
1145         struct nand_ecclayout *layout;
1146         int nsectors;
1147         int i;
1148         int ret;
1149
1150         ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1151         if (ret)
1152                 return ret;
1153
1154         ecc->prepad = 4;
1155         ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1156         ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1157
1158         layout = ecc->layout;
1159         nsectors = mtd->writesize / ecc->size;
1160
1161         for (i = 0; i < (ecc->bytes * nsectors); i++)
1162                 layout->eccpos[i] = i;
1163
1164         layout->oobfree[0].length = mtd->oobsize - i;
1165         layout->oobfree[0].offset = i;
1166
1167         return 0;
1168 }
1169
1170 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1171 {
1172         switch (ecc->mode) {
1173         case NAND_ECC_HW:
1174         case NAND_ECC_HW_SYNDROME:
1175                 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1176                 break;
1177         case NAND_ECC_NONE:
1178                 kfree(ecc->layout);
1179         default:
1180                 break;
1181         }
1182 }
1183
1184 static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
1185                                struct device_node *np)
1186 {
1187         struct nand_chip *nand = mtd->priv;
1188         int ret;
1189
1190         if (!ecc->size) {
1191                 ecc->size = nand->ecc_step_ds;
1192                 ecc->strength = nand->ecc_strength_ds;
1193         }
1194
1195         if (!ecc->size || !ecc->strength)
1196                 return -EINVAL;
1197
1198         switch (ecc->mode) {
1199         case NAND_ECC_SOFT_BCH:
1200                 break;
1201         case NAND_ECC_HW:
1202                 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
1203                 if (ret)
1204                         return ret;
1205                 break;
1206         case NAND_ECC_HW_SYNDROME:
1207                 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np);
1208                 if (ret)
1209                         return ret;
1210                 break;
1211         case NAND_ECC_NONE:
1212                 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
1213                 if (!ecc->layout)
1214                         return -ENOMEM;
1215                 ecc->layout->oobfree[0].length = mtd->oobsize;
1216         case NAND_ECC_SOFT:
1217                 break;
1218         default:
1219                 return -EINVAL;
1220         }
1221
1222         return 0;
1223 }
1224
1225 static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1226                                 struct device_node *np)
1227 {
1228         const struct nand_sdr_timings *timings;
1229         struct sunxi_nand_chip *chip;
1230         struct mtd_part_parser_data ppdata;
1231         struct mtd_info *mtd;
1232         struct nand_chip *nand;
1233         int nsels;
1234         int ret;
1235         int i;
1236         u32 tmp;
1237
1238         if (!of_get_property(np, "reg", &nsels))
1239                 return -EINVAL;
1240
1241         nsels /= sizeof(u32);
1242         if (!nsels) {
1243                 dev_err(dev, "invalid reg property size\n");
1244                 return -EINVAL;
1245         }
1246
1247         chip = devm_kzalloc(dev,
1248                             sizeof(*chip) +
1249                             (nsels * sizeof(struct sunxi_nand_chip_sel)),
1250                             GFP_KERNEL);
1251         if (!chip) {
1252                 dev_err(dev, "could not allocate chip\n");
1253                 return -ENOMEM;
1254         }
1255
1256         chip->nsels = nsels;
1257         chip->selected = -1;
1258
1259         for (i = 0; i < nsels; i++) {
1260                 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1261                 if (ret) {
1262                         dev_err(dev, "could not retrieve reg property: %d\n",
1263                                 ret);
1264                         return ret;
1265                 }
1266
1267                 if (tmp > NFC_MAX_CS) {
1268                         dev_err(dev,
1269                                 "invalid reg value: %u (max CS = 7)\n",
1270                                 tmp);
1271                         return -EINVAL;
1272                 }
1273
1274                 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1275                         dev_err(dev, "CS %d already assigned\n", tmp);
1276                         return -EINVAL;
1277                 }
1278
1279                 chip->sels[i].cs = tmp;
1280
1281                 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
1282                     tmp < 2) {
1283                         chip->sels[i].rb.type = RB_NATIVE;
1284                         chip->sels[i].rb.info.nativeid = tmp;
1285                 } else {
1286                         ret = of_get_named_gpio(np, "rb-gpios", i);
1287                         if (ret >= 0) {
1288                                 tmp = ret;
1289                                 chip->sels[i].rb.type = RB_GPIO;
1290                                 chip->sels[i].rb.info.gpio = tmp;
1291                                 ret = devm_gpio_request(dev, tmp, "nand-rb");
1292                                 if (ret)
1293                                         return ret;
1294
1295                                 ret = gpio_direction_input(tmp);
1296                                 if (ret)
1297                                         return ret;
1298                         } else {
1299                                 chip->sels[i].rb.type = RB_NONE;
1300                         }
1301                 }
1302         }
1303
1304         timings = onfi_async_timing_mode_to_sdr_timings(0);
1305         if (IS_ERR(timings)) {
1306                 ret = PTR_ERR(timings);
1307                 dev_err(dev,
1308                         "could not retrieve timings for ONFI mode 0: %d\n",
1309                         ret);
1310                 return ret;
1311         }
1312
1313         ret = sunxi_nand_chip_set_timings(chip, timings);
1314         if (ret) {
1315                 dev_err(dev, "could not configure chip timings: %d\n", ret);
1316                 return ret;
1317         }
1318
1319         nand = &chip->nand;
1320         /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1321         nand->chip_delay = 200;
1322         nand->controller = &nfc->controller;
1323         /*
1324          * Set the ECC mode to the default value in case nothing is specified
1325          * in the DT.
1326          */
1327         nand->ecc.mode = NAND_ECC_HW;
1328         nand->flash_node = np;
1329         nand->select_chip = sunxi_nfc_select_chip;
1330         nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
1331         nand->read_buf = sunxi_nfc_read_buf;
1332         nand->write_buf = sunxi_nfc_write_buf;
1333         nand->read_byte = sunxi_nfc_read_byte;
1334
1335         mtd = &chip->mtd;
1336         mtd->dev.parent = dev;
1337         mtd->priv = nand;
1338         mtd->owner = THIS_MODULE;
1339
1340         ret = nand_scan_ident(mtd, nsels, NULL);
1341         if (ret)
1342                 return ret;
1343
1344         if (nand->bbt_options & NAND_BBT_USE_FLASH)
1345                 nand->bbt_options |= NAND_BBT_NO_OOB;
1346
1347         ret = sunxi_nand_chip_init_timings(chip, np);
1348         if (ret) {
1349                 dev_err(dev, "could not configure chip timings: %d\n", ret);
1350                 return ret;
1351         }
1352
1353         ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np);
1354         if (ret) {
1355                 dev_err(dev, "ECC init failed: %d\n", ret);
1356                 return ret;
1357         }
1358
1359         ret = nand_scan_tail(mtd);
1360         if (ret) {
1361                 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1362                 return ret;
1363         }
1364
1365         ppdata.of_node = np;
1366         ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1367         if (ret) {
1368                 dev_err(dev, "failed to register mtd device: %d\n", ret);
1369                 nand_release(mtd);
1370                 return ret;
1371         }
1372
1373         list_add_tail(&chip->node, &nfc->chips);
1374
1375         return 0;
1376 }
1377
1378 static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
1379 {
1380         struct device_node *np = dev->of_node;
1381         struct device_node *nand_np;
1382         int nchips = of_get_child_count(np);
1383         int ret;
1384
1385         if (nchips > 8) {
1386                 dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips);
1387                 return -EINVAL;
1388         }
1389
1390         for_each_child_of_node(np, nand_np) {
1391                 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
1392                 if (ret)
1393                         return ret;
1394         }
1395
1396         return 0;
1397 }
1398
1399 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1400 {
1401         struct sunxi_nand_chip *chip;
1402
1403         while (!list_empty(&nfc->chips)) {
1404                 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
1405                                         node);
1406                 nand_release(&chip->mtd);
1407                 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
1408                 list_del(&chip->node);
1409         }
1410 }
1411
1412 static int sunxi_nfc_probe(struct platform_device *pdev)
1413 {
1414         struct device *dev = &pdev->dev;
1415         struct resource *r;
1416         struct sunxi_nfc *nfc;
1417         int irq;
1418         int ret;
1419
1420         nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1421         if (!nfc)
1422                 return -ENOMEM;
1423
1424         nfc->dev = dev;
1425         spin_lock_init(&nfc->controller.lock);
1426         init_waitqueue_head(&nfc->controller.wq);
1427         INIT_LIST_HEAD(&nfc->chips);
1428
1429         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1430         nfc->regs = devm_ioremap_resource(dev, r);
1431         if (IS_ERR(nfc->regs))
1432                 return PTR_ERR(nfc->regs);
1433
1434         irq = platform_get_irq(pdev, 0);
1435         if (irq < 0) {
1436                 dev_err(dev, "failed to retrieve irq\n");
1437                 return irq;
1438         }
1439
1440         nfc->ahb_clk = devm_clk_get(dev, "ahb");
1441         if (IS_ERR(nfc->ahb_clk)) {
1442                 dev_err(dev, "failed to retrieve ahb clk\n");
1443                 return PTR_ERR(nfc->ahb_clk);
1444         }
1445
1446         ret = clk_prepare_enable(nfc->ahb_clk);
1447         if (ret)
1448                 return ret;
1449
1450         nfc->mod_clk = devm_clk_get(dev, "mod");
1451         if (IS_ERR(nfc->mod_clk)) {
1452                 dev_err(dev, "failed to retrieve mod clk\n");
1453                 ret = PTR_ERR(nfc->mod_clk);
1454                 goto out_ahb_clk_unprepare;
1455         }
1456
1457         ret = clk_prepare_enable(nfc->mod_clk);
1458         if (ret)
1459                 goto out_ahb_clk_unprepare;
1460
1461         ret = sunxi_nfc_rst(nfc);
1462         if (ret)
1463                 goto out_mod_clk_unprepare;
1464
1465         writel(0, nfc->regs + NFC_REG_INT);
1466         ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt,
1467                                0, "sunxi-nand", nfc);
1468         if (ret)
1469                 goto out_mod_clk_unprepare;
1470
1471         platform_set_drvdata(pdev, nfc);
1472
1473         ret = sunxi_nand_chips_init(dev, nfc);
1474         if (ret) {
1475                 dev_err(dev, "failed to init nand chips\n");
1476                 goto out_mod_clk_unprepare;
1477         }
1478
1479         return 0;
1480
1481 out_mod_clk_unprepare:
1482         clk_disable_unprepare(nfc->mod_clk);
1483 out_ahb_clk_unprepare:
1484         clk_disable_unprepare(nfc->ahb_clk);
1485
1486         return ret;
1487 }
1488
1489 static int sunxi_nfc_remove(struct platform_device *pdev)
1490 {
1491         struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
1492
1493         sunxi_nand_chips_cleanup(nfc);
1494
1495         return 0;
1496 }
1497
1498 static const struct of_device_id sunxi_nfc_ids[] = {
1499         { .compatible = "allwinner,sun4i-a10-nand" },
1500         { /* sentinel */ }
1501 };
1502 MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
1503
1504 static struct platform_driver sunxi_nfc_driver = {
1505         .driver = {
1506                 .name = "sunxi_nand",
1507                 .of_match_table = sunxi_nfc_ids,
1508         },
1509         .probe = sunxi_nfc_probe,
1510         .remove = sunxi_nfc_remove,
1511 };
1512 module_platform_driver(sunxi_nfc_driver);
1513
1514 MODULE_LICENSE("GPL v2");
1515 MODULE_AUTHOR("Boris BREZILLON");
1516 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
1517 MODULE_ALIAS("platform:sunxi_nand");