drivers/net/can/c_can/c_can_platform.c

   1 /*
   2  * Platform CAN bus driver for Bosch C_CAN controller
   3  *
   4  * Copyright (C) 2010 ST Microelectronics
   5  * Bhupesh Sharma <bhupesh.sharma@st.com>
   6  *
   7  * Borrowed heavily from the C_CAN driver originally written by:
   8  * Copyright (C) 2007
   9  * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
  10  * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
  11  *
  12  * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
  13  * Bosch C_CAN user manual can be obtained from:
  14  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
  15  * users_manual_c_can.pdf
  16  *
  17  * This file is licensed under the terms of the GNU General Public
  18  * License version 2. This program is licensed "as is" without any
  19  * warranty of any kind, whether express or implied.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/if_arp.h>
  28 #include <linux/if_ether.h>
  29 #include <linux/list.h>
  30 #include <linux/io.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/clk.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/mfd/syscon.h>
  36 #include <linux/regmap.h>
  37
  38 #include <linux/can/dev.h>
  39
  40 #include "c_can.h"
  41
  42 #define DCAN_RAM_INIT_BIT               (1 << 3)
  43 static DEFINE_SPINLOCK(raminit_lock);
  44 /*
  45  * 16-bit c_can registers can be arranged differently in the memory
  46  * architecture of different implementations. For example: 16-bit
  47  * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
  48  * Handle the same by providing a common read/write interface.
  49  */
  50 static u16 c_can_plat_read_reg_aligned_to_16bit(const struct c_can_priv *priv,
  51                                                 enum reg index)
  52 {
  53         return readw(priv->base + priv->regs[index]);
  54 }
  55
  56 static void c_can_plat_write_reg_aligned_to_16bit(const struct c_can_priv *priv,
  57                                                 enum reg index, u16 val)
  58 {
  59         writew(val, priv->base + priv->regs[index]);
  60 }
  61
  62 static u16 c_can_plat_read_reg_aligned_to_32bit(const struct c_can_priv *priv,
  63                                                 enum reg index)
  64 {
  65         return readw(priv->base + 2 * priv->regs[index]);
  66 }
  67
  68 static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
  69                                                 enum reg index, u16 val)
  70 {
  71         writew(val, priv->base + 2 * priv->regs[index]);
  72 }
  73
  74 static void c_can_hw_raminit_wait_syscon(const struct c_can_priv *priv,
  75                                          u32 mask, u32 val)
  76 {
  77         const struct c_can_raminit *raminit = &priv->raminit_sys;
  78         int timeout = 0;
  79         u32 ctrl = 0;
  80
  81         /* We look only at the bits of our instance. */
  82         val &= mask;
  83         do {
  84                 udelay(1);
  85                 timeout++;
  86
  87                 regmap_read(raminit->syscon, raminit->reg, &ctrl);
  88                 if (timeout == 1000) {
  89                         dev_err(&priv->dev->dev, "%s: time out\n", __func__);
  90                         break;
  91                 }
  92         } while ((ctrl & mask) != val);
  93 }
  94
  95 static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable)
  96 {
  97         const struct c_can_raminit *raminit = &priv->raminit_sys;
  98         u32 ctrl = 0;
  99         u32 mask;
 100
 101         spin_lock(&raminit_lock);
 102
 103         mask = 1 << raminit->bits.start | 1 << raminit->bits.done;
 104         regmap_read(raminit->syscon, raminit->reg, &ctrl);
 105
 106         /* We clear the done and start bit first. The start bit is
 107          * looking at the 0 -> transition, but is not self clearing;
 108          * And we clear the init done bit as well.
 109          * NOTE: DONE must be written with 1 to clear it.
 110          */
 111         ctrl &= ~(1 << raminit->bits.start);
 112         ctrl |= 1 << raminit->bits.done;
 113         regmap_write(raminit->syscon, raminit->reg, ctrl);
 114
 115         ctrl &= ~(1 << raminit->bits.done);
 116         c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
 117
 118         if (enable) {
 119                 /* Set start bit and wait for the done bit. */
 120                 ctrl |= 1 << raminit->bits.start;
 121                 regmap_write(raminit->syscon, raminit->reg, ctrl);
 122
 123                 /* clear START bit if start pulse is needed */
 124                 if (raminit->needs_pulse) {
 125                         ctrl &= ~(1 << raminit->bits.start);
 126                         regmap_write(raminit->syscon, raminit->reg, ctrl);
 127                 }
 128
 129                 ctrl |= 1 << raminit->bits.done;
 130                 c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
 131         }
 132         spin_unlock(&raminit_lock);
 133 }
 134
 135 static u32 c_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
 136 {
 137         u32 val;
 138
 139         val = priv->read_reg(priv, index);
 140         val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
 141
 142         return val;
 143 }
 144
 145 static void c_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
 146                 u32 val)
 147 {
 148         priv->write_reg(priv, index + 1, val >> 16);
 149         priv->write_reg(priv, index, val);
 150 }
 151
 152 static u32 d_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
 153 {
 154         return readl(priv->base + priv->regs[index]);
 155 }
 156
 157 static void d_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
 158                 u32 val)
 159 {
 160         writel(val, priv->base + priv->regs[index]);
 161 }
 162
 163 static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask)
 164 {
 165         while (priv->read_reg32(priv, C_CAN_FUNCTION_REG) & mask)
 166                 udelay(1);
 167 }
 168
 169 static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable)
 170 {
 171         u32 ctrl;
 172
 173         ctrl = priv->read_reg32(priv, C_CAN_FUNCTION_REG);
 174         ctrl &= ~DCAN_RAM_INIT_BIT;
 175         priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
 176         c_can_hw_raminit_wait(priv, ctrl);
 177
 178         if (enable) {
 179                 ctrl |= DCAN_RAM_INIT_BIT;
 180                 priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
 181                 c_can_hw_raminit_wait(priv, ctrl);
 182         }
 183 }
 184
 185 static const struct c_can_driver_data c_can_drvdata = {
 186         .id = BOSCH_C_CAN,
 187 };
 188
 189 static const struct c_can_driver_data d_can_drvdata = {
 190         .id = BOSCH_D_CAN,
 191 };
 192
 193 static const struct raminit_bits dra7_raminit_bits[] = {
 194         [0] = { .start = 3, .done = 1, },
 195         [1] = { .start = 5, .done = 2, },
 196 };
 197
 198 static const struct c_can_driver_data dra7_dcan_drvdata = {
 199         .id = BOSCH_D_CAN,
 200         .raminit_num = ARRAY_SIZE(dra7_raminit_bits),
 201         .raminit_bits = dra7_raminit_bits,
 202         .raminit_pulse = true,
 203 };
 204
 205 static const struct raminit_bits am3352_raminit_bits[] = {
 206         [0] = { .start = 0, .done = 8, },
 207         [1] = { .start = 1, .done = 9, },
 208 };
 209
 210 static const struct c_can_driver_data am3352_dcan_drvdata = {
 211         .id = BOSCH_D_CAN,
 212         .raminit_num = ARRAY_SIZE(am3352_raminit_bits),
 213         .raminit_bits = am3352_raminit_bits,
 214 };
 215
 216 static struct platform_device_id c_can_id_table[] = {
 217         {
 218                 .name = KBUILD_MODNAME,
 219                 .driver_data = (kernel_ulong_t)&c_can_drvdata,
 220         },
 221         {
 222                 .name = "c_can",
 223                 .driver_data = (kernel_ulong_t)&c_can_drvdata,
 224         },
 225         {
 226                 .name = "d_can",
 227                 .driver_data = (kernel_ulong_t)&d_can_drvdata,
 228         },
 229         { /* sentinel */ },
 230 };
 231 MODULE_DEVICE_TABLE(platform, c_can_id_table);
 232
 233 static const struct of_device_id c_can_of_table[] = {
 234         { .compatible = "bosch,c_can", .data = &c_can_drvdata },
 235         { .compatible = "bosch,d_can", .data = &d_can_drvdata },
 236         { .compatible = "ti,dra7-d_can", .data = &dra7_dcan_drvdata },
 237         { .compatible = "ti,am3352-d_can", .data = &am3352_dcan_drvdata },
 238         { /* sentinel */ },
 239 };
 240 MODULE_DEVICE_TABLE(of, c_can_of_table);
 241
 242 static int c_can_plat_probe(struct platform_device *pdev)
 243 {
 244         int ret;
 245         void __iomem *addr;
 246         struct net_device *dev;
 247         struct c_can_priv *priv;
 248         const struct of_device_id *match;
 249         struct resource *mem;
 250         int irq;
 251         struct clk *clk;
 252         const struct c_can_driver_data *drvdata;
 253         struct device_node *np = pdev->dev.of_node;
 254
 255         match = of_match_device(c_can_of_table, &pdev->dev);
 256         if (match) {
 257                 drvdata = match->data;
 258         } else if (pdev->id_entry->driver_data) {
 259                 drvdata = (struct c_can_driver_data *)
 260                         platform_get_device_id(pdev)->driver_data;
 261         } else {
 262                 return -ENODEV;
 263         }
 264
 265         /* get the appropriate clk */
 266         clk = devm_clk_get(&pdev->dev, NULL);
 267         if (IS_ERR(clk)) {
 268                 ret = PTR_ERR(clk);
 269                 goto exit;
 270         }
 271
 272         /* get the platform data */
 273         irq = platform_get_irq(pdev, 0);
 274         if (irq <= 0) {
 275                 ret = -ENODEV;
 276                 goto exit;
 277         }
 278
 279         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 280         addr = devm_ioremap_resource(&pdev->dev, mem);
 281         if (IS_ERR(addr)) {
 282                 ret =  PTR_ERR(addr);
 283                 goto exit;
 284         }
 285
 286         /* allocate the c_can device */
 287         dev = alloc_c_can_dev();
 288         if (!dev) {
 289                 ret = -ENOMEM;
 290                 goto exit;
 291         }
 292
 293         priv = netdev_priv(dev);
 294         switch (drvdata->id) {
 295         case BOSCH_C_CAN:
 296                 priv->regs = reg_map_c_can;
 297                 switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) {
 298                 case IORESOURCE_MEM_32BIT:
 299                         priv->read_reg = c_can_plat_read_reg_aligned_to_32bit;
 300                         priv->write_reg = c_can_plat_write_reg_aligned_to_32bit;
 301                         priv->read_reg32 = c_can_plat_read_reg32;
 302                         priv->write_reg32 = c_can_plat_write_reg32;
 303                         break;
 304                 case IORESOURCE_MEM_16BIT:
 305                 default:
 306                         priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
 307                         priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
 308                         priv->read_reg32 = c_can_plat_read_reg32;
 309                         priv->write_reg32 = c_can_plat_write_reg32;
 310                         break;
 311                 }
 312                 break;
 313         case BOSCH_D_CAN:
 314                 priv->regs = reg_map_d_can;
 315                 priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
 316                 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
 317                 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
 318                 priv->read_reg32 = d_can_plat_read_reg32;
 319                 priv->write_reg32 = d_can_plat_write_reg32;
 320
 321                 /* Check if we need custom RAMINIT via syscon. Mostly for TI
 322                  * platforms. Only supported with DT boot.
 323                  */
 324                 if (np && of_property_read_bool(np, "syscon-raminit")) {
 325                         u32 id;
 326                         struct c_can_raminit *raminit = &priv->raminit_sys;
 327
 328                         ret = -EINVAL;
 329                         raminit->syscon = syscon_regmap_lookup_by_phandle(np,
 330                                                                           "syscon-raminit");
 331                         if (IS_ERR(raminit->syscon)) {
 332                                 /* can fail with -EPROBE_DEFER */
 333                                 ret = PTR_ERR(raminit->syscon);
 334                                 free_c_can_dev(dev);
 335                                 return ret;
 336                         }
 337
 338                         if (of_property_read_u32_index(np, "syscon-raminit", 1,
 339                                                        &raminit->reg)) {
 340                                 dev_err(&pdev->dev,
 341                                         "couldn't get the RAMINIT reg. offset!\n");
 342                                 goto exit_free_device;
 343                         }
 344
 345                         if (of_property_read_u32_index(np, "syscon-raminit", 2,
 346                                                        &id)) {
 347                                 dev_err(&pdev->dev,
 348                                         "couldn't get the CAN instance ID\n");
 349                                 goto exit_free_device;
 350                         }
 351
 352                         if (id >= drvdata->raminit_num) {
 353                                 dev_err(&pdev->dev,
 354                                         "Invalid CAN instance ID\n");
 355                                 goto exit_free_device;
 356                         }
 357
 358                         raminit->bits = drvdata->raminit_bits[id];
 359                         raminit->needs_pulse = drvdata->raminit_pulse;
 360
 361                         priv->raminit = c_can_hw_raminit_syscon;
 362                 } else {
 363                         priv->raminit = c_can_hw_raminit;
 364                 }
 365                 break;
 366         default:
 367                 ret = -EINVAL;
 368                 goto exit_free_device;
 369         }
 370
 371         dev->irq = irq;
 372         priv->base = addr;
 373         priv->device = &pdev->dev;
 374         priv->can.clock.freq = clk_get_rate(clk);
 375         priv->priv = clk;
 376         priv->type = drvdata->id;
 377
 378         platform_set_drvdata(pdev, dev);
 379         SET_NETDEV_DEV(dev, &pdev->dev);
 380
 381         ret = register_c_can_dev(dev);
 382         if (ret) {
 383                 dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
 384                         KBUILD_MODNAME, ret);
 385                 goto exit_free_device;
 386         }
 387
 388         dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
 389                  KBUILD_MODNAME, priv->base, dev->irq);
 390         return 0;
 391
 392 exit_free_device:
 393         free_c_can_dev(dev);
 394 exit:
 395         dev_err(&pdev->dev, "probe failed\n");
 396
 397         return ret;
 398 }
 399
 400 static int c_can_plat_remove(struct platform_device *pdev)
 401 {
 402         struct net_device *dev = platform_get_drvdata(pdev);
 403
 404         unregister_c_can_dev(dev);
 405
 406         free_c_can_dev(dev);
 407
 408         return 0;
 409 }
 410
 411 #ifdef CONFIG_PM
 412 static int c_can_suspend(struct platform_device *pdev, pm_message_t state)
 413 {
 414         int ret;
 415         struct net_device *ndev = platform_get_drvdata(pdev);
 416         struct c_can_priv *priv = netdev_priv(ndev);
 417
 418         if (priv->type != BOSCH_D_CAN) {
 419                 dev_warn(&pdev->dev, "Not supported\n");
 420                 return 0;
 421         }
 422
 423         if (netif_running(ndev)) {
 424                 netif_stop_queue(ndev);
 425                 netif_device_detach(ndev);
 426         }
 427
 428         ret = c_can_power_down(ndev);
 429         if (ret) {
 430                 netdev_err(ndev, "failed to enter power down mode\n");
 431                 return ret;
 432         }
 433
 434         priv->can.state = CAN_STATE_SLEEPING;
 435
 436         return 0;
 437 }
 438
 439 static int c_can_resume(struct platform_device *pdev)
 440 {
 441         int ret;
 442         struct net_device *ndev = platform_get_drvdata(pdev);
 443         struct c_can_priv *priv = netdev_priv(ndev);
 444
 445         if (priv->type != BOSCH_D_CAN) {
 446                 dev_warn(&pdev->dev, "Not supported\n");
 447                 return 0;
 448         }
 449
 450         ret = c_can_power_up(ndev);
 451         if (ret) {
 452                 netdev_err(ndev, "Still in power down mode\n");
 453                 return ret;
 454         }
 455
 456         priv->can.state = CAN_STATE_ERROR_ACTIVE;
 457
 458         if (netif_running(ndev)) {
 459                 netif_device_attach(ndev);
 460                 netif_start_queue(ndev);
 461         }
 462
 463         return 0;
 464 }
 465 #else
 466 #define c_can_suspend NULL
 467 #define c_can_resume NULL
 468 #endif
 469
 470 static struct platform_driver c_can_plat_driver = {
 471         .driver = {
 472                 .name = KBUILD_MODNAME,
 473                 .owner = THIS_MODULE,
 474                 .of_match_table = c_can_of_table,
 475         },
 476         .probe = c_can_plat_probe,
 477         .remove = c_can_plat_remove,
 478         .suspend = c_can_suspend,
 479         .resume = c_can_resume,
 480         .id_table = c_can_id_table,
 481 };
 482
 483 module_platform_driver(c_can_plat_driver);
 484
 485 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
 486 MODULE_LICENSE("GPL v2");
 487 MODULE_DESCRIPTION("Platform CAN bus driver for Bosch C_CAN controller");