drivers/net/dsa/b53/b53_common.c

   1 /*
   2  * B53 switch driver main logic
   3  *
   4  * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
   5  * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/delay.h>
  23 #include <linux/export.h>
  24 #include <linux/gpio.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_data/b53.h>
  28 #include <linux/phy.h>
  29 #include <linux/phylink.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/if_bridge.h>
  32 #include <net/dsa.h>
  33
  34 #include "b53_regs.h"
  35 #include "b53_priv.h"
  36
  37 struct b53_mib_desc {
  38         u8 size;
  39         u8 offset;
  40         const char *name;
  41 };
  42
  43 /* BCM5365 MIB counters */
  44 static const struct b53_mib_desc b53_mibs_65[] = {
  45         { 8, 0x00, "TxOctets" },
  46         { 4, 0x08, "TxDropPkts" },
  47         { 4, 0x10, "TxBroadcastPkts" },
  48         { 4, 0x14, "TxMulticastPkts" },
  49         { 4, 0x18, "TxUnicastPkts" },
  50         { 4, 0x1c, "TxCollisions" },
  51         { 4, 0x20, "TxSingleCollision" },
  52         { 4, 0x24, "TxMultipleCollision" },
  53         { 4, 0x28, "TxDeferredTransmit" },
  54         { 4, 0x2c, "TxLateCollision" },
  55         { 4, 0x30, "TxExcessiveCollision" },
  56         { 4, 0x38, "TxPausePkts" },
  57         { 8, 0x44, "RxOctets" },
  58         { 4, 0x4c, "RxUndersizePkts" },
  59         { 4, 0x50, "RxPausePkts" },
  60         { 4, 0x54, "Pkts64Octets" },
  61         { 4, 0x58, "Pkts65to127Octets" },
  62         { 4, 0x5c, "Pkts128to255Octets" },
  63         { 4, 0x60, "Pkts256to511Octets" },
  64         { 4, 0x64, "Pkts512to1023Octets" },
  65         { 4, 0x68, "Pkts1024to1522Octets" },
  66         { 4, 0x6c, "RxOversizePkts" },
  67         { 4, 0x70, "RxJabbers" },
  68         { 4, 0x74, "RxAlignmentErrors" },
  69         { 4, 0x78, "RxFCSErrors" },
  70         { 8, 0x7c, "RxGoodOctets" },
  71         { 4, 0x84, "RxDropPkts" },
  72         { 4, 0x88, "RxUnicastPkts" },
  73         { 4, 0x8c, "RxMulticastPkts" },
  74         { 4, 0x90, "RxBroadcastPkts" },
  75         { 4, 0x94, "RxSAChanges" },
  76         { 4, 0x98, "RxFragments" },
  77 };
  78
  79 #define B53_MIBS_65_SIZE        ARRAY_SIZE(b53_mibs_65)
  80
  81 /* BCM63xx MIB counters */
  82 static const struct b53_mib_desc b53_mibs_63xx[] = {
  83         { 8, 0x00, "TxOctets" },
  84         { 4, 0x08, "TxDropPkts" },
  85         { 4, 0x0c, "TxQoSPkts" },
  86         { 4, 0x10, "TxBroadcastPkts" },
  87         { 4, 0x14, "TxMulticastPkts" },
  88         { 4, 0x18, "TxUnicastPkts" },
  89         { 4, 0x1c, "TxCollisions" },
  90         { 4, 0x20, "TxSingleCollision" },
  91         { 4, 0x24, "TxMultipleCollision" },
  92         { 4, 0x28, "TxDeferredTransmit" },
  93         { 4, 0x2c, "TxLateCollision" },
  94         { 4, 0x30, "TxExcessiveCollision" },
  95         { 4, 0x38, "TxPausePkts" },
  96         { 8, 0x3c, "TxQoSOctets" },
  97         { 8, 0x44, "RxOctets" },
  98         { 4, 0x4c, "RxUndersizePkts" },
  99         { 4, 0x50, "RxPausePkts" },
 100         { 4, 0x54, "Pkts64Octets" },
 101         { 4, 0x58, "Pkts65to127Octets" },
 102         { 4, 0x5c, "Pkts128to255Octets" },
 103         { 4, 0x60, "Pkts256to511Octets" },
 104         { 4, 0x64, "Pkts512to1023Octets" },
 105         { 4, 0x68, "Pkts1024to1522Octets" },
 106         { 4, 0x6c, "RxOversizePkts" },
 107         { 4, 0x70, "RxJabbers" },
 108         { 4, 0x74, "RxAlignmentErrors" },
 109         { 4, 0x78, "RxFCSErrors" },
 110         { 8, 0x7c, "RxGoodOctets" },
 111         { 4, 0x84, "RxDropPkts" },
 112         { 4, 0x88, "RxUnicastPkts" },
 113         { 4, 0x8c, "RxMulticastPkts" },
 114         { 4, 0x90, "RxBroadcastPkts" },
 115         { 4, 0x94, "RxSAChanges" },
 116         { 4, 0x98, "RxFragments" },
 117         { 4, 0xa0, "RxSymbolErrors" },
 118         { 4, 0xa4, "RxQoSPkts" },
 119         { 8, 0xa8, "RxQoSOctets" },
 120         { 4, 0xb0, "Pkts1523to2047Octets" },
 121         { 4, 0xb4, "Pkts2048to4095Octets" },
 122         { 4, 0xb8, "Pkts4096to8191Octets" },
 123         { 4, 0xbc, "Pkts8192to9728Octets" },
 124         { 4, 0xc0, "RxDiscarded" },
 125 };
 126
 127 #define B53_MIBS_63XX_SIZE      ARRAY_SIZE(b53_mibs_63xx)
 128
 129 /* MIB counters */
 130 static const struct b53_mib_desc b53_mibs[] = {
 131         { 8, 0x00, "TxOctets" },
 132         { 4, 0x08, "TxDropPkts" },
 133         { 4, 0x10, "TxBroadcastPkts" },
 134         { 4, 0x14, "TxMulticastPkts" },
 135         { 4, 0x18, "TxUnicastPkts" },
 136         { 4, 0x1c, "TxCollisions" },
 137         { 4, 0x20, "TxSingleCollision" },
 138         { 4, 0x24, "TxMultipleCollision" },
 139         { 4, 0x28, "TxDeferredTransmit" },
 140         { 4, 0x2c, "TxLateCollision" },
 141         { 4, 0x30, "TxExcessiveCollision" },
 142         { 4, 0x38, "TxPausePkts" },
 143         { 8, 0x50, "RxOctets" },
 144         { 4, 0x58, "RxUndersizePkts" },
 145         { 4, 0x5c, "RxPausePkts" },
 146         { 4, 0x60, "Pkts64Octets" },
 147         { 4, 0x64, "Pkts65to127Octets" },
 148         { 4, 0x68, "Pkts128to255Octets" },
 149         { 4, 0x6c, "Pkts256to511Octets" },
 150         { 4, 0x70, "Pkts512to1023Octets" },
 151         { 4, 0x74, "Pkts1024to1522Octets" },
 152         { 4, 0x78, "RxOversizePkts" },
 153         { 4, 0x7c, "RxJabbers" },
 154         { 4, 0x80, "RxAlignmentErrors" },
 155         { 4, 0x84, "RxFCSErrors" },
 156         { 8, 0x88, "RxGoodOctets" },
 157         { 4, 0x90, "RxDropPkts" },
 158         { 4, 0x94, "RxUnicastPkts" },
 159         { 4, 0x98, "RxMulticastPkts" },
 160         { 4, 0x9c, "RxBroadcastPkts" },
 161         { 4, 0xa0, "RxSAChanges" },
 162         { 4, 0xa4, "RxFragments" },
 163         { 4, 0xa8, "RxJumboPkts" },
 164         { 4, 0xac, "RxSymbolErrors" },
 165         { 4, 0xc0, "RxDiscarded" },
 166 };
 167
 168 #define B53_MIBS_SIZE   ARRAY_SIZE(b53_mibs)
 169
 170 static const struct b53_mib_desc b53_mibs_58xx[] = {
 171         { 8, 0x00, "TxOctets" },
 172         { 4, 0x08, "TxDropPkts" },
 173         { 4, 0x0c, "TxQPKTQ0" },
 174         { 4, 0x10, "TxBroadcastPkts" },
 175         { 4, 0x14, "TxMulticastPkts" },
 176         { 4, 0x18, "TxUnicastPKts" },
 177         { 4, 0x1c, "TxCollisions" },
 178         { 4, 0x20, "TxSingleCollision" },
 179         { 4, 0x24, "TxMultipleCollision" },
 180         { 4, 0x28, "TxDeferredCollision" },
 181         { 4, 0x2c, "TxLateCollision" },
 182         { 4, 0x30, "TxExcessiveCollision" },
 183         { 4, 0x34, "TxFrameInDisc" },
 184         { 4, 0x38, "TxPausePkts" },
 185         { 4, 0x3c, "TxQPKTQ1" },
 186         { 4, 0x40, "TxQPKTQ2" },
 187         { 4, 0x44, "TxQPKTQ3" },
 188         { 4, 0x48, "TxQPKTQ4" },
 189         { 4, 0x4c, "TxQPKTQ5" },
 190         { 8, 0x50, "RxOctets" },
 191         { 4, 0x58, "RxUndersizePkts" },
 192         { 4, 0x5c, "RxPausePkts" },
 193         { 4, 0x60, "RxPkts64Octets" },
 194         { 4, 0x64, "RxPkts65to127Octets" },
 195         { 4, 0x68, "RxPkts128to255Octets" },
 196         { 4, 0x6c, "RxPkts256to511Octets" },
 197         { 4, 0x70, "RxPkts512to1023Octets" },
 198         { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
 199         { 4, 0x78, "RxOversizePkts" },
 200         { 4, 0x7c, "RxJabbers" },
 201         { 4, 0x80, "RxAlignmentErrors" },
 202         { 4, 0x84, "RxFCSErrors" },
 203         { 8, 0x88, "RxGoodOctets" },
 204         { 4, 0x90, "RxDropPkts" },
 205         { 4, 0x94, "RxUnicastPkts" },
 206         { 4, 0x98, "RxMulticastPkts" },
 207         { 4, 0x9c, "RxBroadcastPkts" },
 208         { 4, 0xa0, "RxSAChanges" },
 209         { 4, 0xa4, "RxFragments" },
 210         { 4, 0xa8, "RxJumboPkt" },
 211         { 4, 0xac, "RxSymblErr" },
 212         { 4, 0xb0, "InRangeErrCount" },
 213         { 4, 0xb4, "OutRangeErrCount" },
 214         { 4, 0xb8, "EEELpiEvent" },
 215         { 4, 0xbc, "EEELpiDuration" },
 216         { 4, 0xc0, "RxDiscard" },
 217         { 4, 0xc8, "TxQPKTQ6" },
 218         { 4, 0xcc, "TxQPKTQ7" },
 219         { 4, 0xd0, "TxPkts64Octets" },
 220         { 4, 0xd4, "TxPkts65to127Octets" },
 221         { 4, 0xd8, "TxPkts128to255Octets" },
 222         { 4, 0xdc, "TxPkts256to511Ocets" },
 223         { 4, 0xe0, "TxPkts512to1023Ocets" },
 224         { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
 225 };
 226
 227 #define B53_MIBS_58XX_SIZE      ARRAY_SIZE(b53_mibs_58xx)
 228
 229 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
 230 {
 231         unsigned int i;
 232
 233         b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
 234
 235         for (i = 0; i < 10; i++) {
 236                 u8 vta;
 237
 238                 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
 239                 if (!(vta & VTA_START_CMD))
 240                         return 0;
 241
 242                 usleep_range(100, 200);
 243         }
 244
 245         return -EIO;
 246 }
 247
 248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
 249                                struct b53_vlan *vlan)
 250 {
 251         if (is5325(dev)) {
 252                 u32 entry = 0;
 253
 254                 if (vlan->members) {
 255                         entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
 256                                  VA_UNTAG_S_25) | vlan->members;
 257                         if (dev->core_rev >= 3)
 258                                 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
 259                         else
 260                                 entry |= VA_VALID_25;
 261                 }
 262
 263                 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
 264                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 265                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 266         } else if (is5365(dev)) {
 267                 u16 entry = 0;
 268
 269                 if (vlan->members)
 270                         entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
 271                                  VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
 272
 273                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
 274                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 275                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 276         } else {
 277                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 278                 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
 279                             (vlan->untag << VTE_UNTAG_S) | vlan->members);
 280
 281                 b53_do_vlan_op(dev, VTA_CMD_WRITE);
 282         }
 283
 284         dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
 285                 vid, vlan->members, vlan->untag);
 286 }
 287
 288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
 289                                struct b53_vlan *vlan)
 290 {
 291         if (is5325(dev)) {
 292                 u32 entry = 0;
 293
 294                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 295                             VTA_RW_STATE_RD | VTA_RW_OP_EN);
 296                 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
 297
 298                 if (dev->core_rev >= 3)
 299                         vlan->valid = !!(entry & VA_VALID_25_R4);
 300                 else
 301                         vlan->valid = !!(entry & VA_VALID_25);
 302                 vlan->members = entry & VA_MEMBER_MASK;
 303                 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
 304
 305         } else if (is5365(dev)) {
 306                 u16 entry = 0;
 307
 308                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 309                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 310                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
 311
 312                 vlan->valid = !!(entry & VA_VALID_65);
 313                 vlan->members = entry & VA_MEMBER_MASK;
 314                 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
 315         } else {
 316                 u32 entry = 0;
 317
 318                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 319                 b53_do_vlan_op(dev, VTA_CMD_READ);
 320                 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
 321                 vlan->members = entry & VTE_MEMBERS;
 322                 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
 323                 vlan->valid = true;
 324         }
 325 }
 326
 327 static void b53_set_forwarding(struct b53_device *dev, int enable)
 328 {
 329         u8 mgmt;
 330
 331         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 332
 333         if (enable)
 334                 mgmt |= SM_SW_FWD_EN;
 335         else
 336                 mgmt &= ~SM_SW_FWD_EN;
 337
 338         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 339
 340         /* Include IMP port in dumb forwarding mode
 341          */
 342         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
 343         mgmt |= B53_MII_DUMB_FWDG_EN;
 344         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
 345 }
 346
 347 static void b53_enable_vlan(struct b53_device *dev, bool enable)
 348 {
 349         u8 mgmt, vc0, vc1, vc4 = 0, vc5;
 350
 351         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 352         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
 353         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
 354
 355         if (is5325(dev) || is5365(dev)) {
 356                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
 357                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
 358         } else if (is63xx(dev)) {
 359                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
 360                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
 361         } else {
 362                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
 363                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
 364         }
 365
 366         mgmt &= ~SM_SW_FWD_MODE;
 367
 368         if (enable) {
 369                 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
 370                 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
 371                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 372                 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
 373                 vc5 |= VC5_DROP_VTABLE_MISS;
 374
 375                 if (is5325(dev))
 376                         vc0 &= ~VC0_RESERVED_1;
 377
 378                 if (is5325(dev) || is5365(dev))
 379                         vc1 |= VC1_RX_MCST_TAG_EN;
 380
 381         } else {
 382                 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
 383                 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
 384                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 385                 vc5 &= ~VC5_DROP_VTABLE_MISS;
 386
 387                 if (is5325(dev) || is5365(dev))
 388                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 389                 else
 390                         vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
 391
 392                 if (is5325(dev) || is5365(dev))
 393                         vc1 &= ~VC1_RX_MCST_TAG_EN;
 394         }
 395
 396         if (!is5325(dev) && !is5365(dev))
 397                 vc5 &= ~VC5_VID_FFF_EN;
 398
 399         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
 400         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
 401
 402         if (is5325(dev) || is5365(dev)) {
 403                 /* enable the high 8 bit vid check on 5325 */
 404                 if (is5325(dev) && enable)
 405                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
 406                                    VC3_HIGH_8BIT_EN);
 407                 else
 408                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 409
 410                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
 411                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
 412         } else if (is63xx(dev)) {
 413                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
 414                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
 415                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
 416         } else {
 417                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 418                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
 419                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
 420         }
 421
 422         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 423 }
 424
 425 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
 426 {
 427         u32 port_mask = 0;
 428         u16 max_size = JMS_MIN_SIZE;
 429
 430         if (is5325(dev) || is5365(dev))
 431                 return -EINVAL;
 432
 433         if (enable) {
 434                 port_mask = dev->enabled_ports;
 435                 max_size = JMS_MAX_SIZE;
 436                 if (allow_10_100)
 437                         port_mask |= JPM_10_100_JUMBO_EN;
 438         }
 439
 440         b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
 441         return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
 442 }
 443
 444 static int b53_flush_arl(struct b53_device *dev, u8 mask)
 445 {
 446         unsigned int i;
 447
 448         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 449                    FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
 450
 451         for (i = 0; i < 10; i++) {
 452                 u8 fast_age_ctrl;
 453
 454                 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 455                           &fast_age_ctrl);
 456
 457                 if (!(fast_age_ctrl & FAST_AGE_DONE))
 458                         goto out;
 459
 460                 msleep(1);
 461         }
 462
 463         return -ETIMEDOUT;
 464 out:
 465         /* Only age dynamic entries (default behavior) */
 466         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
 467         return 0;
 468 }
 469
 470 static int b53_fast_age_port(struct b53_device *dev, int port)
 471 {
 472         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
 473
 474         return b53_flush_arl(dev, FAST_AGE_PORT);
 475 }
 476
 477 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
 478 {
 479         b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
 480
 481         return b53_flush_arl(dev, FAST_AGE_VLAN);
 482 }
 483
 484 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
 485 {
 486         struct b53_device *dev = ds->priv;
 487         unsigned int i;
 488         u16 pvlan;
 489
 490         /* Enable the IMP port to be in the same VLAN as the other ports
 491          * on a per-port basis such that we only have Port i and IMP in
 492          * the same VLAN.
 493          */
 494         b53_for_each_port(dev, i) {
 495                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
 496                 pvlan |= BIT(cpu_port);
 497                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
 498         }
 499 }
 500 EXPORT_SYMBOL(b53_imp_vlan_setup);
 501
 502 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 503 {
 504         struct b53_device *dev = ds->priv;
 505         unsigned int cpu_port = ds->ports[port].cpu_dp->index;
 506         int ret = 0;
 507         u16 pvlan;
 508
 509         if (dev->ops->irq_enable)
 510                 ret = dev->ops->irq_enable(dev, port);
 511         if (ret)
 512                 return ret;
 513
 514         /* Clear the Rx and Tx disable bits and set to no spanning tree */
 515         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
 516
 517         /* Set this port, and only this one to be in the default VLAN,
 518          * if member of a bridge, restore its membership prior to
 519          * bringing down this port.
 520          */
 521         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
 522         pvlan &= ~0x1ff;
 523         pvlan |= BIT(port);
 524         pvlan |= dev->ports[port].vlan_ctl_mask;
 525         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
 526
 527         b53_imp_vlan_setup(ds, cpu_port);
 528
 529         /* If EEE was enabled, restore it */
 530         if (dev->ports[port].eee.eee_enabled)
 531                 b53_eee_enable_set(ds, port, true);
 532
 533         return 0;
 534 }
 535 EXPORT_SYMBOL(b53_enable_port);
 536
 537 void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 538 {
 539         struct b53_device *dev = ds->priv;
 540         u8 reg;
 541
 542         /* Disable Tx/Rx for the port */
 543         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
 544         reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
 545         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
 546
 547         if (dev->ops->irq_disable)
 548                 dev->ops->irq_disable(dev, port);
 549 }
 550 EXPORT_SYMBOL(b53_disable_port);
 551
 552 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
 553 {
 554         bool tag_en = !(ds->ops->get_tag_protocol(ds, port) ==
 555                          DSA_TAG_PROTO_NONE);
 556         struct b53_device *dev = ds->priv;
 557         u8 hdr_ctl, val;
 558         u16 reg;
 559
 560         /* Resolve which bit controls the Broadcom tag */
 561         switch (port) {
 562         case 8:
 563                 val = BRCM_HDR_P8_EN;
 564                 break;
 565         case 7:
 566                 val = BRCM_HDR_P7_EN;
 567                 break;
 568         case 5:
 569                 val = BRCM_HDR_P5_EN;
 570                 break;
 571         default:
 572                 val = 0;
 573                 break;
 574         }
 575
 576         /* Enable Broadcom tags for IMP port */
 577         b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
 578         if (tag_en)
 579                 hdr_ctl |= val;
 580         else
 581                 hdr_ctl &= ~val;
 582         b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
 583
 584         /* Registers below are only accessible on newer devices */
 585         if (!is58xx(dev))
 586                 return;
 587
 588         /* Enable reception Broadcom tag for CPU TX (switch RX) to
 589          * allow us to tag outgoing frames
 590          */
 591         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
 592         if (tag_en)
 593                 reg &= ~BIT(port);
 594         else
 595                 reg |= BIT(port);
 596         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
 597
 598         /* Enable transmission of Broadcom tags from the switch (CPU RX) to
 599          * allow delivering frames to the per-port net_devices
 600          */
 601         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
 602         if (tag_en)
 603                 reg &= ~BIT(port);
 604         else
 605                 reg |= BIT(port);
 606         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
 607 }
 608 EXPORT_SYMBOL(b53_brcm_hdr_setup);
 609
 610 static void b53_enable_cpu_port(struct b53_device *dev, int port)
 611 {
 612         u8 port_ctrl;
 613
 614         /* BCM5325 CPU port is at 8 */
 615         if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
 616                 port = B53_CPU_PORT;
 617
 618         port_ctrl = PORT_CTRL_RX_BCST_EN |
 619                     PORT_CTRL_RX_MCST_EN |
 620                     PORT_CTRL_RX_UCST_EN;
 621         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
 622
 623         b53_brcm_hdr_setup(dev->ds, port);
 624 }
 625
 626 static void b53_enable_mib(struct b53_device *dev)
 627 {
 628         u8 gc;
 629
 630         b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 631         gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
 632         b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
 633 }
 634
 635 int b53_configure_vlan(struct dsa_switch *ds)
 636 {
 637         struct b53_device *dev = ds->priv;
 638         struct b53_vlan vl = { 0 };
 639         int i;
 640
 641         /* clear all vlan entries */
 642         if (is5325(dev) || is5365(dev)) {
 643                 for (i = 1; i < dev->num_vlans; i++)
 644                         b53_set_vlan_entry(dev, i, &vl);
 645         } else {
 646                 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
 647         }
 648
 649         b53_enable_vlan(dev, false);
 650
 651         b53_for_each_port(dev, i)
 652                 b53_write16(dev, B53_VLAN_PAGE,
 653                             B53_VLAN_PORT_DEF_TAG(i), 1);
 654
 655         if (!is5325(dev) && !is5365(dev))
 656                 b53_set_jumbo(dev, dev->enable_jumbo, false);
 657
 658         return 0;
 659 }
 660 EXPORT_SYMBOL(b53_configure_vlan);
 661
 662 static void b53_switch_reset_gpio(struct b53_device *dev)
 663 {
 664         int gpio = dev->reset_gpio;
 665
 666         if (gpio < 0)
 667                 return;
 668
 669         /* Reset sequence: RESET low(50ms)->high(20ms)
 670          */
 671         gpio_set_value(gpio, 0);
 672         mdelay(50);
 673
 674         gpio_set_value(gpio, 1);
 675         mdelay(20);
 676
 677         dev->current_page = 0xff;
 678 }
 679
 680 static int b53_switch_reset(struct b53_device *dev)
 681 {
 682         unsigned int timeout = 1000;
 683         u8 mgmt, reg;
 684
 685         b53_switch_reset_gpio(dev);
 686
 687         if (is539x(dev)) {
 688                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
 689                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
 690         }
 691
 692         /* This is specific to 58xx devices here, do not use is58xx() which
 693          * covers the larger Starfigther 2 family, including 7445/7278 which
 694          * still use this driver as a library and need to perform the reset
 695          * earlier.
 696          */
 697         if (dev->chip_id == BCM58XX_DEVICE_ID ||
 698             dev->chip_id == BCM583XX_DEVICE_ID) {
 699                 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 700                 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
 701                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
 702
 703                 do {
 704                         b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 705                         if (!(reg & SW_RST))
 706                                 break;
 707
 708                         usleep_range(1000, 2000);
 709                 } while (timeout-- > 0);
 710
 711                 if (timeout == 0)
 712                         return -ETIMEDOUT;
 713         }
 714
 715         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 716
 717         if (!(mgmt & SM_SW_FWD_EN)) {
 718                 mgmt &= ~SM_SW_FWD_MODE;
 719                 mgmt |= SM_SW_FWD_EN;
 720
 721                 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 722                 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 723
 724                 if (!(mgmt & SM_SW_FWD_EN)) {
 725                         dev_err(dev->dev, "Failed to enable switch!\n");
 726                         return -EINVAL;
 727                 }
 728         }
 729
 730         b53_enable_mib(dev);
 731
 732         return b53_flush_arl(dev, FAST_AGE_STATIC);
 733 }
 734
 735 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
 736 {
 737         struct b53_device *priv = ds->priv;
 738         u16 value = 0;
 739         int ret;
 740
 741         if (priv->ops->phy_read16)
 742                 ret = priv->ops->phy_read16(priv, addr, reg, &value);
 743         else
 744                 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
 745                                  reg * 2, &value);
 746
 747         return ret ? ret : value;
 748 }
 749
 750 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
 751 {
 752         struct b53_device *priv = ds->priv;
 753
 754         if (priv->ops->phy_write16)
 755                 return priv->ops->phy_write16(priv, addr, reg, val);
 756
 757         return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
 758 }
 759
 760 static int b53_reset_switch(struct b53_device *priv)
 761 {
 762         /* reset vlans */
 763         priv->enable_jumbo = false;
 764
 765         memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
 766         memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
 767
 768         priv->serdes_lane = B53_INVALID_LANE;
 769
 770         return b53_switch_reset(priv);
 771 }
 772
 773 static int b53_apply_config(struct b53_device *priv)
 774 {
 775         /* disable switching */
 776         b53_set_forwarding(priv, 0);
 777
 778         b53_configure_vlan(priv->ds);
 779
 780         /* enable switching */
 781         b53_set_forwarding(priv, 1);
 782
 783         return 0;
 784 }
 785
 786 static void b53_reset_mib(struct b53_device *priv)
 787 {
 788         u8 gc;
 789
 790         b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 791
 792         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
 793         msleep(1);
 794         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
 795         msleep(1);
 796 }
 797
 798 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
 799 {
 800         if (is5365(dev))
 801                 return b53_mibs_65;
 802         else if (is63xx(dev))
 803                 return b53_mibs_63xx;
 804         else if (is58xx(dev))
 805                 return b53_mibs_58xx;
 806         else
 807                 return b53_mibs;
 808 }
 809
 810 static unsigned int b53_get_mib_size(struct b53_device *dev)
 811 {
 812         if (is5365(dev))
 813                 return B53_MIBS_65_SIZE;
 814         else if (is63xx(dev))
 815                 return B53_MIBS_63XX_SIZE;
 816         else if (is58xx(dev))
 817                 return B53_MIBS_58XX_SIZE;
 818         else
 819                 return B53_MIBS_SIZE;
 820 }
 821
 822 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
 823 {
 824         /* These ports typically do not have built-in PHYs */
 825         switch (port) {
 826         case B53_CPU_PORT_25:
 827         case 7:
 828         case B53_CPU_PORT:
 829                 return NULL;
 830         }
 831
 832         return mdiobus_get_phy(ds->slave_mii_bus, port);
 833 }
 834
 835 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
 836                      uint8_t *data)
 837 {
 838         struct b53_device *dev = ds->priv;
 839         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 840         unsigned int mib_size = b53_get_mib_size(dev);
 841         struct phy_device *phydev;
 842         unsigned int i;
 843
 844         if (stringset == ETH_SS_STATS) {
 845                 for (i = 0; i < mib_size; i++)
 846                         strlcpy(data + i * ETH_GSTRING_LEN,
 847                                 mibs[i].name, ETH_GSTRING_LEN);
 848         } else if (stringset == ETH_SS_PHY_STATS) {
 849                 phydev = b53_get_phy_device(ds, port);
 850                 if (!phydev)
 851                         return;
 852
 853                 phy_ethtool_get_strings(phydev, data);
 854         }
 855 }
 856 EXPORT_SYMBOL(b53_get_strings);
 857
 858 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
 859 {
 860         struct b53_device *dev = ds->priv;
 861         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 862         unsigned int mib_size = b53_get_mib_size(dev);
 863         const struct b53_mib_desc *s;
 864         unsigned int i;
 865         u64 val = 0;
 866
 867         if (is5365(dev) && port == 5)
 868                 port = 8;
 869
 870         mutex_lock(&dev->stats_mutex);
 871
 872         for (i = 0; i < mib_size; i++) {
 873                 s = &mibs[i];
 874
 875                 if (s->size == 8) {
 876                         b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
 877                 } else {
 878                         u32 val32;
 879
 880                         b53_read32(dev, B53_MIB_PAGE(port), s->offset,
 881                                    &val32);
 882                         val = val32;
 883                 }
 884                 data[i] = (u64)val;
 885         }
 886
 887         mutex_unlock(&dev->stats_mutex);
 888 }
 889 EXPORT_SYMBOL(b53_get_ethtool_stats);
 890
 891 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
 892 {
 893         struct phy_device *phydev;
 894
 895         phydev = b53_get_phy_device(ds, port);
 896         if (!phydev)
 897                 return;
 898
 899         phy_ethtool_get_stats(phydev, NULL, data);
 900 }
 901 EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
 902
 903 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
 904 {
 905         struct b53_device *dev = ds->priv;
 906         struct phy_device *phydev;
 907
 908         if (sset == ETH_SS_STATS) {
 909                 return b53_get_mib_size(dev);
 910         } else if (sset == ETH_SS_PHY_STATS) {
 911                 phydev = b53_get_phy_device(ds, port);
 912                 if (!phydev)
 913                         return 0;
 914
 915                 return phy_ethtool_get_sset_count(phydev);
 916         }
 917
 918         return 0;
 919 }
 920 EXPORT_SYMBOL(b53_get_sset_count);
 921
 922 static int b53_setup(struct dsa_switch *ds)
 923 {
 924         struct b53_device *dev = ds->priv;
 925         unsigned int port;
 926         int ret;
 927
 928         ret = b53_reset_switch(dev);
 929         if (ret) {
 930                 dev_err(ds->dev, "failed to reset switch\n");
 931                 return ret;
 932         }
 933
 934         b53_reset_mib(dev);
 935
 936         ret = b53_apply_config(dev);
 937         if (ret)
 938                 dev_err(ds->dev, "failed to apply configuration\n");
 939
 940         /* Configure IMP/CPU port, disable unused ports. Enabled
 941          * ports will be configured with .port_enable
 942          */
 943         for (port = 0; port < dev->num_ports; port++) {
 944                 if (dsa_is_cpu_port(ds, port))
 945                         b53_enable_cpu_port(dev, port);
 946                 else if (dsa_is_unused_port(ds, port))
 947                         b53_disable_port(ds, port, NULL);
 948         }
 949
 950         return ret;
 951 }
 952
 953 static void b53_force_link(struct b53_device *dev, int port, int link)
 954 {
 955         u8 reg, val, off;
 956
 957         /* Override the port settings */
 958         if (port == dev->cpu_port) {
 959                 off = B53_PORT_OVERRIDE_CTRL;
 960                 val = PORT_OVERRIDE_EN;
 961         } else {
 962                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
 963                 val = GMII_PO_EN;
 964         }
 965
 966         b53_read8(dev, B53_CTRL_PAGE, off, &reg);
 967         reg |= val;
 968         if (link)
 969                 reg |= PORT_OVERRIDE_LINK;
 970         else
 971                 reg &= ~PORT_OVERRIDE_LINK;
 972         b53_write8(dev, B53_CTRL_PAGE, off, reg);
 973 }
 974
 975 static void b53_force_port_config(struct b53_device *dev, int port,
 976                                   int speed, int duplex, int pause)
 977 {
 978         u8 reg, val, off;
 979
 980         /* Override the port settings */
 981         if (port == dev->cpu_port) {
 982                 off = B53_PORT_OVERRIDE_CTRL;
 983                 val = PORT_OVERRIDE_EN;
 984         } else {
 985                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
 986                 val = GMII_PO_EN;
 987         }
 988
 989         b53_read8(dev, B53_CTRL_PAGE, off, &reg);
 990         reg |= val;
 991         if (duplex == DUPLEX_FULL)
 992                 reg |= PORT_OVERRIDE_FULL_DUPLEX;
 993         else
 994                 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
 995
 996         switch (speed) {
 997         case 2000:
 998                 reg |= PORT_OVERRIDE_SPEED_2000M;
 999                 /* fallthrough */
1000         case SPEED_1000:
1001                 reg |= PORT_OVERRIDE_SPEED_1000M;
1002                 break;
1003         case SPEED_100:
1004                 reg |= PORT_OVERRIDE_SPEED_100M;
1005                 break;
1006         case SPEED_10:
1007                 reg |= PORT_OVERRIDE_SPEED_10M;
1008                 break;
1009         default:
1010                 dev_err(dev->dev, "unknown speed: %d\n", speed);
1011                 return;
1012         }
1013
1014         if (pause & MLO_PAUSE_RX)
1015                 reg |= PORT_OVERRIDE_RX_FLOW;
1016         if (pause & MLO_PAUSE_TX)
1017                 reg |= PORT_OVERRIDE_TX_FLOW;
1018
1019         b53_write8(dev, B53_CTRL_PAGE, off, reg);
1020 }
1021
1022 static void b53_adjust_link(struct dsa_switch *ds, int port,
1023                             struct phy_device *phydev)
1024 {
1025         struct b53_device *dev = ds->priv;
1026         struct ethtool_eee *p = &dev->ports[port].eee;
1027         u8 rgmii_ctrl = 0, reg = 0, off;
1028         int pause = 0;
1029
1030         if (!phy_is_pseudo_fixed_link(phydev))
1031                 return;
1032
1033         /* Enable flow control on BCM5301x's CPU port */
1034         if (is5301x(dev) && port == dev->cpu_port)
1035                 pause = MLO_PAUSE_TXRX_MASK;
1036
1037         if (phydev->pause) {
1038                 if (phydev->asym_pause)
1039                         pause |= MLO_PAUSE_TX;
1040                 pause |= MLO_PAUSE_RX;
1041         }
1042
1043         b53_force_port_config(dev, port, phydev->speed, phydev->duplex, pause);
1044         b53_force_link(dev, port, phydev->link);
1045
1046         if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1047                 if (port == 8)
1048                         off = B53_RGMII_CTRL_IMP;
1049                 else
1050                         off = B53_RGMII_CTRL_P(port);
1051
1052                 /* Configure the port RGMII clock delay by DLL disabled and
1053                  * tx_clk aligned timing (restoring to reset defaults)
1054                  */
1055                 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1056                 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1057                                 RGMII_CTRL_TIMING_SEL);
1058
1059                 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1060                  * sure that we enable the port TX clock internal delay to
1061                  * account for this internal delay that is inserted, otherwise
1062                  * the switch won't be able to receive correctly.
1063                  *
1064                  * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1065                  * any delay neither on transmission nor reception, so the
1066                  * BCM53125 must also be configured accordingly to account for
1067                  * the lack of delay and introduce
1068                  *
1069                  * The BCM53125 switch has its RX clock and TX clock control
1070                  * swapped, hence the reason why we modify the TX clock path in
1071                  * the "RGMII" case
1072                  */
1073                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1074                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1075                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1076                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1077                 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1078                 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1079
1080                 dev_info(ds->dev, "Configured port %d for %s\n", port,
1081                          phy_modes(phydev->interface));
1082         }
1083
1084         /* configure MII port if necessary */
1085         if (is5325(dev)) {
1086                 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1087                           &reg);
1088
1089                 /* reverse mii needs to be enabled */
1090                 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1091                         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1092                                    reg | PORT_OVERRIDE_RV_MII_25);
1093                         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1094                                   &reg);
1095
1096                         if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1097                                 dev_err(ds->dev,
1098                                         "Failed to enable reverse MII mode\n");
1099                                 return;
1100                         }
1101                 }
1102         } else if (is5301x(dev)) {
1103                 if (port != dev->cpu_port) {
1104                         b53_force_port_config(dev, dev->cpu_port, 2000,
1105                                               DUPLEX_FULL, MLO_PAUSE_TXRX_MASK);
1106                         b53_force_link(dev, dev->cpu_port, 1);
1107                 }
1108         }
1109
1110         /* Re-negotiate EEE if it was enabled already */
1111         p->eee_enabled = b53_eee_init(ds, port, phydev);
1112 }
1113
1114 void b53_port_event(struct dsa_switch *ds, int port)
1115 {
1116         struct b53_device *dev = ds->priv;
1117         bool link;
1118         u16 sts;
1119
1120         b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1121         link = !!(sts & BIT(port));
1122         dsa_port_phylink_mac_change(ds, port, link);
1123 }
1124 EXPORT_SYMBOL(b53_port_event);
1125
1126 void b53_phylink_validate(struct dsa_switch *ds, int port,
1127                           unsigned long *supported,
1128                           struct phylink_link_state *state)
1129 {
1130         struct b53_device *dev = ds->priv;
1131         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1132
1133         if (dev->ops->serdes_phylink_validate)
1134                 dev->ops->serdes_phylink_validate(dev, port, mask, state);
1135
1136         /* Allow all the expected bits */
1137         phylink_set(mask, Autoneg);
1138         phylink_set_port_modes(mask);
1139         phylink_set(mask, Pause);
1140         phylink_set(mask, Asym_Pause);
1141
1142         /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we
1143          * support Gigabit, including Half duplex.
1144          */
1145         if (state->interface != PHY_INTERFACE_MODE_MII &&
1146             state->interface != PHY_INTERFACE_MODE_REVMII &&
1147             !phy_interface_mode_is_8023z(state->interface) &&
1148             !(is5325(dev) || is5365(dev))) {
1149                 phylink_set(mask, 1000baseT_Full);
1150                 phylink_set(mask, 1000baseT_Half);
1151         }
1152
1153         if (!phy_interface_mode_is_8023z(state->interface)) {
1154                 phylink_set(mask, 10baseT_Half);
1155                 phylink_set(mask, 10baseT_Full);
1156                 phylink_set(mask, 100baseT_Half);
1157                 phylink_set(mask, 100baseT_Full);
1158         }
1159
1160         bitmap_and(supported, supported, mask,
1161                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1162         bitmap_and(state->advertising, state->advertising, mask,
1163                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1164
1165         phylink_helper_basex_speed(state);
1166 }
1167 EXPORT_SYMBOL(b53_phylink_validate);
1168
1169 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
1170                                struct phylink_link_state *state)
1171 {
1172         struct b53_device *dev = ds->priv;
1173         int ret = -EOPNOTSUPP;
1174
1175         if ((phy_interface_mode_is_8023z(state->interface) ||
1176              state->interface == PHY_INTERFACE_MODE_SGMII) &&
1177              dev->ops->serdes_link_state)
1178                 ret = dev->ops->serdes_link_state(dev, port, state);
1179
1180         return ret;
1181 }
1182 EXPORT_SYMBOL(b53_phylink_mac_link_state);
1183
1184 void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1185                             unsigned int mode,
1186                             const struct phylink_link_state *state)
1187 {
1188         struct b53_device *dev = ds->priv;
1189
1190         if (mode == MLO_AN_PHY)
1191                 return;
1192
1193         if (mode == MLO_AN_FIXED) {
1194                 b53_force_port_config(dev, port, state->speed,
1195                                       state->duplex, state->pause);
1196                 return;
1197         }
1198
1199         if ((phy_interface_mode_is_8023z(state->interface) ||
1200              state->interface == PHY_INTERFACE_MODE_SGMII) &&
1201              dev->ops->serdes_config)
1202                 dev->ops->serdes_config(dev, port, mode, state);
1203 }
1204 EXPORT_SYMBOL(b53_phylink_mac_config);
1205
1206 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port)
1207 {
1208         struct b53_device *dev = ds->priv;
1209
1210         if (dev->ops->serdes_an_restart)
1211                 dev->ops->serdes_an_restart(dev, port);
1212 }
1213 EXPORT_SYMBOL(b53_phylink_mac_an_restart);
1214
1215 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1216                                unsigned int mode,
1217                                phy_interface_t interface)
1218 {
1219         struct b53_device *dev = ds->priv;
1220
1221         if (mode == MLO_AN_PHY)
1222                 return;
1223
1224         if (mode == MLO_AN_FIXED) {
1225                 b53_force_link(dev, port, false);
1226                 return;
1227         }
1228
1229         if (phy_interface_mode_is_8023z(interface) &&
1230             dev->ops->serdes_link_set)
1231                 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1232 }
1233 EXPORT_SYMBOL(b53_phylink_mac_link_down);
1234
1235 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1236                              unsigned int mode,
1237                              phy_interface_t interface,
1238                              struct phy_device *phydev)
1239 {
1240         struct b53_device *dev = ds->priv;
1241
1242         if (mode == MLO_AN_PHY)
1243                 return;
1244
1245         if (mode == MLO_AN_FIXED) {
1246                 b53_force_link(dev, port, true);
1247                 return;
1248         }
1249
1250         if (phy_interface_mode_is_8023z(interface) &&
1251             dev->ops->serdes_link_set)
1252                 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1253 }
1254 EXPORT_SYMBOL(b53_phylink_mac_link_up);
1255
1256 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
1257 {
1258         return 0;
1259 }
1260 EXPORT_SYMBOL(b53_vlan_filtering);
1261
1262 int b53_vlan_prepare(struct dsa_switch *ds, int port,
1263                      const struct switchdev_obj_port_vlan *vlan)
1264 {
1265         struct b53_device *dev = ds->priv;
1266
1267         if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1268                 return -EOPNOTSUPP;
1269
1270         if (vlan->vid_end > dev->num_vlans)
1271                 return -ERANGE;
1272
1273         b53_enable_vlan(dev, true);
1274
1275         return 0;
1276 }
1277 EXPORT_SYMBOL(b53_vlan_prepare);
1278
1279 void b53_vlan_add(struct dsa_switch *ds, int port,
1280                   const struct switchdev_obj_port_vlan *vlan)
1281 {
1282         struct b53_device *dev = ds->priv;
1283         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1284         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1285         struct b53_vlan *vl;
1286         u16 vid;
1287
1288         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1289                 vl = &dev->vlans[vid];
1290
1291                 b53_get_vlan_entry(dev, vid, vl);
1292
1293                 vl->members |= BIT(port);
1294                 if (untagged && !dsa_is_cpu_port(ds, port))
1295                         vl->untag |= BIT(port);
1296                 else
1297                         vl->untag &= ~BIT(port);
1298
1299                 b53_set_vlan_entry(dev, vid, vl);
1300                 b53_fast_age_vlan(dev, vid);
1301         }
1302
1303         if (pvid) {
1304                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1305                             vlan->vid_end);
1306                 b53_fast_age_vlan(dev, vid);
1307         }
1308 }
1309 EXPORT_SYMBOL(b53_vlan_add);
1310
1311 int b53_vlan_del(struct dsa_switch *ds, int port,
1312                  const struct switchdev_obj_port_vlan *vlan)
1313 {
1314         struct b53_device *dev = ds->priv;
1315         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1316         struct b53_vlan *vl;
1317         u16 vid;
1318         u16 pvid;
1319
1320         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1321
1322         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1323                 vl = &dev->vlans[vid];
1324
1325                 b53_get_vlan_entry(dev, vid, vl);
1326
1327                 vl->members &= ~BIT(port);
1328
1329                 if (pvid == vid) {
1330                         if (is5325(dev) || is5365(dev))
1331                                 pvid = 1;
1332                         else
1333                                 pvid = 0;
1334                 }
1335
1336                 if (untagged && !dsa_is_cpu_port(ds, port))
1337                         vl->untag &= ~(BIT(port));
1338
1339                 b53_set_vlan_entry(dev, vid, vl);
1340                 b53_fast_age_vlan(dev, vid);
1341         }
1342
1343         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1344         b53_fast_age_vlan(dev, pvid);
1345
1346         return 0;
1347 }
1348 EXPORT_SYMBOL(b53_vlan_del);
1349
1350 /* Address Resolution Logic routines */
1351 static int b53_arl_op_wait(struct b53_device *dev)
1352 {
1353         unsigned int timeout = 10;
1354         u8 reg;
1355
1356         do {
1357                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1358                 if (!(reg & ARLTBL_START_DONE))
1359                         return 0;
1360
1361                 usleep_range(1000, 2000);
1362         } while (timeout--);
1363
1364         dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1365
1366         return -ETIMEDOUT;
1367 }
1368
1369 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1370 {
1371         u8 reg;
1372
1373         if (op > ARLTBL_RW)
1374                 return -EINVAL;
1375
1376         b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1377         reg |= ARLTBL_START_DONE;
1378         if (op)
1379                 reg |= ARLTBL_RW;
1380         else
1381                 reg &= ~ARLTBL_RW;
1382         b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1383
1384         return b53_arl_op_wait(dev);
1385 }
1386
1387 static int b53_arl_read(struct b53_device *dev, u64 mac,
1388                         u16 vid, struct b53_arl_entry *ent, u8 *idx,
1389                         bool is_valid)
1390 {
1391         unsigned int i;
1392         int ret;
1393
1394         ret = b53_arl_op_wait(dev);
1395         if (ret)
1396                 return ret;
1397
1398         /* Read the bins */
1399         for (i = 0; i < dev->num_arl_entries; i++) {
1400                 u64 mac_vid;
1401                 u32 fwd_entry;
1402
1403                 b53_read64(dev, B53_ARLIO_PAGE,
1404                            B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1405                 b53_read32(dev, B53_ARLIO_PAGE,
1406                            B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1407                 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1408
1409                 if (!(fwd_entry & ARLTBL_VALID))
1410                         continue;
1411                 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1412                         continue;
1413                 *idx = i;
1414         }
1415
1416         return -ENOENT;
1417 }
1418
1419 static int b53_arl_op(struct b53_device *dev, int op, int port,
1420                       const unsigned char *addr, u16 vid, bool is_valid)
1421 {
1422         struct b53_arl_entry ent;
1423         u32 fwd_entry;
1424         u64 mac, mac_vid = 0;
1425         u8 idx = 0;
1426         int ret;
1427
1428         /* Convert the array into a 64-bit MAC */
1429         mac = ether_addr_to_u64(addr);
1430
1431         /* Perform a read for the given MAC and VID */
1432         b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1433         b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1434
1435         /* Issue a read operation for this MAC */
1436         ret = b53_arl_rw_op(dev, 1);
1437         if (ret)
1438                 return ret;
1439
1440         ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1441         /* If this is a read, just finish now */
1442         if (op)
1443                 return ret;
1444
1445         /* We could not find a matching MAC, so reset to a new entry */
1446         if (ret) {
1447                 fwd_entry = 0;
1448                 idx = 1;
1449         }
1450
1451         memset(&ent, 0, sizeof(ent));
1452         ent.port = port;
1453         ent.is_valid = is_valid;
1454         ent.vid = vid;
1455         ent.is_static = true;
1456         memcpy(ent.mac, addr, ETH_ALEN);
1457         b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1458
1459         b53_write64(dev, B53_ARLIO_PAGE,
1460                     B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1461         b53_write32(dev, B53_ARLIO_PAGE,
1462                     B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1463
1464         return b53_arl_rw_op(dev, 0);
1465 }
1466
1467 int b53_fdb_add(struct dsa_switch *ds, int port,
1468                 const unsigned char *addr, u16 vid)
1469 {
1470         struct b53_device *priv = ds->priv;
1471
1472         /* 5325 and 5365 require some more massaging, but could
1473          * be supported eventually
1474          */
1475         if (is5325(priv) || is5365(priv))
1476                 return -EOPNOTSUPP;
1477
1478         return b53_arl_op(priv, 0, port, addr, vid, true);
1479 }
1480 EXPORT_SYMBOL(b53_fdb_add);
1481
1482 int b53_fdb_del(struct dsa_switch *ds, int port,
1483                 const unsigned char *addr, u16 vid)
1484 {
1485         struct b53_device *priv = ds->priv;
1486
1487         return b53_arl_op(priv, 0, port, addr, vid, false);
1488 }
1489 EXPORT_SYMBOL(b53_fdb_del);
1490
1491 static int b53_arl_search_wait(struct b53_device *dev)
1492 {
1493         unsigned int timeout = 1000;
1494         u8 reg;
1495
1496         do {
1497                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1498                 if (!(reg & ARL_SRCH_STDN))
1499                         return 0;
1500
1501                 if (reg & ARL_SRCH_VLID)
1502                         return 0;
1503
1504                 usleep_range(1000, 2000);
1505         } while (timeout--);
1506
1507         return -ETIMEDOUT;
1508 }
1509
1510 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1511                               struct b53_arl_entry *ent)
1512 {
1513         u64 mac_vid;
1514         u32 fwd_entry;
1515
1516         b53_read64(dev, B53_ARLIO_PAGE,
1517                    B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1518         b53_read32(dev, B53_ARLIO_PAGE,
1519                    B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1520         b53_arl_to_entry(ent, mac_vid, fwd_entry);
1521 }
1522
1523 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1524                         dsa_fdb_dump_cb_t *cb, void *data)
1525 {
1526         if (!ent->is_valid)
1527                 return 0;
1528
1529         if (port != ent->port)
1530                 return 0;
1531
1532         return cb(ent->mac, ent->vid, ent->is_static, data);
1533 }
1534
1535 int b53_fdb_dump(struct dsa_switch *ds, int port,
1536                  dsa_fdb_dump_cb_t *cb, void *data)
1537 {
1538         struct b53_device *priv = ds->priv;
1539         struct b53_arl_entry results[2];
1540         unsigned int count = 0;
1541         int ret;
1542         u8 reg;
1543
1544         /* Start search operation */
1545         reg = ARL_SRCH_STDN;
1546         b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1547
1548         do {
1549                 ret = b53_arl_search_wait(priv);
1550                 if (ret)
1551                         return ret;
1552
1553                 b53_arl_search_rd(priv, 0, &results[0]);
1554                 ret = b53_fdb_copy(port, &results[0], cb, data);
1555                 if (ret)
1556                         return ret;
1557
1558                 if (priv->num_arl_entries > 2) {
1559                         b53_arl_search_rd(priv, 1, &results[1]);
1560                         ret = b53_fdb_copy(port, &results[1], cb, data);
1561                         if (ret)
1562                                 return ret;
1563
1564                         if (!results[0].is_valid && !results[1].is_valid)
1565                                 break;
1566                 }
1567
1568         } while (count++ < 1024);
1569
1570         return 0;
1571 }
1572 EXPORT_SYMBOL(b53_fdb_dump);
1573
1574 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1575 {
1576         struct b53_device *dev = ds->priv;
1577         s8 cpu_port = ds->ports[port].cpu_dp->index;
1578         u16 pvlan, reg;
1579         unsigned int i;
1580
1581         /* Make this port leave the all VLANs join since we will have proper
1582          * VLAN entries from now on
1583          */
1584         if (is58xx(dev)) {
1585                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1586                 reg &= ~BIT(port);
1587                 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1588                         reg &= ~BIT(cpu_port);
1589                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1590         }
1591
1592         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1593
1594         b53_for_each_port(dev, i) {
1595                 if (dsa_to_port(ds, i)->bridge_dev != br)
1596                         continue;
1597
1598                 /* Add this local port to the remote port VLAN control
1599                  * membership and update the remote port bitmask
1600                  */
1601                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1602                 reg |= BIT(port);
1603                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1604                 dev->ports[i].vlan_ctl_mask = reg;
1605
1606                 pvlan |= BIT(i);
1607         }
1608
1609         /* Configure the local port VLAN control membership to include
1610          * remote ports and update the local port bitmask
1611          */
1612         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1613         dev->ports[port].vlan_ctl_mask = pvlan;
1614
1615         return 0;
1616 }
1617 EXPORT_SYMBOL(b53_br_join);
1618
1619 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1620 {
1621         struct b53_device *dev = ds->priv;
1622         struct b53_vlan *vl = &dev->vlans[0];
1623         s8 cpu_port = ds->ports[port].cpu_dp->index;
1624         unsigned int i;
1625         u16 pvlan, reg, pvid;
1626
1627         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1628
1629         b53_for_each_port(dev, i) {
1630                 /* Don't touch the remaining ports */
1631                 if (dsa_to_port(ds, i)->bridge_dev != br)
1632                         continue;
1633
1634                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1635                 reg &= ~BIT(port);
1636                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1637                 dev->ports[port].vlan_ctl_mask = reg;
1638
1639                 /* Prevent self removal to preserve isolation */
1640                 if (port != i)
1641                         pvlan &= ~BIT(i);
1642         }
1643
1644         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1645         dev->ports[port].vlan_ctl_mask = pvlan;
1646
1647         if (is5325(dev) || is5365(dev))
1648                 pvid = 1;
1649         else
1650                 pvid = 0;
1651
1652         /* Make this port join all VLANs without VLAN entries */
1653         if (is58xx(dev)) {
1654                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1655                 reg |= BIT(port);
1656                 if (!(reg & BIT(cpu_port)))
1657                         reg |= BIT(cpu_port);
1658                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1659         } else {
1660                 b53_get_vlan_entry(dev, pvid, vl);
1661                 vl->members |= BIT(port) | BIT(cpu_port);
1662                 vl->untag |= BIT(port) | BIT(cpu_port);
1663                 b53_set_vlan_entry(dev, pvid, vl);
1664         }
1665 }
1666 EXPORT_SYMBOL(b53_br_leave);
1667
1668 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1669 {
1670         struct b53_device *dev = ds->priv;
1671         u8 hw_state;
1672         u8 reg;
1673
1674         switch (state) {
1675         case BR_STATE_DISABLED:
1676                 hw_state = PORT_CTRL_DIS_STATE;
1677                 break;
1678         case BR_STATE_LISTENING:
1679                 hw_state = PORT_CTRL_LISTEN_STATE;
1680                 break;
1681         case BR_STATE_LEARNING:
1682                 hw_state = PORT_CTRL_LEARN_STATE;
1683                 break;
1684         case BR_STATE_FORWARDING:
1685                 hw_state = PORT_CTRL_FWD_STATE;
1686                 break;
1687         case BR_STATE_BLOCKING:
1688                 hw_state = PORT_CTRL_BLOCK_STATE;
1689                 break;
1690         default:
1691                 dev_err(ds->dev, "invalid STP state: %d\n", state);
1692                 return;
1693         }
1694
1695         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1696         reg &= ~PORT_CTRL_STP_STATE_MASK;
1697         reg |= hw_state;
1698         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1699 }
1700 EXPORT_SYMBOL(b53_br_set_stp_state);
1701
1702 void b53_br_fast_age(struct dsa_switch *ds, int port)
1703 {
1704         struct b53_device *dev = ds->priv;
1705
1706         if (b53_fast_age_port(dev, port))
1707                 dev_err(ds->dev, "fast ageing failed\n");
1708 }
1709 EXPORT_SYMBOL(b53_br_fast_age);
1710
1711 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
1712 {
1713         /* Broadcom switches will accept enabling Broadcom tags on the
1714          * following ports: 5, 7 and 8, any other port is not supported
1715          */
1716         switch (port) {
1717         case B53_CPU_PORT_25:
1718         case 7:
1719         case B53_CPU_PORT:
1720                 return true;
1721         }
1722
1723         return false;
1724 }
1725
1726 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port)
1727 {
1728         bool ret = b53_possible_cpu_port(ds, port);
1729
1730         if (!ret)
1731                 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
1732                          port);
1733         return ret;
1734 }
1735
1736 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port)
1737 {
1738         struct b53_device *dev = ds->priv;
1739
1740         /* Older models (5325, 5365) support a different tag format that we do
1741          * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed
1742          * mode to be turned on which means we need to specifically manage ARL
1743          * misses on multicast addresses (TBD).
1744          */
1745         if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) ||
1746             !b53_can_enable_brcm_tags(ds, port))
1747                 return DSA_TAG_PROTO_NONE;
1748
1749         /* Broadcom BCM58xx chips have a flow accelerator on Port 8
1750          * which requires us to use the prepended Broadcom tag type
1751          */
1752         if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT)
1753                 return DSA_TAG_PROTO_BRCM_PREPEND;
1754
1755         return DSA_TAG_PROTO_BRCM;
1756 }
1757 EXPORT_SYMBOL(b53_get_tag_protocol);
1758
1759 int b53_mirror_add(struct dsa_switch *ds, int port,
1760                    struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1761 {
1762         struct b53_device *dev = ds->priv;
1763         u16 reg, loc;
1764
1765         if (ingress)
1766                 loc = B53_IG_MIR_CTL;
1767         else
1768                 loc = B53_EG_MIR_CTL;
1769
1770         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1771         reg &= ~MIRROR_MASK;
1772         reg |= BIT(port);
1773         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1774
1775         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1776         reg &= ~CAP_PORT_MASK;
1777         reg |= mirror->to_local_port;
1778         reg |= MIRROR_EN;
1779         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1780
1781         return 0;
1782 }
1783 EXPORT_SYMBOL(b53_mirror_add);
1784
1785 void b53_mirror_del(struct dsa_switch *ds, int port,
1786                     struct dsa_mall_mirror_tc_entry *mirror)
1787 {
1788         struct b53_device *dev = ds->priv;
1789         bool loc_disable = false, other_loc_disable = false;
1790         u16 reg, loc;
1791
1792         if (mirror->ingress)
1793                 loc = B53_IG_MIR_CTL;
1794         else
1795                 loc = B53_EG_MIR_CTL;
1796
1797         /* Update the desired ingress/egress register */
1798         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1799         reg &= ~BIT(port);
1800         if (!(reg & MIRROR_MASK))
1801                 loc_disable = true;
1802         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1803
1804         /* Now look at the other one to know if we can disable mirroring
1805          * entirely
1806          */
1807         if (mirror->ingress)
1808                 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1809         else
1810                 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1811         if (!(reg & MIRROR_MASK))
1812                 other_loc_disable = true;
1813
1814         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1815         /* Both no longer have ports, let's disable mirroring */
1816         if (loc_disable && other_loc_disable) {
1817                 reg &= ~MIRROR_EN;
1818                 reg &= ~mirror->to_local_port;
1819         }
1820         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1821 }
1822 EXPORT_SYMBOL(b53_mirror_del);
1823
1824 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1825 {
1826         struct b53_device *dev = ds->priv;
1827         u16 reg;
1828
1829         b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1830         if (enable)
1831                 reg |= BIT(port);
1832         else
1833                 reg &= ~BIT(port);
1834         b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1835 }
1836 EXPORT_SYMBOL(b53_eee_enable_set);
1837
1838
1839 /* Returns 0 if EEE was not enabled, or 1 otherwise
1840  */
1841 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1842 {
1843         int ret;
1844
1845         ret = phy_init_eee(phy, 0);
1846         if (ret)
1847                 return 0;
1848
1849         b53_eee_enable_set(ds, port, true);
1850
1851         return 1;
1852 }
1853 EXPORT_SYMBOL(b53_eee_init);
1854
1855 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1856 {
1857         struct b53_device *dev = ds->priv;
1858         struct ethtool_eee *p = &dev->ports[port].eee;
1859         u16 reg;
1860
1861         if (is5325(dev) || is5365(dev))
1862                 return -EOPNOTSUPP;
1863
1864         b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1865         e->eee_enabled = p->eee_enabled;
1866         e->eee_active = !!(reg & BIT(port));
1867
1868         return 0;
1869 }
1870 EXPORT_SYMBOL(b53_get_mac_eee);
1871
1872 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1873 {
1874         struct b53_device *dev = ds->priv;
1875         struct ethtool_eee *p = &dev->ports[port].eee;
1876
1877         if (is5325(dev) || is5365(dev))
1878                 return -EOPNOTSUPP;
1879
1880         p->eee_enabled = e->eee_enabled;
1881         b53_eee_enable_set(ds, port, e->eee_enabled);
1882
1883         return 0;
1884 }
1885 EXPORT_SYMBOL(b53_set_mac_eee);
1886
1887 static const struct dsa_switch_ops b53_switch_ops = {
1888         .get_tag_protocol       = b53_get_tag_protocol,
1889         .setup                  = b53_setup,
1890         .get_strings            = b53_get_strings,
1891         .get_ethtool_stats      = b53_get_ethtool_stats,
1892         .get_sset_count         = b53_get_sset_count,
1893         .get_ethtool_phy_stats  = b53_get_ethtool_phy_stats,
1894         .phy_read               = b53_phy_read16,
1895         .phy_write              = b53_phy_write16,
1896         .adjust_link            = b53_adjust_link,
1897         .phylink_validate       = b53_phylink_validate,
1898         .phylink_mac_link_state = b53_phylink_mac_link_state,
1899         .phylink_mac_config     = b53_phylink_mac_config,
1900         .phylink_mac_an_restart = b53_phylink_mac_an_restart,
1901         .phylink_mac_link_down  = b53_phylink_mac_link_down,
1902         .phylink_mac_link_up    = b53_phylink_mac_link_up,
1903         .port_enable            = b53_enable_port,
1904         .port_disable           = b53_disable_port,
1905         .get_mac_eee            = b53_get_mac_eee,
1906         .set_mac_eee            = b53_set_mac_eee,
1907         .port_bridge_join       = b53_br_join,
1908         .port_bridge_leave      = b53_br_leave,
1909         .port_stp_state_set     = b53_br_set_stp_state,
1910         .port_fast_age          = b53_br_fast_age,
1911         .port_vlan_filtering    = b53_vlan_filtering,
1912         .port_vlan_prepare      = b53_vlan_prepare,
1913         .port_vlan_add          = b53_vlan_add,
1914         .port_vlan_del          = b53_vlan_del,
1915         .port_fdb_dump          = b53_fdb_dump,
1916         .port_fdb_add           = b53_fdb_add,
1917         .port_fdb_del           = b53_fdb_del,
1918         .port_mirror_add        = b53_mirror_add,
1919         .port_mirror_del        = b53_mirror_del,
1920 };
1921
1922 struct b53_chip_data {
1923         u32 chip_id;
1924         const char *dev_name;
1925         u16 vlans;
1926         u16 enabled_ports;
1927         u8 cpu_port;
1928         u8 vta_regs[3];
1929         u8 arl_entries;
1930         u8 duplex_reg;
1931         u8 jumbo_pm_reg;
1932         u8 jumbo_size_reg;
1933 };
1934
1935 #define B53_VTA_REGS    \
1936         { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1937 #define B53_VTA_REGS_9798 \
1938         { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1939 #define B53_VTA_REGS_63XX \
1940         { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1941
1942 static const struct b53_chip_data b53_switch_chips[] = {
1943         {
1944                 .chip_id = BCM5325_DEVICE_ID,
1945                 .dev_name = "BCM5325",
1946                 .vlans = 16,
1947                 .enabled_ports = 0x1f,
1948                 .arl_entries = 2,
1949                 .cpu_port = B53_CPU_PORT_25,
1950                 .duplex_reg = B53_DUPLEX_STAT_FE,
1951         },
1952         {
1953                 .chip_id = BCM5365_DEVICE_ID,
1954                 .dev_name = "BCM5365",
1955                 .vlans = 256,
1956                 .enabled_ports = 0x1f,
1957                 .arl_entries = 2,
1958                 .cpu_port = B53_CPU_PORT_25,
1959                 .duplex_reg = B53_DUPLEX_STAT_FE,
1960         },
1961         {
1962                 .chip_id = BCM5389_DEVICE_ID,
1963                 .dev_name = "BCM5389",
1964                 .vlans = 4096,
1965                 .enabled_ports = 0x1f,
1966                 .arl_entries = 4,
1967                 .cpu_port = B53_CPU_PORT,
1968                 .vta_regs = B53_VTA_REGS,
1969                 .duplex_reg = B53_DUPLEX_STAT_GE,
1970                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1971                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1972         },
1973         {
1974                 .chip_id = BCM5395_DEVICE_ID,
1975                 .dev_name = "BCM5395",
1976                 .vlans = 4096,
1977                 .enabled_ports = 0x1f,
1978                 .arl_entries = 4,
1979                 .cpu_port = B53_CPU_PORT,
1980                 .vta_regs = B53_VTA_REGS,
1981                 .duplex_reg = B53_DUPLEX_STAT_GE,
1982                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1983                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1984         },
1985         {
1986                 .chip_id = BCM5397_DEVICE_ID,
1987                 .dev_name = "BCM5397",
1988                 .vlans = 4096,
1989                 .enabled_ports = 0x1f,
1990                 .arl_entries = 4,
1991                 .cpu_port = B53_CPU_PORT,
1992                 .vta_regs = B53_VTA_REGS_9798,
1993                 .duplex_reg = B53_DUPLEX_STAT_GE,
1994                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1995                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1996         },
1997         {
1998                 .chip_id = BCM5398_DEVICE_ID,
1999                 .dev_name = "BCM5398",
2000                 .vlans = 4096,
2001                 .enabled_ports = 0x7f,
2002                 .arl_entries = 4,
2003                 .cpu_port = B53_CPU_PORT,
2004                 .vta_regs = B53_VTA_REGS_9798,
2005                 .duplex_reg = B53_DUPLEX_STAT_GE,
2006                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2007                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2008         },
2009         {
2010                 .chip_id = BCM53115_DEVICE_ID,
2011                 .dev_name = "BCM53115",
2012                 .vlans = 4096,
2013                 .enabled_ports = 0x1f,
2014                 .arl_entries = 4,
2015                 .vta_regs = B53_VTA_REGS,
2016                 .cpu_port = B53_CPU_PORT,
2017                 .duplex_reg = B53_DUPLEX_STAT_GE,
2018                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2019                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2020         },
2021         {
2022                 .chip_id = BCM53125_DEVICE_ID,
2023                 .dev_name = "BCM53125",
2024                 .vlans = 4096,
2025                 .enabled_ports = 0xff,
2026                 .arl_entries = 4,
2027                 .cpu_port = B53_CPU_PORT,
2028                 .vta_regs = B53_VTA_REGS,
2029                 .duplex_reg = B53_DUPLEX_STAT_GE,
2030                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2031                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2032         },
2033         {
2034                 .chip_id = BCM53128_DEVICE_ID,
2035                 .dev_name = "BCM53128",
2036                 .vlans = 4096,
2037                 .enabled_ports = 0x1ff,
2038                 .arl_entries = 4,
2039                 .cpu_port = B53_CPU_PORT,
2040                 .vta_regs = B53_VTA_REGS,
2041                 .duplex_reg = B53_DUPLEX_STAT_GE,
2042                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2043                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2044         },
2045         {
2046                 .chip_id = BCM63XX_DEVICE_ID,
2047                 .dev_name = "BCM63xx",
2048                 .vlans = 4096,
2049                 .enabled_ports = 0, /* pdata must provide them */
2050                 .arl_entries = 4,
2051                 .cpu_port = B53_CPU_PORT,
2052                 .vta_regs = B53_VTA_REGS_63XX,
2053                 .duplex_reg = B53_DUPLEX_STAT_63XX,
2054                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2055                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2056         },
2057         {
2058                 .chip_id = BCM53010_DEVICE_ID,
2059                 .dev_name = "BCM53010",
2060                 .vlans = 4096,
2061                 .enabled_ports = 0x1f,
2062                 .arl_entries = 4,
2063                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2064                 .vta_regs = B53_VTA_REGS,
2065                 .duplex_reg = B53_DUPLEX_STAT_GE,
2066                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2067                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2068         },
2069         {
2070                 .chip_id = BCM53011_DEVICE_ID,
2071                 .dev_name = "BCM53011",
2072                 .vlans = 4096,
2073                 .enabled_ports = 0x1bf,
2074                 .arl_entries = 4,
2075                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2076                 .vta_regs = B53_VTA_REGS,
2077                 .duplex_reg = B53_DUPLEX_STAT_GE,
2078                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2079                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2080         },
2081         {
2082                 .chip_id = BCM53012_DEVICE_ID,
2083                 .dev_name = "BCM53012",
2084                 .vlans = 4096,
2085                 .enabled_ports = 0x1bf,
2086                 .arl_entries = 4,
2087                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2088                 .vta_regs = B53_VTA_REGS,
2089                 .duplex_reg = B53_DUPLEX_STAT_GE,
2090                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2091                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2092         },
2093         {
2094                 .chip_id = BCM53018_DEVICE_ID,
2095                 .dev_name = "BCM53018",
2096                 .vlans = 4096,
2097                 .enabled_ports = 0x1f,
2098                 .arl_entries = 4,
2099                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2100                 .vta_regs = B53_VTA_REGS,
2101                 .duplex_reg = B53_DUPLEX_STAT_GE,
2102                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2103                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2104         },
2105         {
2106                 .chip_id = BCM53019_DEVICE_ID,
2107                 .dev_name = "BCM53019",
2108                 .vlans = 4096,
2109                 .enabled_ports = 0x1f,
2110                 .arl_entries = 4,
2111                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2112                 .vta_regs = B53_VTA_REGS,
2113                 .duplex_reg = B53_DUPLEX_STAT_GE,
2114                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2115                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2116         },
2117         {
2118                 .chip_id = BCM58XX_DEVICE_ID,
2119                 .dev_name = "BCM585xx/586xx/88312",
2120                 .vlans  = 4096,
2121                 .enabled_ports = 0x1ff,
2122                 .arl_entries = 4,
2123                 .cpu_port = B53_CPU_PORT,
2124                 .vta_regs = B53_VTA_REGS,
2125                 .duplex_reg = B53_DUPLEX_STAT_GE,
2126                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2127                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2128         },
2129         {
2130                 .chip_id = BCM583XX_DEVICE_ID,
2131                 .dev_name = "BCM583xx/11360",
2132                 .vlans = 4096,
2133                 .enabled_ports = 0x103,
2134                 .arl_entries = 4,
2135                 .cpu_port = B53_CPU_PORT,
2136                 .vta_regs = B53_VTA_REGS,
2137                 .duplex_reg = B53_DUPLEX_STAT_GE,
2138                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2139                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2140         },
2141         {
2142                 .chip_id = BCM7445_DEVICE_ID,
2143                 .dev_name = "BCM7445",
2144                 .vlans  = 4096,
2145                 .enabled_ports = 0x1ff,
2146                 .arl_entries = 4,
2147                 .cpu_port = B53_CPU_PORT,
2148                 .vta_regs = B53_VTA_REGS,
2149                 .duplex_reg = B53_DUPLEX_STAT_GE,
2150                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2151                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2152         },
2153         {
2154                 .chip_id = BCM7278_DEVICE_ID,
2155                 .dev_name = "BCM7278",
2156                 .vlans = 4096,
2157                 .enabled_ports = 0x1ff,
2158                 .arl_entries= 4,
2159                 .cpu_port = B53_CPU_PORT,
2160                 .vta_regs = B53_VTA_REGS,
2161                 .duplex_reg = B53_DUPLEX_STAT_GE,
2162                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2163                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2164         },
2165 };
2166
2167 static int b53_switch_init(struct b53_device *dev)
2168 {
2169         unsigned int i;
2170         int ret;
2171
2172         for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2173                 const struct b53_chip_data *chip = &b53_switch_chips[i];
2174
2175                 if (chip->chip_id == dev->chip_id) {
2176                         if (!dev->enabled_ports)
2177                                 dev->enabled_ports = chip->enabled_ports;
2178                         dev->name = chip->dev_name;
2179                         dev->duplex_reg = chip->duplex_reg;
2180                         dev->vta_regs[0] = chip->vta_regs[0];
2181                         dev->vta_regs[1] = chip->vta_regs[1];
2182                         dev->vta_regs[2] = chip->vta_regs[2];
2183                         dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2184                         dev->cpu_port = chip->cpu_port;
2185                         dev->num_vlans = chip->vlans;
2186                         dev->num_arl_entries = chip->arl_entries;
2187                         break;
2188                 }
2189         }
2190
2191         /* check which BCM5325x version we have */
2192         if (is5325(dev)) {
2193                 u8 vc4;
2194
2195                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2196
2197                 /* check reserved bits */
2198                 switch (vc4 & 3) {
2199                 case 1:
2200                         /* BCM5325E */
2201                         break;
2202                 case 3:
2203                         /* BCM5325F - do not use port 4 */
2204                         dev->enabled_ports &= ~BIT(4);
2205                         break;
2206                 default:
2207 /* On the BCM47XX SoCs this is the supported internal switch.*/
2208 #ifndef CONFIG_BCM47XX
2209                         /* BCM5325M */
2210                         return -EINVAL;
2211 #else
2212                         break;
2213 #endif
2214                 }
2215         } else if (dev->chip_id == BCM53115_DEVICE_ID) {
2216                 u64 strap_value;
2217
2218                 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
2219                 /* use second IMP port if GMII is enabled */
2220                 if (strap_value & SV_GMII_CTRL_115)
2221                         dev->cpu_port = 5;
2222         }
2223
2224         /* cpu port is always last */
2225         dev->num_ports = dev->cpu_port + 1;
2226         dev->enabled_ports |= BIT(dev->cpu_port);
2227
2228         /* Include non standard CPU port built-in PHYs to be probed */
2229         if (is539x(dev) || is531x5(dev)) {
2230                 for (i = 0; i < dev->num_ports; i++) {
2231                         if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2232                             !b53_possible_cpu_port(dev->ds, i))
2233                                 dev->ds->phys_mii_mask |= BIT(i);
2234                 }
2235         }
2236
2237         dev->ports = devm_kcalloc(dev->dev,
2238                                   dev->num_ports, sizeof(struct b53_port),
2239                                   GFP_KERNEL);
2240         if (!dev->ports)
2241                 return -ENOMEM;
2242
2243         dev->vlans = devm_kcalloc(dev->dev,
2244                                   dev->num_vlans, sizeof(struct b53_vlan),
2245                                   GFP_KERNEL);
2246         if (!dev->vlans)
2247                 return -ENOMEM;
2248
2249         dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2250         if (dev->reset_gpio >= 0) {
2251                 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2252                                             GPIOF_OUT_INIT_HIGH, "robo_reset");
2253                 if (ret)
2254                         return ret;
2255         }
2256
2257         return 0;
2258 }
2259
2260 struct b53_device *b53_switch_alloc(struct device *base,
2261                                     const struct b53_io_ops *ops,
2262                                     void *priv)
2263 {
2264         struct dsa_switch *ds;
2265         struct b53_device *dev;
2266
2267         ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
2268         if (!ds)
2269                 return NULL;
2270
2271         dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2272         if (!dev)
2273                 return NULL;
2274
2275         ds->priv = dev;
2276         dev->dev = base;
2277
2278         dev->ds = ds;
2279         dev->priv = priv;
2280         dev->ops = ops;
2281         ds->ops = &b53_switch_ops;
2282         mutex_init(&dev->reg_mutex);
2283         mutex_init(&dev->stats_mutex);
2284
2285         return dev;
2286 }
2287 EXPORT_SYMBOL(b53_switch_alloc);
2288
2289 int b53_switch_detect(struct b53_device *dev)
2290 {
2291         u32 id32;
2292         u16 tmp;
2293         u8 id8;
2294         int ret;
2295
2296         ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2297         if (ret)
2298                 return ret;
2299
2300         switch (id8) {
2301         case 0:
2302                 /* BCM5325 and BCM5365 do not have this register so reads
2303                  * return 0. But the read operation did succeed, so assume this
2304                  * is one of them.
2305                  *
2306                  * Next check if we can write to the 5325's VTA register; for
2307                  * 5365 it is read only.
2308                  */
2309                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2310                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2311
2312                 if (tmp == 0xf)
2313                         dev->chip_id = BCM5325_DEVICE_ID;
2314                 else
2315                         dev->chip_id = BCM5365_DEVICE_ID;
2316                 break;
2317         case BCM5389_DEVICE_ID:
2318         case BCM5395_DEVICE_ID:
2319         case BCM5397_DEVICE_ID:
2320         case BCM5398_DEVICE_ID:
2321                 dev->chip_id = id8;
2322                 break;
2323         default:
2324                 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2325                 if (ret)
2326                         return ret;
2327
2328                 switch (id32) {
2329                 case BCM53115_DEVICE_ID:
2330                 case BCM53125_DEVICE_ID:
2331                 case BCM53128_DEVICE_ID:
2332                 case BCM53010_DEVICE_ID:
2333                 case BCM53011_DEVICE_ID:
2334                 case BCM53012_DEVICE_ID:
2335                 case BCM53018_DEVICE_ID:
2336                 case BCM53019_DEVICE_ID:
2337                         dev->chip_id = id32;
2338                         break;
2339                 default:
2340                         pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2341                                id8, id32);
2342                         return -ENODEV;
2343                 }
2344         }
2345
2346         if (dev->chip_id == BCM5325_DEVICE_ID)
2347                 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2348                                  &dev->core_rev);
2349         else
2350                 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2351                                  &dev->core_rev);
2352 }
2353 EXPORT_SYMBOL(b53_switch_detect);
2354
2355 int b53_switch_register(struct b53_device *dev)
2356 {
2357         int ret;
2358
2359         if (dev->pdata) {
2360                 dev->chip_id = dev->pdata->chip_id;
2361                 dev->enabled_ports = dev->pdata->enabled_ports;
2362         }
2363
2364         if (!dev->chip_id && b53_switch_detect(dev))
2365                 return -EINVAL;
2366
2367         ret = b53_switch_init(dev);
2368         if (ret)
2369                 return ret;
2370
2371         pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2372
2373         return dsa_register_switch(dev->ds);
2374 }
2375 EXPORT_SYMBOL(b53_switch_register);
2376
2377 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2378 MODULE_DESCRIPTION("B53 switch library");
2379 MODULE_LICENSE("Dual BSD/GPL");