1 // SPDX-License-Identifier: GPL-2.0
3 * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs
5 * Copyright (C) 2010 Lantiq Deutschland
6 * Copyright (C) 2012 John Crispin <john@phrozen.org>
7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
9 * The VLAN and bridge model the GSWIP hardware uses does not directly
10 * matches the model DSA uses.
12 * The hardware has 64 possible table entries for bridges with one VLAN
13 * ID, one flow id and a list of ports for each bridge. All entries which
14 * match the same flow ID are combined in the mac learning table, they
15 * act as one global bridge.
16 * The hardware does not support VLAN filter on the port, but on the
17 * bridge, this driver converts the DSA model to the hardware.
19 * The CPU gets all the exception frames which do not match any forwarding
20 * rule and the CPU port is also added to all bridges. This makes it possible
21 * to handle all the special cases easily in software.
22 * At the initialization the driver allocates one bridge table entry for
23 * each switch port which is used when the port is used without an
24 * explicit bridge. This prevents the frames from being forwarded
25 * between all LAN ports by default.
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/etherdevice.h>
31 #include <linux/firmware.h>
32 #include <linux/if_bridge.h>
33 #include <linux/if_vlan.h>
34 #include <linux/iopoll.h>
35 #include <linux/mfd/syscon.h>
36 #include <linux/module.h>
37 #include <linux/of_mdio.h>
38 #include <linux/of_net.h>
39 #include <linux/of_platform.h>
40 #include <linux/phy.h>
41 #include <linux/phylink.h>
42 #include <linux/platform_device.h>
43 #include <linux/regmap.h>
44 #include <linux/reset.h>
46 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
48 #include "lantiq_pce.h"
50 /* GSWIP MDIO Registers */
51 #define GSWIP_MDIO_GLOB 0x00
52 #define GSWIP_MDIO_GLOB_ENABLE BIT(15)
53 #define GSWIP_MDIO_CTRL 0x08
54 #define GSWIP_MDIO_CTRL_BUSY BIT(12)
55 #define GSWIP_MDIO_CTRL_RD BIT(11)
56 #define GSWIP_MDIO_CTRL_WR BIT(10)
57 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f
58 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5
59 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f
60 #define GSWIP_MDIO_READ 0x09
61 #define GSWIP_MDIO_WRITE 0x0A
62 #define GSWIP_MDIO_MDC_CFG0 0x0B
63 #define GSWIP_MDIO_MDC_CFG1 0x0C
64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p))
65 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000
66 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000
67 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000
68 #define GSWIP_MDIO_PHY_LINK_UP 0x2000
69 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800
70 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800
71 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000
72 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800
73 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000
74 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600
75 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000
76 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200
77 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600
78 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180
79 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000
80 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100
81 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180
82 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060
83 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000
84 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020
85 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060
86 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f
87 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \
88 GSWIP_MDIO_PHY_FCONRX_MASK | \
89 GSWIP_MDIO_PHY_FCONTX_MASK | \
90 GSWIP_MDIO_PHY_LINK_MASK | \
91 GSWIP_MDIO_PHY_SPEED_MASK | \
92 GSWIP_MDIO_PHY_FDUP_MASK)
94 /* GSWIP MII Registers */
95 #define GSWIP_MII_CFGp(p) (0x2 * (p))
96 #define GSWIP_MII_CFG_RESET BIT(15)
97 #define GSWIP_MII_CFG_EN BIT(14)
98 #define GSWIP_MII_CFG_ISOLATE BIT(13)
99 #define GSWIP_MII_CFG_LDCLKDIS BIT(12)
100 #define GSWIP_MII_CFG_RGMII_IBS BIT(8)
101 #define GSWIP_MII_CFG_RMII_CLK BIT(7)
102 #define GSWIP_MII_CFG_MODE_MIIP 0x0
103 #define GSWIP_MII_CFG_MODE_MIIM 0x1
104 #define GSWIP_MII_CFG_MODE_RMIIP 0x2
105 #define GSWIP_MII_CFG_MODE_RMIIM 0x3
106 #define GSWIP_MII_CFG_MODE_RGMII 0x4
107 #define GSWIP_MII_CFG_MODE_GMII 0x9
108 #define GSWIP_MII_CFG_MODE_MASK 0xf
109 #define GSWIP_MII_CFG_RATE_M2P5 0x00
110 #define GSWIP_MII_CFG_RATE_M25 0x10
111 #define GSWIP_MII_CFG_RATE_M125 0x20
112 #define GSWIP_MII_CFG_RATE_M50 0x30
113 #define GSWIP_MII_CFG_RATE_AUTO 0x40
114 #define GSWIP_MII_CFG_RATE_MASK 0x70
115 #define GSWIP_MII_PCDU0 0x01
116 #define GSWIP_MII_PCDU1 0x03
117 #define GSWIP_MII_PCDU5 0x05
118 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0)
119 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7)
121 /* GSWIP Core Registers */
122 #define GSWIP_SWRES 0x000
123 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */
124 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */
125 #define GSWIP_VERSION 0x013
126 #define GSWIP_VERSION_REV_SHIFT 0
127 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0)
128 #define GSWIP_VERSION_MOD_SHIFT 8
129 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8)
130 #define GSWIP_VERSION_2_0 0x100
131 #define GSWIP_VERSION_2_1 0x021
132 #define GSWIP_VERSION_2_2 0x122
133 #define GSWIP_VERSION_2_2_ETC 0x022
135 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
136 #define GSWIP_BM_RAM_ADDR 0x044
137 #define GSWIP_BM_RAM_CTRL 0x045
138 #define GSWIP_BM_RAM_CTRL_BAS BIT(15)
139 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5)
140 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0)
141 #define GSWIP_BM_QUEUE_GCTRL 0x04A
142 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10)
143 /* buffer management Port Configuration Register */
144 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2))
145 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */
146 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */
147 /* buffer management Port Control Register */
148 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2))
149 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */
150 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */
153 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x))
154 #define GSWIP_PCE_TBL_MASK 0x448
155 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x))
156 #define GSWIP_PCE_TBL_ADDR 0x44E
157 #define GSWIP_PCE_TBL_CTRL 0x44F
158 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15)
159 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13)
160 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12)
161 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11)
162 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7)
163 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5)
164 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00
165 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20
166 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40
167 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60
168 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0)
169 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */
170 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */
171 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */
172 #define GSWIP_PCE_GCTRL_0 0x456
173 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */
174 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3)
175 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */
176 #define GSWIP_PCE_GCTRL_1 0x457
177 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */
178 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */
179 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA))
180 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */
181 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */
182 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */
183 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0
184 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1
185 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2
186 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3
187 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7
188 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0)
189 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA))
190 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */
191 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */
192 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */
193 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */
194 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */
195 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA))
197 #define GSWIP_MAC_FLEN 0x8C5
198 #define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC))
199 #define GSWIP_MAC_CTRL_0_PADEN BIT(8)
200 #define GSWIP_MAC_CTRL_0_FCS_EN BIT(7)
201 #define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070
202 #define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000
203 #define GSWIP_MAC_CTRL_0_FCON_RX 0x0010
204 #define GSWIP_MAC_CTRL_0_FCON_TX 0x0020
205 #define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030
206 #define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040
207 #define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C
208 #define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000
209 #define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004
210 #define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C
211 #define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003
212 #define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000
213 #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001
214 #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002
215 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC))
216 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */
218 /* Ethernet Switch Fetch DMA Port Control Register */
219 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6))
220 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */
221 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */
222 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */
223 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */
224 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
225 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
226 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
227 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
229 /* Ethernet Switch Store DMA Port Control Register */
230 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6))
231 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */
232 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */
233 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */
235 #define GSWIP_TABLE_ACTIVE_VLAN 0x01
236 #define GSWIP_TABLE_VLAN_MAPPING 0x02
237 #define GSWIP_TABLE_MAC_BRIDGE 0x0b
238 #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */
240 #define XRX200_GPHY_FW_ALIGN (16 * 1024)
242 struct gswip_hw_info {
245 const struct dsa_switch_ops *ops;
248 struct xway_gphy_match_data {
249 char *fe_firmware_name;
250 char *ge_firmware_name;
253 struct gswip_gphy_fw {
254 struct clk *clk_gate;
255 struct reset_control *reset;
261 struct net_device *bridge;
270 const struct gswip_hw_info *hw_info;
271 const struct xway_gphy_match_data *gphy_fw_name_cfg;
272 struct dsa_switch *ds;
274 struct regmap *rcu_regmap;
275 struct gswip_vlan vlans[64];
277 struct gswip_gphy_fw *gphy_fw;
278 u32 port_vlan_filter;
279 struct mutex pce_table_lock;
282 struct gswip_pce_table_entry {
283 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index
284 u16 table; // PCE_TBL_CTRL.ADDR = pData->table
294 struct gswip_rmon_cnt_desc {
300 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
302 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = {
303 /** Receive Packet Count (only packets that are accepted and not discarded). */
304 MIB_DESC(1, 0x1F, "RxGoodPkts"),
305 MIB_DESC(1, 0x23, "RxUnicastPkts"),
306 MIB_DESC(1, 0x22, "RxMulticastPkts"),
307 MIB_DESC(1, 0x21, "RxFCSErrorPkts"),
308 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"),
309 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"),
310 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"),
311 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"),
312 MIB_DESC(1, 0x20, "RxGoodPausePkts"),
313 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"),
314 MIB_DESC(1, 0x12, "Rx64BytePkts"),
315 MIB_DESC(1, 0x13, "Rx127BytePkts"),
316 MIB_DESC(1, 0x14, "Rx255BytePkts"),
317 MIB_DESC(1, 0x15, "Rx511BytePkts"),
318 MIB_DESC(1, 0x16, "Rx1023BytePkts"),
319 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */
320 MIB_DESC(1, 0x17, "RxMaxBytePkts"),
321 MIB_DESC(1, 0x18, "RxDroppedPkts"),
322 MIB_DESC(1, 0x19, "RxFilteredPkts"),
323 MIB_DESC(2, 0x24, "RxGoodBytes"),
324 MIB_DESC(2, 0x26, "RxBadBytes"),
325 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"),
326 MIB_DESC(1, 0x0C, "TxGoodPkts"),
327 MIB_DESC(1, 0x06, "TxUnicastPkts"),
328 MIB_DESC(1, 0x07, "TxMulticastPkts"),
329 MIB_DESC(1, 0x00, "Tx64BytePkts"),
330 MIB_DESC(1, 0x01, "Tx127BytePkts"),
331 MIB_DESC(1, 0x02, "Tx255BytePkts"),
332 MIB_DESC(1, 0x03, "Tx511BytePkts"),
333 MIB_DESC(1, 0x04, "Tx1023BytePkts"),
334 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
335 MIB_DESC(1, 0x05, "TxMaxBytePkts"),
336 MIB_DESC(1, 0x08, "TxSingleCollCount"),
337 MIB_DESC(1, 0x09, "TxMultCollCount"),
338 MIB_DESC(1, 0x0A, "TxLateCollCount"),
339 MIB_DESC(1, 0x0B, "TxExcessCollCount"),
340 MIB_DESC(1, 0x0D, "TxPauseCount"),
341 MIB_DESC(1, 0x10, "TxDroppedPkts"),
342 MIB_DESC(2, 0x0E, "TxGoodBytes"),
345 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset)
347 return __raw_readl(priv->gswip + (offset * 4));
350 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset)
352 __raw_writel(val, priv->gswip + (offset * 4));
355 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set,
358 u32 val = gswip_switch_r(priv, offset);
362 gswip_switch_w(priv, val, offset);
365 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
370 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val,
371 (val & cleared) == 0, 20, 50000);
374 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset)
376 return __raw_readl(priv->mdio + (offset * 4));
379 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset)
381 __raw_writel(val, priv->mdio + (offset * 4));
384 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set,
387 u32 val = gswip_mdio_r(priv, offset);
391 gswip_mdio_w(priv, val, offset);
394 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset)
396 return __raw_readl(priv->mii + (offset * 4));
399 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset)
401 __raw_writel(val, priv->mii + (offset * 4));
404 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
407 u32 val = gswip_mii_r(priv, offset);
411 gswip_mii_w(priv, val, offset);
414 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
417 /* There's no MII_CFG register for the CPU port */
418 if (!dsa_is_cpu_port(priv->ds, port))
419 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
422 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
427 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);
430 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1);
433 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5);
438 static int gswip_mdio_poll(struct gswip_priv *priv)
442 while (likely(cnt--)) {
443 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL);
445 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0)
447 usleep_range(20, 40);
453 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
455 struct gswip_priv *priv = bus->priv;
458 err = gswip_mdio_poll(priv);
460 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
464 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE);
465 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR |
466 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
467 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
473 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg)
475 struct gswip_priv *priv = bus->priv;
478 err = gswip_mdio_poll(priv);
480 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
484 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD |
485 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
486 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
489 err = gswip_mdio_poll(priv);
491 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
495 return gswip_mdio_r(priv, GSWIP_MDIO_READ);
498 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np)
500 struct dsa_switch *ds = priv->ds;
503 ds->slave_mii_bus = mdiobus_alloc();
504 if (!ds->slave_mii_bus)
507 ds->slave_mii_bus->priv = priv;
508 ds->slave_mii_bus->read = gswip_mdio_rd;
509 ds->slave_mii_bus->write = gswip_mdio_wr;
510 ds->slave_mii_bus->name = "lantiq,xrx200-mdio";
511 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii",
512 dev_name(priv->dev));
513 ds->slave_mii_bus->parent = priv->dev;
514 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask;
516 err = of_mdiobus_register(ds->slave_mii_bus, mdio_np);
518 mdiobus_free(ds->slave_mii_bus);
523 static int gswip_pce_table_entry_read(struct gswip_priv *priv,
524 struct gswip_pce_table_entry *tbl)
529 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD :
530 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD;
532 mutex_lock(&priv->pce_table_lock);
534 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
535 GSWIP_PCE_TBL_CTRL_BAS);
537 mutex_unlock(&priv->pce_table_lock);
541 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
542 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
543 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
544 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS,
547 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
548 GSWIP_PCE_TBL_CTRL_BAS);
550 mutex_unlock(&priv->pce_table_lock);
554 for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
555 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i));
557 for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
558 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i));
560 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK);
562 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
564 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE);
565 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD);
566 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7;
568 mutex_unlock(&priv->pce_table_lock);
573 static int gswip_pce_table_entry_write(struct gswip_priv *priv,
574 struct gswip_pce_table_entry *tbl)
579 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR :
580 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR;
582 mutex_lock(&priv->pce_table_lock);
584 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
585 GSWIP_PCE_TBL_CTRL_BAS);
587 mutex_unlock(&priv->pce_table_lock);
591 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
592 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
593 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
594 tbl->table | addr_mode,
597 for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
598 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i));
600 for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
601 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i));
603 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
604 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
605 tbl->table | addr_mode,
608 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK);
610 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
611 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD |
612 GSWIP_PCE_TBL_CTRL_GMAP_MASK);
614 crtl |= GSWIP_PCE_TBL_CTRL_TYPE;
616 crtl |= GSWIP_PCE_TBL_CTRL_VLD;
617 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK;
618 crtl |= GSWIP_PCE_TBL_CTRL_BAS;
619 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL);
621 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
622 GSWIP_PCE_TBL_CTRL_BAS);
624 mutex_unlock(&priv->pce_table_lock);
629 /* Add the LAN port into a bridge with the CPU port by
630 * default. This prevents automatic forwarding of
631 * packages between the LAN ports when no explicit
632 * bridge is configured.
634 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add)
636 struct gswip_pce_table_entry vlan_active = {0,};
637 struct gswip_pce_table_entry vlan_mapping = {0,};
638 unsigned int cpu_port = priv->hw_info->cpu_port;
639 unsigned int max_ports = priv->hw_info->max_ports;
642 if (port >= max_ports) {
643 dev_err(priv->dev, "single port for %i supported\n", port);
647 vlan_active.index = port + 1;
648 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
649 vlan_active.key[0] = 0; /* vid */
650 vlan_active.val[0] = port + 1 /* fid */;
651 vlan_active.valid = add;
652 err = gswip_pce_table_entry_write(priv, &vlan_active);
654 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
661 vlan_mapping.index = port + 1;
662 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
663 vlan_mapping.val[0] = 0 /* vid */;
664 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port);
665 vlan_mapping.val[2] = 0;
666 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
668 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
675 static int gswip_port_enable(struct dsa_switch *ds, int port,
676 struct phy_device *phydev)
678 struct gswip_priv *priv = ds->priv;
681 if (!dsa_is_user_port(ds, port))
684 if (!dsa_is_cpu_port(ds, port)) {
685 err = gswip_add_single_port_br(priv, port, true);
690 /* RMON Counter Enable for port */
691 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port));
693 /* enable port fetch/store dma & VLAN Modification */
694 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN |
695 GSWIP_FDMA_PCTRL_VLANMOD_BOTH,
696 GSWIP_FDMA_PCTRLp(port));
697 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
698 GSWIP_SDMA_PCTRLp(port));
700 if (!dsa_is_cpu_port(ds, port)) {
704 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
706 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
707 GSWIP_MDIO_PHYp(port));
713 static void gswip_port_disable(struct dsa_switch *ds, int port)
715 struct gswip_priv *priv = ds->priv;
717 if (!dsa_is_user_port(ds, port))
720 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
721 GSWIP_FDMA_PCTRLp(port));
722 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
723 GSWIP_SDMA_PCTRLp(port));
726 static int gswip_pce_load_microcode(struct gswip_priv *priv)
731 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
732 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
733 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL);
734 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK);
736 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) {
737 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR);
738 gswip_switch_w(priv, gswip_pce_microcode[i].val_0,
739 GSWIP_PCE_TBL_VAL(0));
740 gswip_switch_w(priv, gswip_pce_microcode[i].val_1,
741 GSWIP_PCE_TBL_VAL(1));
742 gswip_switch_w(priv, gswip_pce_microcode[i].val_2,
743 GSWIP_PCE_TBL_VAL(2));
744 gswip_switch_w(priv, gswip_pce_microcode[i].val_3,
745 GSWIP_PCE_TBL_VAL(3));
747 /* start the table access: */
748 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS,
750 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
751 GSWIP_PCE_TBL_CTRL_BAS);
756 /* tell the switch that the microcode is loaded */
757 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID,
763 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
765 struct netlink_ext_ack *extack)
767 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
768 struct gswip_priv *priv = ds->priv;
770 /* Do not allow changing the VLAN filtering options while in bridge */
771 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) {
772 NL_SET_ERR_MSG_MOD(extack,
773 "Dynamic toggling of vlan_filtering not supported");
777 if (vlan_filtering) {
778 /* Use port based VLAN tag */
779 gswip_switch_mask(priv,
781 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
782 GSWIP_PCE_VCTRL_VEMR,
783 GSWIP_PCE_VCTRL(port));
784 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
785 GSWIP_PCE_PCTRL_0p(port));
787 /* Use port based VLAN tag */
788 gswip_switch_mask(priv,
789 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
790 GSWIP_PCE_VCTRL_VEMR,
792 GSWIP_PCE_VCTRL(port));
793 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM,
794 GSWIP_PCE_PCTRL_0p(port));
800 static int gswip_setup(struct dsa_switch *ds)
802 struct gswip_priv *priv = ds->priv;
803 unsigned int cpu_port = priv->hw_info->cpu_port;
807 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES);
808 usleep_range(5000, 10000);
809 gswip_switch_w(priv, 0, GSWIP_SWRES);
811 /* disable port fetch/store dma on all ports */
812 for (i = 0; i < priv->hw_info->max_ports; i++) {
813 gswip_port_disable(ds, i);
814 gswip_port_vlan_filtering(ds, i, false, NULL);
818 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB);
820 err = gswip_pce_load_microcode(priv);
822 dev_err(priv->dev, "writing PCE microcode failed, %i", err);
826 /* Default unknown Broadcast/Multicast/Unicast port maps */
827 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1);
828 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2);
829 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3);
831 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an
832 * interoperability problem with this auto polling mechanism because
833 * their status registers think that the link is in a different state
834 * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set
835 * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the
836 * auto polling state machine consider the link being negotiated with
837 * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads
838 * to the switch port being completely dead (RX and TX are both not
840 * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F
841 * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes
842 * it would work fine for a few minutes to hours and then stop, on
843 * other device it would no traffic could be sent or received at all.
844 * Testing shows that when PHY auto polling is disabled these problems
847 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0);
849 /* Configure the MDIO Clock 2.5 MHz */
850 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);
852 /* Disable the xMII interface and clear it's isolation bit */
853 for (i = 0; i < priv->hw_info->max_ports; i++)
854 gswip_mii_mask_cfg(priv,
855 GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE,
858 /* enable special tag insertion on cpu port */
859 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
860 GSWIP_FDMA_PCTRLp(cpu_port));
862 /* accept special tag in ingress direction */
863 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS,
864 GSWIP_PCE_PCTRL_0p(cpu_port));
866 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN,
867 GSWIP_MAC_CTRL_2p(cpu_port));
868 gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8 + ETH_FCS_LEN,
870 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD,
871 GSWIP_BM_QUEUE_GCTRL);
873 /* VLAN aware Switching */
874 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0);
876 /* Flush MAC Table */
877 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0);
879 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0,
880 GSWIP_PCE_GCTRL_0_MTFL);
882 dev_err(priv->dev, "MAC flushing didn't finish\n");
886 gswip_port_enable(ds, cpu_port, NULL);
888 ds->configure_vlan_while_not_filtering = false;
893 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds,
895 enum dsa_tag_protocol mp)
897 return DSA_TAG_PROTO_GSWIP;
900 static int gswip_vlan_active_create(struct gswip_priv *priv,
901 struct net_device *bridge,
904 struct gswip_pce_table_entry vlan_active = {0,};
905 unsigned int max_ports = priv->hw_info->max_ports;
910 /* Look for a free slot */
911 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
912 if (!priv->vlans[i].bridge) {
924 vlan_active.index = idx;
925 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
926 vlan_active.key[0] = vid;
927 vlan_active.val[0] = fid;
928 vlan_active.valid = true;
930 err = gswip_pce_table_entry_write(priv, &vlan_active);
932 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
936 priv->vlans[idx].bridge = bridge;
937 priv->vlans[idx].vid = vid;
938 priv->vlans[idx].fid = fid;
943 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx)
945 struct gswip_pce_table_entry vlan_active = {0,};
948 vlan_active.index = idx;
949 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
950 vlan_active.valid = false;
951 err = gswip_pce_table_entry_write(priv, &vlan_active);
953 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err);
954 priv->vlans[idx].bridge = NULL;
959 static int gswip_vlan_add_unaware(struct gswip_priv *priv,
960 struct net_device *bridge, int port)
962 struct gswip_pce_table_entry vlan_mapping = {0,};
963 unsigned int max_ports = priv->hw_info->max_ports;
964 unsigned int cpu_port = priv->hw_info->cpu_port;
965 bool active_vlan_created = false;
970 /* Check if there is already a page for this bridge */
971 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
972 if (priv->vlans[i].bridge == bridge) {
978 /* If this bridge is not programmed yet, add a Active VLAN table
979 * entry in a free slot and prepare the VLAN mapping table entry.
982 idx = gswip_vlan_active_create(priv, bridge, -1, 0);
985 active_vlan_created = true;
987 vlan_mapping.index = idx;
988 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
989 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
990 vlan_mapping.val[0] = 0;
992 /* Read the existing VLAN mapping entry from the switch */
993 vlan_mapping.index = idx;
994 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
995 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
997 dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
1003 /* Update the VLAN mapping entry and write it to the switch */
1004 vlan_mapping.val[1] |= BIT(cpu_port);
1005 vlan_mapping.val[1] |= BIT(port);
1006 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1008 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1009 /* In case an Active VLAN was creaetd delete it again */
1010 if (active_vlan_created)
1011 gswip_vlan_active_remove(priv, idx);
1015 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1019 static int gswip_vlan_add_aware(struct gswip_priv *priv,
1020 struct net_device *bridge, int port,
1021 u16 vid, bool untagged,
1024 struct gswip_pce_table_entry vlan_mapping = {0,};
1025 unsigned int max_ports = priv->hw_info->max_ports;
1026 unsigned int cpu_port = priv->hw_info->cpu_port;
1027 bool active_vlan_created = false;
1033 /* Check if there is already a page for this bridge */
1034 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1035 if (priv->vlans[i].bridge == bridge) {
1036 if (fid != -1 && fid != priv->vlans[i].fid)
1037 dev_err(priv->dev, "one bridge with multiple flow ids\n");
1038 fid = priv->vlans[i].fid;
1039 if (priv->vlans[i].vid == vid) {
1046 /* If this bridge is not programmed yet, add a Active VLAN table
1047 * entry in a free slot and prepare the VLAN mapping table entry.
1050 idx = gswip_vlan_active_create(priv, bridge, fid, vid);
1053 active_vlan_created = true;
1055 vlan_mapping.index = idx;
1056 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1057 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
1058 vlan_mapping.val[0] = vid;
1060 /* Read the existing VLAN mapping entry from the switch */
1061 vlan_mapping.index = idx;
1062 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1063 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1065 dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
1071 vlan_mapping.val[0] = vid;
1072 /* Update the VLAN mapping entry and write it to the switch */
1073 vlan_mapping.val[1] |= BIT(cpu_port);
1074 vlan_mapping.val[2] |= BIT(cpu_port);
1075 vlan_mapping.val[1] |= BIT(port);
1077 vlan_mapping.val[2] &= ~BIT(port);
1079 vlan_mapping.val[2] |= BIT(port);
1080 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1082 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1083 /* In case an Active VLAN was creaetd delete it again */
1084 if (active_vlan_created)
1085 gswip_vlan_active_remove(priv, idx);
1090 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port));
1095 static int gswip_vlan_remove(struct gswip_priv *priv,
1096 struct net_device *bridge, int port,
1097 u16 vid, bool pvid, bool vlan_aware)
1099 struct gswip_pce_table_entry vlan_mapping = {0,};
1100 unsigned int max_ports = priv->hw_info->max_ports;
1101 unsigned int cpu_port = priv->hw_info->cpu_port;
1106 /* Check if there is already a page for this bridge */
1107 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1108 if (priv->vlans[i].bridge == bridge &&
1109 (!vlan_aware || priv->vlans[i].vid == vid)) {
1116 dev_err(priv->dev, "bridge to leave does not exists\n");
1120 vlan_mapping.index = idx;
1121 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1122 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1124 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err);
1128 vlan_mapping.val[1] &= ~BIT(port);
1129 vlan_mapping.val[2] &= ~BIT(port);
1130 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1132 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1136 /* In case all ports are removed from the bridge, remove the VLAN */
1137 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) {
1138 err = gswip_vlan_active_remove(priv, idx);
1140 dev_err(priv->dev, "failed to write active VLAN: %d\n",
1146 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */
1148 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1153 static int gswip_port_bridge_join(struct dsa_switch *ds, int port,
1154 struct dsa_bridge bridge,
1155 bool *tx_fwd_offload)
1157 struct net_device *br = bridge.dev;
1158 struct gswip_priv *priv = ds->priv;
1161 /* When the bridge uses VLAN filtering we have to configure VLAN
1162 * specific bridges. No bridge is configured here.
1164 if (!br_vlan_enabled(br)) {
1165 err = gswip_vlan_add_unaware(priv, br, port);
1168 priv->port_vlan_filter &= ~BIT(port);
1170 priv->port_vlan_filter |= BIT(port);
1172 return gswip_add_single_port_br(priv, port, false);
1175 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port,
1176 struct dsa_bridge bridge)
1178 struct net_device *br = bridge.dev;
1179 struct gswip_priv *priv = ds->priv;
1181 gswip_add_single_port_br(priv, port, true);
1183 /* When the bridge uses VLAN filtering we have to configure VLAN
1184 * specific bridges. No bridge is configured here.
1186 if (!br_vlan_enabled(br))
1187 gswip_vlan_remove(priv, br, port, 0, true, false);
1190 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port,
1191 const struct switchdev_obj_port_vlan *vlan,
1192 struct netlink_ext_ack *extack)
1194 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1195 struct gswip_priv *priv = ds->priv;
1196 unsigned int max_ports = priv->hw_info->max_ports;
1197 int pos = max_ports;
1200 /* We only support VLAN filtering on bridges */
1201 if (!dsa_is_cpu_port(ds, port) && !bridge)
1204 /* Check if there is already a page for this VLAN */
1205 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1206 if (priv->vlans[i].bridge == bridge &&
1207 priv->vlans[i].vid == vlan->vid) {
1213 /* If this VLAN is not programmed yet, we have to reserve
1214 * one entry in the VLAN table. Make sure we start at the
1215 * next position round.
1218 /* Look for a free slot */
1219 for (; pos < ARRAY_SIZE(priv->vlans); pos++) {
1220 if (!priv->vlans[pos].bridge) {
1228 NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table");
1236 static int gswip_port_vlan_add(struct dsa_switch *ds, int port,
1237 const struct switchdev_obj_port_vlan *vlan,
1238 struct netlink_ext_ack *extack)
1240 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1241 struct gswip_priv *priv = ds->priv;
1242 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1243 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1246 err = gswip_port_vlan_prepare(ds, port, vlan, extack);
1250 /* We have to receive all packets on the CPU port and should not
1251 * do any VLAN filtering here. This is also called with bridge
1252 * NULL and then we do not know for which bridge to configure
1255 if (dsa_is_cpu_port(ds, port))
1258 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid,
1262 static int gswip_port_vlan_del(struct dsa_switch *ds, int port,
1263 const struct switchdev_obj_port_vlan *vlan)
1265 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1266 struct gswip_priv *priv = ds->priv;
1267 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1269 /* We have to receive all packets on the CPU port and should not
1270 * do any VLAN filtering here. This is also called with bridge
1271 * NULL and then we do not know for which bridge to configure
1274 if (dsa_is_cpu_port(ds, port))
1277 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true);
1280 static void gswip_port_fast_age(struct dsa_switch *ds, int port)
1282 struct gswip_priv *priv = ds->priv;
1283 struct gswip_pce_table_entry mac_bridge = {0,};
1287 for (i = 0; i < 2048; i++) {
1288 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1289 mac_bridge.index = i;
1291 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1293 dev_err(priv->dev, "failed to read mac bridge: %d\n",
1298 if (!mac_bridge.valid)
1301 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
1304 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
1307 mac_bridge.valid = false;
1308 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1310 dev_err(priv->dev, "failed to write mac bridge: %d\n",
1317 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1319 struct gswip_priv *priv = ds->priv;
1323 case BR_STATE_DISABLED:
1324 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
1325 GSWIP_SDMA_PCTRLp(port));
1327 case BR_STATE_BLOCKING:
1328 case BR_STATE_LISTENING:
1329 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN;
1331 case BR_STATE_LEARNING:
1332 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING;
1334 case BR_STATE_FORWARDING:
1335 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING;
1338 dev_err(priv->dev, "invalid STP state: %d\n", state);
1342 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
1343 GSWIP_SDMA_PCTRLp(port));
1344 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state,
1345 GSWIP_PCE_PCTRL_0p(port));
1348 static int gswip_port_fdb(struct dsa_switch *ds, int port,
1349 const unsigned char *addr, u16 vid, bool add)
1351 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1352 struct gswip_priv *priv = ds->priv;
1353 struct gswip_pce_table_entry mac_bridge = {0,};
1354 unsigned int cpu_port = priv->hw_info->cpu_port;
1362 for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) {
1363 if (priv->vlans[i].bridge == bridge) {
1364 fid = priv->vlans[i].fid;
1370 dev_err(priv->dev, "Port not part of a bridge\n");
1374 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1375 mac_bridge.key_mode = true;
1376 mac_bridge.key[0] = addr[5] | (addr[4] << 8);
1377 mac_bridge.key[1] = addr[3] | (addr[2] << 8);
1378 mac_bridge.key[2] = addr[1] | (addr[0] << 8);
1379 mac_bridge.key[3] = fid;
1380 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
1381 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
1382 mac_bridge.valid = add;
1384 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1386 dev_err(priv->dev, "failed to write mac bridge: %d\n", err);
1391 static int gswip_port_fdb_add(struct dsa_switch *ds, int port,
1392 const unsigned char *addr, u16 vid,
1395 return gswip_port_fdb(ds, port, addr, vid, true);
1398 static int gswip_port_fdb_del(struct dsa_switch *ds, int port,
1399 const unsigned char *addr, u16 vid,
1402 return gswip_port_fdb(ds, port, addr, vid, false);
1405 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port,
1406 dsa_fdb_dump_cb_t *cb, void *data)
1408 struct gswip_priv *priv = ds->priv;
1409 struct gswip_pce_table_entry mac_bridge = {0,};
1410 unsigned char addr[6];
1414 for (i = 0; i < 2048; i++) {
1415 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1416 mac_bridge.index = i;
1418 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1420 dev_err(priv->dev, "failed to write mac bridge: %d\n",
1425 if (!mac_bridge.valid)
1428 addr[5] = mac_bridge.key[0] & 0xff;
1429 addr[4] = (mac_bridge.key[0] >> 8) & 0xff;
1430 addr[3] = mac_bridge.key[1] & 0xff;
1431 addr[2] = (mac_bridge.key[1] >> 8) & 0xff;
1432 addr[1] = mac_bridge.key[2] & 0xff;
1433 addr[0] = (mac_bridge.key[2] >> 8) & 0xff;
1434 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) {
1435 if (mac_bridge.val[0] & BIT(port)) {
1436 err = cb(addr, 0, true, data);
1441 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) {
1442 err = cb(addr, 0, false, data);
1451 static void gswip_xrx200_phylink_get_caps(struct dsa_switch *ds, int port,
1452 struct phylink_config *config)
1457 phy_interface_set_rgmii(config->supported_interfaces);
1458 __set_bit(PHY_INTERFACE_MODE_MII,
1459 config->supported_interfaces);
1460 __set_bit(PHY_INTERFACE_MODE_REVMII,
1461 config->supported_interfaces);
1462 __set_bit(PHY_INTERFACE_MODE_RMII,
1463 config->supported_interfaces);
1469 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1470 config->supported_interfaces);
1474 phy_interface_set_rgmii(config->supported_interfaces);
1475 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1476 config->supported_interfaces);
1480 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1481 MAC_10 | MAC_100 | MAC_1000;
1484 static void gswip_xrx300_phylink_get_caps(struct dsa_switch *ds, int port,
1485 struct phylink_config *config)
1489 phy_interface_set_rgmii(config->supported_interfaces);
1490 __set_bit(PHY_INTERFACE_MODE_GMII,
1491 config->supported_interfaces);
1492 __set_bit(PHY_INTERFACE_MODE_RMII,
1493 config->supported_interfaces);
1500 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1501 config->supported_interfaces);
1505 phy_interface_set_rgmii(config->supported_interfaces);
1506 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1507 config->supported_interfaces);
1508 __set_bit(PHY_INTERFACE_MODE_RMII,
1509 config->supported_interfaces);
1513 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1514 MAC_10 | MAC_100 | MAC_1000;
1517 static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link)
1522 mdio_phy = GSWIP_MDIO_PHY_LINK_UP;
1524 mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN;
1526 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy,
1527 GSWIP_MDIO_PHYp(port));
1530 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
1531 phy_interface_t interface)
1533 u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0;
1537 mdio_phy = GSWIP_MDIO_PHY_SPEED_M10;
1539 if (interface == PHY_INTERFACE_MODE_RMII)
1540 mii_cfg = GSWIP_MII_CFG_RATE_M50;
1542 mii_cfg = GSWIP_MII_CFG_RATE_M2P5;
1544 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1548 mdio_phy = GSWIP_MDIO_PHY_SPEED_M100;
1550 if (interface == PHY_INTERFACE_MODE_RMII)
1551 mii_cfg = GSWIP_MII_CFG_RATE_M50;
1553 mii_cfg = GSWIP_MII_CFG_RATE_M25;
1555 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1559 mdio_phy = GSWIP_MDIO_PHY_SPEED_G1;
1561 mii_cfg = GSWIP_MII_CFG_RATE_M125;
1563 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII;
1567 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy,
1568 GSWIP_MDIO_PHYp(port));
1569 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port);
1570 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0,
1571 GSWIP_MAC_CTRL_0p(port));
1574 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex)
1576 u32 mac_ctrl_0, mdio_phy;
1578 if (duplex == DUPLEX_FULL) {
1579 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN;
1580 mdio_phy = GSWIP_MDIO_PHY_FDUP_EN;
1582 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS;
1583 mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS;
1586 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0,
1587 GSWIP_MAC_CTRL_0p(port));
1588 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy,
1589 GSWIP_MDIO_PHYp(port));
1592 static void gswip_port_set_pause(struct gswip_priv *priv, int port,
1593 bool tx_pause, bool rx_pause)
1595 u32 mac_ctrl_0, mdio_phy;
1597 if (tx_pause && rx_pause) {
1598 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX;
1599 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1600 GSWIP_MDIO_PHY_FCONRX_EN;
1601 } else if (tx_pause) {
1602 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX;
1603 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1604 GSWIP_MDIO_PHY_FCONRX_DIS;
1605 } else if (rx_pause) {
1606 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX;
1607 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1608 GSWIP_MDIO_PHY_FCONRX_EN;
1610 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE;
1611 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1612 GSWIP_MDIO_PHY_FCONRX_DIS;
1615 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK,
1616 mac_ctrl_0, GSWIP_MAC_CTRL_0p(port));
1617 gswip_mdio_mask(priv,
1618 GSWIP_MDIO_PHY_FCONTX_MASK |
1619 GSWIP_MDIO_PHY_FCONRX_MASK,
1620 mdio_phy, GSWIP_MDIO_PHYp(port));
1623 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
1625 const struct phylink_link_state *state)
1627 struct gswip_priv *priv = ds->priv;
1630 miicfg |= GSWIP_MII_CFG_LDCLKDIS;
1632 switch (state->interface) {
1633 case PHY_INTERFACE_MODE_MII:
1634 case PHY_INTERFACE_MODE_INTERNAL:
1635 miicfg |= GSWIP_MII_CFG_MODE_MIIM;
1637 case PHY_INTERFACE_MODE_REVMII:
1638 miicfg |= GSWIP_MII_CFG_MODE_MIIP;
1640 case PHY_INTERFACE_MODE_RMII:
1641 miicfg |= GSWIP_MII_CFG_MODE_RMIIM;
1643 /* Configure the RMII clock as output: */
1644 miicfg |= GSWIP_MII_CFG_RMII_CLK;
1646 case PHY_INTERFACE_MODE_RGMII:
1647 case PHY_INTERFACE_MODE_RGMII_ID:
1648 case PHY_INTERFACE_MODE_RGMII_RXID:
1649 case PHY_INTERFACE_MODE_RGMII_TXID:
1650 miicfg |= GSWIP_MII_CFG_MODE_RGMII;
1652 case PHY_INTERFACE_MODE_GMII:
1653 miicfg |= GSWIP_MII_CFG_MODE_GMII;
1657 "Unsupported interface: %d\n", state->interface);
1661 gswip_mii_mask_cfg(priv,
1662 GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK |
1663 GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS,
1666 switch (state->interface) {
1667 case PHY_INTERFACE_MODE_RGMII_ID:
1668 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK |
1669 GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1671 case PHY_INTERFACE_MODE_RGMII_RXID:
1672 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1674 case PHY_INTERFACE_MODE_RGMII_TXID:
1675 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port);
1682 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port,
1684 phy_interface_t interface)
1686 struct gswip_priv *priv = ds->priv;
1688 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port);
1690 if (!dsa_is_cpu_port(ds, port))
1691 gswip_port_set_link(priv, port, false);
1694 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
1696 phy_interface_t interface,
1697 struct phy_device *phydev,
1698 int speed, int duplex,
1699 bool tx_pause, bool rx_pause)
1701 struct gswip_priv *priv = ds->priv;
1703 if (!dsa_is_cpu_port(ds, port)) {
1704 gswip_port_set_link(priv, port, true);
1705 gswip_port_set_speed(priv, port, speed, interface);
1706 gswip_port_set_duplex(priv, port, duplex);
1707 gswip_port_set_pause(priv, port, tx_pause, rx_pause);
1710 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
1713 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1718 if (stringset != ETH_SS_STATS)
1721 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++)
1722 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name,
1726 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,
1732 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR);
1733 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK |
1734 GSWIP_BM_RAM_CTRL_OPMOD,
1735 table | GSWIP_BM_RAM_CTRL_BAS,
1738 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
1739 GSWIP_BM_RAM_CTRL_BAS);
1741 dev_err(priv->dev, "timeout while reading table: %u, index: %u",
1746 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0));
1747 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16;
1752 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port,
1755 struct gswip_priv *priv = ds->priv;
1756 const struct gswip_rmon_cnt_desc *rmon_cnt;
1760 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) {
1761 rmon_cnt = &gswip_rmon_cnt[i];
1763 data[i] = gswip_bcm_ram_entry_read(priv, port,
1765 if (rmon_cnt->size == 2) {
1766 high = gswip_bcm_ram_entry_read(priv, port,
1767 rmon_cnt->offset + 1);
1768 data[i] |= high << 32;
1773 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset)
1775 if (sset != ETH_SS_STATS)
1778 return ARRAY_SIZE(gswip_rmon_cnt);
1781 static const struct dsa_switch_ops gswip_xrx200_switch_ops = {
1782 .get_tag_protocol = gswip_get_tag_protocol,
1783 .setup = gswip_setup,
1784 .port_enable = gswip_port_enable,
1785 .port_disable = gswip_port_disable,
1786 .port_bridge_join = gswip_port_bridge_join,
1787 .port_bridge_leave = gswip_port_bridge_leave,
1788 .port_fast_age = gswip_port_fast_age,
1789 .port_vlan_filtering = gswip_port_vlan_filtering,
1790 .port_vlan_add = gswip_port_vlan_add,
1791 .port_vlan_del = gswip_port_vlan_del,
1792 .port_stp_state_set = gswip_port_stp_state_set,
1793 .port_fdb_add = gswip_port_fdb_add,
1794 .port_fdb_del = gswip_port_fdb_del,
1795 .port_fdb_dump = gswip_port_fdb_dump,
1796 .phylink_get_caps = gswip_xrx200_phylink_get_caps,
1797 .phylink_mac_config = gswip_phylink_mac_config,
1798 .phylink_mac_link_down = gswip_phylink_mac_link_down,
1799 .phylink_mac_link_up = gswip_phylink_mac_link_up,
1800 .get_strings = gswip_get_strings,
1801 .get_ethtool_stats = gswip_get_ethtool_stats,
1802 .get_sset_count = gswip_get_sset_count,
1805 static const struct dsa_switch_ops gswip_xrx300_switch_ops = {
1806 .get_tag_protocol = gswip_get_tag_protocol,
1807 .setup = gswip_setup,
1808 .port_enable = gswip_port_enable,
1809 .port_disable = gswip_port_disable,
1810 .port_bridge_join = gswip_port_bridge_join,
1811 .port_bridge_leave = gswip_port_bridge_leave,
1812 .port_fast_age = gswip_port_fast_age,
1813 .port_vlan_filtering = gswip_port_vlan_filtering,
1814 .port_vlan_add = gswip_port_vlan_add,
1815 .port_vlan_del = gswip_port_vlan_del,
1816 .port_stp_state_set = gswip_port_stp_state_set,
1817 .port_fdb_add = gswip_port_fdb_add,
1818 .port_fdb_del = gswip_port_fdb_del,
1819 .port_fdb_dump = gswip_port_fdb_dump,
1820 .phylink_get_caps = gswip_xrx300_phylink_get_caps,
1821 .phylink_mac_config = gswip_phylink_mac_config,
1822 .phylink_mac_link_down = gswip_phylink_mac_link_down,
1823 .phylink_mac_link_up = gswip_phylink_mac_link_up,
1824 .get_strings = gswip_get_strings,
1825 .get_ethtool_stats = gswip_get_ethtool_stats,
1826 .get_sset_count = gswip_get_sset_count,
1829 static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
1830 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
1831 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
1834 static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
1835 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
1836 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
1839 static const struct xway_gphy_match_data xrx300_gphy_data = {
1840 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
1841 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
1844 static const struct of_device_id xway_gphy_match[] = {
1845 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL },
1846 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data },
1847 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data },
1848 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data },
1849 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data },
1853 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw)
1855 struct device *dev = priv->dev;
1856 const struct firmware *fw;
1858 dma_addr_t dma_addr;
1859 dma_addr_t dev_addr;
1863 ret = clk_prepare_enable(gphy_fw->clk_gate);
1867 reset_control_assert(gphy_fw->reset);
1869 /* The vendor BSP uses a 200ms delay after asserting the reset line.
1870 * Without this some users are observing that the PHY is not coming up
1875 ret = request_firmware(&fw, gphy_fw->fw_name, dev);
1877 dev_err(dev, "failed to load firmware: %s, error: %i\n",
1878 gphy_fw->fw_name, ret);
1882 /* GPHY cores need the firmware code in a persistent and contiguous
1883 * memory area with a 16 kB boundary aligned start address.
1885 size = fw->size + XRX200_GPHY_FW_ALIGN;
1887 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
1889 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
1890 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
1891 memcpy(fw_addr, fw->data, fw->size);
1893 dev_err(dev, "failed to alloc firmware memory\n");
1894 release_firmware(fw);
1898 release_firmware(fw);
1900 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr);
1904 reset_control_deassert(gphy_fw->reset);
1909 static int gswip_gphy_fw_probe(struct gswip_priv *priv,
1910 struct gswip_gphy_fw *gphy_fw,
1911 struct device_node *gphy_fw_np, int i)
1913 struct device *dev = priv->dev;
1918 snprintf(gphyname, sizeof(gphyname), "gphy%d", i);
1920 gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
1921 if (IS_ERR(gphy_fw->clk_gate)) {
1922 dev_err(dev, "Failed to lookup gate clock\n");
1923 return PTR_ERR(gphy_fw->clk_gate);
1926 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
1930 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode);
1931 /* Default to GE mode */
1933 gphy_mode = GPHY_MODE_GE;
1935 switch (gphy_mode) {
1937 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name;
1940 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
1943 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
1947 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
1948 if (IS_ERR(gphy_fw->reset)) {
1949 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER)
1950 dev_err(dev, "Failed to lookup gphy reset\n");
1951 return PTR_ERR(gphy_fw->reset);
1954 return gswip_gphy_fw_load(priv, gphy_fw);
1957 static void gswip_gphy_fw_remove(struct gswip_priv *priv,
1958 struct gswip_gphy_fw *gphy_fw)
1962 /* check if the device was fully probed */
1963 if (!gphy_fw->fw_name)
1966 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0);
1968 dev_err(priv->dev, "can not reset GPHY FW pointer");
1970 clk_disable_unprepare(gphy_fw->clk_gate);
1972 reset_control_put(gphy_fw->reset);
1975 static int gswip_gphy_fw_list(struct gswip_priv *priv,
1976 struct device_node *gphy_fw_list_np, u32 version)
1978 struct device *dev = priv->dev;
1979 struct device_node *gphy_fw_np;
1980 const struct of_device_id *match;
1984 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older
1985 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also
1986 * needs a different GPHY firmware.
1988 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) {
1990 case GSWIP_VERSION_2_0:
1991 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data;
1993 case GSWIP_VERSION_2_1:
1994 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
1997 dev_err(dev, "unknown GSWIP version: 0x%x", version);
2002 match = of_match_node(xway_gphy_match, gphy_fw_list_np);
2003 if (match && match->data)
2004 priv->gphy_fw_name_cfg = match->data;
2006 if (!priv->gphy_fw_name_cfg) {
2007 dev_err(dev, "GPHY compatible type not supported");
2011 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
2012 if (!priv->num_gphy_fw)
2015 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np,
2017 if (IS_ERR(priv->rcu_regmap))
2018 return PTR_ERR(priv->rcu_regmap);
2020 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw,
2021 sizeof(*priv->gphy_fw),
2022 GFP_KERNEL | __GFP_ZERO);
2026 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) {
2027 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i],
2034 /* The standalone PHY11G requires 300ms to be fully
2035 * initialized and ready for any MDIO communication after being
2036 * taken out of reset. For the SoC-internal GPHY variant there
2037 * is no (known) documentation for the minimum time after a
2038 * reset. Use the same value as for the standalone variant as
2039 * some users have reported internal PHYs not being detected
2040 * without any delay.
2047 for (i = 0; i < priv->num_gphy_fw; i++)
2048 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2052 static int gswip_probe(struct platform_device *pdev)
2054 struct gswip_priv *priv;
2055 struct device_node *np, *mdio_np, *gphy_fw_np;
2056 struct device *dev = &pdev->dev;
2061 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2065 priv->gswip = devm_platform_ioremap_resource(pdev, 0);
2066 if (IS_ERR(priv->gswip))
2067 return PTR_ERR(priv->gswip);
2069 priv->mdio = devm_platform_ioremap_resource(pdev, 1);
2070 if (IS_ERR(priv->mdio))
2071 return PTR_ERR(priv->mdio);
2073 priv->mii = devm_platform_ioremap_resource(pdev, 2);
2074 if (IS_ERR(priv->mii))
2075 return PTR_ERR(priv->mii);
2077 priv->hw_info = of_device_get_match_data(dev);
2081 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
2085 priv->ds->dev = dev;
2086 priv->ds->num_ports = priv->hw_info->max_ports;
2087 priv->ds->priv = priv;
2088 priv->ds->ops = priv->hw_info->ops;
2090 mutex_init(&priv->pce_table_lock);
2091 version = gswip_switch_r(priv, GSWIP_VERSION);
2095 case GSWIP_VERSION_2_0:
2096 case GSWIP_VERSION_2_1:
2097 if (!of_device_is_compatible(np, "lantiq,xrx200-gswip"))
2100 case GSWIP_VERSION_2_2:
2101 case GSWIP_VERSION_2_2_ETC:
2102 if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") &&
2103 !of_device_is_compatible(np, "lantiq,xrx330-gswip"))
2107 dev_err(dev, "unknown GSWIP version: 0x%x", version);
2111 /* bring up the mdio bus */
2112 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw");
2114 err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
2115 of_node_put(gphy_fw_np);
2117 dev_err(dev, "gphy fw probe failed\n");
2122 /* bring up the mdio bus */
2123 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio");
2125 err = gswip_mdio(priv, mdio_np);
2127 dev_err(dev, "mdio probe failed\n");
2132 err = dsa_register_switch(priv->ds);
2134 dev_err(dev, "dsa switch register failed: %i\n", err);
2137 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
2138 dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
2139 priv->hw_info->cpu_port);
2141 goto disable_switch;
2144 platform_set_drvdata(pdev, priv);
2146 dev_info(dev, "probed GSWIP version %lx mod %lx\n",
2147 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT,
2148 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT);
2152 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
2153 dsa_unregister_switch(priv->ds);
2156 mdiobus_unregister(priv->ds->slave_mii_bus);
2157 mdiobus_free(priv->ds->slave_mii_bus);
2160 of_node_put(mdio_np);
2161 for (i = 0; i < priv->num_gphy_fw; i++)
2162 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2166 static int gswip_remove(struct platform_device *pdev)
2168 struct gswip_priv *priv = platform_get_drvdata(pdev);
2174 /* disable the switch */
2175 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
2177 dsa_unregister_switch(priv->ds);
2179 if (priv->ds->slave_mii_bus) {
2180 mdiobus_unregister(priv->ds->slave_mii_bus);
2181 of_node_put(priv->ds->slave_mii_bus->dev.of_node);
2182 mdiobus_free(priv->ds->slave_mii_bus);
2185 for (i = 0; i < priv->num_gphy_fw; i++)
2186 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2188 platform_set_drvdata(pdev, NULL);
2193 static void gswip_shutdown(struct platform_device *pdev)
2195 struct gswip_priv *priv = platform_get_drvdata(pdev);
2200 dsa_switch_shutdown(priv->ds);
2202 platform_set_drvdata(pdev, NULL);
2205 static const struct gswip_hw_info gswip_xrx200 = {
2208 .ops = &gswip_xrx200_switch_ops,
2211 static const struct gswip_hw_info gswip_xrx300 = {
2214 .ops = &gswip_xrx300_switch_ops,
2217 static const struct of_device_id gswip_of_match[] = {
2218 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 },
2219 { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 },
2220 { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 },
2223 MODULE_DEVICE_TABLE(of, gswip_of_match);
2225 static struct platform_driver gswip_driver = {
2226 .probe = gswip_probe,
2227 .remove = gswip_remove,
2228 .shutdown = gswip_shutdown,
2231 .of_match_table = gswip_of_match,
2235 module_platform_driver(gswip_driver);
2237 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
2238 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
2239 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
2240 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
2241 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
2242 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
2243 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
2244 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver");
2245 MODULE_LICENSE("GPL v2");