2 * Microchip switch driver main logic
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #include <linux/delay.h>
20 #include <linux/export.h>
21 #include <linux/gpio.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_data/microchip-ksz.h>
25 #include <linux/phy.h>
26 #include <linux/etherdevice.h>
27 #include <linux/if_bridge.h>
29 #include <net/switchdev.h>
35 char string[ETH_GSTRING_LEN];
36 } mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
38 { 0x01, "rx_undersize" },
39 { 0x02, "rx_fragments" },
40 { 0x03, "rx_oversize" },
41 { 0x04, "rx_jabbers" },
42 { 0x05, "rx_symbol_err" },
43 { 0x06, "rx_crc_err" },
44 { 0x07, "rx_align_err" },
45 { 0x08, "rx_mac_ctrl" },
50 { 0x0D, "rx_64_or_less" },
51 { 0x0E, "rx_65_127" },
52 { 0x0F, "rx_128_255" },
53 { 0x10, "rx_256_511" },
54 { 0x11, "rx_512_1023" },
55 { 0x12, "rx_1024_1522" },
56 { 0x13, "rx_1523_2000" },
59 { 0x16, "tx_late_col" },
64 { 0x1B, "tx_deferred" },
65 { 0x1C, "tx_total_col" },
66 { 0x1D, "tx_exc_col" },
67 { 0x1E, "tx_single_col" },
68 { 0x1F, "tx_mult_col" },
71 { 0x82, "rx_discards" },
72 { 0x83, "tx_discards" },
75 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
79 ksz_read8(dev, addr, &data);
84 ksz_write8(dev, addr, data);
87 static void ksz_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set)
91 ksz_read32(dev, addr, &data);
96 ksz_write32(dev, addr, data);
99 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
105 addr = PORT_CTRL_ADDR(port, offset);
106 ksz_read8(dev, addr, &data);
113 ksz_write8(dev, addr, data);
116 static void ksz_port_cfg32(struct ksz_device *dev, int port, int offset,
122 addr = PORT_CTRL_ADDR(port, offset);
123 ksz_read32(dev, addr, &data);
130 ksz_write32(dev, addr, data);
133 static int wait_vlan_ctrl_ready(struct ksz_device *dev, u32 waiton, int timeout)
138 ksz_read8(dev, REG_SW_VLAN_CTRL, &data);
139 if (!(data & waiton))
142 } while (timeout-- > 0);
150 static int get_vlan_table(struct dsa_switch *ds, u16 vid, u32 *vlan_table)
152 struct ksz_device *dev = ds->priv;
155 mutex_lock(&dev->vlan_mutex);
157 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
158 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START);
160 /* wait to be cleared */
161 ret = wait_vlan_ctrl_ready(dev, VLAN_START, 1000);
163 dev_dbg(dev->dev, "Failed to read vlan table\n");
167 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]);
168 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]);
169 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]);
171 ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
174 mutex_unlock(&dev->vlan_mutex);
179 static int set_vlan_table(struct dsa_switch *ds, u16 vid, u32 *vlan_table)
181 struct ksz_device *dev = ds->priv;
184 mutex_lock(&dev->vlan_mutex);
186 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]);
187 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]);
188 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]);
190 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
191 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE);
193 /* wait to be cleared */
194 ret = wait_vlan_ctrl_ready(dev, VLAN_START, 1000);
196 dev_dbg(dev->dev, "Failed to write vlan table\n");
200 ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
202 /* update vlan cache table */
203 dev->vlan_cache[vid].table[0] = vlan_table[0];
204 dev->vlan_cache[vid].table[1] = vlan_table[1];
205 dev->vlan_cache[vid].table[2] = vlan_table[2];
208 mutex_unlock(&dev->vlan_mutex);
213 static void read_table(struct dsa_switch *ds, u32 *table)
215 struct ksz_device *dev = ds->priv;
217 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]);
218 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]);
219 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]);
220 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]);
223 static void write_table(struct dsa_switch *ds, u32 *table)
225 struct ksz_device *dev = ds->priv;
227 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]);
228 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]);
229 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]);
230 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]);
233 static int wait_alu_ready(struct ksz_device *dev, u32 waiton, int timeout)
238 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data);
239 if (!(data & waiton))
242 } while (timeout-- > 0);
250 static int wait_alu_sta_ready(struct ksz_device *dev, u32 waiton, int timeout)
255 ksz_read32(dev, REG_SW_ALU_STAT_CTRL__4, &data);
256 if (!(data & waiton))
259 } while (timeout-- > 0);
267 static int ksz_reset_switch(struct dsa_switch *ds)
269 struct ksz_device *dev = ds->priv;
275 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
277 /* turn off SPI DO Edge select */
278 ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
279 data8 &= ~SPI_AUTO_EDGE_DETECTION;
280 ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
282 /* default configuration */
283 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
284 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING |
285 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
286 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
288 /* disable interrupts */
289 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
290 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
291 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
293 /* set broadcast storm protection 10% rate */
294 ksz_read16(dev, REG_SW_MAC_CTRL_2, &data16);
295 data16 &= ~BROADCAST_STORM_RATE;
296 data16 |= (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100;
297 ksz_write16(dev, REG_SW_MAC_CTRL_2, data16);
302 static void port_setup(struct ksz_device *dev, int port, bool cpu_port)
307 /* enable tag tail for host port */
309 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE,
312 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false);
314 /* set back pressure */
315 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true);
317 /* set flow control */
318 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
319 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, true);
321 /* enable broadcast storm limit */
322 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
324 /* disable DiffServ priority */
325 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false);
327 /* replace priority */
328 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
330 ksz_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
331 MTI_PVID_REPLACE, false);
333 /* enable 802.1p priority */
334 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
336 /* configure MAC to 1G & RGMII mode */
337 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
338 data8 |= PORT_RGMII_ID_EG_ENABLE;
339 data8 &= ~PORT_MII_NOT_1GBIT;
340 data8 &= ~PORT_MII_SEL_M;
341 data8 |= PORT_RGMII_SEL;
342 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
344 /* clear pending interrupts */
345 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
348 static void ksz_config_cpu_port(struct dsa_switch *ds)
350 struct ksz_device *dev = ds->priv;
353 ds->num_ports = dev->port_cnt;
355 for (i = 0; i < ds->num_ports; i++) {
356 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) {
359 /* enable cpu port */
360 port_setup(dev, i, true);
365 static int ksz_setup(struct dsa_switch *ds)
367 struct ksz_device *dev = ds->priv;
370 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
371 dev->num_vlans, GFP_KERNEL);
372 if (!dev->vlan_cache)
375 ret = ksz_reset_switch(ds);
377 dev_err(ds->dev, "failed to reset switch\n");
381 /* accept packet up to 2000bytes */
382 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true);
384 ksz_config_cpu_port(ds);
386 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true);
388 /* queue based egress rate limit */
389 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true);
392 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true);
397 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds)
399 return DSA_TAG_PROTO_KSZ;
402 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
404 struct ksz_device *dev = ds->priv;
407 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
412 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
414 struct ksz_device *dev = ds->priv;
416 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
421 static int ksz_enable_port(struct dsa_switch *ds, int port,
422 struct phy_device *phy)
424 struct ksz_device *dev = ds->priv;
426 /* setup slave port */
427 port_setup(dev, port, false);
432 static void ksz_disable_port(struct dsa_switch *ds, int port,
433 struct phy_device *phy)
435 struct ksz_device *dev = ds->priv;
437 /* there is no port disable */
438 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, true);
441 static int ksz_sset_count(struct dsa_switch *ds)
443 return TOTAL_SWITCH_COUNTER_NUM;
446 static void ksz_get_strings(struct dsa_switch *ds, int port, uint8_t *buf)
450 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
451 memcpy(buf + i * ETH_GSTRING_LEN, mib_names[i].string,
456 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
459 struct ksz_device *dev = ds->priv;
464 mutex_lock(&dev->stats_mutex);
466 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
467 data = MIB_COUNTER_READ;
468 data |= ((mib_names[i].index & 0xFF) << MIB_COUNTER_INDEX_S);
469 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data);
473 ksz_pread32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
476 if (!(data & MIB_COUNTER_READ))
478 } while (timeout-- > 0);
480 /* failed to read MIB. get out of loop */
482 dev_dbg(dev->dev, "Failed to get MIB\n");
486 /* count resets upon read */
487 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data);
489 dev->mib_value[i] += (uint64_t)data;
490 buf[i] = dev->mib_value[i];
493 mutex_unlock(&dev->stats_mutex);
496 static void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
498 struct ksz_device *dev = ds->priv;
501 ksz_pread8(dev, port, P_STP_CTRL, &data);
502 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
505 case BR_STATE_DISABLED:
506 data |= PORT_LEARN_DISABLE;
508 case BR_STATE_LISTENING:
509 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
511 case BR_STATE_LEARNING:
512 data |= PORT_RX_ENABLE;
514 case BR_STATE_FORWARDING:
515 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
517 case BR_STATE_BLOCKING:
518 data |= PORT_LEARN_DISABLE;
521 dev_err(ds->dev, "invalid STP state: %d\n", state);
525 ksz_pwrite8(dev, port, P_STP_CTRL, data);
528 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
530 struct ksz_device *dev = ds->priv;
533 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
534 data8 |= SW_FAST_AGING;
535 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
537 data8 &= ~SW_FAST_AGING;
538 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
541 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag)
543 struct ksz_device *dev = ds->priv;
546 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
547 PORT_VLAN_LOOKUP_VID_0, true);
548 ksz_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, true);
549 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true);
551 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false);
552 ksz_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, false);
553 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
554 PORT_VLAN_LOOKUP_VID_0, false);
560 static int ksz_port_vlan_prepare(struct dsa_switch *ds, int port,
561 const struct switchdev_obj_port_vlan *vlan,
562 struct switchdev_trans *trans)
569 static void ksz_port_vlan_add(struct dsa_switch *ds, int port,
570 const struct switchdev_obj_port_vlan *vlan,
571 struct switchdev_trans *trans)
573 struct ksz_device *dev = ds->priv;
576 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
578 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
579 if (get_vlan_table(ds, vid, vlan_table)) {
580 dev_dbg(dev->dev, "Failed to get vlan table\n");
584 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M);
586 vlan_table[1] |= BIT(port);
588 vlan_table[1] &= ~BIT(port);
589 vlan_table[1] &= ~(BIT(dev->cpu_port));
591 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port);
593 if (set_vlan_table(ds, vid, vlan_table)) {
594 dev_dbg(dev->dev, "Failed to set vlan table\n");
599 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
600 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid);
604 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
605 const struct switchdev_obj_port_vlan *vlan)
607 struct ksz_device *dev = ds->priv;
608 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
613 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid);
616 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
617 if (get_vlan_table(ds, vid, vlan_table)) {
618 dev_dbg(dev->dev, "Failed to get vlan table\n");
622 vlan_table[2] &= ~BIT(port);
628 vlan_table[1] &= ~BIT(port);
630 if (set_vlan_table(ds, vid, vlan_table)) {
631 dev_dbg(dev->dev, "Failed to set vlan table\n");
636 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid);
641 static int ksz_port_vlan_dump(struct dsa_switch *ds, int port,
642 struct switchdev_obj_port_vlan *vlan,
643 switchdev_obj_dump_cb_t *cb)
645 struct ksz_device *dev = ds->priv;
648 struct vlan_table *vlan_cache;
651 mutex_lock(&dev->vlan_mutex);
653 /* use dev->vlan_cache due to lack of searching valid vlan entry */
654 for (vid = vlan->vid_begin; vid < dev->num_vlans; vid++) {
655 vlan_cache = &dev->vlan_cache[vid];
657 if (!(vlan_cache->table[0] & VLAN_VALID))
660 vlan->vid_begin = vid;
663 if (vlan_cache->table[2] & BIT(port)) {
664 if (vlan_cache->table[1] & BIT(port))
665 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
666 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &data);
667 if (vid == (data & 0xFFFFF))
668 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
670 err = cb(&vlan->obj);
676 mutex_unlock(&dev->vlan_mutex);
681 static int ksz_port_fdb_prepare(struct dsa_switch *ds, int port,
682 const struct switchdev_obj_port_fdb *fdb,
683 struct switchdev_trans *trans)
709 static void ksz_port_fdb_add(struct dsa_switch *ds, int port,
710 const struct switchdev_obj_port_fdb *fdb,
711 struct switchdev_trans *trans)
713 struct ksz_device *dev = ds->priv;
717 mutex_lock(&dev->alu_mutex);
719 /* find any entry with mac & vid */
720 data = fdb->vid << ALU_FID_INDEX_S;
721 data |= ((fdb->addr[0] << 8) | fdb->addr[1]);
722 ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
724 data = ((fdb->addr[2] << 24) | (fdb->addr[3] << 16));
725 data |= ((fdb->addr[4] << 8) | fdb->addr[5]);
726 ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
728 /* start read operation */
729 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
731 /* wait to be finished */
732 if (wait_alu_ready(dev, ALU_START, 1000) < 0) {
733 dev_dbg(dev->dev, "Failed to read ALU\n");
738 read_table(ds, alu_table);
740 /* update ALU entry */
741 alu_table[0] = ALU_V_STATIC_VALID;
742 alu_table[1] |= BIT(port);
744 alu_table[1] |= ALU_V_USE_FID;
745 alu_table[2] = (fdb->vid << ALU_V_FID_S);
746 alu_table[2] |= ((fdb->addr[0] << 8) | fdb->addr[1]);
747 alu_table[3] = ((fdb->addr[2] << 24) | (fdb->addr[3] << 16));
748 alu_table[3] |= ((fdb->addr[4] << 8) | fdb->addr[5]);
750 write_table(ds, alu_table);
752 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
754 /* wait to be finished */
755 if (wait_alu_ready(dev, ALU_START, 1000) < 0)
756 dev_dbg(dev->dev, "Failed to read ALU\n");
759 mutex_unlock(&dev->alu_mutex);
762 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
763 const struct switchdev_obj_port_fdb *fdb)
765 struct ksz_device *dev = ds->priv;
770 mutex_lock(&dev->alu_mutex);
772 /* read any entry with mac & vid */
773 data = fdb->vid << ALU_FID_INDEX_S;
774 data |= ((fdb->addr[0] << 8) | fdb->addr[1]);
775 ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
777 data = ((fdb->addr[2] << 24) | (fdb->addr[3] << 16));
778 data |= ((fdb->addr[4] << 8) | fdb->addr[5]);
779 ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
781 /* start read operation */
782 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
784 /* wait to be finished */
785 ret = wait_alu_ready(dev, ALU_START, 1000);
787 dev_dbg(dev->dev, "Failed to read ALU\n");
791 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]);
792 if (alu_table[0] & ALU_V_STATIC_VALID) {
793 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]);
794 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]);
795 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]);
797 /* clear forwarding port */
798 alu_table[2] &= ~BIT(port);
800 /* if there is no port to forward, clear table */
801 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) {
814 write_table(ds, alu_table);
816 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
818 /* wait to be finished */
819 ret = wait_alu_ready(dev, ALU_START, 1000);
821 dev_dbg(dev->dev, "Failed to write ALU\n");
824 mutex_unlock(&dev->alu_mutex);
829 static void convert_alu(struct alu_struct *alu, u32 *alu_table)
831 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID);
832 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER);
833 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER);
834 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) &
835 ALU_V_PRIO_AGE_CNT_M;
836 alu->mstp = alu_table[0] & ALU_V_MSTP_M;
838 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE);
839 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID);
840 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP;
842 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M;
844 alu->mac[0] = (alu_table[2] >> 8) & 0xFF;
845 alu->mac[1] = alu_table[2] & 0xFF;
846 alu->mac[2] = (alu_table[3] >> 24) & 0xFF;
847 alu->mac[3] = (alu_table[3] >> 16) & 0xFF;
848 alu->mac[4] = (alu_table[3] >> 8) & 0xFF;
849 alu->mac[5] = alu_table[3] & 0xFF;
852 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
853 struct switchdev_obj_port_fdb *fdb,
854 switchdev_obj_dump_cb_t *cb)
856 struct ksz_device *dev = ds->priv;
860 struct alu_struct alu;
863 mutex_lock(&dev->alu_mutex);
865 /* start ALU search */
866 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH);
871 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data);
872 if ((data & ALU_VALID) || !(data & ALU_START))
875 } while (timeout-- > 0);
878 dev_dbg(dev->dev, "Failed to search ALU\n");
884 read_table(ds, alu_table);
886 convert_alu(&alu, alu_table);
888 if (alu.port_forward & BIT(port)) {
891 fdb->ndm_state = NUD_NOARP;
893 fdb->ndm_state = NUD_REACHABLE;
894 ether_addr_copy(fdb->addr, alu.mac);
900 } while (data & ALU_START);
904 /* stop ALU search */
905 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0);
907 mutex_unlock(&dev->alu_mutex);
912 static int ksz_port_mdb_prepare(struct dsa_switch *ds, int port,
913 const struct switchdev_obj_port_mdb *mdb,
914 struct switchdev_trans *trans)
920 static void ksz_port_mdb_add(struct dsa_switch *ds, int port,
921 const struct switchdev_obj_port_mdb *mdb,
922 struct switchdev_trans *trans)
924 struct ksz_device *dev = ds->priv;
930 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
931 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
932 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
934 mutex_lock(&dev->alu_mutex);
936 for (index = 0; index < dev->num_statics; index++) {
937 /* find empty slot first */
938 data = (index << ALU_STAT_INDEX_S) |
939 ALU_STAT_READ | ALU_STAT_START;
940 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
942 /* wait to be finished */
943 if (wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) {
944 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
948 /* read ALU static table */
949 read_table(ds, static_table);
951 if (static_table[0] & ALU_V_STATIC_VALID) {
952 /* check this has same vid & mac address */
953 if (((static_table[2] >> ALU_V_FID_S) == (mdb->vid)) &&
954 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
955 (static_table[3] == mac_lo)) {
956 /* found matching one */
960 /* found empty one */
965 /* no available entry */
966 if (index == dev->num_statics)
970 static_table[0] = ALU_V_STATIC_VALID;
971 static_table[1] |= BIT(port);
973 static_table[1] |= ALU_V_USE_FID;
974 static_table[2] = (mdb->vid << ALU_V_FID_S);
975 static_table[2] |= mac_hi;
976 static_table[3] = mac_lo;
978 write_table(ds, static_table);
980 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
981 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
983 /* wait to be finished */
984 if (wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0)
985 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
988 mutex_unlock(&dev->alu_mutex);
991 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
992 const struct switchdev_obj_port_mdb *mdb)
994 struct ksz_device *dev = ds->priv;
1001 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
1002 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
1003 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
1005 mutex_lock(&dev->alu_mutex);
1007 for (index = 0; index < dev->num_statics; index++) {
1008 /* find empty slot first */
1009 data = (index << ALU_STAT_INDEX_S) |
1010 ALU_STAT_READ | ALU_STAT_START;
1011 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
1013 /* wait to be finished */
1014 ret = wait_alu_sta_ready(dev, ALU_STAT_START, 1000);
1016 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
1020 /* read ALU static table */
1021 read_table(ds, static_table);
1023 if (static_table[0] & ALU_V_STATIC_VALID) {
1024 /* check this has same vid & mac address */
1026 if (((static_table[2] >> ALU_V_FID_S) == (mdb->vid)) &&
1027 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
1028 (static_table[3] == mac_lo)) {
1029 /* found matching one */
1035 /* no available entry */
1036 if (index == dev->num_statics) {
1042 static_table[1] &= ~BIT(port);
1044 if ((static_table[1] & ALU_V_PORT_MAP) == 0) {
1046 static_table[0] = 0;
1047 static_table[1] = 0;
1048 static_table[2] = 0;
1049 static_table[3] = 0;
1052 write_table(ds, static_table);
1054 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
1055 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
1057 /* wait to be finished */
1058 ret = wait_alu_sta_ready(dev, ALU_STAT_START, 1000);
1060 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
1063 mutex_unlock(&dev->alu_mutex);
1068 static int ksz_port_mdb_dump(struct dsa_switch *ds, int port,
1069 struct switchdev_obj_port_mdb *mdb,
1070 switchdev_obj_dump_cb_t *cb)
1072 /* this is not called by switch layer */
1076 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
1077 struct dsa_mall_mirror_tc_entry *mirror,
1080 struct ksz_device *dev = ds->priv;
1083 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
1085 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
1087 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
1089 /* configure mirror port */
1090 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1091 PORT_MIRROR_SNIFFER, true);
1093 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1098 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
1099 struct dsa_mall_mirror_tc_entry *mirror)
1101 struct ksz_device *dev = ds->priv;
1104 if (mirror->ingress)
1105 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1107 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1109 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1111 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX)))
1112 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1113 PORT_MIRROR_SNIFFER, false);
1116 static const struct dsa_switch_ops ksz_switch_ops = {
1117 .get_tag_protocol = ksz_get_tag_protocol,
1119 .phy_read = ksz_phy_read16,
1120 .phy_write = ksz_phy_write16,
1121 .port_enable = ksz_enable_port,
1122 .port_disable = ksz_disable_port,
1123 .get_strings = ksz_get_strings,
1124 .get_ethtool_stats = ksz_get_ethtool_stats,
1125 .get_sset_count = ksz_sset_count,
1126 .port_stp_state_set = ksz_port_stp_state_set,
1127 .port_fast_age = ksz_port_fast_age,
1128 .port_vlan_filtering = ksz_port_vlan_filtering,
1129 .port_vlan_prepare = ksz_port_vlan_prepare,
1130 .port_vlan_add = ksz_port_vlan_add,
1131 .port_vlan_del = ksz_port_vlan_del,
1132 .port_vlan_dump = ksz_port_vlan_dump,
1133 .port_fdb_prepare = ksz_port_fdb_prepare,
1134 .port_fdb_dump = ksz_port_fdb_dump,
1135 .port_fdb_add = ksz_port_fdb_add,
1136 .port_fdb_del = ksz_port_fdb_del,
1137 .port_mdb_prepare = ksz_port_mdb_prepare,
1138 .port_mdb_add = ksz_port_mdb_add,
1139 .port_mdb_del = ksz_port_mdb_del,
1140 .port_mdb_dump = ksz_port_mdb_dump,
1141 .port_mirror_add = ksz_port_mirror_add,
1142 .port_mirror_del = ksz_port_mirror_del,
1145 struct ksz_chip_data {
1147 const char *dev_name;
1155 static const struct ksz_chip_data ksz_switch_chips[] = {
1157 .chip_id = 0x00947700,
1158 .dev_name = "KSZ9477",
1162 .cpu_ports = 0x7F, /* can be configured as cpu port */
1163 .port_cnt = 7, /* total physical port count */
1167 static int ksz_switch_init(struct ksz_device *dev)
1171 mutex_init(&dev->reg_mutex);
1172 mutex_init(&dev->stats_mutex);
1173 mutex_init(&dev->alu_mutex);
1174 mutex_init(&dev->vlan_mutex);
1176 dev->ds->ops = &ksz_switch_ops;
1178 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1179 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1181 if (dev->chip_id == chip->chip_id) {
1182 dev->name = chip->dev_name;
1183 dev->num_vlans = chip->num_vlans;
1184 dev->num_alus = chip->num_alus;
1185 dev->num_statics = chip->num_statics;
1186 dev->port_cnt = chip->port_cnt;
1187 dev->cpu_ports = chip->cpu_ports;
1193 /* no switch found */
1200 struct ksz_device *ksz_switch_alloc(struct device *base,
1201 const struct ksz_io_ops *ops,
1204 struct dsa_switch *ds;
1205 struct ksz_device *swdev;
1207 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
1211 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
1224 EXPORT_SYMBOL(ksz_switch_alloc);
1226 int ksz_switch_detect(struct ksz_device *dev)
1232 /* turn off SPI DO Edge select */
1233 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
1237 data8 &= ~SPI_AUTO_EDGE_DETECTION;
1238 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1243 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32);
1247 dev->chip_id = id32;
1251 EXPORT_SYMBOL(ksz_switch_detect);
1253 int ksz_switch_register(struct ksz_device *dev)
1258 dev->chip_id = dev->pdata->chip_id;
1260 if (ksz_switch_detect(dev))
1263 ret = ksz_switch_init(dev);
1267 return dsa_register_switch(dev->ds);
1269 EXPORT_SYMBOL(ksz_switch_register);
1271 void ksz_switch_remove(struct ksz_device *dev)
1273 dsa_unregister_switch(dev->ds);
1275 EXPORT_SYMBOL(ksz_switch_remove);
1277 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1278 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
1279 MODULE_LICENSE("GPL");