drivers/net/dsa/microchip/ksz_common.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Microchip switch driver main logic
   4  *
   5  * Copyright (C) 2017-2019 Microchip Technology Inc.
   6  */
   7
   8 #include <linux/delay.h>
   9 #include <linux/dsa/ksz_common.h>
  10 #include <linux/export.h>
  11 #include <linux/gpio/consumer.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_data/microchip-ksz.h>
  15 #include <linux/phy.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/if_bridge.h>
  18 #include <linux/if_vlan.h>
  19 #include <linux/irq.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/of_mdio.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_net.h>
  24 #include <linux/micrel_phy.h>
  25 #include <net/dsa.h>
  26 #include <net/pkt_cls.h>
  27 #include <net/switchdev.h>
  28
  29 #include "ksz_common.h"
  30 #include "ksz_ptp.h"
  31 #include "ksz8.h"
  32 #include "ksz9477.h"
  33 #include "lan937x.h"
  34
  35 #define MIB_COUNTER_NUM 0x20
  36
  37 struct ksz_stats_raw {
  38         u64 rx_hi;
  39         u64 rx_undersize;
  40         u64 rx_fragments;
  41         u64 rx_oversize;
  42         u64 rx_jabbers;
  43         u64 rx_symbol_err;
  44         u64 rx_crc_err;
  45         u64 rx_align_err;
  46         u64 rx_mac_ctrl;
  47         u64 rx_pause;
  48         u64 rx_bcast;
  49         u64 rx_mcast;
  50         u64 rx_ucast;
  51         u64 rx_64_or_less;
  52         u64 rx_65_127;
  53         u64 rx_128_255;
  54         u64 rx_256_511;
  55         u64 rx_512_1023;
  56         u64 rx_1024_1522;
  57         u64 rx_1523_2000;
  58         u64 rx_2001;
  59         u64 tx_hi;
  60         u64 tx_late_col;
  61         u64 tx_pause;
  62         u64 tx_bcast;
  63         u64 tx_mcast;
  64         u64 tx_ucast;
  65         u64 tx_deferred;
  66         u64 tx_total_col;
  67         u64 tx_exc_col;
  68         u64 tx_single_col;
  69         u64 tx_mult_col;
  70         u64 rx_total;
  71         u64 tx_total;
  72         u64 rx_discards;
  73         u64 tx_discards;
  74 };
  75
  76 struct ksz88xx_stats_raw {
  77         u64 rx;
  78         u64 rx_hi;
  79         u64 rx_undersize;
  80         u64 rx_fragments;
  81         u64 rx_oversize;
  82         u64 rx_jabbers;
  83         u64 rx_symbol_err;
  84         u64 rx_crc_err;
  85         u64 rx_align_err;
  86         u64 rx_mac_ctrl;
  87         u64 rx_pause;
  88         u64 rx_bcast;
  89         u64 rx_mcast;
  90         u64 rx_ucast;
  91         u64 rx_64_or_less;
  92         u64 rx_65_127;
  93         u64 rx_128_255;
  94         u64 rx_256_511;
  95         u64 rx_512_1023;
  96         u64 rx_1024_1522;
  97         u64 tx;
  98         u64 tx_hi;
  99         u64 tx_late_col;
 100         u64 tx_pause;
 101         u64 tx_bcast;
 102         u64 tx_mcast;
 103         u64 tx_ucast;
 104         u64 tx_deferred;
 105         u64 tx_total_col;
 106         u64 tx_exc_col;
 107         u64 tx_single_col;
 108         u64 tx_mult_col;
 109         u64 rx_discards;
 110         u64 tx_discards;
 111 };
 112
 113 static const struct ksz_mib_names ksz88xx_mib_names[] = {
 114         { 0x00, "rx" },
 115         { 0x01, "rx_hi" },
 116         { 0x02, "rx_undersize" },
 117         { 0x03, "rx_fragments" },
 118         { 0x04, "rx_oversize" },
 119         { 0x05, "rx_jabbers" },
 120         { 0x06, "rx_symbol_err" },
 121         { 0x07, "rx_crc_err" },
 122         { 0x08, "rx_align_err" },
 123         { 0x09, "rx_mac_ctrl" },
 124         { 0x0a, "rx_pause" },
 125         { 0x0b, "rx_bcast" },
 126         { 0x0c, "rx_mcast" },
 127         { 0x0d, "rx_ucast" },
 128         { 0x0e, "rx_64_or_less" },
 129         { 0x0f, "rx_65_127" },
 130         { 0x10, "rx_128_255" },
 131         { 0x11, "rx_256_511" },
 132         { 0x12, "rx_512_1023" },
 133         { 0x13, "rx_1024_1522" },
 134         { 0x14, "tx" },
 135         { 0x15, "tx_hi" },
 136         { 0x16, "tx_late_col" },
 137         { 0x17, "tx_pause" },
 138         { 0x18, "tx_bcast" },
 139         { 0x19, "tx_mcast" },
 140         { 0x1a, "tx_ucast" },
 141         { 0x1b, "tx_deferred" },
 142         { 0x1c, "tx_total_col" },
 143         { 0x1d, "tx_exc_col" },
 144         { 0x1e, "tx_single_col" },
 145         { 0x1f, "tx_mult_col" },
 146         { 0x100, "rx_discards" },
 147         { 0x101, "tx_discards" },
 148 };
 149
 150 static const struct ksz_mib_names ksz9477_mib_names[] = {
 151         { 0x00, "rx_hi" },
 152         { 0x01, "rx_undersize" },
 153         { 0x02, "rx_fragments" },
 154         { 0x03, "rx_oversize" },
 155         { 0x04, "rx_jabbers" },
 156         { 0x05, "rx_symbol_err" },
 157         { 0x06, "rx_crc_err" },
 158         { 0x07, "rx_align_err" },
 159         { 0x08, "rx_mac_ctrl" },
 160         { 0x09, "rx_pause" },
 161         { 0x0A, "rx_bcast" },
 162         { 0x0B, "rx_mcast" },
 163         { 0x0C, "rx_ucast" },
 164         { 0x0D, "rx_64_or_less" },
 165         { 0x0E, "rx_65_127" },
 166         { 0x0F, "rx_128_255" },
 167         { 0x10, "rx_256_511" },
 168         { 0x11, "rx_512_1023" },
 169         { 0x12, "rx_1024_1522" },
 170         { 0x13, "rx_1523_2000" },
 171         { 0x14, "rx_2001" },
 172         { 0x15, "tx_hi" },
 173         { 0x16, "tx_late_col" },
 174         { 0x17, "tx_pause" },
 175         { 0x18, "tx_bcast" },
 176         { 0x19, "tx_mcast" },
 177         { 0x1A, "tx_ucast" },
 178         { 0x1B, "tx_deferred" },
 179         { 0x1C, "tx_total_col" },
 180         { 0x1D, "tx_exc_col" },
 181         { 0x1E, "tx_single_col" },
 182         { 0x1F, "tx_mult_col" },
 183         { 0x80, "rx_total" },
 184         { 0x81, "tx_total" },
 185         { 0x82, "rx_discards" },
 186         { 0x83, "tx_discards" },
 187 };
 188
 189 static const struct ksz_dev_ops ksz8_dev_ops = {
 190         .setup = ksz8_setup,
 191         .get_port_addr = ksz8_get_port_addr,
 192         .cfg_port_member = ksz8_cfg_port_member,
 193         .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
 194         .port_setup = ksz8_port_setup,
 195         .r_phy = ksz8_r_phy,
 196         .w_phy = ksz8_w_phy,
 197         .r_mib_cnt = ksz8_r_mib_cnt,
 198         .r_mib_pkt = ksz8_r_mib_pkt,
 199         .r_mib_stat64 = ksz88xx_r_mib_stats64,
 200         .freeze_mib = ksz8_freeze_mib,
 201         .port_init_cnt = ksz8_port_init_cnt,
 202         .fdb_dump = ksz8_fdb_dump,
 203         .fdb_add = ksz8_fdb_add,
 204         .fdb_del = ksz8_fdb_del,
 205         .mdb_add = ksz8_mdb_add,
 206         .mdb_del = ksz8_mdb_del,
 207         .vlan_filtering = ksz8_port_vlan_filtering,
 208         .vlan_add = ksz8_port_vlan_add,
 209         .vlan_del = ksz8_port_vlan_del,
 210         .mirror_add = ksz8_port_mirror_add,
 211         .mirror_del = ksz8_port_mirror_del,
 212         .get_caps = ksz8_get_caps,
 213         .config_cpu_port = ksz8_config_cpu_port,
 214         .enable_stp_addr = ksz8_enable_stp_addr,
 215         .reset = ksz8_reset_switch,
 216         .init = ksz8_switch_init,
 217         .exit = ksz8_switch_exit,
 218         .change_mtu = ksz8_change_mtu,
 219 };
 220
 221 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
 222                                         unsigned int mode,
 223                                         phy_interface_t interface,
 224                                         struct phy_device *phydev, int speed,
 225                                         int duplex, bool tx_pause,
 226                                         bool rx_pause);
 227
 228 static const struct ksz_dev_ops ksz9477_dev_ops = {
 229         .setup = ksz9477_setup,
 230         .get_port_addr = ksz9477_get_port_addr,
 231         .cfg_port_member = ksz9477_cfg_port_member,
 232         .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
 233         .port_setup = ksz9477_port_setup,
 234         .set_ageing_time = ksz9477_set_ageing_time,
 235         .r_phy = ksz9477_r_phy,
 236         .w_phy = ksz9477_w_phy,
 237         .r_mib_cnt = ksz9477_r_mib_cnt,
 238         .r_mib_pkt = ksz9477_r_mib_pkt,
 239         .r_mib_stat64 = ksz_r_mib_stats64,
 240         .freeze_mib = ksz9477_freeze_mib,
 241         .port_init_cnt = ksz9477_port_init_cnt,
 242         .vlan_filtering = ksz9477_port_vlan_filtering,
 243         .vlan_add = ksz9477_port_vlan_add,
 244         .vlan_del = ksz9477_port_vlan_del,
 245         .mirror_add = ksz9477_port_mirror_add,
 246         .mirror_del = ksz9477_port_mirror_del,
 247         .get_caps = ksz9477_get_caps,
 248         .fdb_dump = ksz9477_fdb_dump,
 249         .fdb_add = ksz9477_fdb_add,
 250         .fdb_del = ksz9477_fdb_del,
 251         .mdb_add = ksz9477_mdb_add,
 252         .mdb_del = ksz9477_mdb_del,
 253         .change_mtu = ksz9477_change_mtu,
 254         .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
 255         .config_cpu_port = ksz9477_config_cpu_port,
 256         .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
 257         .enable_stp_addr = ksz9477_enable_stp_addr,
 258         .reset = ksz9477_reset_switch,
 259         .init = ksz9477_switch_init,
 260         .exit = ksz9477_switch_exit,
 261 };
 262
 263 static const struct ksz_dev_ops lan937x_dev_ops = {
 264         .setup = lan937x_setup,
 265         .teardown = lan937x_teardown,
 266         .get_port_addr = ksz9477_get_port_addr,
 267         .cfg_port_member = ksz9477_cfg_port_member,
 268         .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
 269         .port_setup = lan937x_port_setup,
 270         .set_ageing_time = lan937x_set_ageing_time,
 271         .r_phy = lan937x_r_phy,
 272         .w_phy = lan937x_w_phy,
 273         .r_mib_cnt = ksz9477_r_mib_cnt,
 274         .r_mib_pkt = ksz9477_r_mib_pkt,
 275         .r_mib_stat64 = ksz_r_mib_stats64,
 276         .freeze_mib = ksz9477_freeze_mib,
 277         .port_init_cnt = ksz9477_port_init_cnt,
 278         .vlan_filtering = ksz9477_port_vlan_filtering,
 279         .vlan_add = ksz9477_port_vlan_add,
 280         .vlan_del = ksz9477_port_vlan_del,
 281         .mirror_add = ksz9477_port_mirror_add,
 282         .mirror_del = ksz9477_port_mirror_del,
 283         .get_caps = lan937x_phylink_get_caps,
 284         .setup_rgmii_delay = lan937x_setup_rgmii_delay,
 285         .fdb_dump = ksz9477_fdb_dump,
 286         .fdb_add = ksz9477_fdb_add,
 287         .fdb_del = ksz9477_fdb_del,
 288         .mdb_add = ksz9477_mdb_add,
 289         .mdb_del = ksz9477_mdb_del,
 290         .change_mtu = lan937x_change_mtu,
 291         .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
 292         .config_cpu_port = lan937x_config_cpu_port,
 293         .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
 294         .enable_stp_addr = ksz9477_enable_stp_addr,
 295         .reset = lan937x_reset_switch,
 296         .init = lan937x_switch_init,
 297         .exit = lan937x_switch_exit,
 298 };
 299
 300 static const u16 ksz8795_regs[] = {
 301         [REG_IND_CTRL_0]                = 0x6E,
 302         [REG_IND_DATA_8]                = 0x70,
 303         [REG_IND_DATA_CHECK]            = 0x72,
 304         [REG_IND_DATA_HI]               = 0x71,
 305         [REG_IND_DATA_LO]               = 0x75,
 306         [REG_IND_MIB_CHECK]             = 0x74,
 307         [REG_IND_BYTE]                  = 0xA0,
 308         [P_FORCE_CTRL]                  = 0x0C,
 309         [P_LINK_STATUS]                 = 0x0E,
 310         [P_LOCAL_CTRL]                  = 0x07,
 311         [P_NEG_RESTART_CTRL]            = 0x0D,
 312         [P_REMOTE_STATUS]               = 0x08,
 313         [P_SPEED_STATUS]                = 0x09,
 314         [S_TAIL_TAG_CTRL]               = 0x0C,
 315         [P_STP_CTRL]                    = 0x02,
 316         [S_START_CTRL]                  = 0x01,
 317         [S_BROADCAST_CTRL]              = 0x06,
 318         [S_MULTICAST_CTRL]              = 0x04,
 319         [P_XMII_CTRL_0]                 = 0x06,
 320         [P_XMII_CTRL_1]                 = 0x06,
 321 };
 322
 323 static const u32 ksz8795_masks[] = {
 324         [PORT_802_1P_REMAPPING]         = BIT(7),
 325         [SW_TAIL_TAG_ENABLE]            = BIT(1),
 326         [MIB_COUNTER_OVERFLOW]          = BIT(6),
 327         [MIB_COUNTER_VALID]             = BIT(5),
 328         [VLAN_TABLE_FID]                = GENMASK(6, 0),
 329         [VLAN_TABLE_MEMBERSHIP]         = GENMASK(11, 7),
 330         [VLAN_TABLE_VALID]              = BIT(12),
 331         [STATIC_MAC_TABLE_VALID]        = BIT(21),
 332         [STATIC_MAC_TABLE_USE_FID]      = BIT(23),
 333         [STATIC_MAC_TABLE_FID]          = GENMASK(30, 24),
 334         [STATIC_MAC_TABLE_OVERRIDE]     = BIT(22),
 335         [STATIC_MAC_TABLE_FWD_PORTS]    = GENMASK(20, 16),
 336         [DYNAMIC_MAC_TABLE_ENTRIES_H]   = GENMASK(6, 0),
 337         [DYNAMIC_MAC_TABLE_MAC_EMPTY]   = BIT(7),
 338         [DYNAMIC_MAC_TABLE_NOT_READY]   = BIT(7),
 339         [DYNAMIC_MAC_TABLE_ENTRIES]     = GENMASK(31, 29),
 340         [DYNAMIC_MAC_TABLE_FID]         = GENMASK(22, 16),
 341         [DYNAMIC_MAC_TABLE_SRC_PORT]    = GENMASK(26, 24),
 342         [DYNAMIC_MAC_TABLE_TIMESTAMP]   = GENMASK(28, 27),
 343         [P_MII_TX_FLOW_CTRL]            = BIT(5),
 344         [P_MII_RX_FLOW_CTRL]            = BIT(5),
 345 };
 346
 347 static const u8 ksz8795_xmii_ctrl0[] = {
 348         [P_MII_100MBIT]                 = 0,
 349         [P_MII_10MBIT]                  = 1,
 350         [P_MII_FULL_DUPLEX]             = 0,
 351         [P_MII_HALF_DUPLEX]             = 1,
 352 };
 353
 354 static const u8 ksz8795_xmii_ctrl1[] = {
 355         [P_RGMII_SEL]                   = 3,
 356         [P_GMII_SEL]                    = 2,
 357         [P_RMII_SEL]                    = 1,
 358         [P_MII_SEL]                     = 0,
 359         [P_GMII_1GBIT]                  = 1,
 360         [P_GMII_NOT_1GBIT]              = 0,
 361 };
 362
 363 static const u8 ksz8795_shifts[] = {
 364         [VLAN_TABLE_MEMBERSHIP_S]       = 7,
 365         [VLAN_TABLE]                    = 16,
 366         [STATIC_MAC_FWD_PORTS]          = 16,
 367         [STATIC_MAC_FID]                = 24,
 368         [DYNAMIC_MAC_ENTRIES_H]         = 3,
 369         [DYNAMIC_MAC_ENTRIES]           = 29,
 370         [DYNAMIC_MAC_FID]               = 16,
 371         [DYNAMIC_MAC_TIMESTAMP]         = 27,
 372         [DYNAMIC_MAC_SRC_PORT]          = 24,
 373 };
 374
 375 static const u16 ksz8863_regs[] = {
 376         [REG_IND_CTRL_0]                = 0x79,
 377         [REG_IND_DATA_8]                = 0x7B,
 378         [REG_IND_DATA_CHECK]            = 0x7B,
 379         [REG_IND_DATA_HI]               = 0x7C,
 380         [REG_IND_DATA_LO]               = 0x80,
 381         [REG_IND_MIB_CHECK]             = 0x80,
 382         [P_FORCE_CTRL]                  = 0x0C,
 383         [P_LINK_STATUS]                 = 0x0E,
 384         [P_LOCAL_CTRL]                  = 0x0C,
 385         [P_NEG_RESTART_CTRL]            = 0x0D,
 386         [P_REMOTE_STATUS]               = 0x0E,
 387         [P_SPEED_STATUS]                = 0x0F,
 388         [S_TAIL_TAG_CTRL]               = 0x03,
 389         [P_STP_CTRL]                    = 0x02,
 390         [S_START_CTRL]                  = 0x01,
 391         [S_BROADCAST_CTRL]              = 0x06,
 392         [S_MULTICAST_CTRL]              = 0x04,
 393 };
 394
 395 static const u32 ksz8863_masks[] = {
 396         [PORT_802_1P_REMAPPING]         = BIT(3),
 397         [SW_TAIL_TAG_ENABLE]            = BIT(6),
 398         [MIB_COUNTER_OVERFLOW]          = BIT(7),
 399         [MIB_COUNTER_VALID]             = BIT(6),
 400         [VLAN_TABLE_FID]                = GENMASK(15, 12),
 401         [VLAN_TABLE_MEMBERSHIP]         = GENMASK(18, 16),
 402         [VLAN_TABLE_VALID]              = BIT(19),
 403         [STATIC_MAC_TABLE_VALID]        = BIT(19),
 404         [STATIC_MAC_TABLE_USE_FID]      = BIT(21),
 405         [STATIC_MAC_TABLE_FID]          = GENMASK(25, 22),
 406         [STATIC_MAC_TABLE_OVERRIDE]     = BIT(20),
 407         [STATIC_MAC_TABLE_FWD_PORTS]    = GENMASK(18, 16),
 408         [DYNAMIC_MAC_TABLE_ENTRIES_H]   = GENMASK(1, 0),
 409         [DYNAMIC_MAC_TABLE_MAC_EMPTY]   = BIT(2),
 410         [DYNAMIC_MAC_TABLE_NOT_READY]   = BIT(7),
 411         [DYNAMIC_MAC_TABLE_ENTRIES]     = GENMASK(31, 24),
 412         [DYNAMIC_MAC_TABLE_FID]         = GENMASK(19, 16),
 413         [DYNAMIC_MAC_TABLE_SRC_PORT]    = GENMASK(21, 20),
 414         [DYNAMIC_MAC_TABLE_TIMESTAMP]   = GENMASK(23, 22),
 415 };
 416
 417 static u8 ksz8863_shifts[] = {
 418         [VLAN_TABLE_MEMBERSHIP_S]       = 16,
 419         [STATIC_MAC_FWD_PORTS]          = 16,
 420         [STATIC_MAC_FID]                = 22,
 421         [DYNAMIC_MAC_ENTRIES_H]         = 8,
 422         [DYNAMIC_MAC_ENTRIES]           = 24,
 423         [DYNAMIC_MAC_FID]               = 16,
 424         [DYNAMIC_MAC_TIMESTAMP]         = 22,
 425         [DYNAMIC_MAC_SRC_PORT]          = 20,
 426 };
 427
 428 static const u16 ksz9477_regs[] = {
 429         [P_STP_CTRL]                    = 0x0B04,
 430         [S_START_CTRL]                  = 0x0300,
 431         [S_BROADCAST_CTRL]              = 0x0332,
 432         [S_MULTICAST_CTRL]              = 0x0331,
 433         [P_XMII_CTRL_0]                 = 0x0300,
 434         [P_XMII_CTRL_1]                 = 0x0301,
 435 };
 436
 437 static const u32 ksz9477_masks[] = {
 438         [ALU_STAT_WRITE]                = 0,
 439         [ALU_STAT_READ]                 = 1,
 440         [P_MII_TX_FLOW_CTRL]            = BIT(5),
 441         [P_MII_RX_FLOW_CTRL]            = BIT(3),
 442 };
 443
 444 static const u8 ksz9477_shifts[] = {
 445         [ALU_STAT_INDEX]                = 16,
 446 };
 447
 448 static const u8 ksz9477_xmii_ctrl0[] = {
 449         [P_MII_100MBIT]                 = 1,
 450         [P_MII_10MBIT]                  = 0,
 451         [P_MII_FULL_DUPLEX]             = 1,
 452         [P_MII_HALF_DUPLEX]             = 0,
 453 };
 454
 455 static const u8 ksz9477_xmii_ctrl1[] = {
 456         [P_RGMII_SEL]                   = 0,
 457         [P_RMII_SEL]                    = 1,
 458         [P_GMII_SEL]                    = 2,
 459         [P_MII_SEL]                     = 3,
 460         [P_GMII_1GBIT]                  = 0,
 461         [P_GMII_NOT_1GBIT]              = 1,
 462 };
 463
 464 static const u32 lan937x_masks[] = {
 465         [ALU_STAT_WRITE]                = 1,
 466         [ALU_STAT_READ]                 = 2,
 467         [P_MII_TX_FLOW_CTRL]            = BIT(5),
 468         [P_MII_RX_FLOW_CTRL]            = BIT(3),
 469 };
 470
 471 static const u8 lan937x_shifts[] = {
 472         [ALU_STAT_INDEX]                = 8,
 473 };
 474
 475 static const struct regmap_range ksz8563_valid_regs[] = {
 476         regmap_reg_range(0x0000, 0x0003),
 477         regmap_reg_range(0x0006, 0x0006),
 478         regmap_reg_range(0x000f, 0x001f),
 479         regmap_reg_range(0x0100, 0x0100),
 480         regmap_reg_range(0x0104, 0x0107),
 481         regmap_reg_range(0x010d, 0x010d),
 482         regmap_reg_range(0x0110, 0x0113),
 483         regmap_reg_range(0x0120, 0x012b),
 484         regmap_reg_range(0x0201, 0x0201),
 485         regmap_reg_range(0x0210, 0x0213),
 486         regmap_reg_range(0x0300, 0x0300),
 487         regmap_reg_range(0x0302, 0x031b),
 488         regmap_reg_range(0x0320, 0x032b),
 489         regmap_reg_range(0x0330, 0x0336),
 490         regmap_reg_range(0x0338, 0x033e),
 491         regmap_reg_range(0x0340, 0x035f),
 492         regmap_reg_range(0x0370, 0x0370),
 493         regmap_reg_range(0x0378, 0x0378),
 494         regmap_reg_range(0x037c, 0x037d),
 495         regmap_reg_range(0x0390, 0x0393),
 496         regmap_reg_range(0x0400, 0x040e),
 497         regmap_reg_range(0x0410, 0x042f),
 498         regmap_reg_range(0x0500, 0x0519),
 499         regmap_reg_range(0x0520, 0x054b),
 500         regmap_reg_range(0x0550, 0x05b3),
 501
 502         /* port 1 */
 503         regmap_reg_range(0x1000, 0x1001),
 504         regmap_reg_range(0x1004, 0x100b),
 505         regmap_reg_range(0x1013, 0x1013),
 506         regmap_reg_range(0x1017, 0x1017),
 507         regmap_reg_range(0x101b, 0x101b),
 508         regmap_reg_range(0x101f, 0x1021),
 509         regmap_reg_range(0x1030, 0x1030),
 510         regmap_reg_range(0x1100, 0x1111),
 511         regmap_reg_range(0x111a, 0x111d),
 512         regmap_reg_range(0x1122, 0x1127),
 513         regmap_reg_range(0x112a, 0x112b),
 514         regmap_reg_range(0x1136, 0x1139),
 515         regmap_reg_range(0x113e, 0x113f),
 516         regmap_reg_range(0x1400, 0x1401),
 517         regmap_reg_range(0x1403, 0x1403),
 518         regmap_reg_range(0x1410, 0x1417),
 519         regmap_reg_range(0x1420, 0x1423),
 520         regmap_reg_range(0x1500, 0x1507),
 521         regmap_reg_range(0x1600, 0x1612),
 522         regmap_reg_range(0x1800, 0x180f),
 523         regmap_reg_range(0x1900, 0x1907),
 524         regmap_reg_range(0x1914, 0x191b),
 525         regmap_reg_range(0x1a00, 0x1a03),
 526         regmap_reg_range(0x1a04, 0x1a08),
 527         regmap_reg_range(0x1b00, 0x1b01),
 528         regmap_reg_range(0x1b04, 0x1b04),
 529         regmap_reg_range(0x1c00, 0x1c05),
 530         regmap_reg_range(0x1c08, 0x1c1b),
 531
 532         /* port 2 */
 533         regmap_reg_range(0x2000, 0x2001),
 534         regmap_reg_range(0x2004, 0x200b),
 535         regmap_reg_range(0x2013, 0x2013),
 536         regmap_reg_range(0x2017, 0x2017),
 537         regmap_reg_range(0x201b, 0x201b),
 538         regmap_reg_range(0x201f, 0x2021),
 539         regmap_reg_range(0x2030, 0x2030),
 540         regmap_reg_range(0x2100, 0x2111),
 541         regmap_reg_range(0x211a, 0x211d),
 542         regmap_reg_range(0x2122, 0x2127),
 543         regmap_reg_range(0x212a, 0x212b),
 544         regmap_reg_range(0x2136, 0x2139),
 545         regmap_reg_range(0x213e, 0x213f),
 546         regmap_reg_range(0x2400, 0x2401),
 547         regmap_reg_range(0x2403, 0x2403),
 548         regmap_reg_range(0x2410, 0x2417),
 549         regmap_reg_range(0x2420, 0x2423),
 550         regmap_reg_range(0x2500, 0x2507),
 551         regmap_reg_range(0x2600, 0x2612),
 552         regmap_reg_range(0x2800, 0x280f),
 553         regmap_reg_range(0x2900, 0x2907),
 554         regmap_reg_range(0x2914, 0x291b),
 555         regmap_reg_range(0x2a00, 0x2a03),
 556         regmap_reg_range(0x2a04, 0x2a08),
 557         regmap_reg_range(0x2b00, 0x2b01),
 558         regmap_reg_range(0x2b04, 0x2b04),
 559         regmap_reg_range(0x2c00, 0x2c05),
 560         regmap_reg_range(0x2c08, 0x2c1b),
 561
 562         /* port 3 */
 563         regmap_reg_range(0x3000, 0x3001),
 564         regmap_reg_range(0x3004, 0x300b),
 565         regmap_reg_range(0x3013, 0x3013),
 566         regmap_reg_range(0x3017, 0x3017),
 567         regmap_reg_range(0x301b, 0x301b),
 568         regmap_reg_range(0x301f, 0x3021),
 569         regmap_reg_range(0x3030, 0x3030),
 570         regmap_reg_range(0x3300, 0x3301),
 571         regmap_reg_range(0x3303, 0x3303),
 572         regmap_reg_range(0x3400, 0x3401),
 573         regmap_reg_range(0x3403, 0x3403),
 574         regmap_reg_range(0x3410, 0x3417),
 575         regmap_reg_range(0x3420, 0x3423),
 576         regmap_reg_range(0x3500, 0x3507),
 577         regmap_reg_range(0x3600, 0x3612),
 578         regmap_reg_range(0x3800, 0x380f),
 579         regmap_reg_range(0x3900, 0x3907),
 580         regmap_reg_range(0x3914, 0x391b),
 581         regmap_reg_range(0x3a00, 0x3a03),
 582         regmap_reg_range(0x3a04, 0x3a08),
 583         regmap_reg_range(0x3b00, 0x3b01),
 584         regmap_reg_range(0x3b04, 0x3b04),
 585         regmap_reg_range(0x3c00, 0x3c05),
 586         regmap_reg_range(0x3c08, 0x3c1b),
 587 };
 588
 589 static const struct regmap_access_table ksz8563_register_set = {
 590         .yes_ranges = ksz8563_valid_regs,
 591         .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
 592 };
 593
 594 static const struct regmap_range ksz9477_valid_regs[] = {
 595         regmap_reg_range(0x0000, 0x0003),
 596         regmap_reg_range(0x0006, 0x0006),
 597         regmap_reg_range(0x0010, 0x001f),
 598         regmap_reg_range(0x0100, 0x0100),
 599         regmap_reg_range(0x0103, 0x0107),
 600         regmap_reg_range(0x010d, 0x010d),
 601         regmap_reg_range(0x0110, 0x0113),
 602         regmap_reg_range(0x0120, 0x012b),
 603         regmap_reg_range(0x0201, 0x0201),
 604         regmap_reg_range(0x0210, 0x0213),
 605         regmap_reg_range(0x0300, 0x0300),
 606         regmap_reg_range(0x0302, 0x031b),
 607         regmap_reg_range(0x0320, 0x032b),
 608         regmap_reg_range(0x0330, 0x0336),
 609         regmap_reg_range(0x0338, 0x033b),
 610         regmap_reg_range(0x033e, 0x033e),
 611         regmap_reg_range(0x0340, 0x035f),
 612         regmap_reg_range(0x0370, 0x0370),
 613         regmap_reg_range(0x0378, 0x0378),
 614         regmap_reg_range(0x037c, 0x037d),
 615         regmap_reg_range(0x0390, 0x0393),
 616         regmap_reg_range(0x0400, 0x040e),
 617         regmap_reg_range(0x0410, 0x042f),
 618         regmap_reg_range(0x0444, 0x044b),
 619         regmap_reg_range(0x0450, 0x046f),
 620         regmap_reg_range(0x0500, 0x0519),
 621         regmap_reg_range(0x0520, 0x054b),
 622         regmap_reg_range(0x0550, 0x05b3),
 623         regmap_reg_range(0x0604, 0x060b),
 624         regmap_reg_range(0x0610, 0x0612),
 625         regmap_reg_range(0x0614, 0x062c),
 626         regmap_reg_range(0x0640, 0x0645),
 627         regmap_reg_range(0x0648, 0x064d),
 628
 629         /* port 1 */
 630         regmap_reg_range(0x1000, 0x1001),
 631         regmap_reg_range(0x1013, 0x1013),
 632         regmap_reg_range(0x1017, 0x1017),
 633         regmap_reg_range(0x101b, 0x101b),
 634         regmap_reg_range(0x101f, 0x1020),
 635         regmap_reg_range(0x1030, 0x1030),
 636         regmap_reg_range(0x1100, 0x1115),
 637         regmap_reg_range(0x111a, 0x111f),
 638         regmap_reg_range(0x1120, 0x112b),
 639         regmap_reg_range(0x1134, 0x113b),
 640         regmap_reg_range(0x113c, 0x113f),
 641         regmap_reg_range(0x1400, 0x1401),
 642         regmap_reg_range(0x1403, 0x1403),
 643         regmap_reg_range(0x1410, 0x1417),
 644         regmap_reg_range(0x1420, 0x1423),
 645         regmap_reg_range(0x1500, 0x1507),
 646         regmap_reg_range(0x1600, 0x1613),
 647         regmap_reg_range(0x1800, 0x180f),
 648         regmap_reg_range(0x1820, 0x1827),
 649         regmap_reg_range(0x1830, 0x1837),
 650         regmap_reg_range(0x1840, 0x184b),
 651         regmap_reg_range(0x1900, 0x1907),
 652         regmap_reg_range(0x1914, 0x191b),
 653         regmap_reg_range(0x1920, 0x1920),
 654         regmap_reg_range(0x1923, 0x1927),
 655         regmap_reg_range(0x1a00, 0x1a03),
 656         regmap_reg_range(0x1a04, 0x1a07),
 657         regmap_reg_range(0x1b00, 0x1b01),
 658         regmap_reg_range(0x1b04, 0x1b04),
 659         regmap_reg_range(0x1c00, 0x1c05),
 660         regmap_reg_range(0x1c08, 0x1c1b),
 661
 662         /* port 2 */
 663         regmap_reg_range(0x2000, 0x2001),
 664         regmap_reg_range(0x2013, 0x2013),
 665         regmap_reg_range(0x2017, 0x2017),
 666         regmap_reg_range(0x201b, 0x201b),
 667         regmap_reg_range(0x201f, 0x2020),
 668         regmap_reg_range(0x2030, 0x2030),
 669         regmap_reg_range(0x2100, 0x2115),
 670         regmap_reg_range(0x211a, 0x211f),
 671         regmap_reg_range(0x2120, 0x212b),
 672         regmap_reg_range(0x2134, 0x213b),
 673         regmap_reg_range(0x213c, 0x213f),
 674         regmap_reg_range(0x2400, 0x2401),
 675         regmap_reg_range(0x2403, 0x2403),
 676         regmap_reg_range(0x2410, 0x2417),
 677         regmap_reg_range(0x2420, 0x2423),
 678         regmap_reg_range(0x2500, 0x2507),
 679         regmap_reg_range(0x2600, 0x2613),
 680         regmap_reg_range(0x2800, 0x280f),
 681         regmap_reg_range(0x2820, 0x2827),
 682         regmap_reg_range(0x2830, 0x2837),
 683         regmap_reg_range(0x2840, 0x284b),
 684         regmap_reg_range(0x2900, 0x2907),
 685         regmap_reg_range(0x2914, 0x291b),
 686         regmap_reg_range(0x2920, 0x2920),
 687         regmap_reg_range(0x2923, 0x2927),
 688         regmap_reg_range(0x2a00, 0x2a03),
 689         regmap_reg_range(0x2a04, 0x2a07),
 690         regmap_reg_range(0x2b00, 0x2b01),
 691         regmap_reg_range(0x2b04, 0x2b04),
 692         regmap_reg_range(0x2c00, 0x2c05),
 693         regmap_reg_range(0x2c08, 0x2c1b),
 694
 695         /* port 3 */
 696         regmap_reg_range(0x3000, 0x3001),
 697         regmap_reg_range(0x3013, 0x3013),
 698         regmap_reg_range(0x3017, 0x3017),
 699         regmap_reg_range(0x301b, 0x301b),
 700         regmap_reg_range(0x301f, 0x3020),
 701         regmap_reg_range(0x3030, 0x3030),
 702         regmap_reg_range(0x3100, 0x3115),
 703         regmap_reg_range(0x311a, 0x311f),
 704         regmap_reg_range(0x3120, 0x312b),
 705         regmap_reg_range(0x3134, 0x313b),
 706         regmap_reg_range(0x313c, 0x313f),
 707         regmap_reg_range(0x3400, 0x3401),
 708         regmap_reg_range(0x3403, 0x3403),
 709         regmap_reg_range(0x3410, 0x3417),
 710         regmap_reg_range(0x3420, 0x3423),
 711         regmap_reg_range(0x3500, 0x3507),
 712         regmap_reg_range(0x3600, 0x3613),
 713         regmap_reg_range(0x3800, 0x380f),
 714         regmap_reg_range(0x3820, 0x3827),
 715         regmap_reg_range(0x3830, 0x3837),
 716         regmap_reg_range(0x3840, 0x384b),
 717         regmap_reg_range(0x3900, 0x3907),
 718         regmap_reg_range(0x3914, 0x391b),
 719         regmap_reg_range(0x3920, 0x3920),
 720         regmap_reg_range(0x3923, 0x3927),
 721         regmap_reg_range(0x3a00, 0x3a03),
 722         regmap_reg_range(0x3a04, 0x3a07),
 723         regmap_reg_range(0x3b00, 0x3b01),
 724         regmap_reg_range(0x3b04, 0x3b04),
 725         regmap_reg_range(0x3c00, 0x3c05),
 726         regmap_reg_range(0x3c08, 0x3c1b),
 727
 728         /* port 4 */
 729         regmap_reg_range(0x4000, 0x4001),
 730         regmap_reg_range(0x4013, 0x4013),
 731         regmap_reg_range(0x4017, 0x4017),
 732         regmap_reg_range(0x401b, 0x401b),
 733         regmap_reg_range(0x401f, 0x4020),
 734         regmap_reg_range(0x4030, 0x4030),
 735         regmap_reg_range(0x4100, 0x4115),
 736         regmap_reg_range(0x411a, 0x411f),
 737         regmap_reg_range(0x4120, 0x412b),
 738         regmap_reg_range(0x4134, 0x413b),
 739         regmap_reg_range(0x413c, 0x413f),
 740         regmap_reg_range(0x4400, 0x4401),
 741         regmap_reg_range(0x4403, 0x4403),
 742         regmap_reg_range(0x4410, 0x4417),
 743         regmap_reg_range(0x4420, 0x4423),
 744         regmap_reg_range(0x4500, 0x4507),
 745         regmap_reg_range(0x4600, 0x4613),
 746         regmap_reg_range(0x4800, 0x480f),
 747         regmap_reg_range(0x4820, 0x4827),
 748         regmap_reg_range(0x4830, 0x4837),
 749         regmap_reg_range(0x4840, 0x484b),
 750         regmap_reg_range(0x4900, 0x4907),
 751         regmap_reg_range(0x4914, 0x491b),
 752         regmap_reg_range(0x4920, 0x4920),
 753         regmap_reg_range(0x4923, 0x4927),
 754         regmap_reg_range(0x4a00, 0x4a03),
 755         regmap_reg_range(0x4a04, 0x4a07),
 756         regmap_reg_range(0x4b00, 0x4b01),
 757         regmap_reg_range(0x4b04, 0x4b04),
 758         regmap_reg_range(0x4c00, 0x4c05),
 759         regmap_reg_range(0x4c08, 0x4c1b),
 760
 761         /* port 5 */
 762         regmap_reg_range(0x5000, 0x5001),
 763         regmap_reg_range(0x5013, 0x5013),
 764         regmap_reg_range(0x5017, 0x5017),
 765         regmap_reg_range(0x501b, 0x501b),
 766         regmap_reg_range(0x501f, 0x5020),
 767         regmap_reg_range(0x5030, 0x5030),
 768         regmap_reg_range(0x5100, 0x5115),
 769         regmap_reg_range(0x511a, 0x511f),
 770         regmap_reg_range(0x5120, 0x512b),
 771         regmap_reg_range(0x5134, 0x513b),
 772         regmap_reg_range(0x513c, 0x513f),
 773         regmap_reg_range(0x5400, 0x5401),
 774         regmap_reg_range(0x5403, 0x5403),
 775         regmap_reg_range(0x5410, 0x5417),
 776         regmap_reg_range(0x5420, 0x5423),
 777         regmap_reg_range(0x5500, 0x5507),
 778         regmap_reg_range(0x5600, 0x5613),
 779         regmap_reg_range(0x5800, 0x580f),
 780         regmap_reg_range(0x5820, 0x5827),
 781         regmap_reg_range(0x5830, 0x5837),
 782         regmap_reg_range(0x5840, 0x584b),
 783         regmap_reg_range(0x5900, 0x5907),
 784         regmap_reg_range(0x5914, 0x591b),
 785         regmap_reg_range(0x5920, 0x5920),
 786         regmap_reg_range(0x5923, 0x5927),
 787         regmap_reg_range(0x5a00, 0x5a03),
 788         regmap_reg_range(0x5a04, 0x5a07),
 789         regmap_reg_range(0x5b00, 0x5b01),
 790         regmap_reg_range(0x5b04, 0x5b04),
 791         regmap_reg_range(0x5c00, 0x5c05),
 792         regmap_reg_range(0x5c08, 0x5c1b),
 793
 794         /* port 6 */
 795         regmap_reg_range(0x6000, 0x6001),
 796         regmap_reg_range(0x6013, 0x6013),
 797         regmap_reg_range(0x6017, 0x6017),
 798         regmap_reg_range(0x601b, 0x601b),
 799         regmap_reg_range(0x601f, 0x6020),
 800         regmap_reg_range(0x6030, 0x6030),
 801         regmap_reg_range(0x6300, 0x6301),
 802         regmap_reg_range(0x6400, 0x6401),
 803         regmap_reg_range(0x6403, 0x6403),
 804         regmap_reg_range(0x6410, 0x6417),
 805         regmap_reg_range(0x6420, 0x6423),
 806         regmap_reg_range(0x6500, 0x6507),
 807         regmap_reg_range(0x6600, 0x6613),
 808         regmap_reg_range(0x6800, 0x680f),
 809         regmap_reg_range(0x6820, 0x6827),
 810         regmap_reg_range(0x6830, 0x6837),
 811         regmap_reg_range(0x6840, 0x684b),
 812         regmap_reg_range(0x6900, 0x6907),
 813         regmap_reg_range(0x6914, 0x691b),
 814         regmap_reg_range(0x6920, 0x6920),
 815         regmap_reg_range(0x6923, 0x6927),
 816         regmap_reg_range(0x6a00, 0x6a03),
 817         regmap_reg_range(0x6a04, 0x6a07),
 818         regmap_reg_range(0x6b00, 0x6b01),
 819         regmap_reg_range(0x6b04, 0x6b04),
 820         regmap_reg_range(0x6c00, 0x6c05),
 821         regmap_reg_range(0x6c08, 0x6c1b),
 822
 823         /* port 7 */
 824         regmap_reg_range(0x7000, 0x7001),
 825         regmap_reg_range(0x7013, 0x7013),
 826         regmap_reg_range(0x7017, 0x7017),
 827         regmap_reg_range(0x701b, 0x701b),
 828         regmap_reg_range(0x701f, 0x7020),
 829         regmap_reg_range(0x7030, 0x7030),
 830         regmap_reg_range(0x7200, 0x7203),
 831         regmap_reg_range(0x7206, 0x7207),
 832         regmap_reg_range(0x7300, 0x7301),
 833         regmap_reg_range(0x7400, 0x7401),
 834         regmap_reg_range(0x7403, 0x7403),
 835         regmap_reg_range(0x7410, 0x7417),
 836         regmap_reg_range(0x7420, 0x7423),
 837         regmap_reg_range(0x7500, 0x7507),
 838         regmap_reg_range(0x7600, 0x7613),
 839         regmap_reg_range(0x7800, 0x780f),
 840         regmap_reg_range(0x7820, 0x7827),
 841         regmap_reg_range(0x7830, 0x7837),
 842         regmap_reg_range(0x7840, 0x784b),
 843         regmap_reg_range(0x7900, 0x7907),
 844         regmap_reg_range(0x7914, 0x791b),
 845         regmap_reg_range(0x7920, 0x7920),
 846         regmap_reg_range(0x7923, 0x7927),
 847         regmap_reg_range(0x7a00, 0x7a03),
 848         regmap_reg_range(0x7a04, 0x7a07),
 849         regmap_reg_range(0x7b00, 0x7b01),
 850         regmap_reg_range(0x7b04, 0x7b04),
 851         regmap_reg_range(0x7c00, 0x7c05),
 852         regmap_reg_range(0x7c08, 0x7c1b),
 853 };
 854
 855 static const struct regmap_access_table ksz9477_register_set = {
 856         .yes_ranges = ksz9477_valid_regs,
 857         .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
 858 };
 859
 860 static const struct regmap_range ksz9896_valid_regs[] = {
 861         regmap_reg_range(0x0000, 0x0003),
 862         regmap_reg_range(0x0006, 0x0006),
 863         regmap_reg_range(0x0010, 0x001f),
 864         regmap_reg_range(0x0100, 0x0100),
 865         regmap_reg_range(0x0103, 0x0107),
 866         regmap_reg_range(0x010d, 0x010d),
 867         regmap_reg_range(0x0110, 0x0113),
 868         regmap_reg_range(0x0120, 0x0127),
 869         regmap_reg_range(0x0201, 0x0201),
 870         regmap_reg_range(0x0210, 0x0213),
 871         regmap_reg_range(0x0300, 0x0300),
 872         regmap_reg_range(0x0302, 0x030b),
 873         regmap_reg_range(0x0310, 0x031b),
 874         regmap_reg_range(0x0320, 0x032b),
 875         regmap_reg_range(0x0330, 0x0336),
 876         regmap_reg_range(0x0338, 0x033b),
 877         regmap_reg_range(0x033e, 0x033e),
 878         regmap_reg_range(0x0340, 0x035f),
 879         regmap_reg_range(0x0370, 0x0370),
 880         regmap_reg_range(0x0378, 0x0378),
 881         regmap_reg_range(0x037c, 0x037d),
 882         regmap_reg_range(0x0390, 0x0393),
 883         regmap_reg_range(0x0400, 0x040e),
 884         regmap_reg_range(0x0410, 0x042f),
 885
 886         /* port 1 */
 887         regmap_reg_range(0x1000, 0x1001),
 888         regmap_reg_range(0x1013, 0x1013),
 889         regmap_reg_range(0x1017, 0x1017),
 890         regmap_reg_range(0x101b, 0x101b),
 891         regmap_reg_range(0x101f, 0x1020),
 892         regmap_reg_range(0x1030, 0x1030),
 893         regmap_reg_range(0x1100, 0x1115),
 894         regmap_reg_range(0x111a, 0x111f),
 895         regmap_reg_range(0x1122, 0x1127),
 896         regmap_reg_range(0x112a, 0x112b),
 897         regmap_reg_range(0x1136, 0x1139),
 898         regmap_reg_range(0x113e, 0x113f),
 899         regmap_reg_range(0x1400, 0x1401),
 900         regmap_reg_range(0x1403, 0x1403),
 901         regmap_reg_range(0x1410, 0x1417),
 902         regmap_reg_range(0x1420, 0x1423),
 903         regmap_reg_range(0x1500, 0x1507),
 904         regmap_reg_range(0x1600, 0x1612),
 905         regmap_reg_range(0x1800, 0x180f),
 906         regmap_reg_range(0x1820, 0x1827),
 907         regmap_reg_range(0x1830, 0x1837),
 908         regmap_reg_range(0x1840, 0x184b),
 909         regmap_reg_range(0x1900, 0x1907),
 910         regmap_reg_range(0x1914, 0x1915),
 911         regmap_reg_range(0x1a00, 0x1a03),
 912         regmap_reg_range(0x1a04, 0x1a07),
 913         regmap_reg_range(0x1b00, 0x1b01),
 914         regmap_reg_range(0x1b04, 0x1b04),
 915
 916         /* port 2 */
 917         regmap_reg_range(0x2000, 0x2001),
 918         regmap_reg_range(0x2013, 0x2013),
 919         regmap_reg_range(0x2017, 0x2017),
 920         regmap_reg_range(0x201b, 0x201b),
 921         regmap_reg_range(0x201f, 0x2020),
 922         regmap_reg_range(0x2030, 0x2030),
 923         regmap_reg_range(0x2100, 0x2115),
 924         regmap_reg_range(0x211a, 0x211f),
 925         regmap_reg_range(0x2122, 0x2127),
 926         regmap_reg_range(0x212a, 0x212b),
 927         regmap_reg_range(0x2136, 0x2139),
 928         regmap_reg_range(0x213e, 0x213f),
 929         regmap_reg_range(0x2400, 0x2401),
 930         regmap_reg_range(0x2403, 0x2403),
 931         regmap_reg_range(0x2410, 0x2417),
 932         regmap_reg_range(0x2420, 0x2423),
 933         regmap_reg_range(0x2500, 0x2507),
 934         regmap_reg_range(0x2600, 0x2612),
 935         regmap_reg_range(0x2800, 0x280f),
 936         regmap_reg_range(0x2820, 0x2827),
 937         regmap_reg_range(0x2830, 0x2837),
 938         regmap_reg_range(0x2840, 0x284b),
 939         regmap_reg_range(0x2900, 0x2907),
 940         regmap_reg_range(0x2914, 0x2915),
 941         regmap_reg_range(0x2a00, 0x2a03),
 942         regmap_reg_range(0x2a04, 0x2a07),
 943         regmap_reg_range(0x2b00, 0x2b01),
 944         regmap_reg_range(0x2b04, 0x2b04),
 945
 946         /* port 3 */
 947         regmap_reg_range(0x3000, 0x3001),
 948         regmap_reg_range(0x3013, 0x3013),
 949         regmap_reg_range(0x3017, 0x3017),
 950         regmap_reg_range(0x301b, 0x301b),
 951         regmap_reg_range(0x301f, 0x3020),
 952         regmap_reg_range(0x3030, 0x3030),
 953         regmap_reg_range(0x3100, 0x3115),
 954         regmap_reg_range(0x311a, 0x311f),
 955         regmap_reg_range(0x3122, 0x3127),
 956         regmap_reg_range(0x312a, 0x312b),
 957         regmap_reg_range(0x3136, 0x3139),
 958         regmap_reg_range(0x313e, 0x313f),
 959         regmap_reg_range(0x3400, 0x3401),
 960         regmap_reg_range(0x3403, 0x3403),
 961         regmap_reg_range(0x3410, 0x3417),
 962         regmap_reg_range(0x3420, 0x3423),
 963         regmap_reg_range(0x3500, 0x3507),
 964         regmap_reg_range(0x3600, 0x3612),
 965         regmap_reg_range(0x3800, 0x380f),
 966         regmap_reg_range(0x3820, 0x3827),
 967         regmap_reg_range(0x3830, 0x3837),
 968         regmap_reg_range(0x3840, 0x384b),
 969         regmap_reg_range(0x3900, 0x3907),
 970         regmap_reg_range(0x3914, 0x3915),
 971         regmap_reg_range(0x3a00, 0x3a03),
 972         regmap_reg_range(0x3a04, 0x3a07),
 973         regmap_reg_range(0x3b00, 0x3b01),
 974         regmap_reg_range(0x3b04, 0x3b04),
 975
 976         /* port 4 */
 977         regmap_reg_range(0x4000, 0x4001),
 978         regmap_reg_range(0x4013, 0x4013),
 979         regmap_reg_range(0x4017, 0x4017),
 980         regmap_reg_range(0x401b, 0x401b),
 981         regmap_reg_range(0x401f, 0x4020),
 982         regmap_reg_range(0x4030, 0x4030),
 983         regmap_reg_range(0x4100, 0x4115),
 984         regmap_reg_range(0x411a, 0x411f),
 985         regmap_reg_range(0x4122, 0x4127),
 986         regmap_reg_range(0x412a, 0x412b),
 987         regmap_reg_range(0x4136, 0x4139),
 988         regmap_reg_range(0x413e, 0x413f),
 989         regmap_reg_range(0x4400, 0x4401),
 990         regmap_reg_range(0x4403, 0x4403),
 991         regmap_reg_range(0x4410, 0x4417),
 992         regmap_reg_range(0x4420, 0x4423),
 993         regmap_reg_range(0x4500, 0x4507),
 994         regmap_reg_range(0x4600, 0x4612),
 995         regmap_reg_range(0x4800, 0x480f),
 996         regmap_reg_range(0x4820, 0x4827),
 997         regmap_reg_range(0x4830, 0x4837),
 998         regmap_reg_range(0x4840, 0x484b),
 999         regmap_reg_range(0x4900, 0x4907),
1000         regmap_reg_range(0x4914, 0x4915),
1001         regmap_reg_range(0x4a00, 0x4a03),
1002         regmap_reg_range(0x4a04, 0x4a07),
1003         regmap_reg_range(0x4b00, 0x4b01),
1004         regmap_reg_range(0x4b04, 0x4b04),
1005
1006         /* port 5 */
1007         regmap_reg_range(0x5000, 0x5001),
1008         regmap_reg_range(0x5013, 0x5013),
1009         regmap_reg_range(0x5017, 0x5017),
1010         regmap_reg_range(0x501b, 0x501b),
1011         regmap_reg_range(0x501f, 0x5020),
1012         regmap_reg_range(0x5030, 0x5030),
1013         regmap_reg_range(0x5100, 0x5115),
1014         regmap_reg_range(0x511a, 0x511f),
1015         regmap_reg_range(0x5122, 0x5127),
1016         regmap_reg_range(0x512a, 0x512b),
1017         regmap_reg_range(0x5136, 0x5139),
1018         regmap_reg_range(0x513e, 0x513f),
1019         regmap_reg_range(0x5400, 0x5401),
1020         regmap_reg_range(0x5403, 0x5403),
1021         regmap_reg_range(0x5410, 0x5417),
1022         regmap_reg_range(0x5420, 0x5423),
1023         regmap_reg_range(0x5500, 0x5507),
1024         regmap_reg_range(0x5600, 0x5612),
1025         regmap_reg_range(0x5800, 0x580f),
1026         regmap_reg_range(0x5820, 0x5827),
1027         regmap_reg_range(0x5830, 0x5837),
1028         regmap_reg_range(0x5840, 0x584b),
1029         regmap_reg_range(0x5900, 0x5907),
1030         regmap_reg_range(0x5914, 0x5915),
1031         regmap_reg_range(0x5a00, 0x5a03),
1032         regmap_reg_range(0x5a04, 0x5a07),
1033         regmap_reg_range(0x5b00, 0x5b01),
1034         regmap_reg_range(0x5b04, 0x5b04),
1035
1036         /* port 6 */
1037         regmap_reg_range(0x6000, 0x6001),
1038         regmap_reg_range(0x6013, 0x6013),
1039         regmap_reg_range(0x6017, 0x6017),
1040         regmap_reg_range(0x601b, 0x601b),
1041         regmap_reg_range(0x601f, 0x6020),
1042         regmap_reg_range(0x6030, 0x6030),
1043         regmap_reg_range(0x6100, 0x6115),
1044         regmap_reg_range(0x611a, 0x611f),
1045         regmap_reg_range(0x6122, 0x6127),
1046         regmap_reg_range(0x612a, 0x612b),
1047         regmap_reg_range(0x6136, 0x6139),
1048         regmap_reg_range(0x613e, 0x613f),
1049         regmap_reg_range(0x6300, 0x6301),
1050         regmap_reg_range(0x6400, 0x6401),
1051         regmap_reg_range(0x6403, 0x6403),
1052         regmap_reg_range(0x6410, 0x6417),
1053         regmap_reg_range(0x6420, 0x6423),
1054         regmap_reg_range(0x6500, 0x6507),
1055         regmap_reg_range(0x6600, 0x6612),
1056         regmap_reg_range(0x6800, 0x680f),
1057         regmap_reg_range(0x6820, 0x6827),
1058         regmap_reg_range(0x6830, 0x6837),
1059         regmap_reg_range(0x6840, 0x684b),
1060         regmap_reg_range(0x6900, 0x6907),
1061         regmap_reg_range(0x6914, 0x6915),
1062         regmap_reg_range(0x6a00, 0x6a03),
1063         regmap_reg_range(0x6a04, 0x6a07),
1064         regmap_reg_range(0x6b00, 0x6b01),
1065         regmap_reg_range(0x6b04, 0x6b04),
1066 };
1067
1068 static const struct regmap_access_table ksz9896_register_set = {
1069         .yes_ranges = ksz9896_valid_regs,
1070         .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1071 };
1072
1073 static const struct regmap_range ksz8873_valid_regs[] = {
1074         regmap_reg_range(0x00, 0x01),
1075         /* global control register */
1076         regmap_reg_range(0x02, 0x0f),
1077
1078         /* port registers */
1079         regmap_reg_range(0x10, 0x1d),
1080         regmap_reg_range(0x1e, 0x1f),
1081         regmap_reg_range(0x20, 0x2d),
1082         regmap_reg_range(0x2e, 0x2f),
1083         regmap_reg_range(0x30, 0x39),
1084         regmap_reg_range(0x3f, 0x3f),
1085
1086         /* advanced control registers */
1087         regmap_reg_range(0x60, 0x6f),
1088         regmap_reg_range(0x70, 0x75),
1089         regmap_reg_range(0x76, 0x78),
1090         regmap_reg_range(0x79, 0x7a),
1091         regmap_reg_range(0x7b, 0x83),
1092         regmap_reg_range(0x8e, 0x99),
1093         regmap_reg_range(0x9a, 0xa5),
1094         regmap_reg_range(0xa6, 0xa6),
1095         regmap_reg_range(0xa7, 0xaa),
1096         regmap_reg_range(0xab, 0xae),
1097         regmap_reg_range(0xaf, 0xba),
1098         regmap_reg_range(0xbb, 0xbc),
1099         regmap_reg_range(0xbd, 0xbd),
1100         regmap_reg_range(0xc0, 0xc0),
1101         regmap_reg_range(0xc2, 0xc2),
1102         regmap_reg_range(0xc3, 0xc3),
1103         regmap_reg_range(0xc4, 0xc4),
1104         regmap_reg_range(0xc6, 0xc6),
1105 };
1106
1107 static const struct regmap_access_table ksz8873_register_set = {
1108         .yes_ranges = ksz8873_valid_regs,
1109         .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1110 };
1111
1112 const struct ksz_chip_data ksz_switch_chips[] = {
1113         [KSZ8563] = {
1114                 .chip_id = KSZ8563_CHIP_ID,
1115                 .dev_name = "KSZ8563",
1116                 .num_vlans = 4096,
1117                 .num_alus = 4096,
1118                 .num_statics = 16,
1119                 .cpu_ports = 0x07,      /* can be configured as cpu port */
1120                 .port_cnt = 3,          /* total port count */
1121                 .port_nirqs = 3,
1122                 .num_tx_queues = 4,
1123                 .tc_cbs_supported = true,
1124                 .tc_ets_supported = true,
1125                 .ops = &ksz9477_dev_ops,
1126                 .mib_names = ksz9477_mib_names,
1127                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1128                 .reg_mib_cnt = MIB_COUNTER_NUM,
1129                 .regs = ksz9477_regs,
1130                 .masks = ksz9477_masks,
1131                 .shifts = ksz9477_shifts,
1132                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1133                 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1134                 .supports_mii = {false, false, true},
1135                 .supports_rmii = {false, false, true},
1136                 .supports_rgmii = {false, false, true},
1137                 .internal_phy = {true, true, false},
1138                 .gbit_capable = {false, false, true},
1139                 .wr_table = &ksz8563_register_set,
1140                 .rd_table = &ksz8563_register_set,
1141         },
1142
1143         [KSZ8795] = {
1144                 .chip_id = KSZ8795_CHIP_ID,
1145                 .dev_name = "KSZ8795",
1146                 .num_vlans = 4096,
1147                 .num_alus = 0,
1148                 .num_statics = 8,
1149                 .cpu_ports = 0x10,      /* can be configured as cpu port */
1150                 .port_cnt = 5,          /* total cpu and user ports */
1151                 .num_tx_queues = 4,
1152                 .ops = &ksz8_dev_ops,
1153                 .ksz87xx_eee_link_erratum = true,
1154                 .mib_names = ksz9477_mib_names,
1155                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1156                 .reg_mib_cnt = MIB_COUNTER_NUM,
1157                 .regs = ksz8795_regs,
1158                 .masks = ksz8795_masks,
1159                 .shifts = ksz8795_shifts,
1160                 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1161                 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1162                 .supports_mii = {false, false, false, false, true},
1163                 .supports_rmii = {false, false, false, false, true},
1164                 .supports_rgmii = {false, false, false, false, true},
1165                 .internal_phy = {true, true, true, true, false},
1166         },
1167
1168         [KSZ8794] = {
1169                 /* WARNING
1170                  * =======
1171                  * KSZ8794 is similar to KSZ8795, except the port map
1172                  * contains a gap between external and CPU ports, the
1173                  * port map is NOT continuous. The per-port register
1174                  * map is shifted accordingly too, i.e. registers at
1175                  * offset 0x40 are NOT used on KSZ8794 and they ARE
1176                  * used on KSZ8795 for external port 3.
1177                  *           external  cpu
1178                  * KSZ8794   0,1,2      4
1179                  * KSZ8795   0,1,2,3    4
1180                  * KSZ8765   0,1,2,3    4
1181                  * port_cnt is configured as 5, even though it is 4
1182                  */
1183                 .chip_id = KSZ8794_CHIP_ID,
1184                 .dev_name = "KSZ8794",
1185                 .num_vlans = 4096,
1186                 .num_alus = 0,
1187                 .num_statics = 8,
1188                 .cpu_ports = 0x10,      /* can be configured as cpu port */
1189                 .port_cnt = 5,          /* total cpu and user ports */
1190                 .num_tx_queues = 4,
1191                 .ops = &ksz8_dev_ops,
1192                 .ksz87xx_eee_link_erratum = true,
1193                 .mib_names = ksz9477_mib_names,
1194                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1195                 .reg_mib_cnt = MIB_COUNTER_NUM,
1196                 .regs = ksz8795_regs,
1197                 .masks = ksz8795_masks,
1198                 .shifts = ksz8795_shifts,
1199                 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1200                 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1201                 .supports_mii = {false, false, false, false, true},
1202                 .supports_rmii = {false, false, false, false, true},
1203                 .supports_rgmii = {false, false, false, false, true},
1204                 .internal_phy = {true, true, true, false, false},
1205         },
1206
1207         [KSZ8765] = {
1208                 .chip_id = KSZ8765_CHIP_ID,
1209                 .dev_name = "KSZ8765",
1210                 .num_vlans = 4096,
1211                 .num_alus = 0,
1212                 .num_statics = 8,
1213                 .cpu_ports = 0x10,      /* can be configured as cpu port */
1214                 .port_cnt = 5,          /* total cpu and user ports */
1215                 .num_tx_queues = 4,
1216                 .ops = &ksz8_dev_ops,
1217                 .ksz87xx_eee_link_erratum = true,
1218                 .mib_names = ksz9477_mib_names,
1219                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1220                 .reg_mib_cnt = MIB_COUNTER_NUM,
1221                 .regs = ksz8795_regs,
1222                 .masks = ksz8795_masks,
1223                 .shifts = ksz8795_shifts,
1224                 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1225                 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1226                 .supports_mii = {false, false, false, false, true},
1227                 .supports_rmii = {false, false, false, false, true},
1228                 .supports_rgmii = {false, false, false, false, true},
1229                 .internal_phy = {true, true, true, true, false},
1230         },
1231
1232         [KSZ8830] = {
1233                 .chip_id = KSZ8830_CHIP_ID,
1234                 .dev_name = "KSZ8863/KSZ8873",
1235                 .num_vlans = 16,
1236                 .num_alus = 0,
1237                 .num_statics = 8,
1238                 .cpu_ports = 0x4,       /* can be configured as cpu port */
1239                 .port_cnt = 3,
1240                 .num_tx_queues = 4,
1241                 .ops = &ksz8_dev_ops,
1242                 .mib_names = ksz88xx_mib_names,
1243                 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1244                 .reg_mib_cnt = MIB_COUNTER_NUM,
1245                 .regs = ksz8863_regs,
1246                 .masks = ksz8863_masks,
1247                 .shifts = ksz8863_shifts,
1248                 .supports_mii = {false, false, true},
1249                 .supports_rmii = {false, false, true},
1250                 .internal_phy = {true, true, false},
1251                 .wr_table = &ksz8873_register_set,
1252                 .rd_table = &ksz8873_register_set,
1253         },
1254
1255         [KSZ9477] = {
1256                 .chip_id = KSZ9477_CHIP_ID,
1257                 .dev_name = "KSZ9477",
1258                 .num_vlans = 4096,
1259                 .num_alus = 4096,
1260                 .num_statics = 16,
1261                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1262                 .port_cnt = 7,          /* total physical port count */
1263                 .port_nirqs = 4,
1264                 .num_tx_queues = 4,
1265                 .tc_cbs_supported = true,
1266                 .tc_ets_supported = true,
1267                 .ops = &ksz9477_dev_ops,
1268                 .mib_names = ksz9477_mib_names,
1269                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1270                 .reg_mib_cnt = MIB_COUNTER_NUM,
1271                 .regs = ksz9477_regs,
1272                 .masks = ksz9477_masks,
1273                 .shifts = ksz9477_shifts,
1274                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1275                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1276                 .supports_mii   = {false, false, false, false,
1277                                    false, true, false},
1278                 .supports_rmii  = {false, false, false, false,
1279                                    false, true, false},
1280                 .supports_rgmii = {false, false, false, false,
1281                                    false, true, false},
1282                 .internal_phy   = {true, true, true, true,
1283                                    true, false, false},
1284                 .gbit_capable   = {true, true, true, true, true, true, true},
1285                 .wr_table = &ksz9477_register_set,
1286                 .rd_table = &ksz9477_register_set,
1287         },
1288
1289         [KSZ9896] = {
1290                 .chip_id = KSZ9896_CHIP_ID,
1291                 .dev_name = "KSZ9896",
1292                 .num_vlans = 4096,
1293                 .num_alus = 4096,
1294                 .num_statics = 16,
1295                 .cpu_ports = 0x3F,      /* can be configured as cpu port */
1296                 .port_cnt = 6,          /* total physical port count */
1297                 .port_nirqs = 2,
1298                 .num_tx_queues = 4,
1299                 .ops = &ksz9477_dev_ops,
1300                 .mib_names = ksz9477_mib_names,
1301                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1302                 .reg_mib_cnt = MIB_COUNTER_NUM,
1303                 .regs = ksz9477_regs,
1304                 .masks = ksz9477_masks,
1305                 .shifts = ksz9477_shifts,
1306                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1307                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1308                 .supports_mii   = {false, false, false, false,
1309                                    false, true},
1310                 .supports_rmii  = {false, false, false, false,
1311                                    false, true},
1312                 .supports_rgmii = {false, false, false, false,
1313                                    false, true},
1314                 .internal_phy   = {true, true, true, true,
1315                                    true, false},
1316                 .gbit_capable   = {true, true, true, true, true, true},
1317                 .wr_table = &ksz9896_register_set,
1318                 .rd_table = &ksz9896_register_set,
1319         },
1320
1321         [KSZ9897] = {
1322                 .chip_id = KSZ9897_CHIP_ID,
1323                 .dev_name = "KSZ9897",
1324                 .num_vlans = 4096,
1325                 .num_alus = 4096,
1326                 .num_statics = 16,
1327                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1328                 .port_cnt = 7,          /* total physical port count */
1329                 .port_nirqs = 2,
1330                 .num_tx_queues = 4,
1331                 .ops = &ksz9477_dev_ops,
1332                 .mib_names = ksz9477_mib_names,
1333                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1334                 .reg_mib_cnt = MIB_COUNTER_NUM,
1335                 .regs = ksz9477_regs,
1336                 .masks = ksz9477_masks,
1337                 .shifts = ksz9477_shifts,
1338                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1339                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1340                 .supports_mii   = {false, false, false, false,
1341                                    false, true, true},
1342                 .supports_rmii  = {false, false, false, false,
1343                                    false, true, true},
1344                 .supports_rgmii = {false, false, false, false,
1345                                    false, true, true},
1346                 .internal_phy   = {true, true, true, true,
1347                                    true, false, false},
1348                 .gbit_capable   = {true, true, true, true, true, true, true},
1349         },
1350
1351         [KSZ9893] = {
1352                 .chip_id = KSZ9893_CHIP_ID,
1353                 .dev_name = "KSZ9893",
1354                 .num_vlans = 4096,
1355                 .num_alus = 4096,
1356                 .num_statics = 16,
1357                 .cpu_ports = 0x07,      /* can be configured as cpu port */
1358                 .port_cnt = 3,          /* total port count */
1359                 .port_nirqs = 2,
1360                 .num_tx_queues = 4,
1361                 .ops = &ksz9477_dev_ops,
1362                 .mib_names = ksz9477_mib_names,
1363                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1364                 .reg_mib_cnt = MIB_COUNTER_NUM,
1365                 .regs = ksz9477_regs,
1366                 .masks = ksz9477_masks,
1367                 .shifts = ksz9477_shifts,
1368                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1369                 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1370                 .supports_mii = {false, false, true},
1371                 .supports_rmii = {false, false, true},
1372                 .supports_rgmii = {false, false, true},
1373                 .internal_phy = {true, true, false},
1374                 .gbit_capable = {true, true, true},
1375         },
1376
1377         [KSZ9563] = {
1378                 .chip_id = KSZ9563_CHIP_ID,
1379                 .dev_name = "KSZ9563",
1380                 .num_vlans = 4096,
1381                 .num_alus = 4096,
1382                 .num_statics = 16,
1383                 .cpu_ports = 0x07,      /* can be configured as cpu port */
1384                 .port_cnt = 3,          /* total port count */
1385                 .port_nirqs = 3,
1386                 .num_tx_queues = 4,
1387                 .tc_cbs_supported = true,
1388                 .tc_ets_supported = true,
1389                 .ops = &ksz9477_dev_ops,
1390                 .mib_names = ksz9477_mib_names,
1391                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1392                 .reg_mib_cnt = MIB_COUNTER_NUM,
1393                 .regs = ksz9477_regs,
1394                 .masks = ksz9477_masks,
1395                 .shifts = ksz9477_shifts,
1396                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1397                 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1398                 .supports_mii = {false, false, true},
1399                 .supports_rmii = {false, false, true},
1400                 .supports_rgmii = {false, false, true},
1401                 .internal_phy = {true, true, false},
1402                 .gbit_capable = {true, true, true},
1403         },
1404
1405         [KSZ9567] = {
1406                 .chip_id = KSZ9567_CHIP_ID,
1407                 .dev_name = "KSZ9567",
1408                 .num_vlans = 4096,
1409                 .num_alus = 4096,
1410                 .num_statics = 16,
1411                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1412                 .port_cnt = 7,          /* total physical port count */
1413                 .port_nirqs = 3,
1414                 .num_tx_queues = 4,
1415                 .tc_cbs_supported = true,
1416                 .tc_ets_supported = true,
1417                 .ops = &ksz9477_dev_ops,
1418                 .mib_names = ksz9477_mib_names,
1419                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1420                 .reg_mib_cnt = MIB_COUNTER_NUM,
1421                 .regs = ksz9477_regs,
1422                 .masks = ksz9477_masks,
1423                 .shifts = ksz9477_shifts,
1424                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1425                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1426                 .supports_mii   = {false, false, false, false,
1427                                    false, true, true},
1428                 .supports_rmii  = {false, false, false, false,
1429                                    false, true, true},
1430                 .supports_rgmii = {false, false, false, false,
1431                                    false, true, true},
1432                 .internal_phy   = {true, true, true, true,
1433                                    true, false, false},
1434                 .gbit_capable   = {true, true, true, true, true, true, true},
1435         },
1436
1437         [LAN9370] = {
1438                 .chip_id = LAN9370_CHIP_ID,
1439                 .dev_name = "LAN9370",
1440                 .num_vlans = 4096,
1441                 .num_alus = 1024,
1442                 .num_statics = 256,
1443                 .cpu_ports = 0x10,      /* can be configured as cpu port */
1444                 .port_cnt = 5,          /* total physical port count */
1445                 .port_nirqs = 6,
1446                 .num_tx_queues = 8,
1447                 .tc_cbs_supported = true,
1448                 .tc_ets_supported = true,
1449                 .ops = &lan937x_dev_ops,
1450                 .mib_names = ksz9477_mib_names,
1451                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1452                 .reg_mib_cnt = MIB_COUNTER_NUM,
1453                 .regs = ksz9477_regs,
1454                 .masks = lan937x_masks,
1455                 .shifts = lan937x_shifts,
1456                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1457                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1458                 .supports_mii = {false, false, false, false, true},
1459                 .supports_rmii = {false, false, false, false, true},
1460                 .supports_rgmii = {false, false, false, false, true},
1461                 .internal_phy = {true, true, true, true, false},
1462         },
1463
1464         [LAN9371] = {
1465                 .chip_id = LAN9371_CHIP_ID,
1466                 .dev_name = "LAN9371",
1467                 .num_vlans = 4096,
1468                 .num_alus = 1024,
1469                 .num_statics = 256,
1470                 .cpu_ports = 0x30,      /* can be configured as cpu port */
1471                 .port_cnt = 6,          /* total physical port count */
1472                 .port_nirqs = 6,
1473                 .num_tx_queues = 8,
1474                 .tc_cbs_supported = true,
1475                 .tc_ets_supported = true,
1476                 .ops = &lan937x_dev_ops,
1477                 .mib_names = ksz9477_mib_names,
1478                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1479                 .reg_mib_cnt = MIB_COUNTER_NUM,
1480                 .regs = ksz9477_regs,
1481                 .masks = lan937x_masks,
1482                 .shifts = lan937x_shifts,
1483                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1484                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1485                 .supports_mii = {false, false, false, false, true, true},
1486                 .supports_rmii = {false, false, false, false, true, true},
1487                 .supports_rgmii = {false, false, false, false, true, true},
1488                 .internal_phy = {true, true, true, true, false, false},
1489         },
1490
1491         [LAN9372] = {
1492                 .chip_id = LAN9372_CHIP_ID,
1493                 .dev_name = "LAN9372",
1494                 .num_vlans = 4096,
1495                 .num_alus = 1024,
1496                 .num_statics = 256,
1497                 .cpu_ports = 0x30,      /* can be configured as cpu port */
1498                 .port_cnt = 8,          /* total physical port count */
1499                 .port_nirqs = 6,
1500                 .num_tx_queues = 8,
1501                 .tc_cbs_supported = true,
1502                 .tc_ets_supported = true,
1503                 .ops = &lan937x_dev_ops,
1504                 .mib_names = ksz9477_mib_names,
1505                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1506                 .reg_mib_cnt = MIB_COUNTER_NUM,
1507                 .regs = ksz9477_regs,
1508                 .masks = lan937x_masks,
1509                 .shifts = lan937x_shifts,
1510                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1511                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1512                 .supports_mii   = {false, false, false, false,
1513                                    true, true, false, false},
1514                 .supports_rmii  = {false, false, false, false,
1515                                    true, true, false, false},
1516                 .supports_rgmii = {false, false, false, false,
1517                                    true, true, false, false},
1518                 .internal_phy   = {true, true, true, true,
1519                                    false, false, true, true},
1520         },
1521
1522         [LAN9373] = {
1523                 .chip_id = LAN9373_CHIP_ID,
1524                 .dev_name = "LAN9373",
1525                 .num_vlans = 4096,
1526                 .num_alus = 1024,
1527                 .num_statics = 256,
1528                 .cpu_ports = 0x38,      /* can be configured as cpu port */
1529                 .port_cnt = 5,          /* total physical port count */
1530                 .port_nirqs = 6,
1531                 .num_tx_queues = 8,
1532                 .tc_cbs_supported = true,
1533                 .tc_ets_supported = true,
1534                 .ops = &lan937x_dev_ops,
1535                 .mib_names = ksz9477_mib_names,
1536                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1537                 .reg_mib_cnt = MIB_COUNTER_NUM,
1538                 .regs = ksz9477_regs,
1539                 .masks = lan937x_masks,
1540                 .shifts = lan937x_shifts,
1541                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1542                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1543                 .supports_mii   = {false, false, false, false,
1544                                    true, true, false, false},
1545                 .supports_rmii  = {false, false, false, false,
1546                                    true, true, false, false},
1547                 .supports_rgmii = {false, false, false, false,
1548                                    true, true, false, false},
1549                 .internal_phy   = {true, true, true, false,
1550                                    false, false, true, true},
1551         },
1552
1553         [LAN9374] = {
1554                 .chip_id = LAN9374_CHIP_ID,
1555                 .dev_name = "LAN9374",
1556                 .num_vlans = 4096,
1557                 .num_alus = 1024,
1558                 .num_statics = 256,
1559                 .cpu_ports = 0x30,      /* can be configured as cpu port */
1560                 .port_cnt = 8,          /* total physical port count */
1561                 .port_nirqs = 6,
1562                 .num_tx_queues = 8,
1563                 .tc_cbs_supported = true,
1564                 .tc_ets_supported = true,
1565                 .ops = &lan937x_dev_ops,
1566                 .mib_names = ksz9477_mib_names,
1567                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1568                 .reg_mib_cnt = MIB_COUNTER_NUM,
1569                 .regs = ksz9477_regs,
1570                 .masks = lan937x_masks,
1571                 .shifts = lan937x_shifts,
1572                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1573                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1574                 .supports_mii   = {false, false, false, false,
1575                                    true, true, false, false},
1576                 .supports_rmii  = {false, false, false, false,
1577                                    true, true, false, false},
1578                 .supports_rgmii = {false, false, false, false,
1579                                    true, true, false, false},
1580                 .internal_phy   = {true, true, true, true,
1581                                    false, false, true, true},
1582         },
1583 };
1584 EXPORT_SYMBOL_GPL(ksz_switch_chips);
1585
1586 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1587 {
1588         int i;
1589
1590         for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1591                 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1592
1593                 if (chip->chip_id == prod_num)
1594                         return chip;
1595         }
1596
1597         return NULL;
1598 }
1599
1600 static int ksz_check_device_id(struct ksz_device *dev)
1601 {
1602         const struct ksz_chip_data *dt_chip_data;
1603
1604         dt_chip_data = of_device_get_match_data(dev->dev);
1605
1606         /* Check for Device Tree and Chip ID */
1607         if (dt_chip_data->chip_id != dev->chip_id) {
1608                 dev_err(dev->dev,
1609                         "Device tree specifies chip %s but found %s, please fix it!\n",
1610                         dt_chip_data->dev_name, dev->info->dev_name);
1611                 return -ENODEV;
1612         }
1613
1614         return 0;
1615 }
1616
1617 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1618                                  struct phylink_config *config)
1619 {
1620         struct ksz_device *dev = ds->priv;
1621
1622         config->legacy_pre_march2020 = false;
1623
1624         if (dev->info->supports_mii[port])
1625                 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1626
1627         if (dev->info->supports_rmii[port])
1628                 __set_bit(PHY_INTERFACE_MODE_RMII,
1629                           config->supported_interfaces);
1630
1631         if (dev->info->supports_rgmii[port])
1632                 phy_interface_set_rgmii(config->supported_interfaces);
1633
1634         if (dev->info->internal_phy[port]) {
1635                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1636                           config->supported_interfaces);
1637                 /* Compatibility for phylib's default interface type when the
1638                  * phy-mode property is absent
1639                  */
1640                 __set_bit(PHY_INTERFACE_MODE_GMII,
1641                           config->supported_interfaces);
1642         }
1643
1644         if (dev->dev_ops->get_caps)
1645                 dev->dev_ops->get_caps(dev, port, config);
1646 }
1647
1648 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
1649 {
1650         struct ethtool_pause_stats *pstats;
1651         struct rtnl_link_stats64 *stats;
1652         struct ksz_stats_raw *raw;
1653         struct ksz_port_mib *mib;
1654
1655         mib = &dev->ports[port].mib;
1656         stats = &mib->stats64;
1657         pstats = &mib->pause_stats;
1658         raw = (struct ksz_stats_raw *)mib->counters;
1659
1660         spin_lock(&mib->stats64_lock);
1661
1662         stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1663                 raw->rx_pause;
1664         stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1665                 raw->tx_pause;
1666
1667         /* HW counters are counting bytes + FCS which is not acceptable
1668          * for rtnl_link_stats64 interface
1669          */
1670         stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
1671         stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
1672
1673         stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1674                 raw->rx_oversize;
1675
1676         stats->rx_crc_errors = raw->rx_crc_err;
1677         stats->rx_frame_errors = raw->rx_align_err;
1678         stats->rx_dropped = raw->rx_discards;
1679         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1680                 stats->rx_frame_errors  + stats->rx_dropped;
1681
1682         stats->tx_window_errors = raw->tx_late_col;
1683         stats->tx_fifo_errors = raw->tx_discards;
1684         stats->tx_aborted_errors = raw->tx_exc_col;
1685         stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1686                 stats->tx_aborted_errors;
1687
1688         stats->multicast = raw->rx_mcast;
1689         stats->collisions = raw->tx_total_col;
1690
1691         pstats->tx_pause_frames = raw->tx_pause;
1692         pstats->rx_pause_frames = raw->rx_pause;
1693
1694         spin_unlock(&mib->stats64_lock);
1695 }
1696
1697 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
1698 {
1699         struct ethtool_pause_stats *pstats;
1700         struct rtnl_link_stats64 *stats;
1701         struct ksz88xx_stats_raw *raw;
1702         struct ksz_port_mib *mib;
1703
1704         mib = &dev->ports[port].mib;
1705         stats = &mib->stats64;
1706         pstats = &mib->pause_stats;
1707         raw = (struct ksz88xx_stats_raw *)mib->counters;
1708
1709         spin_lock(&mib->stats64_lock);
1710
1711         stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1712                 raw->rx_pause;
1713         stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1714                 raw->tx_pause;
1715
1716         /* HW counters are counting bytes + FCS which is not acceptable
1717          * for rtnl_link_stats64 interface
1718          */
1719         stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
1720         stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
1721
1722         stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1723                 raw->rx_oversize;
1724
1725         stats->rx_crc_errors = raw->rx_crc_err;
1726         stats->rx_frame_errors = raw->rx_align_err;
1727         stats->rx_dropped = raw->rx_discards;
1728         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1729                 stats->rx_frame_errors  + stats->rx_dropped;
1730
1731         stats->tx_window_errors = raw->tx_late_col;
1732         stats->tx_fifo_errors = raw->tx_discards;
1733         stats->tx_aborted_errors = raw->tx_exc_col;
1734         stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1735                 stats->tx_aborted_errors;
1736
1737         stats->multicast = raw->rx_mcast;
1738         stats->collisions = raw->tx_total_col;
1739
1740         pstats->tx_pause_frames = raw->tx_pause;
1741         pstats->rx_pause_frames = raw->rx_pause;
1742
1743         spin_unlock(&mib->stats64_lock);
1744 }
1745
1746 static void ksz_get_stats64(struct dsa_switch *ds, int port,
1747                             struct rtnl_link_stats64 *s)
1748 {
1749         struct ksz_device *dev = ds->priv;
1750         struct ksz_port_mib *mib;
1751
1752         mib = &dev->ports[port].mib;
1753
1754         spin_lock(&mib->stats64_lock);
1755         memcpy(s, &mib->stats64, sizeof(*s));
1756         spin_unlock(&mib->stats64_lock);
1757 }
1758
1759 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
1760                                 struct ethtool_pause_stats *pause_stats)
1761 {
1762         struct ksz_device *dev = ds->priv;
1763         struct ksz_port_mib *mib;
1764
1765         mib = &dev->ports[port].mib;
1766
1767         spin_lock(&mib->stats64_lock);
1768         memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
1769         spin_unlock(&mib->stats64_lock);
1770 }
1771
1772 static void ksz_get_strings(struct dsa_switch *ds, int port,
1773                             u32 stringset, uint8_t *buf)
1774 {
1775         struct ksz_device *dev = ds->priv;
1776         int i;
1777
1778         if (stringset != ETH_SS_STATS)
1779                 return;
1780
1781         for (i = 0; i < dev->info->mib_cnt; i++) {
1782                 memcpy(buf + i * ETH_GSTRING_LEN,
1783                        dev->info->mib_names[i].string, ETH_GSTRING_LEN);
1784         }
1785 }
1786
1787 static void ksz_update_port_member(struct ksz_device *dev, int port)
1788 {
1789         struct ksz_port *p = &dev->ports[port];
1790         struct dsa_switch *ds = dev->ds;
1791         u8 port_member = 0, cpu_port;
1792         const struct dsa_port *dp;
1793         int i, j;
1794
1795         if (!dsa_is_user_port(ds, port))
1796                 return;
1797
1798         dp = dsa_to_port(ds, port);
1799         cpu_port = BIT(dsa_upstream_port(ds, port));
1800
1801         for (i = 0; i < ds->num_ports; i++) {
1802                 const struct dsa_port *other_dp = dsa_to_port(ds, i);
1803                 struct ksz_port *other_p = &dev->ports[i];
1804                 u8 val = 0;
1805
1806                 if (!dsa_is_user_port(ds, i))
1807                         continue;
1808                 if (port == i)
1809                         continue;
1810                 if (!dsa_port_bridge_same(dp, other_dp))
1811                         continue;
1812                 if (other_p->stp_state != BR_STATE_FORWARDING)
1813                         continue;
1814
1815                 if (p->stp_state == BR_STATE_FORWARDING) {
1816                         val |= BIT(port);
1817                         port_member |= BIT(i);
1818                 }
1819
1820                 /* Retain port [i]'s relationship to other ports than [port] */
1821                 for (j = 0; j < ds->num_ports; j++) {
1822                         const struct dsa_port *third_dp;
1823                         struct ksz_port *third_p;
1824
1825                         if (j == i)
1826                                 continue;
1827                         if (j == port)
1828                                 continue;
1829                         if (!dsa_is_user_port(ds, j))
1830                                 continue;
1831                         third_p = &dev->ports[j];
1832                         if (third_p->stp_state != BR_STATE_FORWARDING)
1833                                 continue;
1834                         third_dp = dsa_to_port(ds, j);
1835                         if (dsa_port_bridge_same(other_dp, third_dp))
1836                                 val |= BIT(j);
1837                 }
1838
1839                 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
1840         }
1841
1842         dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
1843 }
1844
1845 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
1846 {
1847         struct ksz_device *dev = bus->priv;
1848         u16 val;
1849         int ret;
1850
1851         ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
1852         if (ret < 0)
1853                 return ret;
1854
1855         return val;
1856 }
1857
1858 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
1859                              u16 val)
1860 {
1861         struct ksz_device *dev = bus->priv;
1862
1863         return dev->dev_ops->w_phy(dev, addr, regnum, val);
1864 }
1865
1866 static int ksz_irq_phy_setup(struct ksz_device *dev)
1867 {
1868         struct dsa_switch *ds = dev->ds;
1869         int phy;
1870         int irq;
1871         int ret;
1872
1873         for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) {
1874                 if (BIT(phy) & ds->phys_mii_mask) {
1875                         irq = irq_find_mapping(dev->ports[phy].pirq.domain,
1876                                                PORT_SRC_PHY_INT);
1877                         if (irq < 0) {
1878                                 ret = irq;
1879                                 goto out;
1880                         }
1881                         ds->slave_mii_bus->irq[phy] = irq;
1882                 }
1883         }
1884         return 0;
1885 out:
1886         while (phy--)
1887                 if (BIT(phy) & ds->phys_mii_mask)
1888                         irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1889
1890         return ret;
1891 }
1892
1893 static void ksz_irq_phy_free(struct ksz_device *dev)
1894 {
1895         struct dsa_switch *ds = dev->ds;
1896         int phy;
1897
1898         for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++)
1899                 if (BIT(phy) & ds->phys_mii_mask)
1900                         irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1901 }
1902
1903 static int ksz_mdio_register(struct ksz_device *dev)
1904 {
1905         struct dsa_switch *ds = dev->ds;
1906         struct device_node *mdio_np;
1907         struct mii_bus *bus;
1908         int ret;
1909
1910         mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
1911         if (!mdio_np)
1912                 return 0;
1913
1914         bus = devm_mdiobus_alloc(ds->dev);
1915         if (!bus) {
1916                 of_node_put(mdio_np);
1917                 return -ENOMEM;
1918         }
1919
1920         bus->priv = dev;
1921         bus->read = ksz_sw_mdio_read;
1922         bus->write = ksz_sw_mdio_write;
1923         bus->name = "ksz slave smi";
1924         snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
1925         bus->parent = ds->dev;
1926         bus->phy_mask = ~ds->phys_mii_mask;
1927
1928         ds->slave_mii_bus = bus;
1929
1930         if (dev->irq > 0) {
1931                 ret = ksz_irq_phy_setup(dev);
1932                 if (ret) {
1933                         of_node_put(mdio_np);
1934                         return ret;
1935                 }
1936         }
1937
1938         ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
1939         if (ret) {
1940                 dev_err(ds->dev, "unable to register MDIO bus %s\n",
1941                         bus->id);
1942                 if (dev->irq > 0)
1943                         ksz_irq_phy_free(dev);
1944         }
1945
1946         of_node_put(mdio_np);
1947
1948         return ret;
1949 }
1950
1951 static void ksz_irq_mask(struct irq_data *d)
1952 {
1953         struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1954
1955         kirq->masked |= BIT(d->hwirq);
1956 }
1957
1958 static void ksz_irq_unmask(struct irq_data *d)
1959 {
1960         struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1961
1962         kirq->masked &= ~BIT(d->hwirq);
1963 }
1964
1965 static void ksz_irq_bus_lock(struct irq_data *d)
1966 {
1967         struct ksz_irq *kirq  = irq_data_get_irq_chip_data(d);
1968
1969         mutex_lock(&kirq->dev->lock_irq);
1970 }
1971
1972 static void ksz_irq_bus_sync_unlock(struct irq_data *d)
1973 {
1974         struct ksz_irq *kirq  = irq_data_get_irq_chip_data(d);
1975         struct ksz_device *dev = kirq->dev;
1976         int ret;
1977
1978         ret = ksz_write32(dev, kirq->reg_mask, kirq->masked);
1979         if (ret)
1980                 dev_err(dev->dev, "failed to change IRQ mask\n");
1981
1982         mutex_unlock(&dev->lock_irq);
1983 }
1984
1985 static const struct irq_chip ksz_irq_chip = {
1986         .name                   = "ksz-irq",
1987         .irq_mask               = ksz_irq_mask,
1988         .irq_unmask             = ksz_irq_unmask,
1989         .irq_bus_lock           = ksz_irq_bus_lock,
1990         .irq_bus_sync_unlock    = ksz_irq_bus_sync_unlock,
1991 };
1992
1993 static int ksz_irq_domain_map(struct irq_domain *d,
1994                               unsigned int irq, irq_hw_number_t hwirq)
1995 {
1996         irq_set_chip_data(irq, d->host_data);
1997         irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
1998         irq_set_noprobe(irq);
1999
2000         return 0;
2001 }
2002
2003 static const struct irq_domain_ops ksz_irq_domain_ops = {
2004         .map    = ksz_irq_domain_map,
2005         .xlate  = irq_domain_xlate_twocell,
2006 };
2007
2008 static void ksz_irq_free(struct ksz_irq *kirq)
2009 {
2010         int irq, virq;
2011
2012         free_irq(kirq->irq_num, kirq);
2013
2014         for (irq = 0; irq < kirq->nirqs; irq++) {
2015                 virq = irq_find_mapping(kirq->domain, irq);
2016                 irq_dispose_mapping(virq);
2017         }
2018
2019         irq_domain_remove(kirq->domain);
2020 }
2021
2022 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
2023 {
2024         struct ksz_irq *kirq = dev_id;
2025         unsigned int nhandled = 0;
2026         struct ksz_device *dev;
2027         unsigned int sub_irq;
2028         u8 data;
2029         int ret;
2030         u8 n;
2031
2032         dev = kirq->dev;
2033
2034         /* Read interrupt status register */
2035         ret = ksz_read8(dev, kirq->reg_status, &data);
2036         if (ret)
2037                 goto out;
2038
2039         for (n = 0; n < kirq->nirqs; ++n) {
2040                 if (data & BIT(n)) {
2041                         sub_irq = irq_find_mapping(kirq->domain, n);
2042                         handle_nested_irq(sub_irq);
2043                         ++nhandled;
2044                 }
2045         }
2046 out:
2047         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2048 }
2049
2050 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2051 {
2052         int ret, n;
2053
2054         kirq->dev = dev;
2055         kirq->masked = ~0;
2056
2057         kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0,
2058                                              &ksz_irq_domain_ops, kirq);
2059         if (!kirq->domain)
2060                 return -ENOMEM;
2061
2062         for (n = 0; n < kirq->nirqs; n++)
2063                 irq_create_mapping(kirq->domain, n);
2064
2065         ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
2066                                    IRQF_ONESHOT, kirq->name, kirq);
2067         if (ret)
2068                 goto out;
2069
2070         return 0;
2071
2072 out:
2073         ksz_irq_free(kirq);
2074
2075         return ret;
2076 }
2077
2078 static int ksz_girq_setup(struct ksz_device *dev)
2079 {
2080         struct ksz_irq *girq = &dev->girq;
2081
2082         girq->nirqs = dev->info->port_cnt;
2083         girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2084         girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2085         snprintf(girq->name, sizeof(girq->name), "global_port_irq");
2086
2087         girq->irq_num = dev->irq;
2088
2089         return ksz_irq_common_setup(dev, girq);
2090 }
2091
2092 static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2093 {
2094         struct ksz_irq *pirq = &dev->ports[p].pirq;
2095
2096         pirq->nirqs = dev->info->port_nirqs;
2097         pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2098         pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2099         snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
2100
2101         pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
2102         if (pirq->irq_num < 0)
2103                 return pirq->irq_num;
2104
2105         return ksz_irq_common_setup(dev, pirq);
2106 }
2107
2108 static int ksz_setup(struct dsa_switch *ds)
2109 {
2110         struct ksz_device *dev = ds->priv;
2111         struct dsa_port *dp;
2112         struct ksz_port *p;
2113         const u16 *regs;
2114         int ret;
2115
2116         regs = dev->info->regs;
2117
2118         dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2119                                        dev->info->num_vlans, GFP_KERNEL);
2120         if (!dev->vlan_cache)
2121                 return -ENOMEM;
2122
2123         ret = dev->dev_ops->reset(dev);
2124         if (ret) {
2125                 dev_err(ds->dev, "failed to reset switch\n");
2126                 return ret;
2127         }
2128
2129         /* set broadcast storm protection 10% rate */
2130         regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL],
2131                            BROADCAST_STORM_RATE,
2132                            (BROADCAST_STORM_VALUE *
2133                            BROADCAST_STORM_PROT_RATE) / 100);
2134
2135         dev->dev_ops->config_cpu_port(ds);
2136
2137         dev->dev_ops->enable_stp_addr(dev);
2138
2139         ds->num_tx_queues = dev->info->num_tx_queues;
2140
2141         regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL],
2142                            MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2143
2144         ksz_init_mib_timer(dev);
2145
2146         ds->configure_vlan_while_not_filtering = false;
2147
2148         if (dev->dev_ops->setup) {
2149                 ret = dev->dev_ops->setup(ds);
2150                 if (ret)
2151                         return ret;
2152         }
2153
2154         /* Start with learning disabled on standalone user ports, and enabled
2155          * on the CPU port. In lack of other finer mechanisms, learning on the
2156          * CPU port will avoid flooding bridge local addresses on the network
2157          * in some cases.
2158          */
2159         p = &dev->ports[dev->cpu_port];
2160         p->learning = true;
2161
2162         if (dev->irq > 0) {
2163                 ret = ksz_girq_setup(dev);
2164                 if (ret)
2165                         return ret;
2166
2167                 dsa_switch_for_each_user_port(dp, dev->ds) {
2168                         ret = ksz_pirq_setup(dev, dp->index);
2169                         if (ret)
2170                                 goto out_girq;
2171
2172                         ret = ksz_ptp_irq_setup(ds, dp->index);
2173                         if (ret)
2174                                 goto out_pirq;
2175                 }
2176         }
2177
2178         ret = ksz_ptp_clock_register(ds);
2179         if (ret) {
2180                 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret);
2181                 goto out_ptpirq;
2182         }
2183
2184         ret = ksz_mdio_register(dev);
2185         if (ret < 0) {
2186                 dev_err(dev->dev, "failed to register the mdio");
2187                 goto out_ptp_clock_unregister;
2188         }
2189
2190         /* start switch */
2191         regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL],
2192                            SW_START, SW_START);
2193
2194         return 0;
2195
2196 out_ptp_clock_unregister:
2197         ksz_ptp_clock_unregister(ds);
2198 out_ptpirq:
2199         if (dev->irq > 0)
2200                 dsa_switch_for_each_user_port(dp, dev->ds)
2201                         ksz_ptp_irq_free(ds, dp->index);
2202 out_pirq:
2203         if (dev->irq > 0)
2204                 dsa_switch_for_each_user_port(dp, dev->ds)
2205                         ksz_irq_free(&dev->ports[dp->index].pirq);
2206 out_girq:
2207         if (dev->irq > 0)
2208                 ksz_irq_free(&dev->girq);
2209
2210         return ret;
2211 }
2212
2213 static void ksz_teardown(struct dsa_switch *ds)
2214 {
2215         struct ksz_device *dev = ds->priv;
2216         struct dsa_port *dp;
2217
2218         ksz_ptp_clock_unregister(ds);
2219
2220         if (dev->irq > 0) {
2221                 dsa_switch_for_each_user_port(dp, dev->ds) {
2222                         ksz_ptp_irq_free(ds, dp->index);
2223
2224                         ksz_irq_free(&dev->ports[dp->index].pirq);
2225                 }
2226
2227                 ksz_irq_free(&dev->girq);
2228         }
2229
2230         if (dev->dev_ops->teardown)
2231                 dev->dev_ops->teardown(ds);
2232 }
2233
2234 static void port_r_cnt(struct ksz_device *dev, int port)
2235 {
2236         struct ksz_port_mib *mib = &dev->ports[port].mib;
2237         u64 *dropped;
2238
2239         /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2240         while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2241                 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2242                                         &mib->counters[mib->cnt_ptr]);
2243                 ++mib->cnt_ptr;
2244         }
2245
2246         /* last one in storage */
2247         dropped = &mib->counters[dev->info->mib_cnt];
2248
2249         /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
2250         while (mib->cnt_ptr < dev->info->mib_cnt) {
2251                 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2252                                         dropped, &mib->counters[mib->cnt_ptr]);
2253                 ++mib->cnt_ptr;
2254         }
2255         mib->cnt_ptr = 0;
2256 }
2257
2258 static void ksz_mib_read_work(struct work_struct *work)
2259 {
2260         struct ksz_device *dev = container_of(work, struct ksz_device,
2261                                               mib_read.work);
2262         struct ksz_port_mib *mib;
2263         struct ksz_port *p;
2264         int i;
2265
2266         for (i = 0; i < dev->info->port_cnt; i++) {
2267                 if (dsa_is_unused_port(dev->ds, i))
2268                         continue;
2269
2270                 p = &dev->ports[i];
2271                 mib = &p->mib;
2272                 mutex_lock(&mib->cnt_mutex);
2273
2274                 /* Only read MIB counters when the port is told to do.
2275                  * If not, read only dropped counters when link is not up.
2276                  */
2277                 if (!p->read) {
2278                         const struct dsa_port *dp = dsa_to_port(dev->ds, i);
2279
2280                         if (!netif_carrier_ok(dp->slave))
2281                                 mib->cnt_ptr = dev->info->reg_mib_cnt;
2282                 }
2283                 port_r_cnt(dev, i);
2284                 p->read = false;
2285
2286                 if (dev->dev_ops->r_mib_stat64)
2287                         dev->dev_ops->r_mib_stat64(dev, i);
2288
2289                 mutex_unlock(&mib->cnt_mutex);
2290         }
2291
2292         schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
2293 }
2294
2295 void ksz_init_mib_timer(struct ksz_device *dev)
2296 {
2297         int i;
2298
2299         INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2300
2301         for (i = 0; i < dev->info->port_cnt; i++) {
2302                 struct ksz_port_mib *mib = &dev->ports[i].mib;
2303
2304                 dev->dev_ops->port_init_cnt(dev, i);
2305
2306                 mib->cnt_ptr = 0;
2307                 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2308         }
2309 }
2310
2311 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
2312 {
2313         struct ksz_device *dev = ds->priv;
2314         u16 val = 0xffff;
2315         int ret;
2316
2317         ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
2318         if (ret)
2319                 return ret;
2320
2321         return val;
2322 }
2323
2324 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
2325 {
2326         struct ksz_device *dev = ds->priv;
2327         int ret;
2328
2329         ret = dev->dev_ops->w_phy(dev, addr, reg, val);
2330         if (ret)
2331                 return ret;
2332
2333         return 0;
2334 }
2335
2336 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
2337 {
2338         struct ksz_device *dev = ds->priv;
2339
2340         if (dev->chip_id == KSZ8830_CHIP_ID) {
2341                 /* Silicon Errata Sheet (DS80000830A):
2342                  * Port 1 does not work with LinkMD Cable-Testing.
2343                  * Port 1 does not respond to received PAUSE control frames.
2344                  */
2345                 if (!port)
2346                         return MICREL_KSZ8_P1_ERRATA;
2347         }
2348
2349         return 0;
2350 }
2351
2352 static void ksz_mac_link_down(struct dsa_switch *ds, int port,
2353                               unsigned int mode, phy_interface_t interface)
2354 {
2355         struct ksz_device *dev = ds->priv;
2356         struct ksz_port *p = &dev->ports[port];
2357
2358         /* Read all MIB counters when the link is going down. */
2359         p->read = true;
2360         /* timer started */
2361         if (dev->mib_read_interval)
2362                 schedule_delayed_work(&dev->mib_read, 0);
2363 }
2364
2365 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
2366 {
2367         struct ksz_device *dev = ds->priv;
2368
2369         if (sset != ETH_SS_STATS)
2370                 return 0;
2371
2372         return dev->info->mib_cnt;
2373 }
2374
2375 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
2376                                   uint64_t *buf)
2377 {
2378         const struct dsa_port *dp = dsa_to_port(ds, port);
2379         struct ksz_device *dev = ds->priv;
2380         struct ksz_port_mib *mib;
2381
2382         mib = &dev->ports[port].mib;
2383         mutex_lock(&mib->cnt_mutex);
2384
2385         /* Only read dropped counters if no link. */
2386         if (!netif_carrier_ok(dp->slave))
2387                 mib->cnt_ptr = dev->info->reg_mib_cnt;
2388         port_r_cnt(dev, port);
2389         memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
2390         mutex_unlock(&mib->cnt_mutex);
2391 }
2392
2393 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
2394                                 struct dsa_bridge bridge,
2395                                 bool *tx_fwd_offload,
2396                                 struct netlink_ext_ack *extack)
2397 {
2398         /* port_stp_state_set() will be called after to put the port in
2399          * appropriate state so there is no need to do anything.
2400          */
2401
2402         return 0;
2403 }
2404
2405 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
2406                                   struct dsa_bridge bridge)
2407 {
2408         /* port_stp_state_set() will be called after to put the port in
2409          * forwarding state so there is no need to do anything.
2410          */
2411 }
2412
2413 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
2414 {
2415         struct ksz_device *dev = ds->priv;
2416
2417         dev->dev_ops->flush_dyn_mac_table(dev, port);
2418 }
2419
2420 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2421 {
2422         struct ksz_device *dev = ds->priv;
2423
2424         if (!dev->dev_ops->set_ageing_time)
2425                 return -EOPNOTSUPP;
2426
2427         return dev->dev_ops->set_ageing_time(dev, msecs);
2428 }
2429
2430 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
2431                             const unsigned char *addr, u16 vid,
2432                             struct dsa_db db)
2433 {
2434         struct ksz_device *dev = ds->priv;
2435
2436         if (!dev->dev_ops->fdb_add)
2437                 return -EOPNOTSUPP;
2438
2439         return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
2440 }
2441
2442 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
2443                             const unsigned char *addr,
2444                             u16 vid, struct dsa_db db)
2445 {
2446         struct ksz_device *dev = ds->priv;
2447
2448         if (!dev->dev_ops->fdb_del)
2449                 return -EOPNOTSUPP;
2450
2451         return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
2452 }
2453
2454 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
2455                              dsa_fdb_dump_cb_t *cb, void *data)
2456 {
2457         struct ksz_device *dev = ds->priv;
2458
2459         if (!dev->dev_ops->fdb_dump)
2460                 return -EOPNOTSUPP;
2461
2462         return dev->dev_ops->fdb_dump(dev, port, cb, data);
2463 }
2464
2465 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
2466                             const struct switchdev_obj_port_mdb *mdb,
2467                             struct dsa_db db)
2468 {
2469         struct ksz_device *dev = ds->priv;
2470
2471         if (!dev->dev_ops->mdb_add)
2472                 return -EOPNOTSUPP;
2473
2474         return dev->dev_ops->mdb_add(dev, port, mdb, db);
2475 }
2476
2477 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
2478                             const struct switchdev_obj_port_mdb *mdb,
2479                             struct dsa_db db)
2480 {
2481         struct ksz_device *dev = ds->priv;
2482
2483         if (!dev->dev_ops->mdb_del)
2484                 return -EOPNOTSUPP;
2485
2486         return dev->dev_ops->mdb_del(dev, port, mdb, db);
2487 }
2488
2489 static int ksz_enable_port(struct dsa_switch *ds, int port,
2490                            struct phy_device *phy)
2491 {
2492         struct ksz_device *dev = ds->priv;
2493
2494         if (!dsa_is_user_port(ds, port))
2495                 return 0;
2496
2497         /* setup slave port */
2498         dev->dev_ops->port_setup(dev, port, false);
2499
2500         /* port_stp_state_set() will be called after to enable the port so
2501          * there is no need to do anything.
2502          */
2503
2504         return 0;
2505 }
2506
2507 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
2508 {
2509         struct ksz_device *dev = ds->priv;
2510         struct ksz_port *p;
2511         const u16 *regs;
2512         u8 data;
2513
2514         regs = dev->info->regs;
2515
2516         ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
2517         data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2518
2519         p = &dev->ports[port];
2520
2521         switch (state) {
2522         case BR_STATE_DISABLED:
2523                 data |= PORT_LEARN_DISABLE;
2524                 break;
2525         case BR_STATE_LISTENING:
2526                 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2527                 break;
2528         case BR_STATE_LEARNING:
2529                 data |= PORT_RX_ENABLE;
2530                 if (!p->learning)
2531                         data |= PORT_LEARN_DISABLE;
2532                 break;
2533         case BR_STATE_FORWARDING:
2534                 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2535                 if (!p->learning)
2536                         data |= PORT_LEARN_DISABLE;
2537                 break;
2538         case BR_STATE_BLOCKING:
2539                 data |= PORT_LEARN_DISABLE;
2540                 break;
2541         default:
2542                 dev_err(ds->dev, "invalid STP state: %d\n", state);
2543                 return;
2544         }
2545
2546         ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
2547
2548         p->stp_state = state;
2549
2550         ksz_update_port_member(dev, port);
2551 }
2552
2553 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2554                                      struct switchdev_brport_flags flags,
2555                                      struct netlink_ext_ack *extack)
2556 {
2557         if (flags.mask & ~BR_LEARNING)
2558                 return -EINVAL;
2559
2560         return 0;
2561 }
2562
2563 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
2564                                  struct switchdev_brport_flags flags,
2565                                  struct netlink_ext_ack *extack)
2566 {
2567         struct ksz_device *dev = ds->priv;
2568         struct ksz_port *p = &dev->ports[port];
2569
2570         if (flags.mask & BR_LEARNING) {
2571                 p->learning = !!(flags.val & BR_LEARNING);
2572
2573                 /* Make the change take effect immediately */
2574                 ksz_port_stp_state_set(ds, port, p->stp_state);
2575         }
2576
2577         return 0;
2578 }
2579
2580 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
2581                                                   int port,
2582                                                   enum dsa_tag_protocol mp)
2583 {
2584         struct ksz_device *dev = ds->priv;
2585         enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
2586
2587         if (dev->chip_id == KSZ8795_CHIP_ID ||
2588             dev->chip_id == KSZ8794_CHIP_ID ||
2589             dev->chip_id == KSZ8765_CHIP_ID)
2590                 proto = DSA_TAG_PROTO_KSZ8795;
2591
2592         if (dev->chip_id == KSZ8830_CHIP_ID ||
2593             dev->chip_id == KSZ8563_CHIP_ID ||
2594             dev->chip_id == KSZ9893_CHIP_ID ||
2595             dev->chip_id == KSZ9563_CHIP_ID)
2596                 proto = DSA_TAG_PROTO_KSZ9893;
2597
2598         if (dev->chip_id == KSZ9477_CHIP_ID ||
2599             dev->chip_id == KSZ9896_CHIP_ID ||
2600             dev->chip_id == KSZ9897_CHIP_ID ||
2601             dev->chip_id == KSZ9567_CHIP_ID)
2602                 proto = DSA_TAG_PROTO_KSZ9477;
2603
2604         if (is_lan937x(dev))
2605                 proto = DSA_TAG_PROTO_LAN937X_VALUE;
2606
2607         return proto;
2608 }
2609
2610 static int ksz_connect_tag_protocol(struct dsa_switch *ds,
2611                                     enum dsa_tag_protocol proto)
2612 {
2613         struct ksz_tagger_data *tagger_data;
2614
2615         tagger_data = ksz_tagger_data(ds);
2616         tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
2617
2618         return 0;
2619 }
2620
2621 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
2622                                    bool flag, struct netlink_ext_ack *extack)
2623 {
2624         struct ksz_device *dev = ds->priv;
2625
2626         if (!dev->dev_ops->vlan_filtering)
2627                 return -EOPNOTSUPP;
2628
2629         return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
2630 }
2631
2632 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
2633                              const struct switchdev_obj_port_vlan *vlan,
2634                              struct netlink_ext_ack *extack)
2635 {
2636         struct ksz_device *dev = ds->priv;
2637
2638         if (!dev->dev_ops->vlan_add)
2639                 return -EOPNOTSUPP;
2640
2641         return dev->dev_ops->vlan_add(dev, port, vlan, extack);
2642 }
2643
2644 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
2645                              const struct switchdev_obj_port_vlan *vlan)
2646 {
2647         struct ksz_device *dev = ds->priv;
2648
2649         if (!dev->dev_ops->vlan_del)
2650                 return -EOPNOTSUPP;
2651
2652         return dev->dev_ops->vlan_del(dev, port, vlan);
2653 }
2654
2655 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
2656                                struct dsa_mall_mirror_tc_entry *mirror,
2657                                bool ingress, struct netlink_ext_ack *extack)
2658 {
2659         struct ksz_device *dev = ds->priv;
2660
2661         if (!dev->dev_ops->mirror_add)
2662                 return -EOPNOTSUPP;
2663
2664         return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
2665 }
2666
2667 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
2668                                 struct dsa_mall_mirror_tc_entry *mirror)
2669 {
2670         struct ksz_device *dev = ds->priv;
2671
2672         if (dev->dev_ops->mirror_del)
2673                 dev->dev_ops->mirror_del(dev, port, mirror);
2674 }
2675
2676 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
2677 {
2678         struct ksz_device *dev = ds->priv;
2679
2680         if (!dev->dev_ops->change_mtu)
2681                 return -EOPNOTSUPP;
2682
2683         return dev->dev_ops->change_mtu(dev, port, mtu);
2684 }
2685
2686 static int ksz_max_mtu(struct dsa_switch *ds, int port)
2687 {
2688         struct ksz_device *dev = ds->priv;
2689
2690         switch (dev->chip_id) {
2691         case KSZ8795_CHIP_ID:
2692         case KSZ8794_CHIP_ID:
2693         case KSZ8765_CHIP_ID:
2694                 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2695         case KSZ8830_CHIP_ID:
2696                 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2697         case KSZ8563_CHIP_ID:
2698         case KSZ9477_CHIP_ID:
2699         case KSZ9563_CHIP_ID:
2700         case KSZ9567_CHIP_ID:
2701         case KSZ9893_CHIP_ID:
2702         case KSZ9896_CHIP_ID:
2703         case KSZ9897_CHIP_ID:
2704         case LAN9370_CHIP_ID:
2705         case LAN9371_CHIP_ID:
2706         case LAN9372_CHIP_ID:
2707         case LAN9373_CHIP_ID:
2708         case LAN9374_CHIP_ID:
2709                 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2710         }
2711
2712         return -EOPNOTSUPP;
2713 }
2714
2715 static int ksz_validate_eee(struct dsa_switch *ds, int port)
2716 {
2717         struct ksz_device *dev = ds->priv;
2718
2719         if (!dev->info->internal_phy[port])
2720                 return -EOPNOTSUPP;
2721
2722         switch (dev->chip_id) {
2723         case KSZ8563_CHIP_ID:
2724         case KSZ9477_CHIP_ID:
2725         case KSZ9563_CHIP_ID:
2726         case KSZ9567_CHIP_ID:
2727         case KSZ9893_CHIP_ID:
2728         case KSZ9896_CHIP_ID:
2729         case KSZ9897_CHIP_ID:
2730                 return 0;
2731         }
2732
2733         return -EOPNOTSUPP;
2734 }
2735
2736 static int ksz_get_mac_eee(struct dsa_switch *ds, int port,
2737                            struct ethtool_eee *e)
2738 {
2739         int ret;
2740
2741         ret = ksz_validate_eee(ds, port);
2742         if (ret)
2743                 return ret;
2744
2745         /* There is no documented control of Tx LPI configuration. */
2746         e->tx_lpi_enabled = true;
2747
2748         /* There is no documented control of Tx LPI timer. According to tests
2749          * Tx LPI timer seems to be set by default to minimal value.
2750          */
2751         e->tx_lpi_timer = 0;
2752
2753         return 0;
2754 }
2755
2756 static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
2757                            struct ethtool_eee *e)
2758 {
2759         struct ksz_device *dev = ds->priv;
2760         int ret;
2761
2762         ret = ksz_validate_eee(ds, port);
2763         if (ret)
2764                 return ret;
2765
2766         if (!e->tx_lpi_enabled) {
2767                 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
2768                 return -EINVAL;
2769         }
2770
2771         if (e->tx_lpi_timer) {
2772                 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
2773                 return -EINVAL;
2774         }
2775
2776         return 0;
2777 }
2778
2779 static void ksz_set_xmii(struct ksz_device *dev, int port,
2780                          phy_interface_t interface)
2781 {
2782         const u8 *bitval = dev->info->xmii_ctrl1;
2783         struct ksz_port *p = &dev->ports[port];
2784         const u16 *regs = dev->info->regs;
2785         u8 data8;
2786
2787         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2788
2789         data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
2790                    P_RGMII_ID_EG_ENABLE);
2791
2792         switch (interface) {
2793         case PHY_INTERFACE_MODE_MII:
2794                 data8 |= bitval[P_MII_SEL];
2795                 break;
2796         case PHY_INTERFACE_MODE_RMII:
2797                 data8 |= bitval[P_RMII_SEL];
2798                 break;
2799         case PHY_INTERFACE_MODE_GMII:
2800                 data8 |= bitval[P_GMII_SEL];
2801                 break;
2802         case PHY_INTERFACE_MODE_RGMII:
2803         case PHY_INTERFACE_MODE_RGMII_ID:
2804         case PHY_INTERFACE_MODE_RGMII_TXID:
2805         case PHY_INTERFACE_MODE_RGMII_RXID:
2806                 data8 |= bitval[P_RGMII_SEL];
2807                 /* On KSZ9893, disable RGMII in-band status support */
2808                 if (dev->chip_id == KSZ9893_CHIP_ID ||
2809                     dev->chip_id == KSZ8563_CHIP_ID ||
2810                     dev->chip_id == KSZ9563_CHIP_ID)
2811                         data8 &= ~P_MII_MAC_MODE;
2812                 break;
2813         default:
2814                 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
2815                         phy_modes(interface), port);
2816                 return;
2817         }
2818
2819         if (p->rgmii_tx_val)
2820                 data8 |= P_RGMII_ID_EG_ENABLE;
2821
2822         if (p->rgmii_rx_val)
2823                 data8 |= P_RGMII_ID_IG_ENABLE;
2824
2825         /* Write the updated value */
2826         ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2827 }
2828
2829 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
2830 {
2831         const u8 *bitval = dev->info->xmii_ctrl1;
2832         const u16 *regs = dev->info->regs;
2833         phy_interface_t interface;
2834         u8 data8;
2835         u8 val;
2836
2837         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2838
2839         val = FIELD_GET(P_MII_SEL_M, data8);
2840
2841         if (val == bitval[P_MII_SEL]) {
2842                 if (gbit)
2843                         interface = PHY_INTERFACE_MODE_GMII;
2844                 else
2845                         interface = PHY_INTERFACE_MODE_MII;
2846         } else if (val == bitval[P_RMII_SEL]) {
2847                 interface = PHY_INTERFACE_MODE_RGMII;
2848         } else {
2849                 interface = PHY_INTERFACE_MODE_RGMII;
2850                 if (data8 & P_RGMII_ID_EG_ENABLE)
2851                         interface = PHY_INTERFACE_MODE_RGMII_TXID;
2852                 if (data8 & P_RGMII_ID_IG_ENABLE) {
2853                         interface = PHY_INTERFACE_MODE_RGMII_RXID;
2854                         if (data8 & P_RGMII_ID_EG_ENABLE)
2855                                 interface = PHY_INTERFACE_MODE_RGMII_ID;
2856                 }
2857         }
2858
2859         return interface;
2860 }
2861
2862 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
2863                                    unsigned int mode,
2864                                    const struct phylink_link_state *state)
2865 {
2866         struct ksz_device *dev = ds->priv;
2867
2868         if (ksz_is_ksz88x3(dev))
2869                 return;
2870
2871         /* Internal PHYs */
2872         if (dev->info->internal_phy[port])
2873                 return;
2874
2875         if (phylink_autoneg_inband(mode)) {
2876                 dev_err(dev->dev, "In-band AN not supported!\n");
2877                 return;
2878         }
2879
2880         ksz_set_xmii(dev, port, state->interface);
2881
2882         if (dev->dev_ops->phylink_mac_config)
2883                 dev->dev_ops->phylink_mac_config(dev, port, mode, state);
2884
2885         if (dev->dev_ops->setup_rgmii_delay)
2886                 dev->dev_ops->setup_rgmii_delay(dev, port);
2887 }
2888
2889 bool ksz_get_gbit(struct ksz_device *dev, int port)
2890 {
2891         const u8 *bitval = dev->info->xmii_ctrl1;
2892         const u16 *regs = dev->info->regs;
2893         bool gbit = false;
2894         u8 data8;
2895         bool val;
2896
2897         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2898
2899         val = FIELD_GET(P_GMII_1GBIT_M, data8);
2900
2901         if (val == bitval[P_GMII_1GBIT])
2902                 gbit = true;
2903
2904         return gbit;
2905 }
2906
2907 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
2908 {
2909         const u8 *bitval = dev->info->xmii_ctrl1;
2910         const u16 *regs = dev->info->regs;
2911         u8 data8;
2912
2913         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2914
2915         data8 &= ~P_GMII_1GBIT_M;
2916
2917         if (gbit)
2918                 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
2919         else
2920                 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
2921
2922         /* Write the updated value */
2923         ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2924 }
2925
2926 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
2927 {
2928         const u8 *bitval = dev->info->xmii_ctrl0;
2929         const u16 *regs = dev->info->regs;
2930         u8 data8;
2931
2932         ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
2933
2934         data8 &= ~P_MII_100MBIT_M;
2935
2936         if (speed == SPEED_100)
2937                 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
2938         else
2939                 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
2940
2941         /* Write the updated value */
2942         ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
2943 }
2944
2945 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
2946 {
2947         if (speed == SPEED_1000)
2948                 ksz_set_gbit(dev, port, true);
2949         else
2950                 ksz_set_gbit(dev, port, false);
2951
2952         if (speed == SPEED_100 || speed == SPEED_10)
2953                 ksz_set_100_10mbit(dev, port, speed);
2954 }
2955
2956 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
2957                                 bool tx_pause, bool rx_pause)
2958 {
2959         const u8 *bitval = dev->info->xmii_ctrl0;
2960         const u32 *masks = dev->info->masks;
2961         const u16 *regs = dev->info->regs;
2962         u8 mask;
2963         u8 val;
2964
2965         mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
2966                masks[P_MII_RX_FLOW_CTRL];
2967
2968         if (duplex == DUPLEX_FULL)
2969                 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
2970         else
2971                 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
2972
2973         if (tx_pause)
2974                 val |= masks[P_MII_TX_FLOW_CTRL];
2975
2976         if (rx_pause)
2977                 val |= masks[P_MII_RX_FLOW_CTRL];
2978
2979         ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
2980 }
2981
2982 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
2983                                         unsigned int mode,
2984                                         phy_interface_t interface,
2985                                         struct phy_device *phydev, int speed,
2986                                         int duplex, bool tx_pause,
2987                                         bool rx_pause)
2988 {
2989         struct ksz_port *p;
2990
2991         p = &dev->ports[port];
2992
2993         /* Internal PHYs */
2994         if (dev->info->internal_phy[port])
2995                 return;
2996
2997         p->phydev.speed = speed;
2998
2999         ksz_port_set_xmii_speed(dev, port, speed);
3000
3001         ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
3002 }
3003
3004 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
3005                                     unsigned int mode,
3006                                     phy_interface_t interface,
3007                                     struct phy_device *phydev, int speed,
3008                                     int duplex, bool tx_pause, bool rx_pause)
3009 {
3010         struct ksz_device *dev = ds->priv;
3011
3012         if (dev->dev_ops->phylink_mac_link_up)
3013                 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
3014                                                   phydev, speed, duplex,
3015                                                   tx_pause, rx_pause);
3016 }
3017
3018 static int ksz_switch_detect(struct ksz_device *dev)
3019 {
3020         u8 id1, id2, id4;
3021         u16 id16;
3022         u32 id32;
3023         int ret;
3024
3025         /* read chip id */
3026         ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
3027         if (ret)
3028                 return ret;
3029
3030         id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
3031         id2 = FIELD_GET(SW_CHIP_ID_M, id16);
3032
3033         switch (id1) {
3034         case KSZ87_FAMILY_ID:
3035                 if (id2 == KSZ87_CHIP_ID_95) {
3036                         u8 val;
3037
3038                         dev->chip_id = KSZ8795_CHIP_ID;
3039
3040                         ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
3041                         if (val & KSZ8_PORT_FIBER_MODE)
3042                                 dev->chip_id = KSZ8765_CHIP_ID;
3043                 } else if (id2 == KSZ87_CHIP_ID_94) {
3044                         dev->chip_id = KSZ8794_CHIP_ID;
3045                 } else {
3046                         return -ENODEV;
3047                 }
3048                 break;
3049         case KSZ88_FAMILY_ID:
3050                 if (id2 == KSZ88_CHIP_ID_63)
3051                         dev->chip_id = KSZ8830_CHIP_ID;
3052                 else
3053                         return -ENODEV;
3054                 break;
3055         default:
3056                 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
3057                 if (ret)
3058                         return ret;
3059
3060                 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
3061                 id32 &= ~0xFF;
3062
3063                 switch (id32) {
3064                 case KSZ9477_CHIP_ID:
3065                 case KSZ9896_CHIP_ID:
3066                 case KSZ9897_CHIP_ID:
3067                 case KSZ9567_CHIP_ID:
3068                 case LAN9370_CHIP_ID:
3069                 case LAN9371_CHIP_ID:
3070                 case LAN9372_CHIP_ID:
3071                 case LAN9373_CHIP_ID:
3072                 case LAN9374_CHIP_ID:
3073                         dev->chip_id = id32;
3074                         break;
3075                 case KSZ9893_CHIP_ID:
3076                         ret = ksz_read8(dev, REG_CHIP_ID4,
3077                                         &id4);
3078                         if (ret)
3079                                 return ret;
3080
3081                         if (id4 == SKU_ID_KSZ8563)
3082                                 dev->chip_id = KSZ8563_CHIP_ID;
3083                         else if (id4 == SKU_ID_KSZ9563)
3084                                 dev->chip_id = KSZ9563_CHIP_ID;
3085                         else
3086                                 dev->chip_id = KSZ9893_CHIP_ID;
3087
3088                         break;
3089                 default:
3090                         dev_err(dev->dev,
3091                                 "unsupported switch detected %x)\n", id32);
3092                         return -ENODEV;
3093                 }
3094         }
3095         return 0;
3096 }
3097
3098 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
3099  * is converted to Hex-decimal using the successive multiplication method. On
3100  * every step, integer part is taken and decimal part is carry forwarded.
3101  */
3102 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
3103 {
3104         u32 cinc = 0;
3105         u32 txrate;
3106         u32 rate;
3107         u8 temp;
3108         u8 i;
3109
3110         txrate = idle_slope - send_slope;
3111
3112         if (!txrate)
3113                 return -EINVAL;
3114
3115         rate = idle_slope;
3116
3117         /* 24 bit register */
3118         for (i = 0; i < 6; i++) {
3119                 rate = rate * 16;
3120
3121                 temp = rate / txrate;
3122
3123                 rate %= txrate;
3124
3125                 cinc = ((cinc << 4) | temp);
3126         }
3127
3128         *bw = cinc;
3129
3130         return 0;
3131 }
3132
3133 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
3134                              u8 shaper)
3135 {
3136         return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
3137                            FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
3138                            FIELD_PREP(MTI_SHAPING_M, shaper));
3139 }
3140
3141 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
3142                             struct tc_cbs_qopt_offload *qopt)
3143 {
3144         struct ksz_device *dev = ds->priv;
3145         int ret;
3146         u32 bw;
3147
3148         if (!dev->info->tc_cbs_supported)
3149                 return -EOPNOTSUPP;
3150
3151         if (qopt->queue > dev->info->num_tx_queues)
3152                 return -EINVAL;
3153
3154         /* Queue Selection */
3155         ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue);
3156         if (ret)
3157                 return ret;
3158
3159         if (!qopt->enable)
3160                 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3161                                          MTI_SHAPING_OFF);
3162
3163         /* High Credit */
3164         ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
3165                            qopt->hicredit);
3166         if (ret)
3167                 return ret;
3168
3169         /* Low Credit */
3170         ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
3171                            qopt->locredit);
3172         if (ret)
3173                 return ret;
3174
3175         /* Credit Increment Register */
3176         ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw);
3177         if (ret)
3178                 return ret;
3179
3180         if (dev->dev_ops->tc_cbs_set_cinc) {
3181                 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
3182                 if (ret)
3183                         return ret;
3184         }
3185
3186         return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3187                                  MTI_SHAPING_SRP);
3188 }
3189
3190 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
3191 {
3192         int queue, ret;
3193
3194         /* Configuration will not take effect until the last Port Queue X
3195          * Egress Limit Control Register is written.
3196          */
3197         for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3198                 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
3199                                   KSZ9477_OUT_RATE_NO_LIMIT);
3200                 if (ret)
3201                         return ret;
3202         }
3203
3204         return 0;
3205 }
3206
3207 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
3208                                  int band)
3209 {
3210         /* Compared to queues, bands prioritize packets differently. In strict
3211          * priority mode, the lowest priority is assigned to Queue 0 while the
3212          * highest priority is given to Band 0.
3213          */
3214         return p->bands - 1 - band;
3215 }
3216
3217 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
3218 {
3219         int ret;
3220
3221         ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3222         if (ret)
3223                 return ret;
3224
3225         return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3226                                  MTI_SHAPING_OFF);
3227 }
3228
3229 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
3230                              int weight)
3231 {
3232         int ret;
3233
3234         ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3235         if (ret)
3236                 return ret;
3237
3238         ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3239                                 MTI_SHAPING_OFF);
3240         if (ret)
3241                 return ret;
3242
3243         return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight);
3244 }
3245
3246 static int ksz_tc_ets_add(struct ksz_device *dev, int port,
3247                           struct tc_ets_qopt_offload_replace_params *p)
3248 {
3249         int ret, band, tc_prio;
3250         u32 queue_map = 0;
3251
3252         /* In order to ensure proper prioritization, it is necessary to set the
3253          * rate limit for the related queue to zero. Otherwise strict priority
3254          * or WRR mode will not work. This is a hardware limitation.
3255          */
3256         ret = ksz_disable_egress_rate_limit(dev, port);
3257         if (ret)
3258                 return ret;
3259
3260         /* Configure queue scheduling mode for all bands. Currently only strict
3261          * prio mode is supported.
3262          */
3263         for (band = 0; band < p->bands; band++) {
3264                 int queue = ksz_ets_band_to_queue(p, band);
3265
3266                 ret = ksz_queue_set_strict(dev, port, queue);
3267                 if (ret)
3268                         return ret;
3269         }
3270
3271         /* Configure the mapping between traffic classes and queues. Note:
3272          * priomap variable support 16 traffic classes, but the chip can handle
3273          * only 8 classes.
3274          */
3275         for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
3276                 int queue;
3277
3278                 if (tc_prio > KSZ9477_MAX_TC_PRIO)
3279                         break;
3280
3281                 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]);
3282                 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
3283         }
3284
3285         return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3286 }
3287
3288 static int ksz_tc_ets_del(struct ksz_device *dev, int port)
3289 {
3290         int ret, queue, tc_prio, s;
3291         u32 queue_map = 0;
3292
3293         /* To restore the default chip configuration, set all queues to use the
3294          * WRR scheduler with a weight of 1.
3295          */
3296         for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3297                 ret = ksz_queue_set_wrr(dev, port, queue,
3298                                         KSZ9477_DEFAULT_WRR_WEIGHT);
3299                 if (ret)
3300                         return ret;
3301         }
3302
3303         switch (dev->info->num_tx_queues) {
3304         case 2:
3305                 s = 2;
3306                 break;
3307         case 4:
3308                 s = 1;
3309                 break;
3310         case 8:
3311                 s = 0;
3312                 break;
3313         default:
3314                 return -EINVAL;
3315         }
3316
3317         /* Revert the queue mapping for TC-priority to its default setting on
3318          * the chip.
3319          */
3320         for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) {
3321                 int queue;
3322
3323                 queue = tc_prio >> s;
3324                 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
3325         }
3326
3327         return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3328 }
3329
3330 static int ksz_tc_ets_validate(struct ksz_device *dev, int port,
3331                                struct tc_ets_qopt_offload_replace_params *p)
3332 {
3333         int band;
3334
3335         /* Since it is not feasible to share one port among multiple qdisc,
3336          * the user must configure all available queues appropriately.
3337          */
3338         if (p->bands != dev->info->num_tx_queues) {
3339                 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
3340                         dev->info->num_tx_queues);
3341                 return -EOPNOTSUPP;
3342         }
3343
3344         for (band = 0; band < p->bands; ++band) {
3345                 /* The KSZ switches utilize a weighted round robin configuration
3346                  * where a certain number of packets can be transmitted from a
3347                  * queue before the next queue is serviced. For more information
3348                  * on this, refer to section 5.2.8.4 of the KSZ8565R
3349                  * documentation on the Port Transmit Queue Control 1 Register.
3350                  * However, the current ETS Qdisc implementation (as of February
3351                  * 2023) assigns a weight to each queue based on the number of
3352                  * bytes or extrapolated bandwidth in percentages. Since this
3353                  * differs from the KSZ switches' method and we don't want to
3354                  * fake support by converting bytes to packets, it is better to
3355                  * return an error instead.
3356                  */
3357                 if (p->quanta[band]) {
3358                         dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
3359                         return -EOPNOTSUPP;
3360                 }
3361         }
3362
3363         return 0;
3364 }
3365
3366 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
3367                                   struct tc_ets_qopt_offload *qopt)
3368 {
3369         struct ksz_device *dev = ds->priv;
3370         int ret;
3371
3372         if (!dev->info->tc_ets_supported)
3373                 return -EOPNOTSUPP;
3374
3375         if (qopt->parent != TC_H_ROOT) {
3376                 dev_err(dev->dev, "Parent should be \"root\"\n");
3377                 return -EOPNOTSUPP;
3378         }
3379
3380         switch (qopt->command) {
3381         case TC_ETS_REPLACE:
3382                 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params);
3383                 if (ret)
3384                         return ret;
3385
3386                 return ksz_tc_ets_add(dev, port, &qopt->replace_params);
3387         case TC_ETS_DESTROY:
3388                 return ksz_tc_ets_del(dev, port);
3389         case TC_ETS_STATS:
3390         case TC_ETS_GRAFT:
3391                 return -EOPNOTSUPP;
3392         }
3393
3394         return -EOPNOTSUPP;
3395 }
3396
3397 static int ksz_setup_tc(struct dsa_switch *ds, int port,
3398                         enum tc_setup_type type, void *type_data)
3399 {
3400         switch (type) {
3401         case TC_SETUP_QDISC_CBS:
3402                 return ksz_setup_tc_cbs(ds, port, type_data);
3403         case TC_SETUP_QDISC_ETS:
3404                 return ksz_tc_setup_qdisc_ets(ds, port, type_data);
3405         default:
3406                 return -EOPNOTSUPP;
3407         }
3408 }
3409
3410 static const struct dsa_switch_ops ksz_switch_ops = {
3411         .get_tag_protocol       = ksz_get_tag_protocol,
3412         .connect_tag_protocol   = ksz_connect_tag_protocol,
3413         .get_phy_flags          = ksz_get_phy_flags,
3414         .setup                  = ksz_setup,
3415         .teardown               = ksz_teardown,
3416         .phy_read               = ksz_phy_read16,
3417         .phy_write              = ksz_phy_write16,
3418         .phylink_get_caps       = ksz_phylink_get_caps,
3419         .phylink_mac_config     = ksz_phylink_mac_config,
3420         .phylink_mac_link_up    = ksz_phylink_mac_link_up,
3421         .phylink_mac_link_down  = ksz_mac_link_down,
3422         .port_enable            = ksz_enable_port,
3423         .set_ageing_time        = ksz_set_ageing_time,
3424         .get_strings            = ksz_get_strings,
3425         .get_ethtool_stats      = ksz_get_ethtool_stats,
3426         .get_sset_count         = ksz_sset_count,
3427         .port_bridge_join       = ksz_port_bridge_join,
3428         .port_bridge_leave      = ksz_port_bridge_leave,
3429         .port_stp_state_set     = ksz_port_stp_state_set,
3430         .port_pre_bridge_flags  = ksz_port_pre_bridge_flags,
3431         .port_bridge_flags      = ksz_port_bridge_flags,
3432         .port_fast_age          = ksz_port_fast_age,
3433         .port_vlan_filtering    = ksz_port_vlan_filtering,
3434         .port_vlan_add          = ksz_port_vlan_add,
3435         .port_vlan_del          = ksz_port_vlan_del,
3436         .port_fdb_dump          = ksz_port_fdb_dump,
3437         .port_fdb_add           = ksz_port_fdb_add,
3438         .port_fdb_del           = ksz_port_fdb_del,
3439         .port_mdb_add           = ksz_port_mdb_add,
3440         .port_mdb_del           = ksz_port_mdb_del,
3441         .port_mirror_add        = ksz_port_mirror_add,
3442         .port_mirror_del        = ksz_port_mirror_del,
3443         .get_stats64            = ksz_get_stats64,
3444         .get_pause_stats        = ksz_get_pause_stats,
3445         .port_change_mtu        = ksz_change_mtu,
3446         .port_max_mtu           = ksz_max_mtu,
3447         .get_ts_info            = ksz_get_ts_info,
3448         .port_hwtstamp_get      = ksz_hwtstamp_get,
3449         .port_hwtstamp_set      = ksz_hwtstamp_set,
3450         .port_txtstamp          = ksz_port_txtstamp,
3451         .port_rxtstamp          = ksz_port_rxtstamp,
3452         .port_setup_tc          = ksz_setup_tc,
3453         .get_mac_eee            = ksz_get_mac_eee,
3454         .set_mac_eee            = ksz_set_mac_eee,
3455 };
3456
3457 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
3458 {
3459         struct dsa_switch *ds;
3460         struct ksz_device *swdev;
3461
3462         ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
3463         if (!ds)
3464                 return NULL;
3465
3466         ds->dev = base;
3467         ds->num_ports = DSA_MAX_PORTS;
3468         ds->ops = &ksz_switch_ops;
3469
3470         swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
3471         if (!swdev)
3472                 return NULL;
3473
3474         ds->priv = swdev;
3475         swdev->dev = base;
3476
3477         swdev->ds = ds;
3478         swdev->priv = priv;
3479
3480         return swdev;
3481 }
3482 EXPORT_SYMBOL(ksz_switch_alloc);
3483
3484 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
3485                                   struct device_node *port_dn)
3486 {
3487         phy_interface_t phy_mode = dev->ports[port_num].interface;
3488         int rx_delay = -1, tx_delay = -1;
3489
3490         if (!phy_interface_mode_is_rgmii(phy_mode))
3491                 return;
3492
3493         of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
3494         of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
3495
3496         if (rx_delay == -1 && tx_delay == -1) {
3497                 dev_warn(dev->dev,
3498                          "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
3499                          "please update device tree to specify \"rx-internal-delay-ps\" and "
3500                          "\"tx-internal-delay-ps\"",
3501                          port_num);
3502
3503                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
3504                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3505                         rx_delay = 2000;
3506
3507                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
3508                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3509                         tx_delay = 2000;
3510         }
3511
3512         if (rx_delay < 0)
3513                 rx_delay = 0;
3514         if (tx_delay < 0)
3515                 tx_delay = 0;
3516
3517         dev->ports[port_num].rgmii_rx_val = rx_delay;
3518         dev->ports[port_num].rgmii_tx_val = tx_delay;
3519 }
3520
3521 int ksz_switch_register(struct ksz_device *dev)
3522 {
3523         const struct ksz_chip_data *info;
3524         struct device_node *port, *ports;
3525         phy_interface_t interface;
3526         unsigned int port_num;
3527         int ret;
3528         int i;
3529
3530         if (dev->pdata)
3531                 dev->chip_id = dev->pdata->chip_id;
3532
3533         dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
3534                                                   GPIOD_OUT_LOW);
3535         if (IS_ERR(dev->reset_gpio))
3536                 return PTR_ERR(dev->reset_gpio);
3537
3538         if (dev->reset_gpio) {
3539                 gpiod_set_value_cansleep(dev->reset_gpio, 1);
3540                 usleep_range(10000, 12000);
3541                 gpiod_set_value_cansleep(dev->reset_gpio, 0);
3542                 msleep(100);
3543         }
3544
3545         mutex_init(&dev->dev_mutex);
3546         mutex_init(&dev->regmap_mutex);
3547         mutex_init(&dev->alu_mutex);
3548         mutex_init(&dev->vlan_mutex);
3549
3550         ret = ksz_switch_detect(dev);
3551         if (ret)
3552                 return ret;
3553
3554         info = ksz_lookup_info(dev->chip_id);
3555         if (!info)
3556                 return -ENODEV;
3557
3558         /* Update the compatible info with the probed one */
3559         dev->info = info;
3560
3561         dev_info(dev->dev, "found switch: %s, rev %i\n",
3562                  dev->info->dev_name, dev->chip_rev);
3563
3564         ret = ksz_check_device_id(dev);
3565         if (ret)
3566                 return ret;
3567
3568         dev->dev_ops = dev->info->ops;
3569
3570         ret = dev->dev_ops->init(dev);
3571         if (ret)
3572                 return ret;
3573
3574         dev->ports = devm_kzalloc(dev->dev,
3575                                   dev->info->port_cnt * sizeof(struct ksz_port),
3576                                   GFP_KERNEL);
3577         if (!dev->ports)
3578                 return -ENOMEM;
3579
3580         for (i = 0; i < dev->info->port_cnt; i++) {
3581                 spin_lock_init(&dev->ports[i].mib.stats64_lock);
3582                 mutex_init(&dev->ports[i].mib.cnt_mutex);
3583                 dev->ports[i].mib.counters =
3584                         devm_kzalloc(dev->dev,
3585                                      sizeof(u64) * (dev->info->mib_cnt + 1),
3586                                      GFP_KERNEL);
3587                 if (!dev->ports[i].mib.counters)
3588                         return -ENOMEM;
3589
3590                 dev->ports[i].ksz_dev = dev;
3591                 dev->ports[i].num = i;
3592         }
3593
3594         /* set the real number of ports */
3595         dev->ds->num_ports = dev->info->port_cnt;
3596
3597         /* Host port interface will be self detected, or specifically set in
3598          * device tree.
3599          */
3600         for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
3601                 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
3602         if (dev->dev->of_node) {
3603                 ret = of_get_phy_mode(dev->dev->of_node, &interface);
3604                 if (ret == 0)
3605                         dev->compat_interface = interface;
3606                 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
3607                 if (!ports)
3608                         ports = of_get_child_by_name(dev->dev->of_node, "ports");
3609                 if (ports) {
3610                         for_each_available_child_of_node(ports, port) {
3611                                 if (of_property_read_u32(port, "reg",
3612                                                          &port_num))
3613                                         continue;
3614                                 if (!(dev->port_mask & BIT(port_num))) {
3615                                         of_node_put(port);
3616                                         of_node_put(ports);
3617                                         return -EINVAL;
3618                                 }
3619                                 of_get_phy_mode(port,
3620                                                 &dev->ports[port_num].interface);
3621
3622                                 ksz_parse_rgmii_delay(dev, port_num, port);
3623                         }
3624                         of_node_put(ports);
3625                 }
3626                 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
3627                                                          "microchip,synclko-125");
3628                 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
3629                                                              "microchip,synclko-disable");
3630                 if (dev->synclko_125 && dev->synclko_disable) {
3631                         dev_err(dev->dev, "inconsistent synclko settings\n");
3632                         return -EINVAL;
3633                 }
3634         }
3635
3636         ret = dsa_register_switch(dev->ds);
3637         if (ret) {
3638                 dev->dev_ops->exit(dev);
3639                 return ret;
3640         }
3641
3642         /* Read MIB counters every 30 seconds to avoid overflow. */
3643         dev->mib_read_interval = msecs_to_jiffies(5000);
3644
3645         /* Start the MIB timer. */
3646         schedule_delayed_work(&dev->mib_read, 0);
3647
3648         return ret;
3649 }
3650 EXPORT_SYMBOL(ksz_switch_register);
3651
3652 void ksz_switch_remove(struct ksz_device *dev)
3653 {
3654         /* timer started */
3655         if (dev->mib_read_interval) {
3656                 dev->mib_read_interval = 0;
3657                 cancel_delayed_work_sync(&dev->mib_read);
3658         }
3659
3660         dev->dev_ops->exit(dev);
3661         dsa_unregister_switch(dev->ds);
3662
3663         if (dev->reset_gpio)
3664                 gpiod_set_value_cansleep(dev->reset_gpio, 1);
3665
3666 }
3667 EXPORT_SYMBOL(ksz_switch_remove);
3668
3669 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
3670 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
3671 MODULE_LICENSE("GPL");