2 * Mediatek MT7530 DSA Switch driver
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <linux/etherdevice.h>
15 #include <linux/if_bridge.h>
16 #include <linux/iopoll.h>
17 #include <linux/mdio.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/netdevice.h>
21 #include <linux/of_mdio.h>
22 #include <linux/of_net.h>
23 #include <linux/of_platform.h>
24 #include <linux/phy.h>
25 #include <linux/regmap.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/reset.h>
28 #include <linux/gpio/consumer.h>
33 /* String, offset, and register size in bytes if different from 4 bytes */
34 static const struct mt7530_mib_desc mt7530_mib[] = {
35 MIB_DESC(1, 0x00, "TxDrop"),
36 MIB_DESC(1, 0x04, "TxCrcErr"),
37 MIB_DESC(1, 0x08, "TxUnicast"),
38 MIB_DESC(1, 0x0c, "TxMulticast"),
39 MIB_DESC(1, 0x10, "TxBroadcast"),
40 MIB_DESC(1, 0x14, "TxCollision"),
41 MIB_DESC(1, 0x18, "TxSingleCollision"),
42 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
43 MIB_DESC(1, 0x20, "TxDeferred"),
44 MIB_DESC(1, 0x24, "TxLateCollision"),
45 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
46 MIB_DESC(1, 0x2c, "TxPause"),
47 MIB_DESC(1, 0x30, "TxPktSz64"),
48 MIB_DESC(1, 0x34, "TxPktSz65To127"),
49 MIB_DESC(1, 0x38, "TxPktSz128To255"),
50 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
51 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
52 MIB_DESC(1, 0x44, "Tx1024ToMax"),
53 MIB_DESC(2, 0x48, "TxBytes"),
54 MIB_DESC(1, 0x60, "RxDrop"),
55 MIB_DESC(1, 0x64, "RxFiltering"),
56 MIB_DESC(1, 0x6c, "RxMulticast"),
57 MIB_DESC(1, 0x70, "RxBroadcast"),
58 MIB_DESC(1, 0x74, "RxAlignErr"),
59 MIB_DESC(1, 0x78, "RxCrcErr"),
60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
61 MIB_DESC(1, 0x80, "RxFragErr"),
62 MIB_DESC(1, 0x84, "RxOverSzErr"),
63 MIB_DESC(1, 0x88, "RxJabberErr"),
64 MIB_DESC(1, 0x8c, "RxPause"),
65 MIB_DESC(1, 0x90, "RxPktSz64"),
66 MIB_DESC(1, 0x94, "RxPktSz65To127"),
67 MIB_DESC(1, 0x98, "RxPktSz128To255"),
68 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
71 MIB_DESC(2, 0xa8, "RxBytes"),
72 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
73 MIB_DESC(1, 0xb4, "RxIngressDrop"),
74 MIB_DESC(1, 0xb8, "RxArlDrop"),
78 mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val)
82 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val);
85 "failed to priv write register\n");
90 mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg)
95 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val);
98 "failed to priv read register\n");
106 mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg,
111 val = mt7623_trgmii_read(priv, reg);
114 mt7623_trgmii_write(priv, reg, val);
118 mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val)
120 mt7623_trgmii_rmw(priv, reg, 0, val);
124 mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val)
126 mt7623_trgmii_rmw(priv, reg, val, 0);
130 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
132 struct mii_bus *bus = priv->bus;
135 /* Write the desired MMD Devad */
136 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
140 /* Write the desired MMD register address */
141 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
145 /* Select the Function : DATA with no post increment */
146 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
150 /* Read the content of the MMD's selected register */
151 value = bus->read(bus, 0, MII_MMD_DATA);
155 dev_err(&bus->dev, "failed to read mmd register\n");
161 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
164 struct mii_bus *bus = priv->bus;
167 /* Write the desired MMD Devad */
168 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
172 /* Write the desired MMD register address */
173 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
177 /* Select the Function : DATA with no post increment */
178 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
182 /* Write the data into MMD's selected register */
183 ret = bus->write(bus, 0, MII_MMD_DATA, data);
187 "failed to write mmd register\n");
192 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
194 struct mii_bus *bus = priv->bus;
196 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
198 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
200 mutex_unlock(&bus->mdio_lock);
204 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
206 struct mii_bus *bus = priv->bus;
209 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
211 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
214 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
216 mutex_unlock(&bus->mdio_lock);
220 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
222 core_rmw(priv, reg, 0, val);
226 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
228 core_rmw(priv, reg, val, 0);
232 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
234 struct mii_bus *bus = priv->bus;
238 page = (reg >> 6) & 0x3ff;
239 r = (reg >> 2) & 0xf;
243 /* MT7530 uses 31 as the pseudo port */
244 ret = bus->write(bus, 0x1f, 0x1f, page);
248 ret = bus->write(bus, 0x1f, r, lo);
252 ret = bus->write(bus, 0x1f, 0x10, hi);
256 "failed to write mt7530 register\n");
261 mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
263 struct mii_bus *bus = priv->bus;
267 page = (reg >> 6) & 0x3ff;
268 r = (reg >> 2) & 0xf;
270 /* MT7530 uses 31 as the pseudo port */
271 ret = bus->write(bus, 0x1f, 0x1f, page);
274 "failed to read mt7530 register\n");
278 lo = bus->read(bus, 0x1f, r);
279 hi = bus->read(bus, 0x1f, 0x10);
281 return (hi << 16) | (lo & 0xffff);
285 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
287 struct mii_bus *bus = priv->bus;
289 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
291 mt7530_mii_write(priv, reg, val);
293 mutex_unlock(&bus->mdio_lock);
297 _mt7530_read(struct mt7530_dummy_poll *p)
299 struct mii_bus *bus = p->priv->bus;
302 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
304 val = mt7530_mii_read(p->priv, p->reg);
306 mutex_unlock(&bus->mdio_lock);
312 mt7530_read(struct mt7530_priv *priv, u32 reg)
314 struct mt7530_dummy_poll p;
316 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
317 return _mt7530_read(&p);
321 mt7530_rmw(struct mt7530_priv *priv, u32 reg,
324 struct mii_bus *bus = priv->bus;
327 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
329 val = mt7530_mii_read(priv, reg);
332 mt7530_mii_write(priv, reg, val);
334 mutex_unlock(&bus->mdio_lock);
338 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
340 mt7530_rmw(priv, reg, 0, val);
344 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
346 mt7530_rmw(priv, reg, val, 0);
350 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
354 struct mt7530_dummy_poll p;
356 /* Set the command operating upon the MAC address entries */
357 val = ATC_BUSY | ATC_MAT(0) | cmd;
358 mt7530_write(priv, MT7530_ATC, val);
360 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
361 ret = readx_poll_timeout(_mt7530_read, &p, val,
362 !(val & ATC_BUSY), 20, 20000);
364 dev_err(priv->dev, "reset timeout\n");
368 /* Additional sanity for read command if the specified
371 val = mt7530_read(priv, MT7530_ATC);
372 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
382 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
387 /* Read from ARL table into an array */
388 for (i = 0; i < 3; i++) {
389 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
391 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
392 __func__, __LINE__, i, reg[i]);
395 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
396 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
397 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
398 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
399 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
400 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
401 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
402 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
403 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
404 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
408 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
409 u8 port_mask, const u8 *mac,
415 reg[1] |= vid & CVID_MASK;
416 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
417 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
418 /* STATIC_ENT indicate that entry is static wouldn't
419 * be aged out and STATIC_EMP specified as erasing an
422 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
423 reg[1] |= mac[5] << MAC_BYTE_5;
424 reg[1] |= mac[4] << MAC_BYTE_4;
425 reg[0] |= mac[3] << MAC_BYTE_3;
426 reg[0] |= mac[2] << MAC_BYTE_2;
427 reg[0] |= mac[1] << MAC_BYTE_1;
428 reg[0] |= mac[0] << MAC_BYTE_0;
430 /* Write array into the ARL table */
431 for (i = 0; i < 3; i++)
432 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
436 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
438 struct mt7530_priv *priv = ds->priv;
439 u32 ncpo1, ssc_delta, trgint, i;
442 case PHY_INTERFACE_MODE_RGMII:
447 case PHY_INTERFACE_MODE_TRGMII:
453 dev_err(priv->dev, "xMII mode %d not supported\n", mode);
457 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
458 P6_INTF_MODE(trgint));
460 /* Lower Tx Driving for TRGMII path */
461 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
462 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
463 TD_DM_DRVP(8) | TD_DM_DRVN(8));
465 /* Setup core clock for MT7530 */
467 /* Disable MT7530 core clock */
468 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
470 /* Disable PLL, since phy_device has not yet been created
471 * provided for phy_[read,write]_mmd_indirect is called, we
472 * provide our own core_write_mmd_indirect to complete this
475 core_write_mmd_indirect(priv,
480 /* Set core clock into 500Mhz */
481 core_write(priv, CORE_GSWPLL_GRP2,
482 RG_GSWPLL_POSDIV_500M(1) |
483 RG_GSWPLL_FBKDIV_500M(25));
486 core_write(priv, CORE_GSWPLL_GRP1,
488 RG_GSWPLL_POSDIV_200M(2) |
489 RG_GSWPLL_FBKDIV_200M(32));
491 /* Enable MT7530 core clock */
492 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
495 /* Setup the MT7530 TRGMII Tx Clock */
496 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
497 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
498 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
499 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
500 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
501 core_write(priv, CORE_PLL_GROUP4,
502 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
503 RG_SYSPLL_BIAS_LPF_EN);
504 core_write(priv, CORE_PLL_GROUP2,
505 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
506 RG_SYSPLL_POSDIV(1));
507 core_write(priv, CORE_PLL_GROUP7,
508 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
509 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
510 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
511 REG_GSWCK_EN | REG_TRGMIICK_EN);
514 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
515 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
516 RD_TAP_MASK, RD_TAP(16));
518 mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
524 mt7623_pad_clk_setup(struct dsa_switch *ds)
526 struct mt7530_priv *priv = ds->priv;
529 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
530 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i),
531 TD_DM_DRVP(8) | TD_DM_DRVN(8));
533 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL);
534 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST);
540 mt7530_mib_reset(struct dsa_switch *ds)
542 struct mt7530_priv *priv = ds->priv;
544 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
545 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
549 mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable)
551 u32 mask = PMCR_TX_EN | PMCR_RX_EN;
554 mt7530_set(priv, MT7530_PMCR_P(port), mask);
556 mt7530_clear(priv, MT7530_PMCR_P(port), mask);
559 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
561 struct mt7530_priv *priv = ds->priv;
563 return mdiobus_read_nested(priv->bus, port, regnum);
566 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
569 struct mt7530_priv *priv = ds->priv;
571 return mdiobus_write_nested(priv->bus, port, regnum, val);
575 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
580 if (stringset != ETH_SS_STATS)
583 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
584 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
589 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
592 struct mt7530_priv *priv = ds->priv;
593 const struct mt7530_mib_desc *mib;
597 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
598 mib = &mt7530_mib[i];
599 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
601 data[i] = mt7530_read(priv, reg);
602 if (mib->size == 2) {
603 hi = mt7530_read(priv, reg + 4);
610 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
612 if (sset != ETH_SS_STATS)
615 return ARRAY_SIZE(mt7530_mib);
618 static void mt7530_adjust_link(struct dsa_switch *ds, int port,
619 struct phy_device *phydev)
621 struct mt7530_priv *priv = ds->priv;
623 if (phy_is_pseudo_fixed_link(phydev)) {
624 if (priv->id == ID_MT7530) {
625 dev_dbg(priv->dev, "phy-mode for master device = %x\n",
628 /* Setup TX circuit incluing relevant PAD and driving */
629 mt7530_pad_clk_setup(ds, phydev->interface);
631 /* Setup RX circuit, relevant PAD and driving on the
632 * host which must be placed after the setup on the
633 * device side is all finished.
635 mt7623_pad_clk_setup(ds);
638 u16 lcl_adv = 0, rmt_adv = 0;
640 u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE;
642 switch (phydev->speed) {
644 mcr |= PMCR_FORCE_SPEED_1000;
647 mcr |= PMCR_FORCE_SPEED_100;
652 mcr |= PMCR_FORCE_LNK;
654 if (phydev->duplex) {
655 mcr |= PMCR_FORCE_FDX;
658 rmt_adv = LPA_PAUSE_CAP;
659 if (phydev->asym_pause)
660 rmt_adv |= LPA_PAUSE_ASYM;
662 lcl_adv = linkmode_adv_to_lcl_adv_t(
663 phydev->advertising);
664 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
666 if (flowctrl & FLOW_CTRL_TX)
667 mcr |= PMCR_TX_FC_EN;
668 if (flowctrl & FLOW_CTRL_RX)
669 mcr |= PMCR_RX_FC_EN;
671 mt7530_write(priv, MT7530_PMCR_P(port), mcr);
676 mt7530_cpu_port_enable(struct mt7530_priv *priv,
679 /* Enable Mediatek header mode on the cpu port */
680 mt7530_write(priv, MT7530_PVC_P(port),
683 /* Setup the MAC by default for the cpu port */
684 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK);
686 /* Disable auto learning on the cpu port */
687 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS);
689 /* Unknown unicast frame fordwarding to the cpu port */
690 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port)));
692 /* Set CPU port number */
693 if (priv->id == ID_MT7621)
694 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
696 /* CPU port gets connected to all user ports of
699 mt7530_write(priv, MT7530_PCR_P(port),
700 PCR_MATRIX(dsa_user_ports(priv->ds)));
706 mt7530_port_enable(struct dsa_switch *ds, int port,
707 struct phy_device *phy)
709 struct mt7530_priv *priv = ds->priv;
711 mutex_lock(&priv->reg_mutex);
713 /* Setup the MAC for the user port */
714 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK);
716 /* Allow the user port gets connected to the cpu port and also
717 * restore the port matrix if the port is the member of a certain
720 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
721 priv->ports[port].enable = true;
722 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
723 priv->ports[port].pm);
724 mt7530_port_set_status(priv, port, 1);
726 mutex_unlock(&priv->reg_mutex);
732 mt7530_port_disable(struct dsa_switch *ds, int port,
733 struct phy_device *phy)
735 struct mt7530_priv *priv = ds->priv;
737 mutex_lock(&priv->reg_mutex);
739 /* Clear up all port matrix which could be restored in the next
740 * enablement for the port.
742 priv->ports[port].enable = false;
743 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
745 mt7530_port_set_status(priv, port, 0);
747 mutex_unlock(&priv->reg_mutex);
751 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
753 struct mt7530_priv *priv = ds->priv;
757 case BR_STATE_DISABLED:
758 stp_state = MT7530_STP_DISABLED;
760 case BR_STATE_BLOCKING:
761 stp_state = MT7530_STP_BLOCKING;
763 case BR_STATE_LISTENING:
764 stp_state = MT7530_STP_LISTENING;
766 case BR_STATE_LEARNING:
767 stp_state = MT7530_STP_LEARNING;
769 case BR_STATE_FORWARDING:
771 stp_state = MT7530_STP_FORWARDING;
775 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
779 mt7530_port_bridge_join(struct dsa_switch *ds, int port,
780 struct net_device *bridge)
782 struct mt7530_priv *priv = ds->priv;
783 u32 port_bitmap = BIT(MT7530_CPU_PORT);
786 mutex_lock(&priv->reg_mutex);
788 for (i = 0; i < MT7530_NUM_PORTS; i++) {
789 /* Add this port to the port matrix of the other ports in the
790 * same bridge. If the port is disabled, port matrix is kept
791 * and not being setup until the port becomes enabled.
793 if (dsa_is_user_port(ds, i) && i != port) {
794 if (dsa_to_port(ds, i)->bridge_dev != bridge)
796 if (priv->ports[i].enable)
797 mt7530_set(priv, MT7530_PCR_P(i),
798 PCR_MATRIX(BIT(port)));
799 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
801 port_bitmap |= BIT(i);
805 /* Add the all other ports to this port matrix. */
806 if (priv->ports[port].enable)
807 mt7530_rmw(priv, MT7530_PCR_P(port),
808 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
809 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
811 mutex_unlock(&priv->reg_mutex);
817 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
819 struct mt7530_priv *priv = ds->priv;
820 bool all_user_ports_removed = true;
823 /* When a port is removed from the bridge, the port would be set up
824 * back to the default as is at initial boot which is a VLAN-unaware
827 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
828 MT7530_PORT_MATRIX_MODE);
829 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK,
830 VLAN_ATTR(MT7530_VLAN_TRANSPARENT));
832 priv->ports[port].vlan_filtering = false;
834 for (i = 0; i < MT7530_NUM_PORTS; i++) {
835 if (dsa_is_user_port(ds, i) &&
836 priv->ports[i].vlan_filtering) {
837 all_user_ports_removed = false;
842 /* CPU port also does the same thing until all user ports belonging to
843 * the CPU port get out of VLAN filtering mode.
845 if (all_user_ports_removed) {
846 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
847 PCR_MATRIX(dsa_user_ports(priv->ds)));
848 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT),
854 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
856 struct mt7530_priv *priv = ds->priv;
858 /* The real fabric path would be decided on the membership in the
859 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
860 * means potential VLAN can be consisting of certain subset of all
863 mt7530_rmw(priv, MT7530_PCR_P(port),
864 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
866 /* Trapped into security mode allows packet forwarding through VLAN
869 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
870 MT7530_PORT_SECURITY_MODE);
872 /* Set the port as a user port which is to be able to recognize VID
873 * from incoming packets before fetching entry within the VLAN table.
875 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK,
876 VLAN_ATTR(MT7530_VLAN_USER));
880 mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
881 struct net_device *bridge)
883 struct mt7530_priv *priv = ds->priv;
886 mutex_lock(&priv->reg_mutex);
888 for (i = 0; i < MT7530_NUM_PORTS; i++) {
889 /* Remove this port from the port matrix of the other ports
890 * in the same bridge. If the port is disabled, port matrix
891 * is kept and not being setup until the port becomes enabled.
892 * And the other port's port matrix cannot be broken when the
893 * other port is still a VLAN-aware port.
895 if (!priv->ports[i].vlan_filtering &&
896 dsa_is_user_port(ds, i) && i != port) {
897 if (dsa_to_port(ds, i)->bridge_dev != bridge)
899 if (priv->ports[i].enable)
900 mt7530_clear(priv, MT7530_PCR_P(i),
901 PCR_MATRIX(BIT(port)));
902 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
906 /* Set the cpu port to be the only one in the port matrix of
909 if (priv->ports[port].enable)
910 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
911 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
912 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
914 mt7530_port_set_vlan_unaware(ds, port);
916 mutex_unlock(&priv->reg_mutex);
920 mt7530_port_fdb_add(struct dsa_switch *ds, int port,
921 const unsigned char *addr, u16 vid)
923 struct mt7530_priv *priv = ds->priv;
925 u8 port_mask = BIT(port);
927 mutex_lock(&priv->reg_mutex);
928 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
929 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
930 mutex_unlock(&priv->reg_mutex);
936 mt7530_port_fdb_del(struct dsa_switch *ds, int port,
937 const unsigned char *addr, u16 vid)
939 struct mt7530_priv *priv = ds->priv;
941 u8 port_mask = BIT(port);
943 mutex_lock(&priv->reg_mutex);
944 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
945 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
946 mutex_unlock(&priv->reg_mutex);
952 mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
953 dsa_fdb_dump_cb_t *cb, void *data)
955 struct mt7530_priv *priv = ds->priv;
956 struct mt7530_fdb _fdb = { 0 };
957 int cnt = MT7530_NUM_FDB_RECORDS;
961 mutex_lock(&priv->reg_mutex);
963 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
968 if (rsp & ATC_SRCH_HIT) {
969 mt7530_fdb_read(priv, &_fdb);
970 if (_fdb.port_mask & BIT(port)) {
971 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
978 !(rsp & ATC_SRCH_END) &&
979 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
981 mutex_unlock(&priv->reg_mutex);
987 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
989 struct mt7530_dummy_poll p;
993 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
994 mt7530_write(priv, MT7530_VTCR, val);
996 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
997 ret = readx_poll_timeout(_mt7530_read, &p, val,
998 !(val & VTCR_BUSY), 20, 20000);
1000 dev_err(priv->dev, "poll timeout\n");
1004 val = mt7530_read(priv, MT7530_VTCR);
1005 if (val & VTCR_INVALID) {
1006 dev_err(priv->dev, "read VTCR invalid\n");
1014 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
1015 bool vlan_filtering)
1017 struct mt7530_priv *priv = ds->priv;
1019 priv->ports[port].vlan_filtering = vlan_filtering;
1021 if (vlan_filtering) {
1022 /* The port is being kept as VLAN-unaware port when bridge is
1023 * set up with vlan_filtering not being set, Otherwise, the
1024 * port and the corresponding CPU port is required the setup
1025 * for becoming a VLAN-aware port.
1027 mt7530_port_set_vlan_aware(ds, port);
1028 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
1035 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
1036 const struct switchdev_obj_port_vlan *vlan)
1038 /* nothing needed */
1044 mt7530_hw_vlan_add(struct mt7530_priv *priv,
1045 struct mt7530_hw_vlan_entry *entry)
1050 new_members = entry->old_members | BIT(entry->port) |
1051 BIT(MT7530_CPU_PORT);
1053 /* Validate the entry with independent learning, create egress tag per
1054 * VLAN and joining the port as one of the port members.
1056 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1057 mt7530_write(priv, MT7530_VAWD1, val);
1059 /* Decide whether adding tag or not for those outgoing packets from the
1060 * port inside the VLAN.
1062 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1063 MT7530_VLAN_EGRESS_TAG;
1064 mt7530_rmw(priv, MT7530_VAWD2,
1065 ETAG_CTRL_P_MASK(entry->port),
1066 ETAG_CTRL_P(entry->port, val));
1068 /* CPU port is always taken as a tagged port for serving more than one
1069 * VLANs across and also being applied with egress type stack mode for
1070 * that VLAN tags would be appended after hardware special tag used as
1073 mt7530_rmw(priv, MT7530_VAWD2,
1074 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1075 ETAG_CTRL_P(MT7530_CPU_PORT,
1076 MT7530_VLAN_EGRESS_STACK));
1080 mt7530_hw_vlan_del(struct mt7530_priv *priv,
1081 struct mt7530_hw_vlan_entry *entry)
1086 new_members = entry->old_members & ~BIT(entry->port);
1088 val = mt7530_read(priv, MT7530_VAWD1);
1089 if (!(val & VLAN_VALID)) {
1091 "Cannot be deleted due to invalid entry\n");
1095 /* If certain member apart from CPU port is still alive in the VLAN,
1096 * the entry would be kept valid. Otherwise, the entry is got to be
1099 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1100 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1102 mt7530_write(priv, MT7530_VAWD1, val);
1104 mt7530_write(priv, MT7530_VAWD1, 0);
1105 mt7530_write(priv, MT7530_VAWD2, 0);
1110 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1111 struct mt7530_hw_vlan_entry *entry,
1112 mt7530_vlan_op vlan_op)
1117 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1119 val = mt7530_read(priv, MT7530_VAWD1);
1121 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1123 /* Manipulate entry */
1124 vlan_op(priv, entry);
1126 /* Flush result to hardware */
1127 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1131 mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1132 const struct switchdev_obj_port_vlan *vlan)
1134 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1135 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1136 struct mt7530_hw_vlan_entry new_entry;
1137 struct mt7530_priv *priv = ds->priv;
1140 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1143 if (!priv->ports[port].vlan_filtering)
1146 mutex_lock(&priv->reg_mutex);
1148 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1149 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1150 mt7530_hw_vlan_update(priv, vid, &new_entry,
1151 mt7530_hw_vlan_add);
1155 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1156 G0_PORT_VID(vlan->vid_end));
1157 priv->ports[port].pvid = vlan->vid_end;
1160 mutex_unlock(&priv->reg_mutex);
1164 mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1165 const struct switchdev_obj_port_vlan *vlan)
1167 struct mt7530_hw_vlan_entry target_entry;
1168 struct mt7530_priv *priv = ds->priv;
1171 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1174 if (!priv->ports[port].vlan_filtering)
1177 mutex_lock(&priv->reg_mutex);
1179 pvid = priv->ports[port].pvid;
1180 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1181 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1182 mt7530_hw_vlan_update(priv, vid, &target_entry,
1183 mt7530_hw_vlan_del);
1185 /* PVID is being restored to the default whenever the PVID port
1186 * is being removed from the VLAN.
1189 pvid = G0_PORT_VID_DEF;
1192 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1193 priv->ports[port].pvid = pvid;
1195 mutex_unlock(&priv->reg_mutex);
1200 static enum dsa_tag_protocol
1201 mtk_get_tag_protocol(struct dsa_switch *ds, int port)
1203 struct mt7530_priv *priv = ds->priv;
1205 if (port != MT7530_CPU_PORT) {
1207 "port not matched with tagging CPU port\n");
1208 return DSA_TAG_PROTO_NONE;
1210 return DSA_TAG_PROTO_MTK;
1215 mt7530_setup(struct dsa_switch *ds)
1217 struct mt7530_priv *priv = ds->priv;
1220 struct device_node *dn;
1221 struct mt7530_dummy_poll p;
1223 /* The parent node of master netdev which holds the common system
1224 * controller also is the container for two GMACs nodes representing
1225 * as two netdev instances.
1227 dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent;
1229 if (priv->id == ID_MT7530) {
1230 priv->ethernet = syscon_node_to_regmap(dn);
1231 if (IS_ERR(priv->ethernet))
1232 return PTR_ERR(priv->ethernet);
1234 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1235 ret = regulator_enable(priv->core_pwr);
1238 "Failed to enable core power: %d\n", ret);
1242 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1243 ret = regulator_enable(priv->io_pwr);
1245 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1251 /* Reset whole chip through gpio pin or memory-mapped registers for
1252 * different type of hardware
1255 reset_control_assert(priv->rstc);
1256 usleep_range(1000, 1100);
1257 reset_control_deassert(priv->rstc);
1259 gpiod_set_value_cansleep(priv->reset, 0);
1260 usleep_range(1000, 1100);
1261 gpiod_set_value_cansleep(priv->reset, 1);
1264 /* Waiting for MT7530 got to stable */
1265 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1266 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1269 dev_err(priv->dev, "reset timeout\n");
1273 id = mt7530_read(priv, MT7530_CREV);
1274 id >>= CHIP_NAME_SHIFT;
1275 if (id != MT7530_ID) {
1276 dev_err(priv->dev, "chip %x can't be supported\n", id);
1280 /* Reset the switch through internal reset */
1281 mt7530_write(priv, MT7530_SYS_CTRL,
1282 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1285 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1286 val = mt7530_read(priv, MT7530_MHWTRAP);
1287 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1288 val |= MHWTRAP_MANUAL;
1289 mt7530_write(priv, MT7530_MHWTRAP, val);
1291 /* Enable and reset MIB counters */
1292 mt7530_mib_reset(ds);
1294 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK);
1296 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1297 /* Disable forwarding by default on all ports */
1298 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1301 if (dsa_is_cpu_port(ds, i))
1302 mt7530_cpu_port_enable(priv, i);
1304 mt7530_port_disable(ds, i, NULL);
1307 /* Flush the FDB table */
1308 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1315 static const struct dsa_switch_ops mt7530_switch_ops = {
1316 .get_tag_protocol = mtk_get_tag_protocol,
1317 .setup = mt7530_setup,
1318 .get_strings = mt7530_get_strings,
1319 .phy_read = mt7530_phy_read,
1320 .phy_write = mt7530_phy_write,
1321 .get_ethtool_stats = mt7530_get_ethtool_stats,
1322 .get_sset_count = mt7530_get_sset_count,
1323 .adjust_link = mt7530_adjust_link,
1324 .port_enable = mt7530_port_enable,
1325 .port_disable = mt7530_port_disable,
1326 .port_stp_state_set = mt7530_stp_state_set,
1327 .port_bridge_join = mt7530_port_bridge_join,
1328 .port_bridge_leave = mt7530_port_bridge_leave,
1329 .port_fdb_add = mt7530_port_fdb_add,
1330 .port_fdb_del = mt7530_port_fdb_del,
1331 .port_fdb_dump = mt7530_port_fdb_dump,
1332 .port_vlan_filtering = mt7530_port_vlan_filtering,
1333 .port_vlan_prepare = mt7530_port_vlan_prepare,
1334 .port_vlan_add = mt7530_port_vlan_add,
1335 .port_vlan_del = mt7530_port_vlan_del,
1338 static const struct of_device_id mt7530_of_match[] = {
1339 { .compatible = "mediatek,mt7621", .data = (void *)ID_MT7621, },
1340 { .compatible = "mediatek,mt7530", .data = (void *)ID_MT7530, },
1343 MODULE_DEVICE_TABLE(of, mt7530_of_match);
1346 mt7530_probe(struct mdio_device *mdiodev)
1348 struct mt7530_priv *priv;
1349 struct device_node *dn;
1351 dn = mdiodev->dev.of_node;
1353 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1357 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
1361 /* Use medatek,mcm property to distinguish hardware type that would
1362 * casues a little bit differences on power-on sequence.
1364 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
1366 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
1368 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
1369 if (IS_ERR(priv->rstc)) {
1370 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1371 return PTR_ERR(priv->rstc);
1375 /* Get the hardware identifier from the devicetree node.
1376 * We will need it for some of the clock and regulator setup.
1378 priv->id = (unsigned int)(unsigned long)
1379 of_device_get_match_data(&mdiodev->dev);
1381 if (priv->id == ID_MT7530) {
1382 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1383 if (IS_ERR(priv->core_pwr))
1384 return PTR_ERR(priv->core_pwr);
1386 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1387 if (IS_ERR(priv->io_pwr))
1388 return PTR_ERR(priv->io_pwr);
1391 /* Not MCM that indicates switch works as the remote standalone
1392 * integrated circuit so the GPIO pin would be used to complete
1393 * the reset, otherwise memory-mapped register accessing used
1394 * through syscon provides in the case of MCM.
1397 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
1399 if (IS_ERR(priv->reset)) {
1400 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1401 return PTR_ERR(priv->reset);
1405 priv->bus = mdiodev->bus;
1406 priv->dev = &mdiodev->dev;
1407 priv->ds->priv = priv;
1408 priv->ds->ops = &mt7530_switch_ops;
1409 mutex_init(&priv->reg_mutex);
1410 dev_set_drvdata(&mdiodev->dev, priv);
1412 return dsa_register_switch(priv->ds);
1416 mt7530_remove(struct mdio_device *mdiodev)
1418 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
1421 ret = regulator_disable(priv->core_pwr);
1424 "Failed to disable core power: %d\n", ret);
1426 ret = regulator_disable(priv->io_pwr);
1428 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
1431 dsa_unregister_switch(priv->ds);
1432 mutex_destroy(&priv->reg_mutex);
1435 static struct mdio_driver mt7530_mdio_driver = {
1436 .probe = mt7530_probe,
1437 .remove = mt7530_remove,
1440 .of_match_table = mt7530_of_match,
1444 mdio_module_driver(mt7530_mdio_driver);
1446 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1447 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1448 MODULE_LICENSE("GPL");